JPH1197487A - Mounting method and the device and anisotropic conductive sheet - Google Patents

Mounting method and the device and anisotropic conductive sheet

Info

Publication number
JPH1197487A
JPH1197487A JP9259799A JP25979997A JPH1197487A JP H1197487 A JPH1197487 A JP H1197487A JP 9259799 A JP9259799 A JP 9259799A JP 25979997 A JP25979997 A JP 25979997A JP H1197487 A JPH1197487 A JP H1197487A
Authority
JP
Japan
Prior art keywords
anisotropic conductive
substrate
film
wiring
conductive film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9259799A
Other languages
Japanese (ja)
Inventor
Tetsuya Yamamoto
哲也 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP9259799A priority Critical patent/JPH1197487A/en
Publication of JPH1197487A publication Critical patent/JPH1197487A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
    • H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/29076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29355—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75314—Auxiliary members on the pressing surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2924/01—Chemical elements
    • H01L2924/01021—Scandium [Sc]
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Abstract

PROBLEM TO BE SOLVED: To prevent a projection of an anisotropic conductive film, by a method wherein the anisotropic conductive film is adhered to an area on a substrate containing a wiring terminal, and an insulation resin film having no conductivity is adhered to an area on a substrate enclosing the above area and on the anisotropic conductive film, and a bump electrode is connected to a wiring terminal by heating and pressing. SOLUTION: An anisotropic conductive film 4 arranged previously on a substrate has a film base material 31 of an epoxy resin system and conductive particles 32 dispersed and held therein, and the anisotropic conductive film 4 is adhered to a connection area 1b of a semiconductor element 3 in which a wiring 1a has beforehand formed a terminal formed in a specified circuit pattern, and an insulation resin film 4a is laminated from thereon. The anisotropic conductive film 4 has the substantially analogous relationship to the shape of the semiconductor element 3, the dimension is slightly larger than the semiconductor element, and the insulation resin film 4a has a dimension completely covering not only the anisotropic conductive film 4 but also a wiring 1 containing a peripheral area 1e enclosing a connection area 1b. Thus, it is possible to seal the wiring 1 and the bump electrode 3a without projecting.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、例えばフリップチ
ップなどの半導体装置を基板に実装する実装方法及びそ
の装置及び異方性導電材に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting method for mounting a semiconductor device such as a flip chip on a substrate, a device therefor, and an anisotropic conductive material.

【０００２】[0002]

【従来の技術】たとえば、図９及び図１０に示すよう
に、基板８１に形成された電極８２に半導体素子８３を
異方性導電膜（ＡＣＦ：Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏ
ｎｄｕｃｔｉｖｅ Ｆｉｌｍ）８４を介して、実装ヘッ
ドである加熱加圧ツール８５により実装している。すな
わち、基板８１の電極８２上に異方性導電膜８４を貼り
付け、その上から例えばフリップチップなどの半導体装
置８３の突起電極８３ａを位置決めし、半導体装置５３
を仮固定するために、圧縮空気をエアシリンダに注入
し、加熱加圧ツール８５を下降させて半導体装置８３を
加熱加圧しながら、仮圧着を行う。その後、位置ずれが
無いことを確認した後、異方性導電膜８４を完全に硬化
させるために、再度、加熱加圧ツール８５を下降させ
て、加熱加圧し本圧着する。なお、この場合、異方性導
電膜８４の代わりに、異方性導電ペースト（ＡＣＦ：Ａ
ｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓ
ｔｅ）又はクリームはんだを塗布してもよい。BACKGROUND ART For example, as shown in FIGS. 9 and 10, the anisotropic conductive film of the semiconductor device 83 to the electrode 82 formed on substrate 81 (ACF: A nisotropic C o
through nductive F ilm) 84, are mounted by heating and pressing tool 85 is a mounting head. That is, an anisotropic conductive film 84 is attached on the electrode 82 of the substrate 81, and the protruding electrode 83 a of the semiconductor device 83 such as a flip chip is positioned thereon, and the semiconductor device 53
In order to temporarily fix the semiconductor device 83, compressed air is injected into an air cylinder, and the heating and pressurizing tool 85 is lowered to heat and pressurize the semiconductor device 83, thereby temporarily performing pressure bonding. Then, after confirming that there is no displacement, the heating / pressing tool 85 is again lowered, heated and pressurized, and completely press-bonded in order to completely cure the anisotropic conductive film 84. In this case, instead of the anisotropic conductive film 84, an anisotropic conductive paste (ACF: A
nisotropic C onductive P as
te) or cream solder may be applied.

【０００３】ところで、上記従来の実装方法において
は、次のような問題があった。まず、図１０に示すよう
に、異方性導電膜８４は、ツール８５による加圧・加熱
中に側方にはみ出すが、はみ出した異方性導電膜８４
は、導電粒子８６の充填率が低くなり、隣接する配線間
の絶縁性が低下する。[0003] The above conventional mounting method has the following problems. First, as shown in FIG. 10, the anisotropic conductive film 84 protrudes to the side during pressurization and heating by the tool 85, but the protruding anisotropic conductive film 84
In this case, the filling rate of the conductive particles 86 decreases, and the insulation between adjacent wirings decreases.

【０００４】さらに、はみ出した異方性導電膜８４が、
ツール８５に付着・硬化して基板５１を破壊するのを防
止するためのツール８５に付着・硬化した異方性導電膜
８４を除去する工程が入ることにより作業性が著しく低
下する。Further, the protruding anisotropic conductive film 84
The workability is significantly reduced due to the step of removing the anisotropic conductive film 84 attached and cured to the tool 85 for preventing the substrate 85 from being destroyed by being attached and cured to the tool 85.

【０００５】最後に、異方性導電膜８４の量を半導体装
置８３の実装面積より小さくすると、電極８２がむきだ
しのままになるため、絶縁性樹脂９０で封止する必要が
ある。[0005] Finally, if the amount of the anisotropic conductive film 84 is made smaller than the mounting area of the semiconductor device 83, the electrode 82 remains exposed, so that it is necessary to seal it with the insulating resin 90.

【０００６】[0006]

【発明が解決しようとする課題】上述したように、従来
技術では、異方性導電膜８４は、ツール８５による加圧
・加熱中に側方にはみ出すが、はみ出した異方性導電膜
８４は、導電粒子８６の充填率が低くなり、隣接する配
線間の絶縁性が低下する。さらに、はみ出した異方性導
電膜８４が、ツール８５に付着・硬化して基板８１を破
壊するのを防止するためのツール８５に付着・硬化した
異方性導電膜８４を除去する工程が入ることにより作業
性が著しく低下する。最後に、異方性導電膜８４の量を
半導体装置８３の実装面積より小さくすると、電極８２
がむきだしのままになるため、絶縁性樹脂で封止する必
要がある。本発明は、上記事情を勘案してなされたもの
で、上記技術的課題を解決することのできる実装方法を
提供することを目的とする。As described above, in the prior art, the anisotropic conductive film 84 protrudes laterally during pressurization and heating by the tool 85, but the protruding anisotropic conductive film 84 As a result, the filling rate of the conductive particles 86 decreases, and the insulation between adjacent wirings decreases. Further, a step of removing the anisotropic conductive film 84 attached and hardened to the tool 85 for preventing the protruding anisotropic conductive film 84 from being attached and hardened to the tool 85 and breaking the substrate 81 is included. This significantly reduces workability. Finally, when the amount of the anisotropic conductive film 84 is smaller than the mounting area of the semiconductor device 83, the electrode 82
However, since it is left bare, it is necessary to seal it with an insulating resin. The present invention has been made in view of the above circumstances, and has as its object to provide a mounting method that can solve the above technical problem.

【０００７】[0007]

【課題を解決するための手段】請求項１の実装方法は、
複数のバンプ電極を有する電子部品を基板上に形成され
た複数の配線端子に接続する実装方法において、前記配
線端子を包含する前記基板上の領域に異方性導電膜を被
着する異方性導電膜被着工程と、前記異方性導電膜を囲
繞する前記基板上の領域及び前記異方性導電膜上の領域
に導電性を有しない絶縁性樹脂膜を被着する絶縁性樹脂
膜被着工程と、ツールにより前記電子部品を前記基板に
対して加熱加圧し前記異方性導電膜を介して前記バンプ
電極を前記配線端子に接続する圧着工程とを具備する。According to a first aspect of the present invention, there is provided a mounting method comprising:
In a mounting method for connecting an electronic component having a plurality of bump electrodes to a plurality of wiring terminals formed on a substrate, an anisotropic conductive film is applied to a region on the substrate including the wiring terminals. A conductive film depositing step, and an insulating resin film covering a region on the substrate surrounding the anisotropic conductive film and a region on the anisotropic conductive film with an insulating resin film having no conductivity. And a pressure bonding step of heating and pressing the electronic component against the substrate with a tool and connecting the bump electrode to the wiring terminal via the anisotropic conductive film.

【０００８】請求項２の実装方法は、複数のバンプ電極
を有する電子部品を基板上に形成された複数の配線端子
に接続する実装方法において、前記配線端子上に介挿膜
を前記基板上に被着する介挿膜被着工程と、ツールによ
り前記電子部品を前記基板に対して加熱加圧し前記介挿
膜を介して前記バンプ電極を前記配線端子に接続する圧
着工程とを具備し、前記介挿膜は、前記配線端子を包含
する前記基板上の領域に被着される異方性導電部と、前
記異方性導電部を囲繞する前記基板上の領域に被着され
導電性を有しない絶縁性樹脂部とからなる。According to a second aspect of the present invention, in the mounting method for connecting an electronic component having a plurality of bump electrodes to a plurality of wiring terminals formed on a substrate, an intervening film is formed on the wiring terminals. An interposing film applying step of applying, and a crimping step of connecting the bump electrode to the wiring terminal through the interposing film by heating and pressing the electronic component against the substrate with a tool, The interposed film has an anisotropic conductive portion attached to a region on the substrate including the wiring terminal and a conductive film attached to a region on the substrate surrounding the anisotropic conductive portion. And a non-insulating resin part.

【０００９】請求項３の実装方法は、複数のバンプ電極
を有する電子部品を基板上に形成された複数の配線端子
に接続する実装方法において、前記配線端子を包含する
前記基板上の領域に異方性導電ペーストを前記基板上に
塗布する異方性導電ペースト塗布工程と、前記異方性導
電ペーストを囲繞する前記基板上の領域に導電性を有し
ない絶縁性樹脂ペーストを被着する絶縁性樹脂ペースト
被着工程と、ツールにより前記電子部品を前記基板に対
して加熱加圧し前記異方性導電ペーストを介して前記バ
ンプ電極を前記配線端子に接続する圧着工程とを具備す
る。According to a third aspect of the present invention, there is provided a mounting method for connecting an electronic component having a plurality of bump electrodes to a plurality of wiring terminals formed on a substrate. An anisotropic conductive paste application step of applying an isotropic conductive paste on the substrate; and an insulating property of applying a non-conductive insulating resin paste to a region on the substrate surrounding the anisotropic conductive paste. A resin paste application step; and a pressure bonding step of heating and pressing the electronic component against the substrate with a tool and connecting the bump electrode to the wiring terminal via the anisotropic conductive paste.

【００１０】請求項４の実装装置は、複数のバンプ電極
を有する電子部品を複数の配線端子が形成された基板に
対してツールにより加熱加圧し前記バンプ電極を異方性
導電膜を介して複数の配線端子に接続する実装装置にお
いて、前記ツールの表面にはフッ素樹脂からなる薄膜が
形成されている。According to a fourth aspect of the present invention, there is provided a mounting apparatus, wherein an electronic component having a plurality of bump electrodes is heated and pressed by a tool on a substrate on which a plurality of wiring terminals are formed, and the plurality of bump electrodes are formed via an anisotropic conductive film. In the mounting apparatus connected to the wiring terminal, a thin film made of a fluororesin is formed on the surface of the tool.

【００１１】請求項５の異方性導電シートは、バンプ電
極を対応する配線端子に電気的に接続する異方性導電シ
ートにおいて、配線端子を包含する領域に被着され且つ
前記バンプ電極と前記配線端子との間に電気的導通を付
与する導電粒子を分散状態にて含有する異方性導電部
と、前記異方性導電部を囲繞する位置に一体的に延設さ
れ前記バンプ電極と前記配線端子との間に電気的導通を
付与しない絶縁性樹脂部とを具備する。請求項６の異方
性導電シート、請求項５において、前記導電粒子を含有
しないか、又は、前記異方性導電部よりも含有量が小さ
い。According to a fifth aspect of the present invention, in the anisotropic conductive sheet electrically connecting the bump electrodes to the corresponding wiring terminals, the anisotropic conductive sheet is attached to a region including the wiring terminals, and is connected to the bump electrodes and the wiring terminals. An anisotropic conductive portion containing, in a dispersed state, conductive particles for imparting electrical continuity between the wiring terminal, and the bump electrode and the bump electrode, which are integrally extended at a position surrounding the anisotropic conductive portion. An insulating resin portion that does not provide electrical continuity with the wiring terminal. 7. The anisotropic conductive sheet according to claim 6, wherein the conductive particles are not contained or the content is smaller than that of the anisotropic conductive part.

【００１２】[0012]

【発明の実施の形態】以下、本発明の一実施形態を図面
を参照して詳述する。図１は、この一実施形態の実装装
置を示している。この実装装置は、基板１を載置して位
置決めするテーブル部２と、このテーブル部２の上方に
配設され基板１に対して例えばフリップチップなどのバ
ンプ電極３ａを有する半導体素子３（図２参照）を異方
性導電膜４（図２参照）を介して基板１に形成された例
えば銅薄膜からなる電極１ａ（図２参照）に対して加熱
加圧するための加熱加圧ツール５を有するツール部６
と、このツール部６及びテーブル部２の作動を制御する
ボンディング制御部７とを有している。An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a mounting apparatus according to this embodiment. This mounting apparatus includes a table portion 2 on which a substrate 1 is placed and positioned, and a semiconductor element 3 (FIG. 2) which is disposed above the table portion 2 and has a bump electrode 3a such as a flip chip with respect to the substrate 1. (See FIG. 2) formed on the substrate 1 via the anisotropic conductive film 4 (see FIG. 2). Tool part 6
And a bonding control unit 7 for controlling the operation of the tool unit 6 and the table unit 2.

【００１３】しかして、ツール部４は、加熱加圧ツール
５と、この加熱加圧ツール５を着脱自在に保持するチャ
ック８と、このチャック８を保持して昇降駆動する駆動
機構９と、チャック８の下端部に設けられ加熱加圧ツー
ル５と基板１との距離を計測する測距手段としてのレー
ザ変位計８ａとを有している。そして、加熱加圧ツール
５は、実際に半導体素子３を加熱加圧する横断面がコの
字状をなす一対の当接部５ａ（図２参照）と、この当接
部５ａに加熱電流を通電させる加熱電源５ｂとを有して
いる。そして、加熱加圧ツール５の当接部５ａ表面に
は、フッ素樹脂であるテフロン（商標名：米国デュポン
社製）薄膜５ｃが、被着されている。The tool section 4 includes a heating and pressing tool 5, a chuck 8 for detachably holding the heating and pressing tool 5, a drive mechanism 9 for holding and vertically moving the chuck 8 and a chuck. A laser displacement meter 8 a is provided at the lower end of 8 and measures the distance between the heating and pressing tool 5 and the substrate 1. The heating and pressing tool 5 includes a pair of abutting portions 5a (see FIG. 2) having a U-shaped cross section for actually heating and pressing the semiconductor element 3, and a heating current is applied to the abutting portions 5a. And a heating power supply 5b. On the surface of the contact portion 5a of the heating and pressing tool 5, a thin film 5c of Teflon (trade name: manufactured by DuPont, USA), which is a fluororesin, is applied.

【００１４】さらに、チャック８は、その下端部におい
て加熱加圧ツール５を挾圧・保持するとともに、上端部
において電気的絶縁材を介して駆動機構９に連結されて
いる。そして、チャック８は、前記加熱電源５ｂに電気
的に接続され、その下端部を介して当接部５ａに直流電
流を通電するようになっている。Further, the chuck 8 clamps and holds the heating and pressing tool 5 at a lower end thereof, and is connected to a driving mechanism 9 via an electrical insulating material at an upper end thereof. The chuck 8 is electrically connected to the heating power source 5b, and is configured to supply a direct current to the contact portion 5a via a lower end thereof.

【００１５】しかして、駆動機構９は、空気圧シリンダ
１３と、この空気圧シリンダ１３により昇降駆動される
作動杆１４と、空気圧シリンダ１３内に圧縮空気を導入
かつ導出する空気案内管１５と、前記空気案内管１５を
介して空気圧シリンダ１３に圧縮空気を供給する圧縮空
気源１６と、圧縮空気源１６から供給される圧縮空気の
空気圧シリンダ１３への注入速度を制御して作動杆１４
の昇降速度を制御するスピード制御器１７と、空気案内
管１５の中途に設けられ当接部５ａによる加圧力を検出
する加圧力検出器１８とを有している。The driving mechanism 9 includes a pneumatic cylinder 13, an operating rod 14 driven up and down by the pneumatic cylinder 13, an air guide tube 15 for introducing and leading compressed air into the pneumatic cylinder 13, and the pneumatic cylinder 13. A compressed air source 16 for supplying compressed air to the pneumatic cylinder 13 via the guide tube 15 and an operating rod 14 for controlling the injection speed of the compressed air supplied from the compressed air source 16 into the pneumatic cylinder 13
A speed controller 17 for controlling the ascending / descending speed, and a pressure detector 18 provided in the middle of the air guide tube 15 for detecting the pressure applied by the contact portion 5a.

【００１６】さらに、ボンディング制御部７には、後述
する実装プロセスを実現するための操作プログラムが格
納されていて、レーザ変位計８ａからの出力信号ＳＤ及
び加圧力検出器１８からの出力信号ＳＰに基づいて、加
熱加圧ツール５の昇降及び加圧時間を制御するものであ
る。Further, the bonding control unit 7 stores an operation program for realizing a mounting process to be described later, and outputs the operation signal SD from the laser displacement meter 8 a and the output signal SP from the pressing force detector 18. On the basis of this, the elevation of the heating and pressing tool 5 and the pressurizing time are controlled.

【００１７】つぎに、上記構成の実装装置を用いて、こ
の一実施形態の実装方法について述べる。図２には、こ
の実施形態の実装方法にて基板１上に異方性導電膜４を
介して実装される半導体素子３が示されている。この半
導体素子３は、シリコン（Ｓｉ）製板状の本体３ｂと、
この本体３ｂに突設されたバンプ電極３ａとからなって
いる。このバンプ電極３ａの材質としては、例えば金
（Ａｕ）などが好適している。Next, a mounting method of this embodiment will be described using the mounting apparatus having the above configuration. FIG. 2 shows a semiconductor element 3 mounted on the substrate 1 via the anisotropic conductive film 4 by the mounting method of this embodiment. The semiconductor element 3 includes a plate-shaped main body 3b made of silicon (Si),
It comprises a bump electrode 3a protruding from the main body 3b. As a material of the bump electrode 3a, for example, gold (Au) is suitable.

【００１８】さらに、基板１上にあらかじめ配設される
異方性導電膜４は、図２に示すように、エポキシ樹脂系
のフィルム基材３１と、このフィルム基材３１中に分散
保持された導電粒子３２とを有している。この導電粒子
３２は、例えばニッケル（Ｎｉ），半田，カーボン，導
電めっき樹脂ボール等が好ましい。また、導電粒子３２
の粒径は、例えば数μｍ程度である。Further, as shown in FIG. 2, the anisotropic conductive film 4 disposed in advance on the substrate 1 is made of an epoxy resin-based film substrate 31 and dispersed and held in the film substrate 31. And conductive particles 32. The conductive particles 32 are preferably, for example, nickel (Ni), solder, carbon, conductive plated resin balls, or the like. In addition, the conductive particles 32
Is, for example, about several μm.

【００１９】さて、まず基板１をテーブル部２上に位置
決めする。図２に示すように、この基板１上には、予め
例えば銅などからなる配線１ａが所定の回路パターンに
形成されている。そして、配線１ａの端子をなす半導体
素子３の接続領域１ｂに、例えば厚さ数１００μｍの異
方性導電膜４を被着する。つぎに、異方性導電膜４の上
から例えば厚さ数１００μｍの絶縁性樹脂膜４ａを積層
する。このとき、異方性導電膜４の形状は、半導体素子
３の形状とほぼ相似関係にあり、かつ、寸法は、半導体
素子３よりもわずかに大きい程度に設定する。一方、絶
縁性樹脂膜４ａは、半導体素子３の形状とほぼ相似関係
にあり、かつ、その寸法は、異方性導電膜４はもとよ
り、接続領域１ｂを囲繞する外辺領域１ｅを含む配線１
を完全に被覆する寸法に設定する。First, the substrate 1 is positioned on the table 2. As shown in FIG. 2, a wiring 1a made of, for example, copper is formed in a predetermined circuit pattern on the substrate 1 in advance. Then, an anisotropic conductive film 4 having a thickness of, for example, several 100 μm is applied to the connection region 1b of the semiconductor element 3 which forms a terminal of the wiring 1a. Next, an insulating resin film 4 a having a thickness of, for example, several hundred μm is laminated on the anisotropic conductive film 4. At this time, the shape of the anisotropic conductive film 4 is substantially similar to the shape of the semiconductor element 3, and the dimension is set to be slightly larger than that of the semiconductor element 3. On the other hand, the insulating resin film 4a has a substantially similar relationship to the shape of the semiconductor element 3, and its dimensions are not limited to the anisotropic conductive film 4 but also to the wiring 1 including the outer edge region 1e surrounding the connection region 1b.
Is set to a dimension that completely covers.

【００２０】しかして、バンプ電極３ａが、異方性導電
膜４及び絶縁性樹脂膜４ａを介して、対応する配線１ａ
上になるように、半導体素子３を図示せぬ搬送・位置決
め機構により基板１上に位置決め・載置する。The bump electrode 3a is connected to the corresponding wiring 1a via the anisotropic conductive film 4 and the insulating resin film 4a.
The semiconductor element 3 is positioned and mounted on the substrate 1 by a transport / positioning mechanism (not shown) so as to be on the upper side.

【００２１】つぎに、ボンディング制御部７からは、あ
らかじめ設定されているプログラムに従って駆動機構９
のスピード制御器１７に制御信号ＳＣが印加される。こ
れに伴って、スピード制御器１７にては、下降速度Ｖ１
で作動杆１４が下降するように、圧縮空気を圧縮空気源
１６から空気圧シリンダ１３に注入する。これにともな
って、加熱加圧ツール５は、基板１に向かって接近する
（図２参照）。このとき、レーザ変位計８ａからは加熱
加圧ツール５と基板１との距離Ｄを示す信号ＳＤがボン
ディング制御部７に入力する。しかして、ボンディング
制御部７にては、この信号ＳＤが示す距離Ｄが予め設定
されているＤ０（例えば１０ｍｍ）になったとき、スピ
ード制御器１７に制御信号ＳＣを印加し、下降速度Ｖ２
で作動杆１４が下降するように、注入している圧縮空気
の圧力を減圧する。ここで、下降速度Ｖ１は、例えば６
０ｍｍ／秒、及び、下降速度Ｖ２は、例えば１０ｍｍ／
秒である。すなわち、下降速度Ｖ２は、下降速度Ｖ１の
ほぼ６分の１のように微速で下降する。このように減速
した状態で加熱加圧ツール５の当接体１１を半導体素子
３に当接させるとともに、加熱加圧する。その結果、バ
ンプ電極３ａは、異方性導電膜４及び絶縁性樹脂膜４ａ
を変形させながら侵入し、異方性導電膜４中の導電粒子
３２を介して配線１ａに電気的に接続される（図３参
照）。Next, the bonding control unit 7 sends the driving mechanism 9 in accordance with a preset program.
The control signal SC is applied to the speed controller 17 of FIG. Accordingly, the speed controller 17 sets the descending speed V1
Compressed air is injected into the pneumatic cylinder 13 from the compressed air source 16 so that the operating rod 14 descends. Accordingly, the heating and pressing tool 5 approaches the substrate 1 (see FIG. 2). At this time, a signal SD indicating the distance D between the heating and pressing tool 5 and the substrate 1 is input to the bonding control unit 7 from the laser displacement meter 8a. When the distance D indicated by the signal SD becomes a preset value D0 (for example, 10 mm), the bonding control unit 7 applies the control signal SC to the speed controller 17 to reduce the descent speed V2.
, The pressure of the compressed air being injected is reduced so that the operating rod 14 descends. Here, the descending speed V1 is, for example, 6
0 mm / sec and the descending speed V2 are, for example, 10 mm / sec.
Seconds. That is, the descending speed V2 descends at a very low speed, such as approximately one sixth of the descending speed V1. In this decelerated state, the contact body 11 of the heating and pressing tool 5 is brought into contact with the semiconductor element 3 and is heated and pressed. As a result, the bump electrode 3a becomes the anisotropic conductive film 4 and the insulating resin film 4a.
Penetrate while deforming, and are electrically connected to the wiring 1a via the conductive particles 32 in the anisotropic conductive film 4 (see FIG. 3).

【００２２】一方、異方性導電膜４及び絶縁性樹脂膜４
ａは、加熱加圧ツール５による加熱により硬化し、半導
体素子３は、基板１に固着される。このとき、加熱加圧
ツール５の当接部５ａ表面には、テフロン薄膜５ｃが施
されているため、異方性導電膜４及び絶縁性樹脂膜４ａ
が付着・硬化しても簡単に剥がすことができ、生産性向
上に寄与できる。On the other hand, anisotropic conductive film 4 and insulating resin film 4
a is hardened by heating by the heating and pressing tool 5, and the semiconductor element 3 is fixed to the substrate 1. At this time, since the Teflon thin film 5c is applied to the surface of the contact portion 5a of the heating and pressing tool 5, the anisotropic conductive film 4 and the insulating resin film 4a
Can be easily peeled off even if adhered and cured, which can contribute to an improvement in productivity.

【００２３】また、絶縁性樹脂膜４ａは、半導体素子３
の形状とほぼ相似関係にあり、かつ、その寸法は、異方
性導電膜４はもとより、配線１を完全に被覆する寸法に
設定されているので、加圧加熱による硬化後において
も、半導体素子３と基板１との間に十分な量が介在する
こととなり、配線１及びバンプ電極３ａを完全に封止す
ることができ、従来のように、封止剤を追加する工程が
必要となることはなく、生産性向上に寄与できる。Further, the insulating resin film 4a is
And the dimensions are set to dimensions that completely cover the wiring 1 as well as the anisotropic conductive film 4. 3 and the substrate 1 are interposed in a sufficient amount, the wiring 1 and the bump electrode 3a can be completely sealed, and a step of adding a sealing agent is required as in the conventional case. No, it can contribute to productivity improvement.

【００２４】つぎに、本発明の他の実施形態について図
４乃至図６に基づいて述べる。なお、前記実施例の説明
と同一部分には、同一記号を付し、詳細な説明を省略す
る。この実施形態においては、まず基板１をテーブル部
２上に位置決め・載置する。そして、配線１ａの半導体
素子３の接続領域に、例えば厚さ数１０μｍの異方性導
電シート４０（図６参照）を被着させる。この異方性導
電シート４０は、例えばニッケル（Ｎｉ）やカーボン
（Ｃ）などの粒径数μｍ程度の導電粒子３２を含有し接
続領域１ｂを被覆する導電部位４０−１と、この導電部
位４０−１の周辺である外辺領域１ｅを被覆し且つ導電
粒子３２を含有しない絶縁部位４０−２とからなってい
る。これら導電部位４０−１及び絶縁部位４０−２は、
エポキシ樹脂系のフィルム基材３１を共通基材としてい
る。Next, another embodiment of the present invention will be described with reference to FIGS. Note that the same parts as those in the description of the above embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, first, the substrate 1 is positioned and placed on the table 2. Then, an anisotropic conductive sheet 40 (see FIG. 6) having a thickness of, for example, several tens of μm is attached to the connection region of the semiconductor element 3 of the wiring 1a. The anisotropic conductive sheet 40 includes, for example, a conductive part 40-1 containing conductive particles 32 having a particle size of about several μm such as nickel (Ni) or carbon (C) and covering the connection region 1 b, and a conductive part 40-1. -1 and an insulating portion 40-2 which covers the outer peripheral region 1e and does not contain the conductive particles 32. These conductive part 40-1 and insulating part 40-2 are
An epoxy resin-based film substrate 31 is used as a common substrate.

【００２５】このとき、異方性導電シート４０の導電部
位４０−１の形状は、半導体素子３の形状とほぼ相似関
係にあり、かつ、寸法は、半導体素子３よりもわずかに
大きい程度に設定する。一方、異方性導電シート４０の
絶縁部位４０−２の外形寸法は、異方性導電シート４０
はもとより、配線１を完全に被覆する寸法に設定する。At this time, the shape of the conductive portion 40-1 of the anisotropic conductive sheet 40 is substantially similar to the shape of the semiconductor element 3, and the size is set to be slightly larger than that of the semiconductor element 3. I do. On the other hand, the outer dimensions of the insulating portion 40-2 of the anisotropic conductive sheet 40 are
In addition, the dimensions are set so as to completely cover the wiring 1.

【００２６】しかして、半導体素子３を図示せぬ搬送・
位置決め機構により異方性導電シート４０上に位置決め
・載置し、バンプ電極３ａが、異方性導電シート４０を
介して、対応する配線１ａ上になるようにする。そし
て、加熱加圧ツール５の当接部５ａを半導体素子３に当
接させるとともに、加熱加圧する。その結果、バンプ電
極３ａは、異方性導電シート４０を変形させながら侵入
し、異方性導電シート４０の導電部位４０−１中の導電
粒子３２を介して配線１ａに電気的に接続される（図５
参照）。Thus, the semiconductor element 3 is transported and transported (not shown).
The bump electrode 3a is positioned and placed on the corresponding wiring 1a via the anisotropic conductive sheet 40 by the positioning mechanism. Then, the contact portion 5a of the heating and pressing tool 5 is brought into contact with the semiconductor element 3 and is heated and pressed. As a result, the bump electrode 3a penetrates while deforming the anisotropic conductive sheet 40, and is electrically connected to the wiring 1a via the conductive particles 32 in the conductive portion 40-1 of the anisotropic conductive sheet 40. (FIG. 5
reference).

【００２７】一方、異方性導電シート４０全体を構成し
ているフィルム基材３１は、加熱加圧ツール５による加
熱により硬化し、半導体素子３は、基板１に固着される
が、異方性導電シート４０の絶縁部位４０−２の外形寸
法は、配線１を完全に被覆する大きさに設定されている
ので、加圧加熱による硬化後においても、半導体素子３
と基板１との間にフィルム基材３１ａが十分な量だけ介
在することとなり、配線１及びバンプ電極３ａを完全に
封止することができ、従来のように、封止剤を追加する
工程が必要となることはなく、生産性向上に寄与でき
る。On the other hand, the film substrate 31 constituting the whole of the anisotropic conductive sheet 40 is hardened by heating by the heating and pressing tool 5, and the semiconductor element 3 is fixed to the substrate 1. Since the outer dimensions of the insulating portion 40-2 of the conductive sheet 40 are set to a size that completely covers the wiring 1, the semiconductor element 3 is hardened even after being cured by pressurizing and heating.
A sufficient amount of the film base material 31a is interposed between the substrate 1 and the substrate 1, so that the wiring 1 and the bump electrode 3a can be completely sealed. It is not required, and can contribute to productivity improvement.

【００２８】つぎに、本発明の第３の実施形態について
図７及び図８に基づいて述べる。なお、第１の実施例の
説明と同一部分には、同一記号を付し、詳細な説明を省
略する。Next, a third embodiment of the present invention will be described with reference to FIGS. The same parts as those in the description of the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

【００２９】この実施形態においては、まず基板１をテ
ーブル部２上に位置決めする。そして、配線１ａの半導
体素子３の接続領域１ｂに、図示せぬシリンジ機構によ
り、例えば厚さ数１０μｍ程度に異方性導電ペースト５
０を塗布させる。この異方性導電ペースト５０は、例え
ばニッケル（Ｎｉ）やカーボン（Ｃ）などの粒径数μｍ
程度の導電粒子３２を含有する例えばエポキシ樹脂など
の材質からなるペースト５２からなっている。このと
き、被着している異方性導電ペースト５０の形状は、半
導体素子３の形状とほぼ相似関係にあり、かつ、寸法
は、半導体素子３よりもわずかに大きい程度に設定す
る。In this embodiment, first, the substrate 1 is positioned on the table 2. Then, an anisotropic conductive paste 5 having a thickness of, for example, about several tens μm is formed in the connection region 1b of the semiconductor element 3 of the wiring 1a by a syringe mechanism (not shown).
0 is applied. The anisotropic conductive paste 50 has a particle size of several μm such as nickel (Ni) or carbon (C).
It is made of a paste 52 made of a material such as an epoxy resin containing conductive particles 32 of a certain degree. At this time, the shape of the applied anisotropic conductive paste 50 is substantially similar to the shape of the semiconductor element 3, and the size is set to be slightly larger than that of the semiconductor element 3.

【００３０】つぎに、異方性導電ペースト５０を囲繞す
るようにエポキシ樹脂系の接着剤のみからなっている絶
縁性ペースト５３を図示せぬシリンジ機構により外辺領
域１ｅに塗布する。この絶縁性ペースト５３には導電粒
子３２は含有しない絶縁性の例えばエポキシ樹脂などの
材質からなっていて、その外形寸法は、異方性導電ペー
スト５０はもとより、配線１を完全に被覆する大きさに
設定する。Next, an insulating paste 53 made of only an epoxy resin-based adhesive is applied to the outer peripheral region 1e by a syringe mechanism (not shown) so as to surround the anisotropic conductive paste 50. The insulating paste 53 is made of an insulating material that does not contain the conductive particles 32, such as an epoxy resin, and has an external dimension sufficient to completely cover the wiring 1 as well as the anisotropic conductive paste 50. Set to.

【００３１】しかして、バンプ電極３ａが、異方性導電
ペースト５０を介して、対応する配線１ａ上になるよう
に、半導体素子３を図示せぬ搬送・位置決め機構により
基板１上に位置決めする。そして、加熱加圧ツール５の
当接部５ａを半導体素子３に当接させるとともに、加熱
加圧する。その結果、バンプ電極３ａは、異方性導電ペ
ースト５０を変形させながら侵入し、異方性導電ペース
ト５０を介して配線１ａに電気的に接続されるが、絶縁
性ペースト５３の外形寸法は、配線１を完全に被覆する
大きさに設定されているので、加圧加熱による硬化後に
おいても、半導体素子３と基板１との間にエポキシ樹脂
が十分な量だけ介在することとなり、配線１及びバンプ
電極３ａを完全に封止することができ、従来のように、
封止剤を追加する工程が必要となることはなく、生産性
向上に寄与できる。Thus, the semiconductor element 3 is positioned on the substrate 1 by a transport / positioning mechanism (not shown) so that the bump electrode 3a is on the corresponding wiring 1a via the anisotropic conductive paste 50. Then, the contact portion 5a of the heating and pressing tool 5 is brought into contact with the semiconductor element 3 and is heated and pressed. As a result, the bump electrode 3a penetrates while deforming the anisotropic conductive paste 50, and is electrically connected to the wiring 1a via the anisotropic conductive paste 50. Since the size is set to completely cover the wiring 1, a sufficient amount of epoxy resin is interposed between the semiconductor element 3 and the substrate 1 even after curing by pressurizing and heating. The bump electrode 3a can be completely sealed, and as in the prior art,
There is no need for a step of adding a sealant, which can contribute to an improvement in productivity.

【００３２】なお、上記第３の実施形態において、絶縁
性ペースト５３の代わりに、エポキシ樹脂系のフィルム
基材３１を被着させても同様の効果を得ることができ
る。また、上記第３の実施形態において、異方性導電ペ
ースト５０の代わりにエポキシ樹脂系のフィルム基材か
らなり例えばニッケル（Ｎｉ）やカーボン（Ｃ）などの
導電粒子を含有する異方性導電フィルムを被着させるよ
うにしてもよい。In the third embodiment, the same effect can be obtained by attaching an epoxy resin-based film substrate 31 instead of the insulating paste 53. In the third embodiment, an anisotropic conductive film made of an epoxy resin-based film base instead of the anisotropic conductive paste 50 and containing conductive particles such as nickel (Ni) or carbon (C) is used. May be adhered.

【００３３】[0033]

【発明の効果】請求項１の実装方法は、複数のバンプ電
極を有する電子部品を基板上に形成された複数の配線端
子に接続する実装方法において、前記配線端子を包含す
る前記基板上の領域に異方性導電膜を前記基板上に被着
する異方性導電膜被着工程と、前記異方性導電膜を囲繞
する前記基板上の領域及び前記異方性導電膜上の領域に
導電性を有しない絶縁性樹脂膜を被着する絶縁性樹脂膜
被着工程と、ツールにより前記電子部品を前記基板に対
して加熱加圧し前記異方性導電膜を介して前記バンプ電
極を前記配線端子に接続する圧着工程とを具備する。According to a first aspect of the present invention, there is provided a mounting method for connecting an electronic component having a plurality of bump electrodes to a plurality of wiring terminals formed on a substrate, the region on the substrate including the wiring terminals. Forming an anisotropic conductive film on the substrate, and applying a conductive material to a region on the substrate surrounding the anisotropic conductive film and a region on the anisotropic conductive film. An insulating resin film applying step of applying an insulating resin film having no insulating property, and heating and pressurizing the electronic component with respect to the substrate using a tool, and connecting the bump electrode to the wiring via the anisotropic conductive film. Crimping step of connecting to the terminal.

【００３４】しかして、請求項１の実装方法は、加圧加
熱による硬化後においても、電子部品基板との間に十分
な量の封止樹脂が介在することとなり、配線端子及びバ
ンプ電極を完全に封止することができ、従来のように、
封止剤を追加する工程が必要となることはなく、生産性
向上に寄与できる。According to the mounting method of the present invention, a sufficient amount of the sealing resin is interposed between the wiring board and the electronic component substrate even after curing by pressurizing and heating. Can be sealed as before,
There is no need for a step of adding a sealant, which can contribute to an improvement in productivity.

【００３５】請求項２の実装方法は、複数のバンプ電極
を有する電子部品を基板上に形成された複数の配線端子
に接続する実装方法において、前記配線端子上に介挿膜
を前記基板上に被着する介挿膜被着工程と、ツールによ
り前記電子部品を前記基板に対して加熱加圧し前記介挿
膜を介して前記バンプ電極を前記配線端子に接続する圧
着工程とを具備し、前記介挿膜は、前記配線端子を包含
する前記基板上の領域に被着される異方性導電部と、前
記異方性導電部を囲繞する前記基板上の領域に被着され
導電性を有しない絶縁性樹脂部とからなる。According to a second aspect of the present invention, in the mounting method for connecting an electronic component having a plurality of bump electrodes to a plurality of wiring terminals formed on a substrate, an intervening film is formed on the wiring terminals on the substrate. An interposing film applying step of applying, and a crimping step of connecting the bump electrode to the wiring terminal through the interposing film by heating and pressing the electronic component against the substrate with a tool, The interposed film has an anisotropic conductive portion attached to a region on the substrate including the wiring terminal and a conductive film attached to a region on the substrate surrounding the anisotropic conductive portion. And a non-insulating resin part.

【００３６】しかして、請求項２の実装方法は、加圧加
熱による硬化後においても、電子部品と基板との間に封
止樹脂が十分な量だけ介在することとなり、配線端子及
びバンプ電極を完全に封止することができ、従来のよう
に、封止剤を追加する工程が必要となることはなく、生
産性向上に寄与できる。According to the mounting method of the present invention, a sufficient amount of the sealing resin is interposed between the electronic component and the substrate even after curing by pressurizing and heating. The sealing can be completed completely, and a step of adding a sealing agent is not required unlike the related art, which can contribute to improvement in productivity.

【００３７】請求項３の実装方法は、複数のバンプ電極
を有する電子部品を基板上に形成された複数の配線端子
に接続する実装方法において、前記配線端子を包含する
前記基板上の領域に異方性導電ペーストを前記基板上に
塗布する異方性導電ペースト塗布工程と、前記異方性導
電ペーストを囲繞する前記基板上の領域に導電性を有し
ない絶縁性樹脂ペーストを被着する絶縁性樹脂ペースト
被着工程と、ツールにより前記電子部品を前記基板に対
して加熱加圧し前記異方性導電ペーストを介して前記バ
ンプ電極を前記配線端子に接続する圧着工程とを具備す
る。According to a third aspect of the present invention, there is provided a mounting method for connecting an electronic component having a plurality of bump electrodes to a plurality of wiring terminals formed on a substrate. An anisotropic conductive paste application step of applying an isotropic conductive paste on the substrate; and an insulating property of applying a non-conductive insulating resin paste to a region on the substrate surrounding the anisotropic conductive paste. A resin paste application step; and a pressure bonding step of heating and pressing the electronic component against the substrate with a tool and connecting the bump electrode to the wiring terminal via the anisotropic conductive paste.

【００３８】しかして、請求項３の実装方法は、加圧加
熱による硬化後においても、電子部品と基板との間に封
止樹脂が十分な量だけ介在することとなり、配線端子及
びバンプ電極を完全に封止することができ、従来のよう
に、封止剤を追加する工程が必要となることはなく、生
産性向上に寄与できる。According to the mounting method of the present invention, a sufficient amount of the sealing resin is interposed between the electronic component and the substrate even after curing by pressurizing and heating. The sealing can be completed completely, and a step of adding a sealing agent is not required unlike the related art, which can contribute to improvement in productivity.

【００３９】請求項４の実装装置は、複数のバンプ電極
を有する電子部品を複数の配線端子が形成された基板に
対してツールにより加熱加圧し前記バンプ電極を異方性
導電膜を介して複数の配線端子に接続する実装装置にお
いて、前記ツールの表面にはフッ素樹脂からなる薄膜が
形成されている。According to a fourth aspect of the present invention, an electronic component having a plurality of bump electrodes is heated and pressed by a tool on a substrate on which a plurality of wiring terminals are formed, and the plurality of bump electrodes are formed via an anisotropic conductive film. In the mounting apparatus connected to the wiring terminal, a thin film made of a fluororesin is formed on the surface of the tool.

【００４０】しかして、請求項４の実装装置は、加熱加
圧用のツールの表面にテフロン処理が施されているた
め、封止樹脂が付着・硬化しても簡単に剥がすことがで
き、生産性向上に寄与できる。According to the mounting device of the fourth aspect, since the surface of the heating / pressing tool is subjected to Teflon treatment, even if the sealing resin adheres and hardens, it can be easily peeled off, and the productivity can be improved. It can contribute to improvement.

【００４１】請求項５の異方性導電シートは、バンプ電
極を対応する配線端子に電気的に接続する異方性導電シ
ートにおいて、配線端子を包含する領域に被着され且つ
前記バンプ電極と前記配線端子との間に電気的導通を付
与する導電粒子を分散状態にて含有する異方性導電部
と、前記異方性導電部を囲繞する位置に一体的に延設さ
れ前記バンプ電極と前記配線端子との間に電気的導通を
付与しない絶縁性樹脂部とを具備する。According to a fifth aspect of the present invention, in the anisotropic conductive sheet electrically connecting the bump electrodes to the corresponding wiring terminals, the anisotropic conductive sheet is attached to a region including the wiring terminals, and is connected to the bump electrodes. An anisotropic conductive portion containing, in a dispersed state, conductive particles for imparting electrical continuity between the wiring terminal, and the bump electrode and the bump electrode, which are integrally extended at a position surrounding the anisotropic conductive portion. An insulating resin portion that does not provide electrical continuity with the wiring terminal.

【００４２】また、請求項６の異方性導電シート、請求
項５において、前記導電粒子を含有しないか、又は、前
記異方性導電部よりも含有量が小さい。しかして、請求
項５及び請求項６の異方性導電シートは、加圧加熱によ
る硬化後においても、電子部品と基板との間に封止樹脂
が十分な量だけ介在することとなり、配線端子及びバン
プ電極を完全に封止することができ、従来のように、封
止剤を追加する工程が必要となることはなく、生産性向
上に寄与できる。The anisotropic conductive sheet according to claim 6 or claim 5 does not contain the conductive particles or has a smaller content than the anisotropic conductive part. In the anisotropic conductive sheet according to the fifth and sixth aspects, a sufficient amount of the sealing resin is interposed between the electronic component and the substrate even after curing by pressurizing and heating, so that the wiring terminals In addition, the bump electrode can be completely sealed, and a step of adding a sealing agent is not required unlike the related art, which can contribute to improvement in productivity.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施形態の実装装置の全体構成図で
ある。FIG. 1 is an overall configuration diagram of a mounting apparatus according to an embodiment of the present invention.

【図２】本発明の一実施形態の実装方法の説明図であ
る。FIG. 2 is an explanatory diagram of a mounting method according to an embodiment of the present invention.

【図３】本発明の一実施形態の実装方法の説明図であ
る。FIG. 3 is an explanatory diagram of a mounting method according to an embodiment of the present invention.

【図４】本発明の第２の実施形態の実装方法の説明図で
ある。FIG. 4 is an explanatory diagram of a mounting method according to a second embodiment of the present invention.

【図５】本発明の第２の実施形態の実装方法の説明図で
ある。FIG. 5 is an explanatory diagram of a mounting method according to a second embodiment of the present invention.

【図６】本発明の異方性導電シートの説明図である。FIG. 6 is an explanatory view of the anisotropic conductive sheet of the present invention.

【図７】本発明の第３の実施形態の実装方法の説明図で
ある。FIG. 7 is an explanatory diagram of a mounting method according to a third embodiment of the present invention.

【図８】本発明の第３の実施形態の実装方法の説明図で
ある。FIG. 8 is an explanatory diagram of a mounting method according to a third embodiment of the present invention.

【図９】従来技術の説明図である。FIG. 9 is an explanatory diagram of a conventional technique.

【図１０】従来技術の説明図である。FIG. 10 is an explanatory diagram of a conventional technique.

【符号の説明】[Explanation of symbols]

１：基板，３：半導体素子，３ａ：バンプ電極，４：異
方性導電膜，５：加熱加圧ツール。1: substrate, 3: semiconductor element, 3a: bump electrode, 4: anisotropic conductive film, 5: heating and pressing tool.

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】複数のバンプ電極を有する電子部品を基板
上に形成された複数の配線端子に接続する実装方法にお
いて、前記配線端子を包含する前記基板上の領域に異方
性導電膜を被着する異方性導電膜被着工程と、前記異方
性導電膜を囲繞する前記基板上の領域及び前記異方性導
電膜上の領域に導電性を有しない絶縁性樹脂膜を被着す
る絶縁性樹脂膜被着工程と、ツールにより前記電子部品
を前記基板に対して加熱加圧し前記異方性導電膜を介し
て前記バンプ電極を前記配線端子に接続する圧着工程と
を具備することを特徴とする実装方法。In a mounting method for connecting an electronic component having a plurality of bump electrodes to a plurality of wiring terminals formed on a substrate, an area on the substrate including the wiring terminals is coated with an anisotropic conductive film. Applying an anisotropic conductive film, and applying a non-conductive insulating resin film to a region on the substrate surrounding the anisotropic conductive film and a region on the anisotropic conductive film. An insulating resin film applying step, and a crimping step of connecting the bump electrode to the wiring terminal via the anisotropic conductive film by heating and pressing the electronic component against the substrate with a tool. Characteristic mounting method. 【請求項２】複数のバンプ電極を有する電子部品を基板
上に形成された複数の配線端子に接続する実装方法にお
いて、前記配線端子上に介挿膜を前記基板上に被着する
介挿膜被着工程と、ツールにより前記電子部品を前記基
板に対して加熱加圧し前記介挿膜を介して前記バンプ電
極を前記配線端子に接続する圧着工程とを具備し、前記
介挿膜は、前記配線端子を包含する前記基板上の領域に
被着される異方性導電部と、前記異方性導電部を囲繞す
る前記基板上の領域に被着され導電性を有しない絶縁性
樹脂部とからなることを特徴とする実装方法。2. A mounting method for connecting an electronic component having a plurality of bump electrodes to a plurality of wiring terminals formed on a substrate, wherein an interposing film is provided on the wiring terminals on the substrate. A bonding step, and a press-bonding step of heating and pressing the electronic component against the substrate by a tool and connecting the bump electrode to the wiring terminal via the insertion film, wherein the insertion film is An anisotropic conductive portion attached to a region on the substrate including a wiring terminal, and an insulating resin portion having no conductivity attached to a region on the substrate surrounding the anisotropic conductive portion; A mounting method characterized by comprising: 【請求項３】複数のバンプ電極を有する電子部品を基板
上に形成された複数の配線端子に接続する実装方法にお
いて、前記配線端子を包含する前記基板上の領域に異方
性導電ペーストを前記基板上に塗布する異方性導電ペー
スト塗布工程と、前記異方性導電ペーストを囲繞する前
記基板上の領域に導電性を有しない絶縁性樹脂ペースト
を被着する絶縁性樹脂ペースト被着工程と、ツールによ
り前記電子部品を前記基板に対して加熱加圧し前記異方
性導電ペーストを介して前記バンプ電極を前記配線端子
に接続する圧着工程とを具備することを特徴とする実装
方法。3. A mounting method for connecting an electronic component having a plurality of bump electrodes to a plurality of wiring terminals formed on a substrate, wherein the anisotropic conductive paste is applied to a region on the substrate including the wiring terminals. Applying an anisotropic conductive paste on a substrate, and applying an insulating resin paste having no conductivity to a region on the substrate surrounding the anisotropic conductive paste; And a pressure bonding step of heating and pressing the electronic component against the substrate with a tool and connecting the bump electrode to the wiring terminal via the anisotropic conductive paste. 【請求項４】複数のバンプ電極を有する電子部品を複数
の配線端子が形成された基板に対してツールにより加熱
加圧し前記バンプ電極を異方性導電膜を介して複数の配
線端子に接続する実装装置において、前記ツールの表面
にはフッ素樹脂からなる薄膜が形成されていることを特
徴とする実装装置。4. An electronic component having a plurality of bump electrodes is heated and pressed by a tool on a substrate on which a plurality of wiring terminals are formed, and the bump electrodes are connected to the plurality of wiring terminals via an anisotropic conductive film. In a mounting apparatus, a thin film made of a fluororesin is formed on a surface of the tool. 【請求項５】バンプ電極を対応する配線端子に電気的に
接続する異方性導電シートにおいて、配線端子を包含す
る領域に被着され且つ前記バンプ電極と前記配線端子と
の間に電気的導通を付与する導電粒子を分散状態にて含
有する異方性導電部と、前記異方性導電部を囲繞する位
置に一体的に延設され前記バンプ電極と前記配線端子と
の間に電気的導通を付与しない絶縁性樹脂部とを具備す
ることを特徴とする異方性導電シート。5. An anisotropic conductive sheet for electrically connecting a bump electrode to a corresponding wiring terminal, wherein said anisotropic conductive sheet is attached to a region including said wiring terminal and is electrically connected between said bump electrode and said wiring terminal. Anisotropic conductive portion containing conductive particles imparting a dispersed state, and electrically extending between the bump electrode and the wiring terminal integrally extended at a position surrounding the anisotropic conductive portion. And an insulating resin portion not provided with an anisotropic conductive sheet. 【請求項６】前記絶縁性樹脂部は、前記導電粒子を含有
しないか、又は、前記異方性導電部よりも含有量が小さ
いことを特徴とする請求項５記載の異方性導電シート。6. The anisotropic conductive sheet according to claim 5, wherein the insulating resin portion does not contain the conductive particles or has a smaller content than the anisotropic conductive portion.
JP9259799A 1997-09-25 1997-09-25 Mounting method and the device and anisotropic conductive sheet Pending JPH1197487A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9259799A JPH1197487A (en) 1997-09-25 1997-09-25 Mounting method and the device and anisotropic conductive sheet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9259799A JPH1197487A (en) 1997-09-25 1997-09-25 Mounting method and the device and anisotropic conductive sheet

Publications (1)

Publication Number Publication Date
JPH1197487A true JPH1197487A (en) 1999-04-09

Family

ID=17339168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9259799A Pending JPH1197487A (en) 1997-09-25 1997-09-25 Mounting method and the device and anisotropic conductive sheet

Country Status (1)

Country Link
JP (1) JPH1197487A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100441578B1 (en) * 2001-07-24 2004-07-23 제이에스알 가부시끼가이샤 Anisotropically Conductive Sheet and Connector
EP1076360A3 (en) * 1999-08-09 2005-02-02 Sony Chemicals Corporation Process for mounting semiconductor device and mounting apparatus
JP2007094412A (en) * 2005-09-27 2007-04-12 Samsung Sdi Co Ltd Plasma display device
JP2010239153A (en) * 2010-06-24 2010-10-21 Sony Chemical & Information Device Corp Method of manufacturing semiconductor device
JP2017107926A (en) * 2015-12-08 2017-06-15 株式会社新川 Electronic component mounting device
WO2021177409A1 (en) * 2020-03-04 2021-09-10 Tdk株式会社 Element array pressurizing device, manufacturing device, and manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1076360A3 (en) * 1999-08-09 2005-02-02 Sony Chemicals Corporation Process for mounting semiconductor device and mounting apparatus
KR100441578B1 (en) * 2001-07-24 2004-07-23 제이에스알 가부시끼가이샤 Anisotropically Conductive Sheet and Connector
JP2007094412A (en) * 2005-09-27 2007-04-12 Samsung Sdi Co Ltd Plasma display device
JP2010239153A (en) * 2010-06-24 2010-10-21 Sony Chemical & Information Device Corp Method of manufacturing semiconductor device
JP2017107926A (en) * 2015-12-08 2017-06-15 株式会社新川 Electronic component mounting device
WO2021177409A1 (en) * 2020-03-04 2021-09-10 Tdk株式会社 Element array pressurizing device, manufacturing device, and manufacturing method

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