JPH1167959A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1167959A JPH1167959A JP22365597A JP22365597A JPH1167959A JP H1167959 A JPH1167959 A JP H1167959A JP 22365597 A JP22365597 A JP 22365597A JP 22365597 A JP22365597 A JP 22365597A JP H1167959 A JPH1167959 A JP H1167959A
- Authority
- JP
- Japan
- Prior art keywords
- metal plate
- board
- mounting
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、表面実装型で外部
端子となる半田ボールを格子状に配列するＢＧＡ（ＢＡ
ＬＬ ＧＲＩＤ ＡＲＲＡＹ）タイプの半導体装置に関
し、特に樹脂材料からなる基板の外部端子取り付け面に
於ける構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BGA (BA
More particularly, the present invention relates to a structure of an external terminal mounting surface of a substrate made of a resin material.
【０００２】[0002]
【従来の技術】図５は、従来のプラスティックＢＧＡ型
半導体装置を示す断面図である。プリント基板２の表面
に半導体素子１がマウント材３により搭載され、ボンデ
ィングワイヤー４にてプリント基板２上の導電配線６と
電気接続された後、封止樹脂５にて封止される。プリン
ト基板２の裏面には半田ボールからなる外部端子９が取
付けられている。また、プリント基板２にはスルーホー
ルが設けてあり、特に放熱効果を持つサーマルピア７が
プリント基板２の半導体素子搭載部に設けられており、
半導体素子１の発熱、または接地電位を基板の裏面側の
外部端子９に伝える役目をしている。前記スルーホール
はφ０．３ｍｍの貫通孔であり、壁面には銅メッキが施
されているが、場合によっては絶縁、導電性樹脂または
金属を充填することもある。2. Description of the Related Art FIG. 5 is a sectional view showing a conventional plastic BGA type semiconductor device. The semiconductor element 1 is mounted on the surface of the printed board 2 by the mounting material 3, electrically connected to the conductive wiring 6 on the printed board 2 by the bonding wire 4, and then sealed by the sealing resin 5. External terminals 9 made of solder balls are attached to the back surface of the printed circuit board 2. Further, a through hole is provided in the printed circuit board 2, and a thermal pier 7 having a heat radiation effect is provided in a semiconductor element mounting portion of the printed circuit board 2,
It serves to transmit the heat generated by the semiconductor element 1 or the ground potential to the external terminals 9 on the back surface side of the substrate. The through hole is a through hole having a diameter of 0.3 mm, and the wall surface is plated with copper. In some cases, the through hole may be filled with an insulating material, a conductive resin, or a metal.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、図５に
示す半導体装置は、実装時のＩＲリフローでクラックを
起こす不具合（ポップコーンクラック）があった。これ
は、半導体装置の構成材料が有機材料であるため、吸湿
した水分がリフロー時の加熱により急激に気化膨張し、
プリント基板２と半導体素子１との間で剥離を引き起こ
し、クラックに至るためである。However, the semiconductor device shown in FIG. 5 has a defect (popcorn crack) that causes a crack due to IR reflow during mounting. This is because the constituent material of the semiconductor device is an organic material, so that the absorbed moisture rapidly evaporates and expands due to heating during reflow,
This is because peeling is caused between the printed circuit board 2 and the semiconductor element 1 and leads to cracks.
【０００４】図５に示す従来の半導体装置の吸湿経路
は、プリント基板２の裏面からの水分浸透が支配的と考
えられており、特にスルーホールは水分の浸透が最も多
いと考えられている。このスルーホールには、樹脂、ま
たは金属を充填するものもあるが、ポップコーンを十分
に回避するほど水分浸透を防ぐには至っておらず、信頼
性、コスト、作業性の面も含めて、根本的な解決策が開
発されていない。It is considered that the moisture absorption path of the conventional semiconductor device shown in FIG. 5 is dominated by moisture permeation from the back surface of the printed circuit board 2, and in particular, it is considered that moisture permeates the through holes most. Some of these through-holes are filled with resin or metal, but they do not prevent moisture penetration enough to avoid popcorn, and fundamentally include reliability, cost, and workability. No solution has been developed.
【０００５】また、スルーホールの中でも、特に半導体
素子搭載部に当たる箇所に設けたものを放熱効果の役目
からサーマルピアと呼ぶ。プリント基板２は熱伝導性が
悪く、半導体素子１の発熱を基板裏面の外部端子９に伝
えるためには、このスルーホール内の銅配線を経由して
熱伝導させる。[0005] Among the through holes, a through hole provided particularly at a portion corresponding to a semiconductor element mounting portion is referred to as a thermal pier because of a heat radiation effect. The printed circuit board 2 has poor thermal conductivity. In order to transmit the heat generated by the semiconductor element 1 to the external terminals 9 on the back surface of the printed circuit board, the printed circuit board 2 conducts heat via the copper wiring in the through hole.
【０００６】しかし、プリント基板２が厚くなると、放
熱性は悪くなり、その効果も低下してくる。放熱性に関
しては、プリント基板２の板厚の薄い方が好ましいが、
半導体装置の強度確保、反り防止、加えて水分の吸湿低
減の観点からは、プリント基板２の板厚は厚い方が好ま
しい。したがって、この相反する効果を回避するために
は、プリント基板２の裏面からの吸湿が低く、かつ放熱
性の高い半導体装置が必要となる。However, when the thickness of the printed circuit board 2 is increased, the heat radiation becomes worse, and its effect is reduced. Regarding the heat radiation, the smaller the thickness of the printed circuit board 2 is, the better.
From the viewpoint of securing the strength of the semiconductor device, preventing warpage, and reducing the absorption of moisture, it is preferable that the thickness of the printed circuit board 2 be large. Therefore, in order to avoid this conflicting effect, a semiconductor device that has low moisture absorption from the back surface of the printed circuit board 2 and high heat dissipation is required.
【０００７】本発明の目的は、基板裏面からの水分の吸
湿を防止し、かつ、実装時の半田リフロー加熱による基
板剥離、クラックを防止した半導体装置を提供すること
にある。An object of the present invention is to provide a semiconductor device which prevents moisture absorption from the back surface of a substrate and prevents peeling and cracking of the substrate due to solder reflow heating during mounting.
【０００８】[0008]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置は、半導体素子を基板に搭
載し、該素子を基板の導体配線と電気的に接続し、かつ
基板の外部端子に電気的に接続した半導体装置におい
て、前記基板の外部端子取付け面を金属板にて被覆した
ものである。In order to achieve the above object, a semiconductor device according to the present invention has a semiconductor element mounted on a substrate, the element electrically connected to conductor wiring on the substrate, and an external part of the substrate. In a semiconductor device electrically connected to terminals, an external terminal mounting surface of the substrate is covered with a metal plate.
【０００９】また、前記金属板は、少なくとも半導体素
子搭載部に対応する範囲、或いは外部端子の取付位置よ
り内周側に配置されたものである。Further, the metal plate is arranged at least in a range corresponding to the semiconductor element mounting portion or on the inner peripheral side with respect to the mounting position of the external terminal.
【００１０】また、前記金属板は、前記基板に設けたス
ルーホールの少なくとも一部を覆うように取り付けられ
たものである。Further, the metal plate is attached so as to cover at least a part of a through hole provided in the substrate.
【００１１】また、前記金属板は、前記基板に設けた開
口の底部を覆うように取り付けられ、半導体素子を搭載
するキャビティを前記基板に形成したものである。The metal plate is mounted so as to cover a bottom of an opening provided in the substrate, and a cavity for mounting a semiconductor element is formed in the substrate.
【００１２】また、前記金属板の高さは、前記外部端子
の高さより０．３ｍｍ以下に設定したものである。Further, the height of the metal plate is set to be 0.3 mm or less than the height of the external terminal.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１４】（実施形態１）図１は、本発明の実施形態
１に係る半導体装置を示す断面図である。なお、図１に
おいて、図４の従来例と同一の構成要素には同一の符号
を付してある。Embodiment 1 FIG. 1 is a sectional view showing a semiconductor device according to Embodiment 1 of the present invention. In FIG. 1, the same components as those in the conventional example of FIG. 4 are denoted by the same reference numerals.
【００１５】図１において、本発明の実施形態１に係る
半導体装置は、プリント基板２の一主面に半導体素子１
をマウント材３により搭載し、ボンディングワイヤー４
でプリント基板２上の導電配線６と電気接続した後に封
止樹脂５にて封止してある。また、封止樹脂から露出し
たプリント基板２の裏面には、半田ボールからなる外部
端子９を取り付けている。In FIG. 1, a semiconductor device according to a first embodiment of the present invention has a semiconductor element 1 on one main surface of a printed circuit board 2.
Is mounted by a mounting material 3 and a bonding wire 4
Then, after electrically connecting to the conductive wiring 6 on the printed circuit board 2, it is sealed with the sealing resin 5. External terminals 9 made of solder balls are attached to the back surface of the printed circuit board 2 exposed from the sealing resin.
【００１６】さらに、プリント基板２の半導体素子搭載
部から基板裏面に貫通するサーマルピア７を設けてお
り、半導体素子１からの熱をサーマルピア７を通して基
板裏面側に伝熱して放熱するようになっている。Further, a thermal pier 7 penetrating from the semiconductor element mounting portion of the printed circuit board 2 to the rear surface of the substrate is provided, and heat from the semiconductor element 1 is transferred to the rear surface of the substrate through the thermal pier 7 and radiated. ing.
【００１７】また外部端子９は、プリント基板２の裏面
周辺部にのみ格子状に配置されており、外部端子９より
内側のプリント基板２の裏面には、半導体素子搭載部に
対応して金属板８を取付けている。金属板８は、アルミ
ニウム等に黒化処理、または電極酸化等により酸化膜を
施す、或いはニッケル、金等のメッキを施しても良い。
また、金属板８のプリント基板２への取付けは、ソルダ
ーレジスト等の絶縁樹脂、金属フィラー入り導電性樹
脂、または低融点半田を用いて行うが、これらは、金属
板８の外装処理に応じて適宜選択される。The external terminals 9 are arranged in a lattice only on the periphery of the rear surface of the printed circuit board 2, and on the rear surface of the printed circuit board 2 inside the external terminals 9, a metal plate corresponding to the semiconductor element mounting portion is provided. 8 is attached. The metal plate 8 may be formed by subjecting aluminum or the like to a blackening treatment, applying an oxide film by electrode oxidation or the like, or plating a metal such as nickel or gold.
The metal plate 8 is attached to the printed circuit board 2 using an insulating resin such as a solder resist, a conductive resin containing a metal filler, or a low-melting-point solder. It is appropriately selected.
【００１８】本発明の実施形態１では、プリント基板２
の裏面を金属板８により覆ったため、プリント基板２へ
の水分の吸湿を防止することができる。In the first embodiment of the present invention, the printed circuit board 2
Is covered with the metal plate 8, it is possible to prevent the printed circuit board 2 from absorbing moisture.
【００１９】さらに、金属板８には、選択的に半田ボー
ル９1を取付けても良く、半田ボール９1を取付けること
によって、金属板８を通した放熱、または接地電位の強
化を行うことができる。Furthermore, the metal plate 8 may be attached selectively solder balls 9 1, by mounting the solder balls 9 1, is possible to enhance the heat radiation, or ground potential through the metal plate 8 it can.
【００２０】（実施形態２）図２は、本発明の実施形態
２を示す断面図である。(Embodiment 2) FIG. 2 is a sectional view showing Embodiment 2 of the present invention.
【００２１】図２に示す本発明の実施形態２では、金属
板８の板厚を半田ボール９の直径とほぼ等しくなるよう
に厚くしたことを特徴とするものである。金属板８と半
田ボール９との高差は０．３ｍｍ以下が好ましい。それ
は、実装後の半田ボール９のつぶれ高さが低くなるた
め、その低くなる高さ分を予め金属板８を低く見積もっ
ている。その他の構成は、実施形態１と同じである。The second embodiment of the present invention shown in FIG. 2 is characterized in that the thickness of the metal plate 8 is increased to be substantially equal to the diameter of the solder ball 9. The height difference between the metal plate 8 and the solder balls 9 is preferably 0.3 mm or less. Since the crushing height of the solder ball 9 after mounting is reduced, the height of the metal plate 8 is preliminarily estimated lower by the reduced height. Other configurations are the same as in the first embodiment.
【００２２】これは、金属板８を直接半田付けすること
を可能にせしめるためで、実装後は金属板８がスタンド
オフ値になり、実装後の半田ボール９の高さは金属板８
と等しくなるように設定するのが好ましい。This is to enable the metal plate 8 to be directly soldered. After mounting, the metal plate 8 has a stand-off value, and the height of the solder ball 9 after mounting is
It is preferable to set them so as to be equal to
【００２３】（実施形態３）図３は、本発明の実施形態
３を示す断面図である。(Embodiment 3) FIG. 3 is a sectional view showing Embodiment 3 of the present invention.
【００２４】図３に示す本発明の実施形態３では、プリ
ント基板２に半導体素子１を搭載する貫通口を設け、基
板裏面の外部端子取付け面に金属板８を取り付け、金属
板８で貫通口を閉塞してプリント基板２の中央部にキャ
ビティ１０を形成し、キャビティ１０内に半導体素子１
を収容するようになっている。また、金属板８は、外部
端子９より内側に位置している。その他の構成は、実施
形態１と同じである。In the third embodiment of the present invention shown in FIG. 3, a through hole for mounting the semiconductor element 1 is provided on the printed circuit board 2, a metal plate 8 is mounted on the external terminal mounting surface on the back surface of the substrate, Is closed to form a cavity 10 in the center of the printed circuit board 2, and the semiconductor element 1 is
Is to be accommodated. The metal plate 8 is located inside the external terminal 9. Other configurations are the same as in the first embodiment.
【００２５】本発明の実施形態３によれば、半導体素子
１は、キャビティ１０内に収容されて直接金属板８に搭
載可能なため、熱伝導の悪いプリント基板２を介さず
に、半導体素子１の熱を金属板８から放熱することによ
り、放熱性を飛躍的に向上させることができる。さら
に、半導体素子１を基板２のキャビティ１０内に収納す
ることができるため、半導体装置本体の高さを基板の厚
さ分だけ縮小することができる。According to the third embodiment of the present invention, since the semiconductor element 1 can be housed in the cavity 10 and directly mounted on the metal plate 8, the semiconductor element 1 can be mounted without the interposition of the printed circuit board 2 having poor heat conductivity. By dissipating this heat from the metal plate 8, the heat radiation can be dramatically improved. Further, since the semiconductor element 1 can be accommodated in the cavity 10 of the substrate 2, the height of the semiconductor device main body can be reduced by the thickness of the substrate.
【００２６】（実施形態４）図４は、本発明の実施形態
４に係る半導体装置を示す断面図である。実施形態４で
は、プリント基板２１の裏面全体に拡大して金属板８を
取り付けている。金属板８には、周辺部に開口１１を設
け、開口１１内に外部端子９を収容して基板裏面に電気
接続している。その他の構成は、実施形態１と同じであ
る。(Embodiment 4) FIG. 4 is a sectional view showing a semiconductor device according to Embodiment 4 of the present invention. In the fourth embodiment, the metal plate 8 is attached to the entire back surface of the printed circuit board 21 in an enlarged manner. An opening 11 is provided in the peripheral portion of the metal plate 8, and the external terminal 9 is accommodated in the opening 11, and is electrically connected to the back surface of the substrate. Other configurations are the same as in the first embodiment.
【００２７】本実施形態４によれば、基板裏面の露出部
分を極力ゼロに近付けられるため、基板裏面からの吸湿
を最小限に押さえることができる。金属板８に酸化膜等
の絶縁被膜をしておけば、外部端子９，９間の短絡を防
止することができる。また、基板２と金属板８の取付け
に当たって、金属板８をフレーム状に連結しておくと良
く、基板２と金属板８の両者がフレーム状であれば、金
属板８の基板２への取付けが容易で、取付けの精度、工
数の低減が可能となる。According to the fourth embodiment, the exposed portion on the back surface of the substrate can be made as close to zero as possible, so that the absorption of moisture from the back surface of the substrate can be minimized. If an insulating film such as an oxide film is formed on the metal plate 8, a short circuit between the external terminals 9, 9 can be prevented. In attaching the substrate 2 and the metal plate 8, the metal plate 8 is preferably connected in a frame shape. If both the substrate 2 and the metal plate 8 are in a frame shape, the metal plate 8 is attached to the substrate 2. , And the mounting accuracy and man-hours can be reduced.
【００２８】なお、本発明の実施形態は、ＢＧＡ構造の
ものを対象として説明したが、リード付き当てタイプの
バットリード（ＢＵＴＴ ＬＥＡＤ）ＰＧＡタイプにも
同様に適用することができる。Although the embodiment of the present invention has been described for the case of the BGA structure, the present invention can be similarly applied to a butt lead (BUTT LEAD) PGA type with a lead type.
【００２９】[0029]
【発明の効果】以上説明したように本発明によれば、プ
リント基板の裏面を金属板で被覆することにより、水分
の吸湿を防止して、実装時のリフロークラックを最小限
に押さえることができる。実験の結果、実装前の放置時
間を２倍以上に延長することができた。As described above, according to the present invention, by covering the back surface of the printed circuit board with the metal plate, it is possible to prevent moisture absorption and to minimize reflow cracks during mounting. . As a result of the experiment, the standing time before mounting was able to be extended more than twice.
【００３０】さらに、プリント基板の裏面に金属板が設
けられているため、半導体素子の放熱性を２割以上向上
させることができ、しかも直接金属板に半導体素子をマ
ウントし、実装基板に半田付けした場合には、半導体素
子の放熱性を５割以上も向上させることができる。Further, since the metal plate is provided on the back surface of the printed circuit board, the heat dissipation of the semiconductor element can be improved by 20% or more, and the semiconductor element is directly mounted on the metal plate and soldered to the mounting board. In this case, the heat dissipation of the semiconductor element can be improved by 50% or more.
【図１】本発明の実施形態１を示す断面図である。FIG. 1 is a sectional view showing Embodiment 1 of the present invention.
【図２】本発明の実施形態２を示す断面図である。FIG. 2 is a sectional view showing Embodiment 2 of the present invention.
【図３】本発明の実施形態３を示す断面図である。FIG. 3 is a sectional view showing Embodiment 3 of the present invention.
【図４】本発明の実施形態４を示す断面図である。FIG. 4 is a sectional view showing a fourth embodiment of the present invention.
【図５】従来例を示す断面図である。FIG. 5 is a sectional view showing a conventional example.
１ 半導体素子 ２ プリント基板 ３ マウント材 ４ ボンディングワイヤ ５ 封止樹脂 ６ 導電配線 ７ サーマルピア ８、金属板 ９ 外部端子 １０ キャビティ １１ 開口 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Printed circuit board 3 Mounting material 4 Bonding wire 5 Sealing resin 6 Conductive wiring 7 Thermal pier 8, Metal plate 9 External terminal 10 Cavity 11 Opening
Claims (5)
板の導体配線と電気的に接続し、かつ基板の外部端子に
電気的に接続した半導体装置において、 前記基板の外部端子取付け面を金属板にて被覆したもの
であることを特徴とする半導体装置。1. A semiconductor device having a semiconductor element mounted on a substrate, electrically connecting the element to conductor wiring of the substrate, and electrically connecting to an external terminal of the substrate. A semiconductor device characterized by being covered with a metal plate.
載部に対応する範囲、或いは外部端子の取付位置より内
周側に配置されたものであることを特徴とする請求項１
に記載の半導体装置。2. The metal plate according to claim 1, wherein the metal plate is arranged at least in a range corresponding to a semiconductor element mounting portion or on an inner peripheral side with respect to a mounting position of an external terminal.
3. The semiconductor device according to claim 1.
ホールの少なくとも一部を覆うように取り付けられたも
のであることを特徴とする請求項２に記載の半導体装
置。3. The semiconductor device according to claim 2, wherein the metal plate is attached so as to cover at least a part of a through hole provided in the substrate.
底部を覆うように取り付けられ、半導体素子を搭載する
キャビティを前記基板に形成したものであることを特徴
とする請求項１叉は２に記載の半導体装置。4. The substrate according to claim 1, wherein the metal plate is attached so as to cover a bottom of an opening provided in the substrate, and a cavity for mounting a semiconductor element is formed in the substrate. 3. The semiconductor device according to 2.
さより０．３ｍｍ以下に設定したものであることを特徴
とする請求項２、３叉は４に記載の半導体装置。5. The semiconductor device according to claim 2, wherein a height of said metal plate is set to be 0.3 mm or less than a height of said external terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22365597A JPH1167959A (en) | 1997-08-20 | 1997-08-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22365597A JPH1167959A (en) | 1997-08-20 | 1997-08-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1167959A true JPH1167959A (en) | 1999-03-09 |
Family
ID=16801593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22365597A Pending JPH1167959A (en) | 1997-08-20 | 1997-08-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1167959A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11140280A (en) * | 1997-11-11 | 1999-05-25 | Ngk Spark Plug Co Ltd | Paste for filling through hole and printed circuit board using the same |
| JPH11199759A (en) * | 1997-11-11 | 1999-07-27 | Ngk Spark Plug Co Ltd | Hole-filling material for printed circuit board and printed circuit board prepared by using same |
| WO2001015237A1 (en) * | 1999-08-20 | 2001-03-01 | Amkor Technology, Inc. | Chip-sized optical sensor package |
| JP2003309483A (en) * | 2002-04-16 | 2003-10-31 | Mitsubishi Electric Corp | High frequency module, active phased array antenna and communication equipment |
| JP2005500685A (en) * | 2001-08-14 | 2005-01-06 | スカイワークス ソリューションズ，インコーポレイテッド | Structure of leadless chip carrier with embedded inductor and method for its fabrication |
| US6962829B2 (en) | 1996-10-31 | 2005-11-08 | Amkor Technology, Inc. | Method of making near chip size integrated circuit package |
| JP2006524904A (en) * | 2003-02-10 | 2006-11-02 | スカイワークス ソリューションズ，インコーポレイテッド | Semiconductor die package with reduced inductance and reduced die adhesive flow |
| JP2016178221A (en) * | 2015-03-20 | 2016-10-06 | 三菱電機株式会社 | Microwave device |
| WO2021009920A1 (en) * | 2019-07-18 | 2021-01-21 | ウルトラメモリ株式会社 | Semiconductor module, method for manufacturing same, and semiconductor module mounting body |
-
1997
- 1997-08-20 JP JP22365597A patent/JPH1167959A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6962829B2 (en) | 1996-10-31 | 2005-11-08 | Amkor Technology, Inc. | Method of making near chip size integrated circuit package |
| JPH11140280A (en) * | 1997-11-11 | 1999-05-25 | Ngk Spark Plug Co Ltd | Paste for filling through hole and printed circuit board using the same |
| JPH11199759A (en) * | 1997-11-11 | 1999-07-27 | Ngk Spark Plug Co Ltd | Hole-filling material for printed circuit board and printed circuit board prepared by using same |
| WO2001015237A1 (en) * | 1999-08-20 | 2001-03-01 | Amkor Technology, Inc. | Chip-sized optical sensor package |
| JP2005500685A (en) * | 2001-08-14 | 2005-01-06 | スカイワークス ソリューションズ，インコーポレイテッド | Structure of leadless chip carrier with embedded inductor and method for its fabrication |
| JP2003309483A (en) * | 2002-04-16 | 2003-10-31 | Mitsubishi Electric Corp | High frequency module, active phased array antenna and communication equipment |
| JP2006524904A (en) * | 2003-02-10 | 2006-11-02 | スカイワークス ソリューションズ，インコーポレイテッド | Semiconductor die package with reduced inductance and reduced die adhesive flow |
| JP2010192925A (en) * | 2003-02-10 | 2010-09-02 | Skyworks Solutions Inc | Semiconductor die package with reduced inductance and reduced die attach flow out |
| JP2016178221A (en) * | 2015-03-20 | 2016-10-06 | 三菱電機株式会社 | Microwave device |
| WO2021009920A1 (en) * | 2019-07-18 | 2021-01-21 | ウルトラメモリ株式会社 | Semiconductor module, method for manufacturing same, and semiconductor module mounting body |
| JPWO2021009920A1 (en) * | 2019-07-18 | 2021-01-21 |
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