JPH1154673A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH1154673A
JPH1154673A JP9205561A JP20556197A JPH1154673A JP H1154673 A JPH1154673 A JP H1154673A JP 9205561 A JP9205561 A JP 9205561A JP 20556197 A JP20556197 A JP 20556197A JP H1154673 A JPH1154673 A JP H1154673A
Authority
JP
Japan
Prior art keywords
semiconductor device
connection member
adhesive
semiconductor
semiconductor pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9205561A
Other languages
Japanese (ja)
Inventor
Jiichi Hino
滋一 樋野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP9205561A priority Critical patent/JPH1154673A/en
Publication of JPH1154673A publication Critical patent/JPH1154673A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor device of flip chip structure which is thin, small-sized and capable of large power operation, by connecting a rear electrode through which a main current of a power transistor pellet flows with a wiring board, by using a thermoelectric connection member of low resistance which is free from self heat generation and excellent in thermal conduction. SOLUTION: Bump electrodes 3 and a rear electrode 1a are formed on both surfaces of a semiconductor pellet 1. Fine pad electrodes 7 and a large diameter pad electrode 15 to which a main current is supplied are formed on a wiring board 4. In this device, the bump electrodes 3 and the fine pad electrodes 7 are overlapped and made to face each other. Overlapping parts of the respective electrodes are electrically connected. The rear electrode 1a and the large diameter pad electrode 15 are connected with a thermoelectric connection member 16 having thermally and electrically excellent conductivity, via adhesive materials 17, 18 having thermally and electrically excellent conductivity.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明はフリップチップ構造
の半導体装置に関し、特に大電流動作する半導体ペレッ
トを具えた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a flip-chip structure, and more particularly, to a semiconductor device having a semiconductor pellet operating with a large current.

【０００２】[0002]

【従来の技術】電子回路装置は、配線基板に小型の電子
部品を高密度実装し、装置の小型化と高機能、高性能化
を実現している。この小型の電子部品の一例を図６から
説明する。図において、１は半導体ペレットで、内部に
多数の半導体素子（図示せず）を形成した半導体基板２
の一主面に多数のバンプ電極３を形成している。４は配
線基板で、樹脂やセラミクスなどの絶縁部材よりなる絶
縁基板５に導電パターン６を形成し、この導電パターン
６の一部で半導体ペレット１のバンプ電極３と対向する
部分にパッド電極７を形成している。この半導体ペレッ
ト１と配線基板４とはバンプ電極３とパッド電極７とが
重合するように対向配置され、各電極３、７は熱圧着や
溶融接続により電気的に接続される。８は半導体ペレッ
ト１と配線基板４とを機械的に接続し半導体ペレット１
表面の配線パターン（図示せず）を外部の腐食性ガスか
ら保護する接着用樹脂を示す。この種半導体装置は、半
導体ペレット１として高密度集積されたものを用いるこ
とにより、小型で薄い電子部品を実現できる。またこの
種半導体装置は、半導体ペレット１としてマイクロプロ
セッサを用い、配線基板４の図外領域に、メモリや入出
力インターフェースなどの周辺電子部品をマウントする
ことにより、配線基板４の単位で電子回路装置を構成す
ることもできる。ところで、半導体ペレット１は小信号
用のものでは、図示例のように一主面にバンプ電極３を
集中させることができる。一方、大電流を取り扱う半導
体ペレットでは、微小なバンプ電極に大電流が集中する
と電極部分や電極の重合部を損傷するため、複数のバン
プ電極を並列接続して電流を分散させ電流容量を増大さ
せている。また、電力用のトランジスタやＦＥＴなどを
含み、両面に主電流が流れる電極を形成した半導体ペレ
ットでは、バンプ電極側の主電流電極とともに他の面
（裏面）の主電流電極を、それぞれ配線基板の導電パタ
ーンに接続する必要がある。そのため裏面電極と配線基
板とをワイヤボンディングすることが考えられるが、ワ
イヤによる接続はワイヤの立ち上がり部分の高さ分だけ
半導体装置の厚さが厚くなり、小型化、薄型化の目的に
反する。このような問題を解決するものとして、特表平
７−５０３５７９号公報には図７に示すように、半導体
ペレット１にスパッタ金属フィルム９を、その導電面の
中央部を半導体ペレット１の裏面電極１ａに当接させ、
周縁部を配線基板４上の導電パターン１０に当接させ
て、それぞれの当接面を電気的に接続した構造の半導体
装置が開示されている。また、米国特許第５、５８６、
０１０号明細書には、図８に示すように矩形穴１１ａを
有する絶縁基板１１の一方の面に導電層１２を形成し、
この導電層１２を矩形穴１１ａ部分で中央部が平坦なド
ーム状に成形して、このドーム状成形部１２ａに肉厚の
支持部材１３を固定し、さらにこの支持部材１３に半導
体ペレット１４を固定した構造の半導体装置が開示され
ている。上記図７半導体装置は半導体ペレット１の裏面
電極１ａを配線基板４に電気的に接続し、図８半導体装
置はバンプ電極を有する半導体ペレットではないが、半
導体ペレット１４が発生する熱を支持部材１３と導電層
１２に伝達し、さらに導電層１２から絶縁基板１１に伝
達して、半導体ペレット１４を冷却するものである。こ
れらはいずれも、半導体ペレット１、１４の裏面電極を
配線基板４、１１に接続することができ、薄型の半導体
装置に好適である。2. Description of the Related Art In an electronic circuit device, small electronic components are mounted on a wiring board at a high density, thereby realizing the miniaturization, high function and high performance of the device. An example of this small electronic component will be described with reference to FIG. In the drawing, reference numeral 1 denotes a semiconductor pellet, and a semiconductor substrate 2 having a number of semiconductor elements (not shown) formed therein.
A large number of bump electrodes 3 are formed on one main surface of the substrate. Reference numeral 4 denotes a wiring board, on which an electrically conductive pattern 6 is formed on an insulating substrate 5 made of an insulating material such as resin or ceramics, and a pad electrode 7 is formed on a part of the electrically conductive pattern 6 which faces the bump electrode 3 of the semiconductor pellet 1. Has formed. The semiconductor pellet 1 and the wiring board 4 are arranged to face each other such that the bump electrode 3 and the pad electrode 7 overlap, and the electrodes 3 and 7 are electrically connected by thermocompression bonding or fusion connection. Reference numeral 8 denotes a semiconductor pellet 1 which mechanically connects the semiconductor pellet 1 and the wiring board 4 to each other.
4 shows an adhesive resin for protecting a surface wiring pattern (not shown) from an external corrosive gas. This type of semiconductor device can realize a small and thin electronic component by using a high-density integrated semiconductor pellet 1. In addition, this type of semiconductor device uses a microprocessor as the semiconductor pellet 1 and mounts peripheral electronic components such as a memory and an input / output interface in a non-illustrated area of the wiring board 4 so that the electronic circuit device can be mounted in units of the wiring board 4. Can also be configured. By the way, if the semiconductor pellet 1 is for a small signal, the bump electrodes 3 can be concentrated on one main surface as shown in the example in the figure. On the other hand, in a semiconductor pellet that handles a large current, if a large current is concentrated on a minute bump electrode, the electrode portion and the overlapping portion of the electrode will be damaged.Therefore, multiple bump electrodes are connected in parallel to distribute the current and increase the current capacity. ing. In the case of a semiconductor pellet including a power transistor and an FET, and having an electrode through which a main current flows on both surfaces, the main current electrode on the other surface (back surface) is used together with the main current electrode on the bump electrode side. It is necessary to connect to the conductive pattern. For this reason, wire bonding between the back electrode and the wiring board is conceivable. However, the connection by the wire increases the thickness of the semiconductor device by the height of the rising portion of the wire, which is contrary to the purpose of miniaturization and thinning. To solve such a problem, Japanese Patent Publication No. 7-503579 discloses a sputtered metal film 9 on a semiconductor pellet 1 and a central portion of a conductive surface of the semiconductor pellet 1 as shown in FIG. 1a
A semiconductor device having a structure in which a peripheral portion is in contact with a conductive pattern 10 on a wiring board 4 and respective contact surfaces are electrically connected is disclosed. Also, US Pat. No. 5,586,
No. 010, a conductive layer 12 is formed on one surface of an insulating substrate 11 having a rectangular hole 11a as shown in FIG.
The conductive layer 12 is formed into a dome shape having a flat central portion at the rectangular hole 11a, a thick supporting member 13 is fixed to the dome-shaped formed portion 12a, and a semiconductor pellet 14 is further fixed to the supporting member 13. A semiconductor device having the above structure is disclosed. The semiconductor device shown in FIG. 7 electrically connects the back electrode 1a of the semiconductor pellet 1 to the wiring substrate 4, and the semiconductor device shown in FIG. 8 is not a semiconductor pellet having a bump electrode. Is transmitted to the conductive layer 12 and further from the conductive layer 12 to the insulating substrate 11 to cool the semiconductor pellet 14. In any of these, the back electrodes of the semiconductor pellets 1 and 14 can be connected to the wiring substrates 4 and 11 and are suitable for thin semiconductor devices.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、図７、
図８に示す半導体装置はいずれも、熱および電流の通過
断面積が極めて小さい導電膜によって半導体ペレットの
裏面電極と配線基板との間の接続が行われるため、熱伝
導量が小さく、放熱性が実質的に支持部材１３で決定さ
れ、導電膜の許容電流で半導体装置の動作電流が制限さ
れるという問題があった。即ち、半導体ペレットは動作
開始すると室温状態から温度上昇し、この半導体ペレッ
トと熱的に密着した導電膜の電気抵抗も温度上昇ととも
に増大する。導電膜材料が例えば銅の場合、その電気抵
抗は２０℃で１．７２Ω・ｍであるのに対し、１００℃
では２．２８Ω・ｍとなり３３％増大し、自己発熱量も
増大して周囲温度より高くなり半導体ペレットからの熱
の流入を阻止し、熱的、電気的抵抗が増大するため半導
体ペレットからの電流が低下し出力が低下する。そのた
め、図７、図８に示す構造の半導体は大電流で連続的に
動作するモータなどの駆動制御用半導体装置には適用し
にくく、適用するとしてもブロアなどの冷却手段が必要
で装置全体の小型化は困難であった。However, FIG.
In each of the semiconductor devices shown in FIG. 8, since the connection between the back electrode of the semiconductor pellet and the wiring board is made by a conductive film having an extremely small heat and current passing cross-sectional area, the amount of heat conduction is small and the heat dissipation is low. There is a problem that the operating current of the semiconductor device is substantially determined by the support member 13 and is limited by the allowable current of the conductive film. That is, when the semiconductor pellet starts operating, the temperature rises from the room temperature state, and the electrical resistance of the conductive film that is in thermal contact with the semiconductor pellet also increases with the temperature rise. When the conductive film material is, for example, copper, its electric resistance is 1.72 Ω · m at 20 ° C., whereas it is 100 ° C.
In this case, 2.28 Ω · m, an increase of 33%, the self-heating value also increases, the temperature becomes higher than the ambient temperature, the flow of heat from the semiconductor pellet is prevented, and the thermal and electrical resistance increases. And the output decreases. Therefore, the semiconductor having the structure shown in FIGS. 7 and 8 is difficult to be applied to a drive control semiconductor device such as a motor which operates continuously with a large current, and even if it is applied, a cooling means such as a blower is required, and Miniaturization was difficult.

【０００４】[0004]

【課題を解決するための手段】本発明は上記課題の解決
を目的として提案されたもので、一方の面にバンプ電極
を他の面に裏面電極をそれぞれ形成した半導体ペレット
を、微小パッド電極と径大パッド電極とをそれぞれ形成
した配線基板に、バンプ電極と微小パッド電極とを重合
させて対向させ各電極の重合部を電気的に接続するとと
もに、半導体ペレットの他の面に形成した裏面電極と径
大パッド電極間を、熱的、電気的に良好な伝導性を有す
る接着材を介して熱的、電気的に良好な伝導性を有する
熱電気接続部材に接続したことを特徴とする半導体装置
を提供する。SUMMARY OF THE INVENTION The present invention has been proposed for the purpose of solving the above-mentioned problems. A semiconductor pellet having a bump electrode formed on one surface and a back electrode formed on the other surface is formed with a fine pad electrode. A bump electrode and a micro pad electrode are superimposed on a wiring board on which a large-diameter pad electrode is formed, respectively, and the superposed portions of the electrodes are electrically connected to each other, and a back electrode formed on the other surface of the semiconductor pellet. A semiconductor connected to the thermoelectric connection member having good thermal and electrical conductivity through an adhesive having good thermal and electrical conductivity. Provide equipment.

【０００５】[0005]

【発明の実施の形態】本発明による半導体装置は、半導
体ペレットの裏面電極と径大パッド電極間を、熱的、電
気的に良好な伝導性を有する接着材を介して熱的、電気
的に良好な伝導性を有する熱電気接続部材に接続したこ
とを特徴とするが、熱電気接続部材の半導体ペレットと
接続される部分に接着材の厚みを規制する第１の突起を
設けることにより、半導体ペレットのオンオフ動作の繰
り返しによる温度上昇、低下その結果としての熱膨張、
収縮による半導体ペレットと接着材間に生じる応力を緩
和させることができる。また、熱電気接続部材の半導体
ペレットと接続される部分に余剰の接着材を逃がす穴ま
たは溝を形成することもできる。これにより余剰の接着
材が半導体ペレットの側壁など不所望部分に広がり付着
するのを防止でき、接着材の厚みのばらつきを抑えるこ
とができる。また肉薄部と肉厚部とを隣接させた金属板
にて熱電気接続部材を構成し、肉薄部を半導体ペレット
の他の主面と、肉厚部を配線基板の径大パッド電極とそ
れぞれ対向させ、接着材を介して電気的に接続すること
により、放熱性が良好で組立性の良い半導体装置を実現
できる。この場合、熱電気接続部材の外面に凹凸を形成
し、表面積を増大させ放熱効果を向上させることができ
る。熱電気接続部材は熱的、電気的に良好な伝導性を有
する材料を用いられるが、具体的には加工性も良好な銅
またはアルミニウムが好適で、接着材と接触する部分は
接着材に対して濡れ性の良好な面に形成される。熱電気
接続部材が半導体ペレットの充電部に接続される場合に
は、熱電気接続部材の接着材との接触部を除く部分を予
め絶縁被覆しておくことが好ましい。BEST MODE FOR CARRYING OUT THE INVENTION In a semiconductor device according to the present invention, a back electrode of a semiconductor pellet and a pad electrode having a large diameter are thermally and electrically connected via an adhesive having good thermal and electrical conductivity. The semiconductor device is characterized in that it is connected to a thermoelectric connecting member having good conductivity, but is provided with a first projection that regulates the thickness of the adhesive at a portion of the thermoelectric connecting member that is connected to the semiconductor pellet. Temperature rise and fall as a result of repeated on / off operations of the pellets, resulting in thermal expansion,
Stress generated between the semiconductor pellet and the adhesive due to shrinkage can be reduced. In addition, a hole or a groove for allowing excess adhesive to escape may be formed in a portion of the thermoelectric connection member connected to the semiconductor pellet. As a result, the excess adhesive can be prevented from spreading and adhering to undesired portions such as the side walls of the semiconductor pellet, and variations in the thickness of the adhesive can be suppressed. In addition, a thermoelectric connection member is formed of a metal plate having a thin portion and a thick portion adjacent to each other, and the thin portion faces the other main surface of the semiconductor pellet, and the thick portion faces the large-diameter pad electrode of the wiring board. Then, by electrically connecting through the adhesive, a semiconductor device having good heat dissipation and good assembling property can be realized. In this case, irregularities can be formed on the outer surface of the thermoelectric connection member to increase the surface area and improve the heat radiation effect. For the thermoelectric connection member, a material having good thermal and electrical conductivity is used.Specifically, copper or aluminum, which has good workability, is preferable. Formed on the surface with good wettability. When the thermoelectric connection member is connected to the charged portion of the semiconductor pellet, it is preferable that the portion of the thermoelectric connection member other than the contact portion with the adhesive is previously insulated.

【０００６】[0006]

【実施例】以下に本発明の実施例を図１から説明する。
図において、図６と同一物には同一符号を付して重複す
る説明を省略する。本発明による半導体装置が図６半導
体装置と相違する点を説明する。即ち、半導体ペレット
１は一方の面にバンプ電極３が形成され、他の面には主
電流が流れる裏面電極１ａが形成されている。配線基板
４は、絶縁基板５上の半導体ペレット１に形成されたバ
ンプ電極３と対向する位置にバンプ電極３とほぼ同じ大
きさの径小パッド電極７が形成され、このパッド電極３
の形成領域の外方にパッド電極７に比して十分大きな径
大パッド電極１５を形成している。１６は熱的、電気的
に良好な伝導性を有する銅などの金属平板をその両端部
が平行となるように中間部を折り曲げて段差を設けた熱
電気接続部材で、段差部分１６ａで隣り合う平面部１６
ｂ、１６ｃを半導体ペレット１の裏面電極１ａ、径大パ
ッド電極１５にそれぞれ対向させている。段差部１６ａ
は、半導体ペレット１の厚さ、バンプ電極３及びパッド
電極７、１５の高さ、接着材１７、１８の厚みなどが考
慮され設定される。１７、１８はそれぞれ熱的、電気的
に良好な伝導性を有する半田や導電ペーストなどの接着
材で、熱電気接続部材１６を半導体ペレット１の裏面電
極１ａ、径大パッド電極１５にそれぞれ接続する。この
半導体装置は、複数のパッド電極が裏面電極１ａに対応
して主電流が供給され、半導体ペレット１の大電流動作
を可能にしている。熱電気接続部材１６は半導体ペレッ
ト１の厚さの１／３以上あればよく、例えば厚さ１００
μｍとし、巾を半導体ペレット１の一辺の長さとほぼ同
じ巾、例えば１５ｍｍとすることにより、図７、図８に
示す装置で導電膜の厚さが最大でも３０μｍ程度しかで
きないことに比較して、熱的、電気的通過断面積を格段
に大きくできる。図１実施例では、熱電気接続部材１６
の接着部分をエンボス加工し３０μｍ程度突出させ、こ
の突出部１６ｄの一辺の長さを半導体ペレット１の一辺
の長さの９０％程度に設定している。これにより、突出
部１６ｄからはみ出した余剰の接着材１７は突出部１６
ｄの周縁に留まり、半導体ペレット１からはみ出さず、
配線基板４上への流出が防止できる。また、図１実施例
では、熱電気接続部材１６の突出部１６ｄを半導体ペレ
ット１の裏面電極１ａとほぼ同じ面積に設定したが、図
２に示すように、半導体ペレット１の面積に比して十分
小さい微小突起１６ｅを形成することもできる。この微
小突起１６ｅは直径１ｍｍ程度で高さ５０〜１００μｍ
程度に設定され、その下端は接着材１７を突き抜けて半
導体ペレットの裏面電極１ａに当接している。半導体ペ
レット１はオンオフ動作を繰り返すことによって、温度
上昇、温度低下するが、微小突起１６ｅにより接着材１
７の厚さを上記範囲に規制することにより半導体ペレッ
ト１、接着材１７、熱電気接続部材１６のそれぞれ熱膨
張率の異なる接合界面にかかる応力を緩和し接合界面に
クラックが発生するのを抑制し長時間動作の可能な半導
体装置を実現できる。図３は本発明の他の実施例を示
す。この実施例では熱電気接続部材１６に接着材１７の
余剰分を逃がす穴１６ｆを貫通している。これにより、
接着材１７の内、塗付領域中央の接着材を逃がし穴１６
ｆ内に収容し、接着材１７のはみ出しを効果的に防止で
きる。この逃がし穴１６ｆは貫通穴だけでなく、両端が
側壁に開口した溝でもよい。図４は本発明の他の実施例
を示す。図１乃至図３実施例は金属平板を屈曲して熱電
気接続構体１６を形成したが、この実施例では、肉厚の
金属平板の中間部乃至一側方に切削、ロール加工、プレ
ス加工などの手段により肉薄部１９ａを形成し、この肉
薄部１９ａに上面が面一となるように肉厚部１９ｂを隣
接させた熱電気接続部材１９を用いている。この実施例
では、半導体ペレット１で発生した熱は、肉薄部１９ａ
から半導体ペレット１と隣接する部分で肉厚部１９ｂに
伝達されるため、図１実施例に比較しても段差部１６ａ
の長さ分、実質的に熱伝達経路を短縮でき、しかも肉厚
部１９ｂは断面積が広いため、熱抵抗、電気抵抗ともに
小さくでき、フリップチップ構造で大電力動作が可能な
半導体装置を実現できる。この実施例に図２、図３にて
説明した微小突起（１６ｅ）、逃がし穴（１６ｆ）を適
用することによりそれぞれの有する効果を奏することが
できる。また図５に示すように熱電気接続部材１９の上
面に多数の溝１９ｃを形成し、表面積を増大させて放熱
性を向上させることもできる。上記それぞれの実施例に
おいて、熱電気接続部材１６、１９の具体的材料として
銅を示したが、電気抵抗はやや高くなるものの軽量で加
工性の良好なアルミニウムを用いることもできる。この
場合、接着材１７、１８が接続される部分に、蒸着や溶
射メッキなどの手段により銅や金、銀、半田、銀ロウな
ど接着性の良好な金属や合金の層を形成すればよい。ま
た、熱電気接続部材１６、１９が高電位部分に接続され
て用いられ、触れると感電の虞がある場合には、この熱
電気接続部材１６、１９の外面を絶縁被覆することもで
きる。この場合、静電塗装法などの手段により熱電気接
続部材１６、１９の全面に樹脂層を形成し、接着材１
７、１８が接続される部分にサンドブラストや切削によ
り樹脂層に窓明けして熱電気接続部材の素地を露出させ
ればよい。またこの窓明け部分に蒸着、溶射メッキなど
により熱的、電気的に接着性の良好な層を形成しても良
い。また図１乃至図４の実施例では、熱電気接続部材１
６、１９を半導体ペレット１の裏面からその一側方に延
在させた構造を示したが、半導体ペレット１に跨って周
縁を半導体ペレット１を囲む位置に延在させてもよい。FIG. 1 shows an embodiment of the present invention.
In the figure, the same components as those in FIG. 6 are denoted by the same reference numerals, and redundant description will be omitted. The difference between the semiconductor device according to the present invention and the semiconductor device shown in FIG. 6 will be described. That is, the semiconductor pellet 1 has the bump electrode 3 formed on one surface, and the back surface electrode 1a through which the main current flows is formed on the other surface. On the wiring substrate 4, a small-diameter pad electrode 7 having substantially the same size as the bump electrode 3 is formed at a position facing the bump electrode 3 formed on the semiconductor pellet 1 on the insulating substrate 5.
A pad electrode 15 having a diameter sufficiently larger than that of the pad electrode 7 is formed outside the formation region of. Reference numeral 16 denotes a thermoelectric connecting member in which a metal flat plate made of copper or the like having good thermal and electrical conductivity is bent at an intermediate portion so that both ends thereof are parallel to each other to provide a step, and are adjacent at a step 16a. Flat part 16
b and 16c are opposed to the back electrode 1a and the large-diameter pad electrode 15 of the semiconductor pellet 1, respectively. Step 16a
Is set in consideration of the thickness of the semiconductor pellet 1, the heights of the bump electrodes 3 and the pad electrodes 7, 15, the thicknesses of the adhesives 17, 18, and the like. Reference numerals 17 and 18 denote adhesives such as solder and conductive paste having good thermal and electrical conductivity, respectively, and connect the thermoelectric connection member 16 to the back surface electrode 1a and the large-diameter pad electrode 15 of the semiconductor pellet 1, respectively. . In this semiconductor device, a plurality of pad electrodes are supplied with a main current corresponding to the back surface electrode 1a, thereby enabling the semiconductor pellet 1 to operate at a large current. The thermoelectric connection member 16 may have a thickness of at least 1/3 of the thickness of the semiconductor pellet 1, for example, a thickness of 100 mm.
By setting the width to be approximately the same as the length of one side of the semiconductor pellet 1, for example, 15 mm, the thickness of the conductive film can be reduced to about 30 μm at the maximum in the apparatus shown in FIGS. , Thermal and electrical cross section can be significantly increased. In the embodiment shown in FIG.
Is embossed to protrude by about 30 μm, and the length of one side of the protrusion 16 d is set to about 90% of the length of one side of the semiconductor pellet 1. As a result, the excess adhesive 17 protruding from the protruding portion 16 d is removed.
d, does not protrude from the semiconductor pellet 1,
Outflow onto the wiring board 4 can be prevented. In the embodiment shown in FIG. 1, the projecting portion 16d of the thermoelectric connection member 16 is set to have substantially the same area as the back electrode 1a of the semiconductor pellet 1. However, as shown in FIG. It is also possible to form sufficiently small minute projections 16e. The minute projections 16e have a diameter of about 1 mm and a height of 50 to 100 μm.
The lower end thereof penetrates the adhesive 17 and is in contact with the back electrode 1a of the semiconductor pellet. The temperature of the semiconductor pellet 1 rises and falls by repeating the on / off operation.
By restricting the thickness of 7 to the above range, the stress applied to the bonding interface of the semiconductor pellet 1, the adhesive 17, and the thermoelectric connection member 16 having different coefficients of thermal expansion is alleviated, and the occurrence of cracks at the bonding interface is suppressed. In addition, a semiconductor device which can operate for a long time can be realized. FIG. 3 shows another embodiment of the present invention. In this embodiment, the thermoelectric connection member 16 is penetrated through a hole 16f for letting the surplus adhesive 17 escape. This allows
The adhesive 16 in the center of the coating area of the adhesive 17
The adhesive 17 can be effectively prevented from sticking out of the adhesive 17. The relief holes 16f may be not only through holes but also grooves having both ends opened in the side wall. FIG. 4 shows another embodiment of the present invention. In the embodiment shown in FIGS. 1 to 3, the thermoelectric connection structure 16 is formed by bending a metal flat plate. In this embodiment, cutting, rolling, pressing, or the like is performed on the middle portion or one side of the thick metal flat plate. A thermoelectric connection member 19 is used in which a thin portion 19a is formed by the means described above, and a thick portion 19b is adjacent to the thin portion 19a so that the upper surface is flush. In this embodiment, the heat generated in the semiconductor pellet 1 is reduced by the thin portion 19a.
1 is transmitted to the thick portion 19b at a portion adjacent to the semiconductor pellet 1, so that the step portion 16a is
, The heat transfer path can be substantially shortened, and the thick section 19b has a large cross-sectional area, so that both the thermal resistance and the electrical resistance can be reduced, and a semiconductor device capable of operating with high power with a flip-chip structure is realized. it can. By applying the minute projections (16e) and the relief holes (16f) described in FIGS. 2 and 3 to this embodiment, the respective effects can be obtained. Further, as shown in FIG. 5, a large number of grooves 19c may be formed on the upper surface of the thermoelectric connection member 19 to increase the surface area and improve heat radiation. Although copper is shown as a specific material of the thermoelectric connection members 16 and 19 in each of the above embodiments, aluminum which has a slightly higher electric resistance but is lightweight and has good workability can also be used. In this case, a layer of a metal or alloy having good adhesion, such as copper, gold, silver, solder, silver brazing, or the like, may be formed at a portion where the adhesives 17 and 18 are connected by means such as vapor deposition or thermal spray plating. Further, when the thermoelectric connection members 16 and 19 are used by being connected to the high-potential portion and there is a risk of electric shock when touched, the outer surfaces of the thermoelectric connection members 16 and 19 can be insulated and coated. In this case, a resin layer is formed on the entire surface of the thermoelectric connection members 16 and 19 by means such as an electrostatic coating method, and the adhesive 1
A window may be opened in the resin layer by sand blasting or cutting at a portion where 7 and 18 are connected to expose the base of the thermoelectric connection member. Further, a layer having good thermal and electrical adhesion may be formed in the window opening by vapor deposition, thermal spray plating, or the like. 1 to 4, the thermoelectric connection member 1
Although the structure is shown in which the semiconductor devices 6 and 19 extend from the back surface of the semiconductor pellet 1 to one side thereof, the periphery may extend to the position surrounding the semiconductor pellet 1 over the semiconductor pellet 1.

【０００７】[0007]

【発明の効果】以上のように本発明によれば、電力用半
導体ペレットの主電流が流れる裏面電極と配線基板とを
低抵抗で自己発熱がなく、熱伝導性の良好な熱電気接続
部材にて接続したから、薄く小型で大電力動作可能なフ
リップチップ構造の半導体装置を実現できる。As described above, according to the present invention, the back electrode through which the main current of the power semiconductor pellet flows and the wiring board are connected to a thermoelectric connecting member having low resistance, no self-heating and good heat conductivity. Therefore, a flip-chip semiconductor device that is thin, small, and operable at high power can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明による半導体装置の実施例を示す側断
面図FIG. 1 is a side sectional view showing an embodiment of a semiconductor device according to the present invention.

【図２】 図１実施例の変形例を示す要部側断面図FIG. 2 is a sectional side view of a main part showing a modification of the embodiment of FIG. 1;

【図３】 図１実施例の他の変形例を示す要部側断面図FIG. 3 is a sectional side view of a main part showing another modification of the embodiment of FIG. 1;

【図４】 本発明による半導体装置の他の実施例を示す
側断面図FIG. 4 is a side sectional view showing another embodiment of the semiconductor device according to the present invention;

【図５】 図４実施例の変形例を示す側断面図FIG. 5 is a side sectional view showing a modification of the embodiment in FIG. 4;

【図６】 フリップチップ構造の半導体装置を示す側断
面図FIG. 6 is a side sectional view showing a semiconductor device having a flip chip structure;

【図７】 裏面電極と配線基板とを電気的に接続した半
導体装置を示す側断面図FIG. 7 is a side sectional view showing a semiconductor device in which a back electrode and a wiring board are electrically connected.

【図８】 半導体ペレットの放熱性を改善した半導体装
置を示す側断面図FIG. 8 is a side sectional view showing a semiconductor device with improved heat dissipation of a semiconductor pellet.

【符号の説明】[Explanation of symbols]

１ 半導体ペレット １ａ 裏面電極 ３ バンプ電極 ４ 配線基板 ７ 微小パッド電極 １５ 径大パッド電極 １６ 熱電気接続部材 １７ 接着材 １８ 接着材 １９ 熱電気接続部材 DESCRIPTION OF SYMBOLS 1 Semiconductor pellet 1a Back electrode 3 Bump electrode 4 Wiring board 7 Micro pad electrode 15 Large pad electrode 16 Thermoelectric connection member 17 Adhesive material 18 Adhesive material 19 Thermoelectric connection material

Claims (7)

【特許請求の範囲】[Claims] 【請求項１】一主面にバンプ電極を形成し他の主面に裏
面電極を形成した半導体ペレットと、半導体ペレットの
バンプ電極に対応する位置に微小パッド電極を形成する
とともに微小パッド電極形成領域の外方に主電流が供給
される径大パッド電極を形成した配線基板とを、バンプ
電極と微小パッド電極とを重合させて対向させ各電極の
重合部を電気的に接続するとともに、半導体ペレットの
他の主面と径大パッド電極間を、熱的、電気的に良好な
伝導性を有する接着材を介して熱的、電気的に良好な伝
導性を有する熱電気接続部材に接続したことを特徴とす
る半導体装置。1. A semiconductor pellet having a bump electrode formed on one main surface and a back electrode formed on the other main surface, a fine pad electrode formed at a position corresponding to the bump electrode of the semiconductor pellet, and a fine pad electrode formation region. The wiring substrate on which a large-diameter pad electrode to which a main current is supplied is placed on the outside of the substrate, and the bump electrode and the minute pad electrode are superimposed to face each other, and the overlapping portions of the electrodes are electrically connected and the semiconductor pellet is formed. The other main surface and the large-diameter pad electrode are connected to a thermoelectric connection member having good thermal and electrical conductivity through an adhesive material having good thermal and electrical conductivity. A semiconductor device characterized by the above-mentioned. 【請求項２】熱電気接続部材の半導体ペレットと接続さ
れる部分に接着材の厚みを規制する突起を設けたことを
特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein a projection for regulating the thickness of the adhesive is provided at a portion of the thermoelectric connection member connected to the semiconductor pellet. 【請求項３】熱電気接続部材の半導体ペレットと接続さ
れる部分に余剰の接着材を逃がす穴または溝を形成した
ことを特徴とする請求項１に記載の半導体装置。3. The semiconductor device according to claim 1, wherein a hole or a groove for allowing excess adhesive to escape is formed in a portion of the thermoelectric connection member connected to the semiconductor pellet. 【請求項４】肉薄部と肉厚部とを隣接させた金属板にて
熱電気接続部材を構成し、肉薄部を半導体ペレットの他
の主面と、肉厚部を配線基板の径大パッド電極とそれぞ
れ対向させ、接着材を介して電気的に接続したことを特
徴とする請求項１に記載の半導体装置。4. A thermoelectric connection member comprising a metal plate having a thin portion and a thick portion adjacent to each other, wherein the thin portion is the other main surface of the semiconductor pellet and the thick portion is a large-diameter pad of a wiring board. The semiconductor device according to claim 1, wherein the semiconductor device is opposed to each of the electrodes and is electrically connected via an adhesive. 【請求項５】熱電気接続部材の外面に凹凸を形成したこ
とを特徴とする請求項４に記載の半導体装置。5. The semiconductor device according to claim 4, wherein irregularities are formed on an outer surface of the thermoelectric connection member. 【請求項６】熱電気接続部材が銅またはアルミニウムか
らなり、接着材と接触する部分が接着材に対して濡れ性
の良好な面に形成されたことを特徴する請求項１に記載
の半導体装置。6. The semiconductor device according to claim 1, wherein the thermoelectric connection member is made of copper or aluminum, and a portion in contact with the adhesive is formed on a surface having good wettability with respect to the adhesive. . 【請求項７】熱電気接続部材の接着材との接触部を除く
部分が絶縁被覆されたことを特徴する請求項１に記載の
半導体装置。7. The semiconductor device according to claim 1, wherein a portion of the thermoelectric connection member other than a contact portion with the adhesive is coated with an insulating material.
JP9205561A 1997-07-31 1997-07-31 Semiconductor device Pending JPH1154673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9205561A JPH1154673A (en) 1997-07-31 1997-07-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9205561A JPH1154673A (en) 1997-07-31 1997-07-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH1154673A true JPH1154673A (en) 1999-02-26

Family

ID=16508942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9205561A Pending JPH1154673A (en) 1997-07-31 1997-07-31 Semiconductor device

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Country Link
JP (1) JPH1154673A (en)

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