JPH11340925A - Semiconductor integrated circuit for receiving light - Google Patents

Semiconductor integrated circuit for receiving light

Info

Publication number
JPH11340925A
JPH11340925A JP10147399A JP14739998A JPH11340925A JP H11340925 A JPH11340925 A JP H11340925A JP 10147399 A JP10147399 A JP 10147399A JP 14739998 A JP14739998 A JP 14739998A JP H11340925 A JPH11340925 A JP H11340925A
Authority
JP
Japan
Prior art keywords
light receiving
receiving element
current
output
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10147399A
Other languages
Japanese (ja)
Inventor
Masaaki Nara
正明 奈良
Masashi Arai
政至 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10147399A priority Critical patent/JPH11340925A/en
Publication of JPH11340925A publication Critical patent/JPH11340925A/en
Pending legal-status Critical Current

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  • Optical Communication System (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for receiving light in that adverse effect due to parasitic capacitance is reduced. SOLUTION: Output signals from light receiving elements 5a-5c that are plural divisions of a light receiving element of a prescribed size are given to current voltage conversion circuits 6-8, where the currents are converted into voltages, they are summed by an adder circuit 9, from which an output voltage is generated. Since the light receiving element is divided into light receiving element divisions 5a-5c to reduce the respective areas, then the parasitic capacitance is decreased and the output frequency characteristic is improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体基板上に発
生する寄生容量の悪影響を低減する受光用半導体集積回
路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light receiving semiconductor integrated circuit for reducing the adverse effect of parasitic capacitance generated on a semiconductor substrate.

【0002】[0002]

【従来の技術】例えば、CDプレーヤーや赤外線通信機
においては、レザー光や赤外線等を受光する受光素子が
備えられている。一般に、受光素子としてフォトダイオ
ードが使用され、受光された光の強度に応じて出力電流
が発生する。この受光素子からは電流モードで出力信号
が発生するが、受光素子の後段の信号処理する回路は電
圧モードで動作する。従って、受光素子と信号処理回路
との間には受光素子の出力電流を電圧変換する電流電圧
変換回路が必要となる。図2は従来の電流電圧変換回路
を示す。
2. Description of the Related Art For example, a CD player or an infrared communication device is provided with a light receiving element for receiving laser light, infrared light or the like. Generally, a photodiode is used as a light receiving element, and an output current is generated according to the intensity of received light. An output signal is generated from this light receiving element in a current mode, but a signal processing circuit at a subsequent stage of the light receiving element operates in a voltage mode. Therefore, a current-to-voltage conversion circuit for converting the output current of the light receiving element into a voltage is required between the light receiving element and the signal processing circuit. FIG. 2 shows a conventional current-voltage conversion circuit.

【0003】図2の増幅器1は、受光素子2からの出力
信号がない時、平衡状態にある。つまり、増幅器1の出
力信号が帰還抵抗3を介して増幅器1の負入力端子に帰
還される。その際、増幅器1の出力信号は、増幅器1の
負入力端子の入力電圧が正入力端子の入力電圧に等しく
なるように調整される。帰還抵抗3に流れる電流をI
1、出力電圧をV1、帰還抵抗3の抵抗値をR1とする
と、V1=R1×I1となる。この状態にて、受光素子
に例えば赤外線が照射され、受光素子2から出力電流I
2が発生したとすると、出力電流I2は帰還抵抗3に流
れるので、出力電圧V2は、V2=R1×(I1+I
2)となる。従って、受光素子の出力電流は帰還抵抗3
で電流電圧変換されたことになる。
The amplifier 1 shown in FIG. 2 is in a balanced state when there is no output signal from the light receiving element 2. That is, the output signal of the amplifier 1 is fed back to the negative input terminal of the amplifier 1 via the feedback resistor 3. At this time, the output signal of the amplifier 1 is adjusted so that the input voltage of the negative input terminal of the amplifier 1 becomes equal to the input voltage of the positive input terminal. The current flowing through the feedback resistor 3 is represented by I
Assuming that 1, the output voltage is V1, and the resistance value of the feedback resistor 3 is R1, V1 = R1 × I1. In this state, the light receiving element is irradiated with, for example, infrared light, and the output current I
2 occurs, the output current I2 flows through the feedback resistor 3, so that the output voltage V2 is V2 = R1 × (I1 + I
2). Therefore, the output current of the light receiving element is equal to the feedback resistance 3
This means that current-voltage conversion has been performed.

【0004】[0004]

【発明が解決しようとする課題】近年では、少なくとも
増幅器1及び受光素子2が同一の半導体基板上に集積化
される。しかし、このような半導体基板上では、受光素
子1となるフォトダイオードのカソードと、サブストレ
ートとの間に、図2の如く寄生容量Cが発生する。寄生
容量Cの大きさは電圧電流変換回路の特性に影響を与え
る大きさであって、無視することはできなかった。ま
た、従来では、増幅器1の出力電圧にノイズが発生する
ことを防止するため、ノイズ低減用の抵抗4が接続され
る。その結果、寄生容量Cと抵抗4との時定数により電
流電圧変換回路の周波数特性が悪化するという問題があ
った。
In recent years, at least the amplifier 1 and the light receiving element 2 are integrated on the same semiconductor substrate. However, on such a semiconductor substrate, a parasitic capacitance C is generated between the cathode of the photodiode serving as the light receiving element 1 and the substrate as shown in FIG. The magnitude of the parasitic capacitance C affects the characteristics of the voltage-current conversion circuit and cannot be ignored. Conventionally, a noise reducing resistor 4 is connected to prevent noise from occurring in the output voltage of the amplifier 1. As a result, there is a problem that the time constant of the parasitic capacitance C and the resistance 4 deteriorates the frequency characteristics of the current-voltage conversion circuit.

【0005】[0005]

【課題を解決するための手段】本発明に依れば、受光素
子と、受光素子の出力信号を電流電圧変換する電流電圧
変換回路とを同一半導体基板上に集積化された受光用半
導体集積回路において、前記受光素子は複数の領域に分
割されると共に、電流電圧変換回路は複数の受光素子に
対応して複数の変換部を備えて成り、さらに、前記変換
部の出力信号を加算する加算回路を備えることを特徴と
する。
According to the present invention, a light-receiving semiconductor integrated circuit in which a light-receiving element and a current-to-voltage conversion circuit for converting the output signal of the light-receiving element into a current-voltage circuit are integrated on the same semiconductor substrate. , The light receiving element is divided into a plurality of regions, the current-voltage conversion circuit includes a plurality of conversion units corresponding to the plurality of light receiving elements, and further, an addition circuit for adding an output signal of the conversion unit It is characterized by having.

【0006】特に、前記変換部は、基準電圧が印加され
る正入力端子、前記受光素子が接続される負入力端子、
及び出力電圧が発生する出力端子を有する増幅器と、前
記負入力端子及び出力端子間に接続された帰還抵抗とに
より構成されることを特徴とする。
In particular, the converter includes a positive input terminal to which a reference voltage is applied, a negative input terminal to which the light receiving element is connected,
And an amplifier having an output terminal for generating an output voltage, and a feedback resistor connected between the negative input terminal and the output terminal.

【0007】本発明に依れば、受光素子を複数個に分割
したことにより、寄生容量が小さくなり、出力周波数特
性が改善される。
According to the present invention, by dividing the light receiving element into a plurality, the parasitic capacitance is reduced and the output frequency characteristic is improved.

【0008】[0008]

【発明の実施の形態】図1は本発明の実施の形態を示す
図であり、5は例えば3つに分割された受光部5a〜5
cから成る受光素子、6乃至8は受光素子5a〜5cの
出力信号をそれぞれ電流電圧変換する電流電圧変換回
路、9は電流電圧変換回路6乃至8の出力電圧を加算す
る加算回路である。
FIG. 1 is a view showing an embodiment of the present invention. Reference numeral 5 denotes, for example, three divided light receiving portions 5a to 5a.
The light receiving elements 6 to 8 are current-to-voltage conversion circuits for converting the output signals of the light receiving elements 5a to 5c into current-to-voltage conversions, respectively.

【0009】図1において、受光素子5a〜5cに光が
照射されていないと、受光素子5a〜5cから出力信号
が発生しない。この状態では、電流電圧変換回路6乃至
8は平衡状態になり、無信号時に対応する所定レベルの
出力電圧が電流電圧変換回路6乃至8から発生する。
In FIG. 1, if the light receiving elements 5a to 5c are not irradiated with light, no output signal is generated from the light receiving elements 5a to 5c. In this state, the current-voltage conversion circuits 6 to 8 are in a balanced state, and output voltages of a predetermined level corresponding to the absence of a signal are generated from the current-voltage conversion circuits 6 to 8.

【0010】例えば、電流電圧変換回路6では、増幅器
6aの出力信号が帰還抵抗6bを介して増幅器6aの負
入力端子に帰還される。その際、増幅器6aの出力信号
は、増幅器6aの負入力端子の入力電圧が正入力端子の
入力電圧に等しくなるように調整される。無信号時帰還
抵抗6bには帰還信号しか流れず、受光素子5aの出力
信号は流れない。無信号時、帰還抵抗6bに流れる電流
をIa1、出力電圧をVa1、帰還抵抗6bの抵抗値を
Raとすると、Va1=Ra×Ia1となる。
For example, in the current-voltage conversion circuit 6, the output signal of the amplifier 6a is fed back to the negative input terminal of the amplifier 6a via the feedback resistor 6b. At this time, the output signal of the amplifier 6a is adjusted so that the input voltage of the negative input terminal of the amplifier 6a becomes equal to the input voltage of the positive input terminal. Only the feedback signal flows through the feedback resistor 6b when there is no signal, and the output signal of the light receiving element 5a does not flow. When there is no signal, if the current flowing through the feedback resistor 6b is Ia1, the output voltage is Va1, and the resistance value of the feedback resistor 6b is Ra, then Va1 = Ra × Ia1.

【0011】無信号時には、電流電圧変換回路7及び8
においても電流電圧変換回路6と同様の動作が行われ
る。無信号時、他の受光素子5b及び5cからも出力信
号が発生しないので、電流電圧変換回路7及び8の出力
電圧は無信号時に対応する所定レベルの電圧が発生す
る。つまり、増幅器7a及び8aの帰還信号をそれぞれ
帰還抵抗7b及び8bで電圧変換した出力電圧Vb1及
びVc1が発生する。
When there is no signal, the current-voltage conversion circuits 7 and 8
The same operation as in the current-voltage conversion circuit 6 is performed in When there is no signal, no output signal is generated from the other light receiving elements 5b and 5c, so that the output voltage of the current / voltage conversion circuits 7 and 8 has a predetermined level corresponding to the time when there is no signal. That is, output voltages Vb1 and Vc1 are generated by converting the feedback signals of the amplifiers 7a and 8a by the feedback resistors 7b and 8b, respectively.

【0012】電流電圧変換回路6乃至8の出力電圧Va
1乃至Vc1は、加算回路9で加算され、出力電圧Vo
utとして出力される。
The output voltage Va of the current-voltage conversion circuits 6 to 8
1 to Vc1 are added by the adding circuit 9, and the output voltage Vo
ut is output.

【0013】ここで、受光素子5a乃至5cに例えば赤
外線が照射されると、各々の受光素子5a乃至5cから
出力信号が発生する。それぞれの受光素子5a乃至5c
からの出力電流は帰還抵抗6b乃至8bで電圧変換され
る。例えば、受光素子5aから出力電流Ia2が発生し
たとすると、出力電流Ia2は帰還抵抗6bに流れるの
で、出力電圧Va2は、Va2=Ra×(Ia1+Ia
2)となる。
Here, when the light receiving elements 5a to 5c are irradiated with, for example, infrared rays, output signals are generated from the respective light receiving elements 5a to 5c. Each light receiving element 5a to 5c
Is converted into a voltage by the feedback resistors 6b to 8b. For example, if an output current Ia2 is generated from the light receiving element 5a, the output current Ia2 flows through the feedback resistor 6b, so that the output voltage Va2 is Va2 = Ra × (Ia1 + Ia
2).

【0014】また、他の受光素子5b及び5cでも、出
力電流が発生すると、電流電圧変換回路6の出力電圧と
同様にして、電流電圧変換回路7及び8から電圧変換さ
れた出力電圧Vb2及びVc2が発生する。
When an output current is generated in the other light receiving elements 5b and 5c, the output voltages Vb2 and Vc2 converted from the current / voltage conversion circuits 7 and 8 are converted in the same manner as the output voltage of the current / voltage conversion circuit 6. Occurs.

【0015】それぞれの電流電圧発生回路6乃至8から
の出力電圧Va2乃至Vc2は加算された後、出力電圧
Voutとして出力される。
The output voltages Va2 to Vc2 from the current voltage generators 6 to 8 are added and output as an output voltage Vout.

【0016】ところで、本発明の回路をIC化した場
合、受光素子や電流電圧変換回路、加算回路のパターン
は、例えば、図3のように形成される。本発明の受光素
子の全体の面積は、従来の受光素子の面積に略等しい大
きさに設定される。従って、本発明による受光素子の分
割は、従来の受光素子を複数個に分割したのであり、新
たに受光素子領域を付加したものではない。
By the way, when the circuit of the present invention is formed into an IC, the patterns of the light receiving element, the current-voltage conversion circuit, and the addition circuit are formed as shown in FIG. 3, for example. The entire area of the light receiving element of the present invention is set to a size substantially equal to the area of the conventional light receiving element. Therefore, the division of the light receiving element according to the present invention is obtained by dividing the conventional light receiving element into a plurality, and does not add a new light receiving element region.

【0017】受光素子に生成される寄生容量の大きさ
は、受光素子の面積に比例される。各々の受光素子の面
積は従来に比べ小さくなるので、本発明の受光素子での
寄生容量は小さくなる。その為、ノイズ低減用の抵抗と
寄生容量とによる時定数も小さくなり、各々の電流電圧
変換回路6乃至8の出力の周波数特性が改善される。従
って、加算回路9は入力信号を単に加算するだけなの
で、加算回路9の出力の周波数特性も改善される。尚、
前記時定数は遮断周波数を定め、遮断周波数は寄生容量
が大きくなるほど低くなる。
The magnitude of the parasitic capacitance generated in the light receiving element is proportional to the area of the light receiving element. Since the area of each light receiving element is smaller than that of the related art, the parasitic capacitance of the light receiving element of the present invention is smaller. Therefore, the time constant due to the noise reducing resistor and the parasitic capacitance is also reduced, and the frequency characteristics of the outputs of the current-to-voltage conversion circuits 6 to 8 are improved. Accordingly, since the addition circuit 9 simply adds the input signals, the frequency characteristic of the output of the addition circuit 9 is also improved. still,
The time constant determines the cutoff frequency, and the cutoff frequency decreases as the parasitic capacitance increases.

【0018】[0018]

【発明の効果】本発明に依れば、受光素子を分割したの
で、寄生容量が小さくなり、電流電圧発生回路の周波数
特性を改善することができる。
According to the present invention, since the light receiving element is divided, the parasitic capacitance is reduced, and the frequency characteristics of the current / voltage generating circuit can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【図2】従来例を示す回路図である。FIG. 2 is a circuit diagram showing a conventional example.

【図3】本発明の回路図を半導体基板上に配置したパタ
ーンを示す図である。
FIG. 3 is a diagram showing a pattern in which the circuit diagram of the present invention is arranged on a semiconductor substrate.

【符号の説明】[Explanation of symbols]

5a〜5c 受光素子 6〜8 電流電圧変換回路 9 加算回路 5a-5c Light receiving element 6-8 Current-voltage conversion circuit 9 Addition circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 受光素子と、受光素子の出力信号を電流
電圧変換する電流電圧変換回路とを同一半導体基板上に
集積化された受光用半導体集積回路において、前記受光
素子は複数の領域に分割されると共に、電流電圧変換回
路は複数の受光素子に対応して複数の変換部を備えて成
り、さらに、前記変換部の出力信号を加算する加算回路
を備えることを特徴とする受光用半導体集積回路。
1. A light-receiving semiconductor integrated circuit in which a light-receiving element and a current-to-voltage conversion circuit for current-to-voltage conversion of an output signal of the light-receiving element are integrated on the same semiconductor substrate, wherein the light-receiving element is divided into a plurality of regions. And a current-voltage conversion circuit including a plurality of conversion units corresponding to the plurality of light-receiving elements, and further including an addition circuit for adding an output signal of the conversion unit. circuit.
【請求項2】 前記変換部は、基準電圧が印加される正
入力端子、前記受光素子が接続される負入力端子、及び
出力電圧が発生する出力端子を有する増幅器と、前記負
入力端子及び出力端子間に接続された帰還抵抗とにより
構成されることを特徴とする請求項1記載の受光用半導
体集積回路。
2. An amplifier having a positive input terminal to which a reference voltage is applied, a negative input terminal to which the light receiving element is connected, and an output terminal to generate an output voltage, the conversion unit comprising: a negative input terminal; 2. The light receiving semiconductor integrated circuit according to claim 1, comprising a feedback resistor connected between terminals.
JP10147399A 1998-05-28 1998-05-28 Semiconductor integrated circuit for receiving light Pending JPH11340925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10147399A JPH11340925A (en) 1998-05-28 1998-05-28 Semiconductor integrated circuit for receiving light

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10147399A JPH11340925A (en) 1998-05-28 1998-05-28 Semiconductor integrated circuit for receiving light

Publications (1)

Publication Number Publication Date
JPH11340925A true JPH11340925A (en) 1999-12-10

Family

ID=15429415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10147399A Pending JPH11340925A (en) 1998-05-28 1998-05-28 Semiconductor integrated circuit for receiving light

Country Status (1)

Country Link
JP (1) JPH11340925A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005531129A (en) * 2002-03-22 2005-10-13 メレキシス ゲーエムベーハー Optical fiber receiver with increasing bandwidth
JP2007318645A (en) * 2006-05-29 2007-12-06 Sanyo Electric Co Ltd Subtraction circuit
JP2008153930A (en) * 2006-12-18 2008-07-03 Taiko Denki Co Ltd Light receiving device for spatial optical communication
JP2014044841A (en) * 2012-08-27 2014-03-13 West Japan Railway Co Arc detection device for dc high-voltage circuit breaker

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005531129A (en) * 2002-03-22 2005-10-13 メレキシス ゲーエムベーハー Optical fiber receiver with increasing bandwidth
JP2007318645A (en) * 2006-05-29 2007-12-06 Sanyo Electric Co Ltd Subtraction circuit
JP2008153930A (en) * 2006-12-18 2008-07-03 Taiko Denki Co Ltd Light receiving device for spatial optical communication
JP2014044841A (en) * 2012-08-27 2014-03-13 West Japan Railway Co Arc detection device for dc high-voltage circuit breaker

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