JPH1131786A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH1131786A JPH1131786A JP18624797A JP18624797A JPH1131786A JP H1131786 A JPH1131786 A JP H1131786A JP 18624797 A JP18624797 A JP 18624797A JP 18624797 A JP18624797 A JP 18624797A JP H1131786 A JPH1131786 A JP H1131786A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- wiring
- observation
- vdd
- vss
- Prior art date
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体基板上に形成
された電源配線上の電源ノイズを観測する回路を有する
半導体集積回路に関する。The present invention relates to a semiconductor integrated circuit having a circuit for observing power supply noise on power supply wiring formed on a semiconductor substrate.
【0002】[0002]
【従来の技術】近年、電子計算機などのディジタル処理
装置の高速化が進み、それに用いられる半導体集積回路
も高速化・高密度化の一途をたどっている。それに伴
い、従来では問題にならなかった様々なノイズの影響を
考慮する必要が生じている。その1つに半導体集積回路
内の電源電圧の変動、すなわち電源ノイズが挙げられ
る。2. Description of the Related Art In recent years, the speed of digital processing devices such as electronic computers has been increased, and the speed of semiconductor integrated circuits used therein has been steadily increased. Accordingly, it is necessary to consider the influence of various noises that have not been a problem in the past. One of them is fluctuation of power supply voltage in a semiconductor integrated circuit, that is, power supply noise.
【0003】半導体集積回路の動作速度の向上に伴い、
動作周期に対する電源ノイズの時間幅の占める割合が増
大する。また半導体集積回路の高速化および低電力化の
ために電源電圧を下げる傾向にあるため、電源電圧に対
する電源ノイズの電圧振幅の割合も増大する。さらに、
信号の立ち上がり時間の高速化や回路の高密度化に伴
い、電源ノイズ自身の大きさも増大の傾向にある。電源
ノイズが大きくなると回路の遅延時間の増大や誤動作の
原因となるため、局所的な電源ノイズの影響を考慮する
必要性が高まりつつある。With the improvement of the operation speed of semiconductor integrated circuits,
The ratio of the time width of the power supply noise to the operation cycle increases. In addition, since the power supply voltage tends to be reduced in order to increase the speed and reduce the power of the semiconductor integrated circuit, the ratio of the voltage amplitude of the power supply noise to the power supply voltage also increases. further,
As the rise time of a signal is increased and the circuit density is increased, the magnitude of power supply noise itself tends to increase. If the power supply noise increases, it causes an increase in the delay time of the circuit or a malfunction, so that it is increasingly necessary to consider the influence of local power supply noise.
【0004】従来の半導体集積回路の電源ノイズ観測方
法を図3に示す。半導体集積回路116は多層構造にな
っており、半導体基板111,VSS電源層112,信
号配線層113,VDD電源層114、および表面層1
15で構成される。半導体基板111は主に半導体と配
線用導体で構成され、回路素子101,信号配線10
2,電源配線VSS,電源配線VDDなどが形成され
る。VSS電源層112,VDD電源層114は一般に網目
状あるいは板状になっており、それぞれ半導体基板11
1上の電源配線VSS,電源配線VDDに給電するため
に複数箇所にて接続される。信号配線層113は半導体
基板111内で接続できない部分の配線を行うときに使
用する。表面層115は信号入力端子121,VSS給
電端子122,VDD給電端子123など、半導体集積
回路116に対する入出力信号や電源接続用の端子を有
する。実際の半導体集積回路にはVSS電源層112,
信号配線層113,VDD電源層114の各層が複数存
在するものもある。FIG. 3 shows a conventional method for observing power supply noise of a semiconductor integrated circuit. The semiconductor integrated circuit 116 has a multilayer structure, and includes a semiconductor substrate 111, a VSS power supply layer 112, a signal wiring layer 113, a VDD power supply layer 114, and a surface layer 1.
15 is comprised. The semiconductor substrate 111 mainly includes a semiconductor and a wiring conductor, and includes the circuit element 101 and the signal wiring 10.
2. Power supply wiring VSS, power supply wiring VDD, etc. are formed. The VSS power supply layer 112 and the VDD power supply layer 114 are generally mesh-shaped or plate-shaped, and
The power supply wiring VSS and the power supply wiring VDD on the power supply line 1 are connected at a plurality of locations to supply power. The signal wiring layer 113 is used when wiring of a portion that cannot be connected in the semiconductor substrate 111 is performed. The surface layer 115 has input / output signals for the semiconductor integrated circuit 116 and terminals for power supply connection, such as a signal input terminal 121, a VSS power supply terminal 122, and a VDD power supply terminal 123. In an actual semiconductor integrated circuit, the VSS power supply layer 112,
Some include a plurality of signal wiring layers 113 and a plurality of VDD power supply layers 114.
【0005】図3において、VSS給電端子122,V
DD給電端子123に電源を接続し、信号入力端子12
1の信号を切り替えると、回路素子101の出力信号も
切り替わる。このとき、回路素子101に接続されてい
る電源配線の給電点VSS0や給電点VDD0を介して
電荷の移動が生じ、一時的に電源電圧が変動する。これ
が電源ノイズである。電源ノイズは出力信号や内部信号
が切り替わった各々の回路素子で生じ、電源配線VS
S,電源配線VDDからVSS電源層112,VDD電
源層114を経由してVSS給電端子122,VDD給
電端子123へと伝播する。従来はVSS給電端子12
2とVDD給電端子123に測定装置131を接続して
電源ノイズを観測していた。In FIG. 3, VSS power supply terminals 122, V
A power supply is connected to the DD power supply terminal 123, and the signal input terminal 12
When the signal 1 is switched, the output signal of the circuit element 101 is also switched. At this time, charges move through the power supply point VSS0 or the power supply point VDD0 of the power supply wiring connected to the circuit element 101, and the power supply voltage temporarily changes. This is power supply noise. Power supply noise is generated in each circuit element whose output signal or internal signal is switched, and the power supply wiring VS
S, the power is transmitted from the power supply wiring VDD to the VSS power supply terminal 122 and the VDD power supply terminal 123 via the VSS power supply layer 112 and the VDD power supply layer 114. Conventionally, VSS power supply terminal 12
The power supply noise was observed by connecting the measuring device 131 to the power supply terminal 2 and the VDD power supply terminal 123.
【0006】[0006]
【発明が解決しようとする課題】VSS電源層112,
VDD電源層114は電源と回路素子に接続されている
ため、半導体集積回路116動作時には電流が流れてい
る。この電流とVSS電源層112,VDD電源層11
4の持つインピーダンスにより、回路素子101で発生
した電源ノイズはVSS給電端子122,VDD給電端
子123に伝達されるまでに波形が劣化する。また、回
路素子101で発生した電源ノイズはVSS電源層11
2,VDD電源層114で他の回路素子で発生した電源
ノイズと合成されてVSS給電端子122,VDD給電
端子123に伝達される。以上2点の理由により、従来
の観測方法では回路素子101で発生した電源ノイズの
みを抽出して測定することができない。SUMMARY OF THE INVENTION The VSS power supply layer 112,
Since the VDD power supply layer 114 is connected to a power supply and circuit elements, a current flows when the semiconductor integrated circuit 116 operates. This current and the VSS power supply layer 112 and the VDD power supply layer 11
Due to the impedance of 4, the waveform of the power supply noise generated in the circuit element 101 is deteriorated before being transmitted to the VSS power supply terminal 122 and the VDD power supply terminal 123. The power supply noise generated by the circuit element 101 is
2. In the VDD power supply layer 114, the power supply noise is combined with power supply noise generated in other circuit elements and transmitted to the VSS power supply terminal 122 and the VDD power supply terminal 123. For the above two reasons, the conventional observation method cannot extract and measure only the power supply noise generated in the circuit element 101.
【0007】本発明の目的は、半導体基板上に形成され
た電源配線上の電源ノイズを観測する回路を有する半導
体集積回路を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit having a circuit for observing power supply noise on power supply wiring formed on a semiconductor substrate.
【0008】[0008]
【課題を解決するための手段】上記目的を達成するた
め、本発明は、電源配線上の複数個の点と電源配線の電
圧を測定するための複数個の観測用端子との間を、配線
長がほぼ等しい観測用配線を用いて一対一に接続する。To achieve the above object, the present invention provides a method for connecting a plurality of points on a power supply wiring to a plurality of observation terminals for measuring the voltage of the power supply wiring. One-to-one connection is made using observation wirings of approximately equal length.
【0009】[0009]
【発明の実施の形態】図1に本発明の実施例を示す。半
導体集積回路の基本構成は図3とほとんど同じである。
回路素子101で発生する電源ノイズを観測する場合に
ついて以下説明する。回路素子101の近傍に電源観測
用セル201を配置し、回路素子101と同一の電源配線
VSS,電源配線VDDに接続する。この際、給電点V
SS0と接続点VSS1,給電点VDD0と接続点VD
D1をそれぞれごく近傍に設ける。電源観測用セル20
1は電源配線を信号配線に接続するためのセルであり、
電源配線VSS,電源配線VDDと同様の導体で構成さ
れる。電源観測用セル201からVSS観測用配線20
4,VDD観測用配線205の配線長と遅延時間がそれ
ぞれほぼ等しくなるように引き出し、表面層115上の
VSS観測用端子206,VDD観測用端子207に接
続する。以上の仕組みを半導体集積回路116の作成時
に組み込んでおく。FIG. 1 shows an embodiment of the present invention. The basic configuration of the semiconductor integrated circuit is almost the same as FIG.
The case where power supply noise generated in the circuit element 101 is observed will be described below. The power supply observing cell 201 is arranged near the circuit element 101, and is connected to the same power supply wiring VSS and power supply wiring VDD as the circuit element 101. At this time, the feeding point V
SS0 and connection point VSS1, feeding point VDD0 and connection point VDD
D1 is provided very close to each. Power observation cell 20
1 is a cell for connecting the power supply wiring to the signal wiring,
The power supply line VSS and the power supply line VDD are formed of the same conductor. Power observation cell 201 to VSS observation wiring 20
4. The wiring is pulled out so that the wiring length and the delay time of the VDD observation wiring 205 are substantially equal to each other, and connected to the VSS observation terminal 206 and the VDD observation terminal 207 on the surface layer 115. The above mechanism is incorporated when the semiconductor integrated circuit 116 is created.
【0010】回路素子101での電源ノイズを観測する
ときはオシロスコープなどの測定装置131をVSS観
測用端子206,VDD観測用端子207に接続し、電
圧波形を観測する。ハイインピーダンスプローブを用い
て測定するとVSS観測用配線204,VDD観測用配
線205には電流が流れないため、従来例のように観測
する配線に電流が流れることによる波形劣化がほとんど
生じない。また、給電点VSS0と接続点VSS1,給
電点VDD0と接続点VDD1をそれぞれごく近傍に設
けることにより、他の回路素子で生じた電源ノイズとほ
とんど合成されずに回路素子101の電源ノイズを観測
することができる。なお、電源ノイズを観測しないとき
にはVSS観測用端子206,VDD観測用端子207
を開放にしておけばよい。When observing power supply noise in the circuit element 101, a measuring device 131 such as an oscilloscope is connected to the VSS observation terminal 206 and the VDD observation terminal 207 to observe a voltage waveform. When a measurement is performed using a high impedance probe, no current flows through the VSS observation wiring 204 and the VDD observation wiring 205, so that waveform deterioration due to current flowing through the wiring to be observed unlike the conventional example hardly occurs. Further, by providing the power supply point VSS0 and the connection point VSS1 and the power supply point VDD0 and the connection point VDD1 very close to each other, the power supply noise of the circuit element 101 is observed almost without being combined with the power supply noise generated in other circuit elements. be able to. When the power supply noise is not observed, the VSS observation terminal 206 and the VDD observation terminal 207 are used.
Should be left open.
【0011】図2に電源ノイズ波形を示す。横軸は時
間、縦軸は観測点におけるVDDからVSSを引いた電
圧を示している。実線301は図1の給電点VSS0,
給電点VDD0間の電圧波形,破線302はVSS観測
用端子206,VDD観測用端子207間で観測した電
圧波形を示す。VSS観測用配線204,VDD観測用
配線205のインピーダンスの影響があるため、VSS
観測用端子206,VDD観測用端子207における観測
波形は実際の電源ノイズ波形より伝達時間分遅れ、多少
減衰した波形となるが、回路シミュレーションや予備実
験等で観測波形から実際の電源ノイズ波形への変換方法
を確立しておくことにより本来の電源ノイズを推測する
ことが可能となる。FIG. 2 shows a power supply noise waveform. The horizontal axis indicates time, and the vertical axis indicates a voltage obtained by subtracting VSS from VDD at the observation point. The solid line 301 is the power supply point VSS0,
A voltage waveform between the power supply points VDD0 and a broken line 302 indicate a voltage waveform observed between the VSS observation terminal 206 and the VDD observation terminal 207. Because of the impedance of the VSS observation wiring 204 and the VDD observation wiring 205,
Observation waveforms at the observation terminal 206 and the VDD observation terminal 207 are delayed by transmission time from the actual power supply noise waveform and become somewhat attenuated waveforms. By establishing the conversion method, the original power supply noise can be estimated.
【0012】電源ノイズをできる限り忠実に観測するた
めに、以下の点に留意する。まず、それぞれの電源から
の引き出し配線の伝送遅延その他の特性を同一にするた
め、抵抗,キャパシタンス,インダクタンスを極力揃え
る。具体的には、配線の材質,長さ,断面積,引き出し
経路を揃える。引き出し経路を揃えるのは、他の配線か
らのクロストークノイズなどの影響を同一にして測定時
に打ち消すためである。In order to observe power supply noise as faithfully as possible, the following points are noted. First, the resistance, capacitance, and inductance are made as uniform as possible in order to make the transmission delay and other characteristics of the lead wires from each power supply the same. Specifically, the wiring material, length, cross-sectional area, and lead-out path are made uniform. The reason why the leading paths are aligned is to cancel out the influence of crosstalk noise and the like from other wirings at the time of measurement.
【0013】また、観測用配線の長さのばらつきが大き
いと観測する電源ノイズの伝播時間に差が生じるため、
正しい測定ができなくなる。電源ノイズを正しく観測す
るためには、観測用配線の信号伝播時間のずれを電源ノ
イズの半値幅の例えば5%以下程度に抑える必要があ
る。半導体集積回路のクロック周波数が100MHzの
場合、動作周期は10nsであり、信号の立ち上がり時
間は動作周期の10分の1の1ns程度となる。電源ノ
イズも信号と同等の立ち上がり時間を持つため、電源ノ
イズの半値幅は1〜2nsとなる。これの5%は50〜
100psとなり、通常のLSI内配線の1〜2mm分の
信号伝播時間に相当する。よって、この例の場合、観測
用配線長のばらつきは1〜2mmに抑える必要がある。In addition, if the length of the observation wiring has a large variation, a difference occurs in the propagation time of the observed power supply noise.
Correct measurement cannot be performed. In order to correctly observe the power supply noise, it is necessary to suppress the deviation of the signal propagation time of the observation wiring to, for example, about 5% or less of the half width of the power supply noise. When the clock frequency of the semiconductor integrated circuit is 100 MHz, the operation cycle is 10 ns, and the rise time of the signal is about 1 ns, which is 1/10 of the operation cycle. Since the power supply noise also has the same rise time as the signal, the half width of the power supply noise is 1 to 2 ns. 5% of this is 50 ~
100 ps, which is equivalent to a signal propagation time of 1 to 2 mm of a normal LSI wiring. Therefore, in the case of this example, it is necessary to suppress the variation of the observation wiring length to 1 to 2 mm.
【0014】引き出し配線の抵抗が大きいと波形振幅が
減衰し、また電源ノイズの高周波成分が伝達できなくす
るため、太く短い配線を用い、抵抗を小さくする。電源
ノイズの高周波成分を受信できるようにするため、測定
装置131のプローブはピコプローブなどの入力容量の
小さいものを用いる。If the resistance of the lead wiring is large, the waveform amplitude is attenuated and the high frequency component of the power supply noise cannot be transmitted. Therefore, a thick and short wiring is used and the resistance is reduced. In order to be able to receive the high frequency component of the power supply noise, a probe having a small input capacitance such as a pico probe is used as the probe of the measuring device 131.
【0015】図1に示した実施例以外にも様々なバリエ
ーションが考えられる。実施例では観測用配線を電源配
線に接続するために電源観測用セルを用いている。この
場合、一般セルのレイアウトと同一の手順で電源配線か
らの引き出しが設計できる。しかしこれは本発明の本質
ではなく、他の手段、例えば電源ノイズを観測する場所
に予め電源配線から引き出し線を出しておく、等の方法
を用いてもよい。この場合、電源観測用セルの大きさ分
の余裕が不要となり、観測したい点そのものから観測用
配線を引き出すことができる。Various variations other than the embodiment shown in FIG. 1 are conceivable. In this embodiment, a power supply observation cell is used to connect the observation wiring to the power supply wiring. In this case, the lead-out from the power supply wiring can be designed in the same procedure as the layout of the general cell. However, this is not the essence of the present invention, and other means, for example, a method in which a lead wire is previously drawn from a power supply wiring at a place where power supply noise is observed may be used. In this case, a margin for the size of the power supply observation cell is not required, and the observation wiring can be drawn from the point to be observed.
【0016】[0016]
【発明の効果】本発明によれば、半導体基板上に形成さ
れた電源配線上の電源ノイズを観測することができ、電
源ノイズの解析に極めて有用である。According to the present invention, power supply noise on a power supply wiring formed on a semiconductor substrate can be observed, which is extremely useful for analyzing power supply noise.
【図1】本発明による電源ノイズの測定回路を有する半
導体集積回路の説明図。FIG. 1 is an explanatory diagram of a semiconductor integrated circuit having a power supply noise measuring circuit according to the present invention.
【図2】本発明による電源ノイズの実際の波形と測定波
形の一例を示す波形図。FIG. 2 is a waveform chart showing an example of an actual power supply noise waveform and a measured waveform according to the present invention.
【図3】従来の半導体集積回路における電源ノイズの測
定方法を示す説明図。FIG. 3 is an explanatory diagram showing a method for measuring power supply noise in a conventional semiconductor integrated circuit.
101…回路素子、102…信号配線、111…半導体
基板、112…VSS電源層、113…信号配線層、1
14…VDD電源層、115…表面層、116…半導体
集積回路、121…信号入力端子、122…VSS給電
端子、123…VDD給電端子、131…測定装置、2
01…電源観測用セル、204…VSS観測用配線、2
05…VDD観測用配線、206…VSS観測用端子、
207…VDD観測用端子、301…実線、302…破
線、VDD…電源配線、VDD0…給電点、VDD1…
接続点、VSS…電源配線、VSS0…給電点、VSS
1…接続点。101 circuit element, 102 signal wiring, 111 semiconductor substrate, 112 VSS power supply layer, 113 signal wiring layer, 1
14 VDD power supply layer, 115 surface layer, 116 semiconductor integrated circuit, 121 signal input terminal, 122 VSS power supply terminal, 123 VDD power supply terminal, 131 measuring device, 2
01: power supply observation cell, 204: VSS observation wiring, 2
05: VDD observation wiring, 206: VSS observation terminal,
207: VDD observation terminal, 301: solid line, 302: broken line, VDD: power supply wiring, VDD0: feeding point, VDD1 ...
Connection point, VSS: Power supply wiring, VSS0: Power supply point, VSS
1: Connection point.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 斉藤 達也 東京都国分寺市東恋ケ窪一丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 田中 勝也 東京都国分寺市東恋ケ窪一丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 上村 哲也 東京都国分寺市東恋ケ窪一丁目280番地 株式会社日立製作所中央研究所内 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Tatsuya Saito 1-280 Higashi-Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Central Research Laboratory (72) Inventor Tetsuya Uemura 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.
Claims (1)
記半導体基板上に形成されており上記回路素子に電力を
供給するための電源配線と、上記電源配線の電圧を測定
するための複数個の観測用端子とを有し、上記電源配線
上の複数個の点と上記観測用端子との間を観測用配線を
用いて一対一に接続し、上記観測用配線のそれぞれの配
線長がほぼ等しいことを特徴とする半導体集積回路。1. A circuit element formed on a semiconductor substrate, a power supply line formed on the semiconductor substrate for supplying power to the circuit element, and a plurality of power supply lines for measuring a voltage of the power supply line. And a plurality of points on the power supply wiring are connected one-to-one with the observation terminals using the observation wiring, and the length of each of the observation wirings is A semiconductor integrated circuit characterized by being substantially equal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18624797A JPH1131786A (en) | 1997-07-11 | 1997-07-11 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18624797A JPH1131786A (en) | 1997-07-11 | 1997-07-11 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
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JPH1131786A true JPH1131786A (en) | 1999-02-02 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP18624797A Pending JPH1131786A (en) | 1997-07-11 | 1997-07-11 | Semiconductor integrated circuit |
Country Status (1)
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JP (1) | JPH1131786A (en) |
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1997
- 1997-07-11 JP JP18624797A patent/JPH1131786A/en active Pending
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