JPH11304618A - Semiconductor strain sensor - Google Patents
Semiconductor strain sensorInfo
- Publication number
- JPH11304618A JPH11304618A JP11375698A JP11375698A JPH11304618A JP H11304618 A JPH11304618 A JP H11304618A JP 11375698 A JP11375698 A JP 11375698A JP 11375698 A JP11375698 A JP 11375698A JP H11304618 A JPH11304618 A JP H11304618A
- Authority
- JP
- Japan
- Prior art keywords
- pressure receiving
- semiconductor
- strain
- diaphragm
- receiving diaphragm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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- Measuring Fluid Pressure (AREA)
- Pressure Sensors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、圧力や加速度の検
出に用いる半導体歪みセンサに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor strain sensor used for detecting pressure and acceleration.
【０００２】[0002]
【従来の技術】この種の半導体歪みセンサとしては、例
えば図５に示すように、半導体シリコン基板１を加工し
て形成された受圧ダイアフラム１ｂ上に、受圧ダイアフ
ラム１ｂの歪みを検出するためのピエゾ抵抗素子（ゲー
ジ抵抗）２ａ〜２ｄからなる歪み検出部３を形成し、受
圧ダイアフラム１ｂ以外の半導体シリコン基板１の領域
に歪み検出部３の検出信号を増幅するための増幅回路や
歪み検出部３の出力信号の温度補償を行うための温度補
償回路からなる信号処理回路４ａ〜４ｃの回路素子を形
成したものがある（例えば、特開平７―２５３３７４号
公報参照）。2. Description of the Related Art As a semiconductor strain sensor of this type, for example, as shown in FIG. 5, a piezo for detecting a strain of a pressure receiving diaphragm 1b is formed on a pressure receiving diaphragm 1b formed by processing a semiconductor silicon substrate 1. An amplifying circuit or a distortion detecting unit 3 for forming a distortion detecting unit 3 including resistance elements (gauge resistors) 2a to 2d and amplifying a detection signal of the distortion detecting unit 3 in an area of the semiconductor silicon substrate 1 other than the pressure receiving diaphragm 1b. (See, for example, Japanese Patent Application Laid-Open No. Hei 7-253374) in which circuit elements of signal processing circuits 4a to 4c each including a temperature compensating circuit for performing temperature compensation of the output signal are formed.
【０００３】[0003]
【発明が解決しようとする課題】上記構成の半導体歪み
センサでは、受圧ダイアフラム１ｂ上にはピエゾ抵抗素
子２ａ〜２ｄからなる歪み検出部３しか形成されておら
ず、受圧ダイアフラム１ｂに空き領域があったとして
も、信号処理回路４ａ〜４ｃは、受圧ダイアフラム１ｂ
の変形（歪み）により電気的特性が変化するのを防止す
るために、受圧ダイアフラム１ｂ以外の半導体シリコン
基板１の領域に形成されているので、半導体歪みセンサ
のチップサイズが大きくなるという問題がある。In the semiconductor strain sensor having the above-mentioned structure, only the strain detecting section 3 including the piezoresistive elements 2a to 2d is formed on the pressure receiving diaphragm 1b, and there is no free space in the pressure receiving diaphragm 1b. Even if the signal processing circuits 4a to 4c
Is formed in the region of the semiconductor silicon substrate 1 other than the pressure receiving diaphragm 1b in order to prevent the electric characteristics from changing due to the deformation (strain) of the semiconductor strain sensor, there is a problem that the chip size of the semiconductor strain sensor becomes large. .
【０００４】本発明は上記問題点に鑑みて為されたもの
であり、チップサイズの小型化を図った半導体歪みセン
サを提供することにある。The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor strain sensor with a reduced chip size.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
に、請求項１の発明では、半導体基板を加工して形成さ
れた受圧ダイアフラムに、受圧ダイアフラムの歪みを検
出するゲージ抵抗からなる歪み検出部を形成するととも
に、歪み検出部が形成される受圧ダイアフラムの領域以
外の受圧ダイアフラムの領域に、歪み検出部の検出信号
を信号処理する信号処理回路の能動素子が、能動素子に
流れる電流の方向をピエゾ抵抗係数の小さくなる方向と
一致するようにして形成されており、能動素子の電流方
向がピエゾ抵抗係数の小さくなる方向と一致しているの
で、受圧ダイアフラムの歪みによる能動素子の電気的特
性の変化を低減でき、しかも能動素子を受圧ダイアフラ
ムの空き領域に形成することによって、受圧ダイアフラ
ムの面積を有効に利用し、半導体歪みセンサの小型化を
図ることができる。According to a first aspect of the present invention, there is provided a pressure detecting diaphragm formed by processing a semiconductor substrate, comprising a gauge resistor for detecting a distortion of the pressure receiving diaphragm. The active element of the signal processing circuit that processes the detection signal of the distortion detecting unit is formed in the area of the pressure receiving diaphragm other than the area of the pressure receiving diaphragm in which the distortion detecting unit is formed. Is formed so as to coincide with the direction in which the piezoresistance coefficient decreases, and since the current direction of the active element coincides with the direction in which the piezoresistance coefficient decreases, the electrical characteristics of the active element due to the distortion of the pressure receiving diaphragm. Of the pressure receiving diaphragm can be effectively reduced by forming the active element in the empty area of the pressure receiving diaphragm. And use, it is possible to reduce the size of the semiconductor strain sensor.
【０００６】請求項２の発明では、請求項１の発明にお
いて、上記能動素子はＭＯＳ型電界効果トランジスタか
らなっており、ＭＯＳ型電界効果トランジスタではドレ
イン−ソース間に一方向に電流が流れるため、電流方向
とピエゾ抵抗係数の小さくなる方向とを一致させて、Ｍ
ＯＳ型電界効果トランジスタを受圧ダイアフラム上に形
成することにより、受圧ダイアフラムの歪みによるＭＯ
Ｓ型電界効果トランジスタの電気的特性の変化を低減で
きる。According to a second aspect of the present invention, in the first aspect of the present invention, the active element comprises a MOS type field effect transistor. In the MOS type field effect transistor, a current flows in one direction between a drain and a source. By matching the current direction with the direction in which the piezoresistance coefficient decreases, M
By forming the OS type field effect transistor on the pressure receiving diaphragm, the MO due to the distortion of the pressure receiving diaphragm is reduced.
Changes in the electrical characteristics of the S-type field effect transistor can be reduced.
【０００７】請求項３の発明では、請求項１又は２の発
明において、上記半導体基板がシリコン基板からなり、
上記歪み検出部や上記信号処理回路の間を接続する配線
パターンが多結晶シリコンからなっており、多結晶シリ
コンとシリコン基板の熱膨張係数が略等しいので、温度
変化によってシリコン基板と配線パターンとの間に発生
する熱応力を低減できる。According to a third aspect of the present invention, in the first or second aspect, the semiconductor substrate comprises a silicon substrate;
The wiring pattern connecting the distortion detection unit and the signal processing circuit is made of polycrystalline silicon, and the thermal expansion coefficients of the polycrystalline silicon and the silicon substrate are substantially equal. Thermal stress generated therebetween can be reduced.
【０００８】[0008]
【発明の実施の形態】本実施形態の半導体歪みセンサの
平面図を図１（ａ）に示し、断面図を図１（ｂ）に示
す。この半導体歪みセンサは、半導体基板としての半導
体シリコン基板１をエッチングして凹所１ａを設けるこ
とにより形成された受圧ダイアフラム１ｂ上に、ゲージ
抵抗たるピエゾ抵抗素子２ａ〜２ｄよりなる歪み検出部
３を形成するとともに、歪み検出部３が形成される受圧
ダイアフラム１ｂの領域以外の受圧ダイアフラム１ｂの
領域に、歪み検出部３の検出信号を信号処理する信号処
理回路４ａ〜４ｃの能動素子が、能動素子に流れる電流
の方向をピエゾ抵抗係数の小さくなる方向と一致するよ
うにして形成されている。FIG. 1A is a plan view of a semiconductor strain sensor according to the present embodiment, and FIG. 1B is a cross-sectional view thereof. In this semiconductor strain sensor, a strain detecting section 3 composed of piezoresistive elements 2a to 2d as a gauge resistance is provided on a pressure receiving diaphragm 1b formed by etching a semiconductor silicon substrate 1 as a semiconductor substrate to form a recess 1a. The active elements of the signal processing circuits 4a to 4c for processing the detection signal of the distortion detecting section 3 in the area of the pressure receiving diaphragm 1b other than the area of the pressure receiving diaphragm 1b in which the distortion detecting section 3 is formed. Is formed such that the direction of the current flowing through the piezoresistive element coincides with the direction in which the piezoresistance coefficient decreases.
【０００９】ここで、ｐ型シリコンを例にピエゾ抵抗係
数の結晶軸方向による特性を説明する。図２はｐ型シリ
コンの（００１）面におけるピエゾ抵抗係数を示してお
り、原点からの長さがピエゾ抵抗係数の大きさを表し、
原点からの方向が結晶軸方向を表している。このよう
に、ピエゾ抵抗係数の大きさは結晶軸方向によって異な
るので、ピエゾ抵抗素子２ａ〜２ｄはピエゾ抵抗係数が
最も大きくなる方向、すなわち［１１０］方向や［１ｎ
１０］方向に形成される。ここに、ｎ１は１の否定を示
す記号であり、［１ｎ１０］方向は［１１０］方向に直
交する方向を示している。このピエゾ抵抗係数の結晶軸
方向による電気的特性の変化は抵抗だけではなく、トラ
ンジスタなどの能動素子についても当てはまる。特にＭ
ＯＳ型電界効果トランジスタ（以下、ＭＯＳＦＥＴと略
す）のように、ドレイン・ソース間に一方向に電流が流
れる能動素子では、結晶軸方向によって電気的特性が異
なっている。したがって、受圧ダイアフラム１ｂ上にＭ
ＯＳＦＥＴを形成する場合、ＭＯＳＦＥＴに流れる電流
の方向がピエゾ抵抗係数の小さくなる方向（例えば［０
１０］方向や［１００］方向など）と一致するようにし
て、ＭＯＳＦＥＴを受圧ダイアフラム１ｂに形成するこ
とにより、受圧ダイアフラム１ｂの歪みによるＭＯＳＦ
ＥＴの電気的特性の変化を低減できる。Here, the characteristics of the piezoresistance coefficient depending on the crystal axis direction will be described using p-type silicon as an example. FIG. 2 shows the piezoresistance coefficient on the (001) plane of p-type silicon, and the length from the origin indicates the magnitude of the piezoresistance coefficient.
The direction from the origin indicates the crystal axis direction. As described above, since the magnitude of the piezoresistive coefficient differs depending on the crystal axis direction, the piezoresistive elements 2a to 2d are arranged in the direction in which the piezoresistive coefficient is the largest, that is, in the [110] direction or [1n].
10] direction. Here, n1 is a symbol indicating the negation of 1, and the [1n10] direction indicates a direction orthogonal to the [110] direction. The change in the electrical characteristics of the piezoresistance coefficient depending on the crystal axis direction applies not only to resistance but also to active elements such as transistors. Especially M
In an active element in which a current flows in one direction between a drain and a source, such as an OS type field effect transistor (hereinafter abbreviated as MOSFET), electric characteristics are different depending on a crystal axis direction. Therefore, M
When an OSFET is formed, the direction of the current flowing through the MOSFET decreases in the direction in which the piezoresistance coefficient decreases (for example, [0
10] and [100] directions, the MOSFET is formed on the pressure receiving diaphragm 1b, so that the MOSF due to the distortion of the pressure receiving diaphragm 1b.
Changes in the electrical characteristics of the ET can be reduced.
【００１０】すなわち、信号処理回路４ａ〜４ｃを構成
する能動素子を、ピエゾ抵抗素子２ａ〜２ｄが形成され
る受圧ダイアフラム１ｂの領域以外の受圧ダイアフラム
１ｂの領域に、能動素子の電流方向をピエゾ抵抗係数の
小さくなる方向と一致するようにして形成することによ
り、受圧ダイアフラム１ｂに歪みが発生しても能動素子
の電気的特性の変化を少なくでき、しかも受圧ダイアフ
ラム１ｂの空き領域に信号処理回路４ａ〜４ｃの能動素
子を形成しているので、受圧ダイアフラム１ｂの面積を
有効に利用して、半導体歪みセンサのチップサイズを小
型化することができる。That is, the active elements constituting the signal processing circuits 4a to 4c are connected to the area of the pressure receiving diaphragm 1b other than the area of the pressure receiving diaphragm 1b in which the piezoresistive elements 2a to 2d are formed, and the current direction of the active elements is changed by the piezoresistor. When the pressure receiving diaphragm 1b is formed so as to coincide with the direction in which the coefficient decreases, the change in the electrical characteristics of the active element can be reduced even if the pressure receiving diaphragm 1b is distorted. Since the active elements of 4c to 4c are formed, the chip size of the semiconductor strain sensor can be reduced by effectively utilizing the area of the pressure receiving diaphragm 1b.
【００１１】また本実施形態の半導体歪みセンサでは、
図３に示すように、信号処理回路４ａ〜４ｃを構成する
ＮチャネルＭＯＳＦＥＴ５，５’のソースＳ，Ｓ間や、
各ＮチャネルＭＯＳＦＥＴ５，５’のドレインＤ，Ｄと
他の回路素子（図示せず）又は歪み検出部３との間を、
半導体シリコン基板１上に形成された多結晶シリコンか
らなる配線パターン６により接続している。このよう
に、歪み検出部３や信号処理回路４ａ〜４ｃの間を接続
する配線パターン６は多結晶シリコンから形成されてお
り、多結晶シリコンの熱膨張率が半導体シリコン基板１
の熱膨張率に近いので、配線パターン６にアルミ配線を
用いた場合に比べて、温度変化により半導体シリコン基
板１と配線パターン６との間に発生する熱応力を低減す
ることができる。なお、図３中のＡは、ＮチャネルＭＯ
ＳＦＥＴ５，５’のドレインＤ−ソースＳ間に流れる電
流の方向を示している。Further, in the semiconductor strain sensor of the present embodiment,
As shown in FIG. 3, between the sources S and S of the N-channel MOSFETs 5 and 5 'constituting the signal processing circuits 4a to 4c,
The connection between the drains D, D of the N-channel MOSFETs 5, 5 'and another circuit element (not shown) or the strain detecting unit 3
The connection is made by a wiring pattern 6 made of polycrystalline silicon formed on the semiconductor silicon substrate 1. As described above, the wiring pattern 6 for connecting the distortion detection unit 3 and the signal processing circuits 4a to 4c is formed of polycrystalline silicon, and the coefficient of thermal expansion of polycrystalline silicon is
, The thermal stress generated between the semiconductor silicon substrate 1 and the wiring pattern 6 due to a temperature change can be reduced as compared with the case where aluminum wiring is used for the wiring pattern 6. A in FIG. 3 is an N-channel MO
The direction of the current flowing between the drain D and the source S of the SFETs 5 and 5 'is shown.
【００１２】ところで、歪み検出部３の検出信号を増幅
する増幅回路や検出信号を温度補償するための温度補償
回路からなる信号処理回路４は、例えば図４に示すよう
な演算増幅器ＯＰ１〜ＯＰ３及び抵抗Ｒ１〜Ｒ７を用い
て構成された高入力インピーダンスの差動増幅器からな
り、各抵抗値を調整することによって、ブリッジ接続さ
れたピエゾ抵抗素子からなる歪み検出部３の検出信号の
増幅率を変化させたり、歪み検出部３の検出信号の温度
補償を行うことができる。ここで、演算増幅器ＯＰ１〜
ＯＰ３はＭＯＳＦＥＴなどの能動素子（図示せず）を用
いて構成されており、これらの能動素子は、上述のよう
に能動素子の電流方向がピエゾ抵抗係数の小さくなる方
向と一致するようにして、受圧ダイアフラム１ｂ上に形
成されている。尚、信号処理回路４ａ〜４ｃの回路構成
は上記の回路構成に限定する趣旨のものではなく、歪み
検出部３の検出信号を信号処理して出力する回路であれ
ば、上記以外の構成のものでも良い。The signal processing circuit 4 including an amplifier circuit for amplifying the detection signal of the distortion detecting section 3 and a temperature compensation circuit for temperature-compensating the detection signal includes, for example, operational amplifiers OP1 to OP3 as shown in FIG. It consists of a differential amplifier of high input impedance composed of resistors R1 to R7, and adjusts each resistance value to change the amplification factor of the detection signal of the strain detection unit 3 composed of bridge-connected piezoresistive elements. Or temperature compensation of the detection signal of the distortion detection unit 3 can be performed. Here, the operational amplifiers OP1 to OP1
OP3 is configured using active elements such as MOSFETs (not shown), and these active elements are arranged such that the current direction of the active elements matches the direction in which the piezoresistance coefficient decreases as described above. It is formed on the pressure receiving diaphragm 1b. The circuit configuration of the signal processing circuits 4a to 4c is not intended to be limited to the above-described circuit configuration. Any other circuit may be used as long as it is a circuit that processes the detection signal of the distortion detection unit 3 and outputs the signal. But it is good.
【００１３】また、本実施形態では能動素子としてＭＯ
ＳＦＥＴ５，５’を例に説明を行ったが、能動素子をＭ
ＯＳＦＥＴに限定する趣旨のものではなく、バイポーラ
トランジスタなどの能動素子を用いても良いことは言う
までもない。Further, in the present embodiment, MO is used as an active element.
The description has been given by taking the SFETs 5 and 5 'as an example.
It goes without saying that the present invention is not limited to the OSFET, and an active element such as a bipolar transistor may be used.
【００１４】[0014]
【発明の効果】上述のように、請求項１の発明は、半導
体基板を加工して形成された受圧ダイアフラムに、受圧
ダイアフラムの歪みを検出するゲージ抵抗からなる歪み
検出部を形成するとともに、歪み検出部が形成される受
圧ダイアフラムの領域以外の受圧ダイアフラムの領域
に、歪み検出部の検出信号を信号処理する信号処理回路
の能動素子が、能動素子に流れる電流の方向をピエゾ抵
抗係数の小さくなる方向と一致するようにして形成され
ており、能動素子の電流方向がピエゾ抵抗係数の小さく
なる方向と一致しているので、受圧ダイアフラムの歪み
による能動素子の電気的特性の変化を低減でき、しかも
能動素子を受圧ダイアフラムの空き領域に形成すること
によって、受圧ダイアフラムの面積を有効に利用し、半
導体歪みセンサの小型化を図ることができるという効果
がある。As described above, according to the first aspect of the present invention, a strain detecting portion comprising a gauge resistor for detecting a strain of a pressure receiving diaphragm is formed on a pressure receiving diaphragm formed by processing a semiconductor substrate. In the area of the pressure receiving diaphragm other than the area of the pressure receiving diaphragm in which the detection unit is formed, the active element of the signal processing circuit that processes the detection signal of the distortion detection unit reduces the piezo resistance coefficient in the direction of the current flowing through the active element. Since the current direction of the active element matches the direction in which the piezoresistance coefficient decreases, the change in the electrical characteristics of the active element due to the distortion of the pressure receiving diaphragm can be reduced. By forming the active element in an empty area of the pressure receiving diaphragm, the area of the pressure receiving diaphragm can be effectively used to reduce the size of the semiconductor strain sensor. There is an effect that can be achieved reduction.
【００１５】請求項２の発明は、上記能動素子はＭＯＳ
型電界効果トランジスタからなっており、ＭＯＳ型電界
効果トランジスタではドレイン−ソース間に一方向に電
流が流れるため、電流方向とピエゾ抵抗係数の小さくな
る方向とを一致させて、ＭＯＳ型電界効果トランジスタ
を受圧ダイアフラム上に形成することにより、請求項１
の発明と同様に、受圧ダイアフラムの歪によるＭＯＳ型
電界効果トランジスタの電気的特性の変化を低減できる
という効果がある。According to a second aspect of the present invention, the active element is a MOS
Since the current flows in one direction between the drain and the source in the MOS field effect transistor, the current direction is made to coincide with the direction in which the piezoresistance coefficient decreases, and the MOS field effect transistor is formed. Claim 1 by forming on a pressure receiving diaphragm.
As in the invention of the third aspect, there is an effect that a change in the electrical characteristics of the MOS field effect transistor due to the distortion of the pressure receiving diaphragm can be reduced.
【００１６】請求項３の発明は、上記半導体基板がシリ
コン基板からなり、上記歪み検出部や上記信号処理回路
の間を接続する配線パターンが多結晶シリコンからなっ
ており、多結晶シリコンとシリコン基板の熱膨張係数が
略等しいので、請求項１の発明の効果に加えて、温度変
化によってシリコン基板と配線パターンとの間に発生す
る熱応力を低減できるという効果がある。According to a third aspect of the present invention, the semiconductor substrate is made of a silicon substrate, and the wiring pattern for connecting between the strain detecting section and the signal processing circuit is made of polycrystalline silicon. Has substantially the same thermal expansion coefficient, and in addition to the effect of the first aspect of the invention, there is an effect that thermal stress generated between the silicon substrate and the wiring pattern due to a temperature change can be reduced.
【図１】本実施形態の半導体歪みセンサを示し、（ａ）
は平面図、（ｂ）は断面図である。FIG. 1 shows a semiconductor strain sensor of the present embodiment, and (a)
Is a plan view, and (b) is a sectional view.
【図２】同上に用いる半導体シリコン基板のピエゾ抵抗
係数の特性を説明する図である。FIG. 2 is a diagram illustrating characteristics of a piezoresistance coefficient of the semiconductor silicon substrate used in the above.
【図３】同上に用いる回路素子間の配線を説明する図で
ある。FIG. 3 is a diagram for explaining wiring between circuit elements used in the embodiment.
【図４】同上の信号処理回路を示す回路図である。FIG. 4 is a circuit diagram showing a signal processing circuit of the above.
【図５】従来の半導体歪みセンサを示す平面図である。FIG. 5 is a plan view showing a conventional semiconductor strain sensor.
１ 半導体シリコン基板 １ａ 凹所 １ｂ 受圧ダイアフラム ２ａ〜２ｄ ピエゾ抵抗素子 ３ 歪み検出部 ４ａ〜４ｃ 信号処理回路 REFERENCE SIGNS LIST 1 semiconductor silicon substrate 1 a recess 1 b pressure receiving diaphragm 2 a to 2 d piezoresistive element 3 distortion detector 4 a to 4 c signal processing circuit
Claims (3)
アフラムに、受圧ダイアフラムの歪みを検出するゲージ
抵抗からなる歪み検出部を形成するとともに、歪み検出
部が形成される受圧ダイアフラムの領域以外の受圧ダイ
アフラムの領域に、歪み検出部の検出信号を信号処理す
る信号処理回路の能動素子が、能動素子に流れる電流の
方向をピエゾ抵抗係数の小さくなる方向と一致するよう
にして形成されたことを特徴とする半導体歪みセンサ。1. A pressure detecting diaphragm formed by processing a semiconductor substrate, a strain detecting portion comprising a gauge resistor for detecting distortion of the pressure receiving diaphragm is formed, and a strain detecting portion other than a region of the pressure receiving diaphragm in which the strain detecting portion is formed. In the area of the pressure receiving diaphragm, the active element of the signal processing circuit that processes the detection signal of the distortion detection unit was formed so that the direction of the current flowing through the active element coincided with the direction in which the piezoresistance coefficient decreased. Characteristic semiconductor strain sensor.
スタからなることを特徴とする請求項１記載の半導体歪
みセンサ。2. The semiconductor strain sensor according to claim 1, wherein said active element comprises a MOS field effect transistor.
上記歪み検出部や上記信号処理回路の間を接続する配線
パターンが多結晶シリコンからなることを特徴とする請
求項１又は２記載の半導体歪みセンサ。3. The semiconductor substrate according to claim 1, wherein the semiconductor substrate comprises a silicon substrate.
3. The semiconductor strain sensor according to claim 1, wherein a wiring pattern connecting between the strain detection unit and the signal processing circuit is made of polycrystalline silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11375698A JPH11304618A (en) | 1998-04-23 | 1998-04-23 | Semiconductor strain sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11375698A JPH11304618A (en) | 1998-04-23 | 1998-04-23 | Semiconductor strain sensor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11304618A true JPH11304618A (en) | 1999-11-05 |
Family
ID=14620351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11375698A Withdrawn JPH11304618A (en) | 1998-04-23 | 1998-04-23 | Semiconductor strain sensor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11304618A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002131161A (en) * | 2000-10-27 | 2002-05-09 | Denso Corp | Semiconductor pressure sensor |
| JP2005351901A (en) * | 2004-06-11 | 2005-12-22 | Samsung Electronics Co Ltd | Combined sensor and its manufacturing method |
| JP2009019973A (en) * | 2007-07-11 | 2009-01-29 | Fuji Electric Device Technology Co Ltd | Semiconductor pressure sensor |
| JP2009519454A (en) * | 2005-12-15 | 2009-05-14 | エコル ポリテクニーク | Microelectromechanical system with deformable part and stress sensor |
| JP2013501925A (en) * | 2009-08-11 | 2013-01-17 | ピレオス エルテーデー | Compact infrared light detector, method for manufacturing the same, and infrared light detection system including the infrared light detector |
| JP2015152501A (en) * | 2014-02-17 | 2015-08-24 | セイコーエプソン株式会社 | Physical quantity sensor, electronic apparatus and mobile body |
| WO2021010247A1 (en) * | 2019-07-12 | 2021-01-21 | Ntn株式会社 | Bearing device and spindle device |
| CN113203514A (en) * | 2020-01-30 | 2021-08-03 | 阿自倍尔株式会社 | Pressure sensor |
-
1998
- 1998-04-23 JP JP11375698A patent/JPH11304618A/en not_active Withdrawn
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002131161A (en) * | 2000-10-27 | 2002-05-09 | Denso Corp | Semiconductor pressure sensor |
| JP2005351901A (en) * | 2004-06-11 | 2005-12-22 | Samsung Electronics Co Ltd | Combined sensor and its manufacturing method |
| JP2009519454A (en) * | 2005-12-15 | 2009-05-14 | エコル ポリテクニーク | Microelectromechanical system with deformable part and stress sensor |
| JP2009019973A (en) * | 2007-07-11 | 2009-01-29 | Fuji Electric Device Technology Co Ltd | Semiconductor pressure sensor |
| JP2013501925A (en) * | 2009-08-11 | 2013-01-17 | ピレオス エルテーデー | Compact infrared light detector, method for manufacturing the same, and infrared light detection system including the infrared light detector |
| JP2015152501A (en) * | 2014-02-17 | 2015-08-24 | セイコーエプソン株式会社 | Physical quantity sensor, electronic apparatus and mobile body |
| WO2021010247A1 (en) * | 2019-07-12 | 2021-01-21 | Ntn株式会社 | Bearing device and spindle device |
| JP2021014886A (en) * | 2019-07-12 | 2021-02-12 | Ntn株式会社 | Bearing device and spindle device |
| CN114207305A (en) * | 2019-07-12 | 2022-03-18 | Ntn株式会社 | Bearing device and spindle device |
| CN113203514A (en) * | 2020-01-30 | 2021-08-03 | 阿自倍尔株式会社 | Pressure sensor |
| CN113203514B (en) * | 2020-01-30 | 2022-11-08 | 阿自倍尔株式会社 | Pressure sensor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20050705 |