JPH11274852A - Oscillation circuit - Google Patents
Oscillation circuitInfo
- Publication number
- JPH11274852A JPH11274852A JP7939598A JP7939598A JPH11274852A JP H11274852 A JPH11274852 A JP H11274852A JP 7939598 A JP7939598 A JP 7939598A JP 7939598 A JP7939598 A JP 7939598A JP H11274852 A JPH11274852 A JP H11274852A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- circuit
- resistor
- emitter
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は発振回路に関し、特
に温度変化に対し安定化を図った自励発振方式の発振回
路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillating circuit, and more particularly to an oscillating circuit of a self-excited oscillating method which is stabilized against a change in temperature.
【０００２】[0002]
【従来の技術】この種の温度安定化を図った特開平４−
２３５０５号（文献１）記載の従来の発振回路を回路図
で示す図５を参照すると、この従来の発振回路は、正帰
還信号の供給に応答して所定の発振周波数の発振信号を
発生する差動増幅回路１と、ＬＣＧ回路からなり上記発
振周波数の正帰還信号経路を構成する帰還回路２と、温
度補償用の基準電圧信号を発生増幅し差動増幅回路１の
動作電流を制御するする温度補償回路３とを備える。2. Description of the Related Art This kind of temperature stabilization is disclosed in
Referring to FIG. 5, which is a circuit diagram showing a conventional oscillation circuit described in Japanese Patent No. 23505 (Document 1), the conventional oscillation circuit generates a oscillation signal having a predetermined oscillation frequency in response to the supply of a positive feedback signal. A dynamic amplifier circuit 1, a feedback circuit 2 comprising an LCG circuit and constituting a positive feedback signal path of the oscillation frequency, and a temperature for generating and amplifying a reference voltage signal for temperature compensation and controlling an operating current of the differential amplifier circuit 1. And a compensation circuit 3.
【０００３】差動増幅回路１は、それぞれ一端を電源Ｖ
ＣＣに接続した負荷抵抗Ｒ１，Ｒ２の他端を各々のコレ
クタに接続し差動対を構成するＮＰＮ型のトランジスタ
Ｑ１，Ｑ２と、コレクタをトランジスタＱ１，Ｑ２の共
通接続されたエミッタにエミッタを一端が接地された抵
抗Ｒ５の他端にそれぞれ接続し前記差動対の電流源を構
成するＮＰＮ型のトランジスタＱ３と、各々の１端をト
ランジスタＱ１，Ｑ２の各々のベースに各々の他端をバ
イアス電源ＶＢ１に接続した抵抗Ｒ３，Ｒ４と、一端を
トランジスタＱ２のベースに他端を接地にそれぞれ接続
したコンデンサＣ３とを備える。The differential amplifier circuit 1 has a power supply V at one end.
NPN type transistors Q1 and Q2 forming a differential pair by connecting the other ends of load resistors R1 and R2 connected to CC to respective collectors, and collectors having one end connected to the commonly connected emitters of transistors Q1 and Q2. Are connected to the other ends of the grounded resistors R5, respectively, to form an NPN-type transistor Q3 which constitutes the current source of the differential pair. One end of each is biased to the base of each of the transistors Q1 and Q2. The circuit includes resistors R3 and R4 connected to the power supply VB1, and a capacitor C3 having one end connected to the base of the transistor Q2 and the other end grounded.
【０００４】帰還回路２は、一端をトランジスタＱ２の
コレクタに接続したコンデンサＣ１と、他端をコンデン
サＣ１の他端に一端をトランジスタＱ１のベースにそれ
ぞれ接続したコンデンサＣ２と、一端を結合用のコンデ
ンサＣ１，Ｃ２の共通接続点である各々の他端に他端を
接地したコンデンサＣｏ１と、コンデンサＣｏ１と並列
接続したインダクタンスＬｏ１とインダクタンスＬｏ１
の抵抗分の逆数であるコンダクタンスＧｏ１とを含む。The feedback circuit 2 includes a capacitor C1 having one end connected to the collector of the transistor Q2, a capacitor C2 having the other end connected to the other end of the capacitor C1 and one end connected to the base of the transistor Q1, and a coupling capacitor having one end connected. A capacitor Co1 having the other end grounded to each other end which is a common connection point of C1 and C2, an inductance Lo1 and an inductance Lo1 connected in parallel with the capacitor Co1.
And a conductance Go1 which is the reciprocal of the resistance of
【０００５】温度補償回路３は、基準電圧信号を増幅し
差動増幅回路１の動作電流を制御する演算増幅器３１
と、ベースとコレクタとを共通接続しエミッタを電源Ｖ
ＣＣに接続したＰＮＰ型のトランジスタＱ３１と、エミ
ッタを電源ＶＣＣにベースをトランジスタＱ３１のベー
スに共通接続しこのトランジスタＱ３１とカレントミラ
ー回路を構成するＰＮＰ型のトランジスタＱ３２と、コ
レクタを電源ＶＣＣにベースをトランジスタＱ３２のコ
レクタにエミッタを演算増幅器３１の非反転入力端にそ
れぞれ接続したＮＰＮ型のトランジスタＱ３３と、コレ
クタをトランジスタＱ３１のコレクタにベースをトラン
ジスタＱ３３のエミッタにそれぞれ接続したＮＰＮ型の
トランジスタＱ３４と、コレクタをトランジスタＱ３２
のコレクタにベースをトランジスタＱ３３のエミッタに
それぞれ接続したＮＰＮ型のトランジスタＱ３５と、ト
ランジスタＱ３４，Ｑ３５の各々のコレクタ間に接続し
たコンデンサＣ１２と、演算増幅器３１の反転入力端と
接地間に接続した抵抗Ｒ３３と、出力端と反転入力端間
に接続した抵抗Ｒ３２と、一端をトランジスタＱ３４の
エミッタに接続した抵抗Ｒ３４と、一端を抵抗Ｒ３４の
他端とトランジスタＱ３５のエミッタに他端を接地にそ
れぞれ接続した抵抗Ｒ３５と、一端をトランジスタＱ３
３のエミッタに他端を接地にそれぞれ接続した抵抗Ｒ３
６とを備える。A temperature compensating circuit 3 amplifies a reference voltage signal and controls an operational current of the differential amplifying circuit 1.
And the base and collector are connected in common and the emitter is
A PNP transistor Q31 connected to CC, a PNP transistor Q32 having an emitter connected to the power supply VCC and a base commonly connected to the base of the transistor Q31 to form a current mirror circuit with the transistor Q31, and a collector connected to the power supply VCC. An NPN transistor Q33 having an emitter connected to the non-inverting input terminal of the operational amplifier 31 at the collector of the transistor Q32, an NPN transistor Q34 having a collector connected to the collector of the transistor Q31 and a base connected to the emitter of the transistor Q33, respectively; Collector Q32
, A NPN transistor Q35 having a base connected to the emitter of the transistor Q33, a capacitor C12 connected between the collectors of the transistors Q34 and Q35, and a resistor connected between the inverting input terminal of the operational amplifier 31 and ground. R33, a resistor R32 connected between the output terminal and the inverting input terminal, a resistor R34 having one end connected to the emitter of the transistor Q34, and one end connected to the other end of the resistor R34 and the emitter of the transistor Q35, and the other end connected to ground, respectively. Resistor R35 and one end of transistor Q3
A resistor R3 having the other end connected to ground and the emitter of
6 is provided.
【０００６】次に、図５を参照して、従来の発振回路の
動作について説明すると、この従来の発振回路は、差動
増幅回路１のトランジスタＱ２のコレクタに発生する発
振信号Ｖｏを帰還回路２のコンデンサＣ１、Ｃ２を介し
てトランジスタＱ１のベースに入力信号Ｖｉｎとして正
帰還し、この信号ＶｉｎをこれらトランジスタＱ１，Ｑ
２から成る差動対で増幅する。Next, the operation of the conventional oscillating circuit will be described with reference to FIG. 5. This conventional oscillating circuit applies an oscillating signal Vo generated at the collector of the transistor Q2 of the differential amplifier circuit 1 to the feedback circuit 2 Is positively fed back as an input signal Vin to the base of the transistor Q1 via the capacitors C1 and C2 of the transistors Q1 and Q2.
Amplify with a differential pair consisting of two.
【０００７】帰還回路２の等価回路を示す図６を参照す
ると、この帰還回路２のコンデンサＣｏ１，インダクタ
ンスＬｏ１は、共振回路を形成し、インダクタンスＬｏ
１のコンダクタンスＧｏ１，コンデンサＣ１，Ｃ２を含
めて発振周波数を決定する。信号Ｖｏは、トランジスタ
Ｑ２のコレクタ電圧であり、信号Ｖｉｎはトランジスタ
Ｑ１のベース電圧である。Ｚｉｎは、トランジスタＱ１
のベースから見た差動増幅回路１の入力インピーダンス
である。Referring to FIG. 6 showing an equivalent circuit of the feedback circuit 2, the capacitor Co1 and the inductance Lo1 of the feedback circuit 2 form a resonance circuit, and the inductance Lo is
The oscillation frequency is determined including the conductance Go1 and the capacitors C1 and C2. Signal Vo is the collector voltage of transistor Q2, and signal Vin is the base voltage of transistor Q1. Zin is the transistor Q1
Is the input impedance of the differential amplifier circuit 1 as viewed from the base of FIG.
【０００８】トランジスタＱ１，Ｑ２の各々のベースに
接続した抵抗Ｒ３，Ｒ４は、ベースバイアス抵抗でＶＢ
１はバイアス電源、コンデンサＣ３はバイパスコンデン
サである。The resistors R3 and R4 connected to the respective bases of the transistors Q1 and Q2 are connected to a base bias resistor VB.
1 is a bias power supply, and the capacitor C3 is a bypass capacitor.
【０００９】温度補償回路３は、トランジスタＱ３３の
エミッタからバンドギャップ電圧を基準電圧信号として
出力し、演算増幅器３１に供給する。ここで、トランジ
スタＱ３４，Ｑ３５のエミッタ面積比をＮ：１（Ｎ＞
２）と設定する。演算増幅器３１は、バンドギャップ電
圧対応の基準電圧信号を直流増幅し、差動増幅回路１の
トランジスタＱ３のベースに供給する。The temperature compensating circuit 3 outputs a bandgap voltage from the emitter of the transistor Q33 as a reference voltage signal and supplies it to the operational amplifier 31. Here, the emitter area ratio of the transistors Q34 and Q35 is N: 1 (N>
Set 2). The operational amplifier 31 DC-amplifies the reference voltage signal corresponding to the bandgap voltage and supplies the reference voltage signal to the base of the transistor Q3 of the differential amplifier circuit 1.
【００１０】差動増幅回路１のトランジスタＱ３と抵抗
Ｒ５は差動増幅器の定電流源を構成し、トランジスタＱ
３のベース電位により、差動増幅回路１の定電流Ｉを決
定する。The transistor Q3 and the resistor R5 of the differential amplifier circuit 1 constitute a constant current source of the differential amplifier.
3, the constant current I of the differential amplifier circuit 1 is determined.
【００１１】従来の発振回路の発振周波数ｆｐは、トラ
ンジスタの電流増幅率をｈFEとすると、次式（１）で表
される。 ｆｐ＝１／２π｛Ｌｏ１（Ｃｏ１＋Ｃ１＋Ｃ２＋Ｇｏ１
ｈFE Ｃ１・４／Ｋ１）｝1/2 ここで、Ｋ１は次式で表される。 Ｋ１＝２（１＋Ｒ３２／Ｒ３３）ＶＴｌｎ（Ｎ・Ｒ３５／Ｒ３４）／Ｒ３１ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・（１） 式（１）より、温度の項を含まないため、温度変化に対
して発振周波数ｆｐは一定となる。ただし、式（１）の
成立のための前提条件として次式（２）を満足する必要
がある。The oscillation frequency fp of the conventional oscillation circuit is expressed by the following equation (1), where h FE is the current amplification factor of the transistor. fp = 1 / 2π ｛Lo1 (Co1 + C1 + C2 + Go1
h FE C1 / 4 / K1)｝ 1/2 where K1 is represented by the following equation. K1 = 2 (1 + R32 / R33) VTln (N · R35 / R34) / R31 (1) From the equation (1), since the term of temperature is not included, the oscillation frequency fp is constant with respect to the temperature change. However, it is necessary to satisfy the following equation (2) as a precondition for establishing the equation (1).
【００１２】 （１＋Ｒ３２／Ｒ３３）ＶBE(Q35) ＝ＶBE(Q33)・・・・・・・・・（２） ここで、ＶBE(Q33) ，ＶBE(Q35) はそれぞれトランジス
タＱ３５，Ｑ３３のベース、エミッタ間電圧を示す。し
かし、この従来の発振回路では、式（１）で示すよう
に、基準電圧回路の抵抗Ｒ３２、Ｒ３３と抵抗Ｒ３５，
Ｒ３４の相対抵抗値のばらつきと差動増幅回路１の抵抗
Ｒ５の絶対抵抗値のばらつきにより発振周波数ｆｐが変
化する。(1 + R32 / R33) V BE (Q35) = V BE (Q33) (2) Here, V BE (Q33) and V BE (Q35) are transistors Q35, This shows the base-emitter voltage of Q33. However, in this conventional oscillation circuit, as shown in equation (1), the resistors R32 and R33 and the resistors R35 and R35 of the reference voltage circuit are used.
The oscillation frequency fp changes due to the variation in the relative resistance value of R34 and the variation in the absolute resistance value of the resistor R5 of the differential amplifier circuit 1.
【００１３】一般に、集積回路（ＩＣ）の基板上に形成
される抵抗すなわちＩＣ化抵抗の相対抵抗値のばらつき
は数％程度であるため、温度補償回路３の基準電圧生成
用の抵抗Ｒ３２，Ｒ３３と抵抗Ｒ３５，Ｒ３４の相対抵
抗値ばらつきによる発振周波数の変化は無視出来る。し
かし、絶対抵抗値ばらつきは数＋％程度であるため、差
動増幅回路１の電流源抵抗Ｒ５の絶対抵抗値ばらつきに
より発振周波数ｆｐの変動が大きくなる。In general, the resistance formed on the substrate of the integrated circuit (IC), that is, the variation in the relative resistance value of the IC resistance is about several percent, and therefore, the reference voltage generating resistors R32 and R33 of the temperature compensation circuit 3 are used. The change in the oscillation frequency due to the variation in the relative resistance values of the resistors R35 and R34 can be ignored. However, since the variation in the absolute resistance value is about several +%, the variation in the oscillation frequency fp increases due to the variation in the absolute resistance value of the current source resistor R5 of the differential amplifier circuit 1.
【００１４】また、差動増幅回路１の動作電流Ｉは、次
式（３）で表される。 Ｉ＝２（１＋Ｒ３２／Ｒ３３）Ｖｔ・ｌｎ（ＮＲ３５／Ｒ３４）／Ｒ３１・・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・（３） ここで、Ｖｔはトランジスタのサーマル電圧を示す。The operating current I of the differential amplifier circuit 1 is expressed by the following equation (3). I = 2 (1 + R32 / R33) Vt · ln (NR35 / R34) / R31 (3) Here, Vt indicates a thermal voltage of the transistor.
【００１５】すなわち、差動増幅回路１の動作電流Ｉは
電流源抵抗Ｒ５の絶対抵抗値ばらつきにより大きく変動
する。That is, the operating current I of the differential amplifier circuit 1 fluctuates greatly due to the variation in the absolute resistance of the current source resistor R5.
【００１６】[0016]
【発明が解決しようとする課題】上述した従来の発振回
路は、集積回路上で形成されるＩＣ化抵抗の絶対抵抗値
のばらつきが大きいため、ＩＣ化抵抗である差動増幅回
路の電流源抵抗の絶対抵抗値ばらつきにより発振周波数
の変動が大きくなるという欠点があった。In the above-mentioned conventional oscillation circuit, the variation in the absolute resistance value of the IC resistor formed on the integrated circuit is large, so that the current source resistance of the differential amplifier circuit which is the IC resistor is large. However, there is a disadvantage that the fluctuation of the oscillation frequency becomes large due to the variation of the absolute resistance value.
【００１７】また、上記電流源抵抗の絶対抵抗値ばらつ
きにより差動増幅回路の動作電流も大きく変動し動作の
不安定化要因となるという欠点があった。Further, there is a disadvantage that the operating current of the differential amplifier circuit largely fluctuates due to the variation in the absolute resistance value of the current source resistance, which causes an unstable operation.
【００１８】本発明の目的は、絶対抵抗値のばらつきが
あっても安定な発振周波数で発振し、電流の変動が少な
い発振回路を提供することにある。It is an object of the present invention to provide an oscillation circuit which oscillates at a stable oscillation frequency even if the absolute resistance value varies, and has a small current fluctuation.
【００１９】[0019]
【課題を解決するための手段】本発明の発振回路は、集
積回路基板上に形成されトランジスタと第１の抵抗素子
とを有する増幅回路とこの増幅回路の出力信号の所定の
周波数成分を正帰還し前記増幅回路の入力に供給する帰
還回路とを有する発振回路において、前記集積回路基板
上に形成された複数の第２の抵抗素子の絶対抵抗値のば
らつきに対応する補償電圧を発生し温度変動及び製造工
程に起因する前記抵抗素子の絶対抵抗値のばらつきに対
して前記増幅回路の動作電流の変動を抑圧する温度抵抗
補償手段を備えて構成されている。An oscillation circuit according to the present invention comprises an amplifier circuit formed on an integrated circuit substrate and having a transistor and a first resistance element, and a positive feedback of a predetermined frequency component of an output signal of the amplifier circuit. An oscillation circuit having a feedback circuit for supplying to the input of the amplifier circuit, generating a compensation voltage corresponding to a variation in the absolute resistance value of the plurality of second resistance elements formed on the integrated circuit substrate, and generating a temperature fluctuation. And a temperature resistance compensating means for suppressing a variation in an operation current of the amplifier circuit with respect to a variation in an absolute resistance value of the resistance element caused by a manufacturing process.
【００２０】[0020]
【発明の実施の形態】次に、本発明の第１の実施の形態
を図５と共通の構成要素には共通の参照文字／数字を付
して同様に回路図で示す図１を参照すると、この図に示
す本実施の形態の発振回路は、従来と共通の差動増幅回
路１と、帰還回路２とに加えて、温度補償回路３の代わ
りに温度変動に加えて差動増幅回路１の電流源抵抗Ｒ５
の抵抗値の変動を補償する温度抵抗補償回路４を備え
る。FIG. 1 is a circuit diagram of a first embodiment of the present invention, in which components common to those of FIG. 5 are denoted by common reference characters / numbers. The oscillation circuit according to the present embodiment shown in FIG. 1 includes a differential amplifier circuit 1 and a feedback circuit 2 which are common to the conventional art, and a temperature compensation circuit 3 instead of the temperature compensation circuit 3 in addition to the temperature fluctuation. Current source resistance R5
And a temperature resistance compensating circuit 4 for compensating for the fluctuation of the resistance value of
【００２１】温度抵抗補償回路４は、エミッタを差動増
幅回路１のトランジスタＱ３のベースに接続したＮＰＮ
型のトランジスタＱ４と、ベースとコレクタとを電源Ｖ
ＣＣにエミッタをトランジスタＱ４のコレクタにそれぞ
れ接続したＮＰＮ型のトランジスタＱ５と、コレクタと
ベースとを短絡してトランジスタＱ４のベースに接続し
たＮＰＮ型のトランジスタＱ６と、ベースとコレクタと
を短絡しエミッタを接地に接続したＮＰＮ型のトランジ
スタＱ７と、ベースをトランジスタＱ７のべーに接続し
トランジスタＱ７とカレントミラー回路を構成するＮＰ
Ｎ型のトランジスタＱ８と、コレクタをトランジスタＱ
６のエミッタにベースをトランジスタＱ８のコレクタに
エミッタを接地にそれぞれ接続したＮＰＮ型のトランジ
スタＱ９と、一端をトランジスタＱ４のエミッタに他端
を接地にそれぞれ接続した抵抗Ｒ６と、一端をトランジ
スタＱ５のエミッタに他端をトランジスタＱ４のベース
にそれぞれ接続した抵抗Ｒ７と、一端をトランジスタＱ
６のエミッタに他端をトランジスタＱ７のコレクタにそ
れぞれ接続した抵抗Ｒ８と、一端をトランジスタＱ６の
エミッタに他端をトランジスタＱ８のコレクタにそれぞ
れ接続した抵抗Ｒ９と、一端をトランジスタＱ８のエミ
ッタに他端を接地にそれぞれ接続した抵抗Ｒ１０とを備
える。The temperature resistance compensating circuit 4 has an emitter connected to the base of the transistor Q3 of the differential amplifier circuit 1,
Type transistor Q4 and a base and a collector connected to a power supply V.
An NPN transistor Q5 whose emitter is connected to the collector of the transistor Q4 is connected to CC, an NPN transistor Q6 whose collector and base are short-circuited and connected to the base of the transistor Q4, and a base and collector are short-circuited and the emitter is connected. An NPN transistor Q7 connected to the ground, and an NP connecting the base to the base of the transistor Q7 and forming a current mirror circuit with the transistor Q7.
N-type transistor Q8 and collector Q
6, an NPN transistor Q9 having a base connected to the collector of the transistor Q8 and an emitter connected to the ground, a resistor R6 having one end connected to the emitter of the transistor Q4 and the other end connected to the ground, and one end connected to the emitter of the transistor Q5. A resistor R7 having the other end connected to the base of the transistor Q4, and one end connected to the transistor Q4.
6, a resistor R8 having the other end connected to the collector of the transistor Q7, a resistor R9 having one end connected to the emitter of the transistor Q6 and the other end connected to the collector of the transistor Q8, and one end connected to the emitter of the transistor Q8. And a resistor R10 connected to the ground.
【００２２】次に、図１を参照して本実施の形態の動作
について説明すると、差動増幅回路１と帰還回路２との
動作は従来と共通であるが、ここでは、本発明に関連す
る部分についてさらに詳細に説明する。Next, the operation of the present embodiment will be described with reference to FIG. 1. The operations of the differential amplifier circuit 1 and the feedback circuit 2 are the same as those of the related art, but here, the present invention relates to the present invention. The parts will be described in more detail.
【００２３】まず、帰還回路２の入力信号Ｖｉｎと出力
信号Ｖｏの比Ｖｉｎ／Ｖｏつまり帰還率βは、Ｓ＝ｊω
とすると次式（４）で表される。ここで、ｊは虚数、ω
は角周波数である。 β＝〔Ｚｉｎ／｛Ｚｉｎ＋（１／（ＳＣ１））｝〕×［１／〔Ｃｏ１・Ｓ＋（１ ／（Ｌｏ１Ｓ））＋Ｇｏ１＋１／｛Ｚｉｎ＋（１／（ＳＣ１））｝〕］／（１／ （Ｃｏ１Ｓ））＋［１／〔Ｃｏ１Ｓ＋（１／（Ｌｏ１Ｓ））＋Ｇｏ１＋１／｛Ｚ ｉｎ＋（１／（ＳＣ１））｝〕］・・・・・・・・・・・・・・・・・（４） 式（４）を簡略化すると次式（５）となる。 β＝Ｓ2 ・Ｃ１・Ｃ2 ・Ｚｉｎ／｛（Ｃｏ１＋Ｇｏ１・Ｚｉｎ・Ｃ１＋Ｃ１＋Ｃ ２）Ｓ＋（１／（Ｌｏ１Ｓ））＋Ｇｏ１＋（ＺｉｎＣ１／Ｌｏ１）＋（Ｚｉｎ・ Ｃｏ１・Ｃ１＋Ｚｉｎ・Ｃ１・Ｃ２）Ｓ2 ｝・・・・・・・・・・・・・（５） 差動増幅回路１のオープンゲインをＡとすると発振条件
は、次式（６）で表される。 Ａ・β＝１・・・・・・・・・・・・・・・・・・・・・・・・・・・（６） 式（５），（６）より、次式（７）の関係を得る。 Ａ・Ｓ2 ・Ｃ１・Ｃ2 ・Ｚｉｎ／｛（Ｃｏ１＋Ｇｏ１・Ｚｉｎ・Ｃ１＋Ｃ１＋Ｃ ２）Ｓ＋（１／（Ｌｏ１・Ｓ））＋Ｇｏ１＋（Ｚｉｎ・Ｃ１／Ｌｏ１）＋（Ｚｉ ｎ・Ｃｏ１・Ｃ１＋Ｚｉｎ・Ｃ１・Ｃ２）Ｓ2 ｝＝１・・・・・・・・（７） 高周波になると差動増幅回路１の入力インピーダンスＺ
ｉｎは、純抵抗だけでなくベースエミッタ間容量が影響
するため、次式（８）の値となる。 Ｚｉｎ ｈＦＥ／ｇｍ＋１／（ＳＣπ）＝ｈＦＥ／ｇｍ＋１／Ｓ（τＦ・ｇｍ・ Ｃｊｅ）・・・・・・・・・・・・・・・・・・・・・・・・・・・・（８） ｇｍ＝４ＫＴ／ｑＩ・・・・・・・・・・・・・・・・・・・・・（９） ここで、ｈＦＥはトランジスタの電流増幅率、ｇｍは差
動増幅回路１の相互コンダクタンス、Ｋはボルツマン定
数、Ｔは絶対温度、ｑは電子の電荷量、Ｉは差動増幅回
路１の動作電流、τＦは遷移時間、Ｃｊｅはベースエミ
ッタ間接合容量をそれぞれ示す。式（８），（９）より
差動増幅回路１の入力インピーダンスＺｉｎは、差動増
幅回路１の動作電流Ｉの影響を受けることが分かる。First, the ratio Vin / Vo of the input signal Vin and the output signal Vo of the feedback circuit 2, that is, the feedback ratio β is S = jω
Then, it is expressed by the following equation (4). Where j is an imaginary number, ω
Is the angular frequency. β = [Zin / {Zin + (1 / (SC1))}] × [1 / [Co1 · S + (1 / (Lo1S)) + Go1 + 1 / {Zin + (1 / (SC1))}]] / (1 / ( (Co1S)) + [1 / [Co1S + (1 / (Lo1S)) + Go1 + 1 / {Zin + (1 / (SC1))}]] (4) Equation (4) is simplified to the following equation (5). β = S 2 · C1 · C 2 · Zin / {(Co1 + Go1 · Zin · C1 + C1 + C 2) S + (1 / (Lo1S)) + Go1 + (ZinC1 / Lo1) + (Zin · Co1 · C1 + Zin · C1 · C2) S 2} (5) Assuming that the open gain of the differential amplifier circuit 1 is A, the oscillation condition is expressed by the following equation (6). A · β = 1 (6) From equations (5) and (6), the following equation (7) Get the relationship. A · S 2 · C 1 · C 2 · Zin / ｛(Co 1 + Go 1 · Zin · C 1 + C 1 + C 2) S + (1 / (Lo 1 · S)) + Go 1 + (Zin · C 1 / Lo 1) + (Zin · Co 1 · C 1 + Zin · C 1 · C2) S 2 ｝ = 1 (7) At high frequencies, the input impedance Z of the differential amplifier circuit 1
The value of in is given by the following equation (8) because not only the pure resistance but also the capacitance between the base and the emitter is affected. Zin hFE / gm + 1 / (SCπ) = hFE / gm + 1 / S (τF · gm · Cje) 8) gm = 4KT / qI (9) where hFE is the current amplification factor of the transistor, and gm is the differential amplification circuit 1 Mutual conductance, K is Boltzmann's constant, T is absolute temperature, q is electron charge, I is operating current of differential amplifier circuit 1, τF is transition time, and Cje is base-emitter junction capacitance. Equations (8) and (9) show that the input impedance Zin of the differential amplifier circuit 1 is affected by the operating current I of the differential amplifier circuit 1.
【００２４】式の単純化のためＺｉｎを純抵抗と仮定
し、式（７）の虚数部が零になれば発振条件が成立する
ため、この式（７）より発振条件を求める。Assuming that Zin is a pure resistance for the sake of simplification of the equation, the oscillation condition is satisfied if the imaginary part of the equation (7) becomes zero. Therefore, the oscillation condition is obtained from the equation (7).
【００２５】 （Ｃｏ１＋Ｇｏ１・Ｚｉｎ・Ｃ１＋Ｃ１＋Ｃ２）Ｓ＋（１／（Ｌｏ１Ｓ））＝ ０・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・（１０） 式（１０）にＳ＝ｊωを代入すると、ωは次式（１１）
で表される。 ω＝１／｛Ｌｏ１（Ｃｏ１＋Ｇｏ１・Ｚｉｎ・Ｃ１＋Ｃ１＋Ｃ２）｝1/2 ・・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・（１１） ω＝２πｆであるから、式（１１）より、周波数ｆは、
次式（１２）で表される。 ｆ＝１／２π｛Ｌｏ１（Ｃｏ１＋Ｇｏ１・Ｚｉｎ・Ｃ１＋Ｃ１＋Ｃ２）｝1/2 ・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・（１２） 差動増幅回路１の入力インピーダンスＺｉｎを純抵抗と
仮定すると次式（１３）が得られる。 Ｚｉｎ ｈＦＥ／ｇｍ＝４Ｋ・Ｔ・ｈＦＥ／（ｑ・Ｉ）・・・・・・・（１３） 式（１２），（１３）から、電流Ｉの変化により発振周
波数ｆが変化することが分かる。そこで、本実施の形態
では、差動増幅回路１のトランジスタＱ３に流れる動作
電流ＩＱ３の変動を減少させる。(Co1 + Go1 · Zin · C1 + C1 + C2) S + (1 / (Lo1S)) = 0 0 (10) By substituting S = jω into the equation (10), ω becomes the following equation (11)
It is represented by ω = 1 / {Lo1 (Co1 + Go1 / Zin ・ C1 + C1 + C2)} 1/2 .. (11) Since ω = 2πf, the frequency f is calculated from the equation (11) as follows:
It is expressed by the following equation (12). f = 1 / 2π ｛Lo1 (Co1 + Go1 ・ Zin ・ C1 + C1 + C2)｝ 1/2 ... (12) Assuming that the input impedance Zin of the differential amplifier circuit 1 is a pure resistance, the following equation (13) is obtained. Zin hFE / gm = 4K · T · hFE / (q · I) (13) From equations (12) and (13), it can be seen that the oscillation frequency f changes with the change of the current I. . Therefore, in the present embodiment, the fluctuation of the operating current IQ3 flowing through the transistor Q3 of the differential amplifier circuit 1 is reduced.
【００２６】まず、トランジスタＱ５のエミッタ抵抗Ｒ
５の抵抗値変動による電流ＩＱ３の変動とトランジスタ
Ｑ３，Ｑ４のベース電圧との関係を求める。First, the emitter resistance R of the transistor Q5
The relationship between the fluctuation of the current IQ3 due to the fluctuation of the resistance value of No. 5 and the base voltage of the transistors Q3 and Q4 is obtained.
【００２７】電流ＩＱ３は、トランジスタＱ３のベース
電圧Ｖｂ３とトランジスタＱ３のベース・ミッタ間電圧
ＶＢＥ３と抵抗Ｒ５とより、次式で表される。 Ｖｂ３＝ＶＢＥ３＋Ｒ５・ＩＱ３・・・・・・・・・・・・・・・・（１４） ここで、抵抗Ｒ５の抵抗値がａ倍の変動をすると仮定
し、この抵抗値変動によるベース電圧Ｖｂ３の変化結果
のベース電圧ＶＢ３ｄは次式で表される。 Ｖｂ３ｄ＝ＶＢＥ３＋ａ・Ｒ５・ＩＱ３ｄ・・・・・・・・・・・・（１５） ＩＱ３＝ＩＱ３ｄにするためには式（１４），（１５）
より次式（１６）が成立すればよい。 （ＩＱ３＝ＩＱ３ｄよりＶＢＥ３は一定） Ｖｂ３ｄ＝ａ・Ｖｂ３＋（１−ａ）ＶＢＥ３・・・・・・・・・・・（１６） ベース電圧Ｖｂ３，Ｖｂ３ｄは、次式（１７），（１
８）で表される。 Ｖｂ３＝ＩＱ４・Ｒ６・・・・・・・・・・・・・・・・・・・・・（１７） Ｖｂ３ｄ＝ＩＱ４ｄ・ａＲ６・・・・・・・・・・・・・・・・・（１８） ここで、ＩＱ４，ＩＱ４ｄは、温度抵抗補償回路４のト
ランジスタＱ４に流れる電流とする。The current IQ3 is represented by the following equation based on the base voltage Vb3 of the transistor Q3, the base-mitter voltage VBE3 of the transistor Q3, and the resistor R5. Vb3 = VBE3 + R5.IQ3 (14) Here, it is assumed that the resistance value of the resistor R5 fluctuates by a times, and the base voltage Vb3 due to the fluctuation of the resistance value is obtained. Is obtained by the following equation. Vb3d = VBE3 + aR5.IQ3d (15) In order to make IQ3 = IQ3d, equations (14) and (15) are used.
The following equation (16) should be satisfied. (VBE3 is constant from IQ3 = IQ3d) Vb3d = aVb3 + (1-a) VBE3 (16) The base voltages Vb3 and Vb3d are expressed by the following equations (17) and (1).
8). Vb3 = IQ4 · R6 (17) Vb3d = IQ4d · aR6 (17) (18) Here, IQ4 and IQ4d are currents flowing through the transistor Q4 of the temperature resistance compensation circuit 4.
【００２８】ここで、式（１７），（１８）を式（１
６）に代入すると、次式が得られる。 ＩＱ４ｄ−ＩＱ４＝（１−ａ）ＶＢＥ３／（ａＲ６）・・・・・・・（１９） ここで、電流ＩＱ４，ＩＱ４ｄはトランジスタＱ４のベ
ース電圧Ｖｂ４で設定されるため、それぞれ次式（２
０），（２１）で表される。 Ｖｂ４＝ＶＢＥ４＋ＩＱ４・Ｒ６・・・・・・・・・・・・・・・・（２０） Ｖｂ４ｄ＝ＶＢＥ４ｄ＋ＩＱ４ｄ・ａＲ６・・・・・・・・・・・（２１） ここで、Ｖｂ４，Ｖｂ４ｄはトランジスタＱ４のベース
電圧、ＶＢＥ４，ＶＢＥ４ｄはトランジスタＱ４のベー
スエミッタ間電圧である。式（２０），（２１）より式
（１９）のＩＱ４ｄを削除すると、次式（２２）の関係
を得る。 Ｖｂ４ｄ−Ｖｂ４＝ＶＴ・ｌｎ（ＩＱ４ｄ／ＩＱ４）＋（ａＩＱ４ｄ−ＩＱ４） Ｒ６ Ｖｂ４ｄ−Ｖｂ４＝ＶＴ・ｌｎ〔｛（１−ａ）ＶＢＥ３／（ａＩＱ４Ｒ６）｝＋ １〕＋（１−ａ）ＶＢＥ３＋（ａ−１）ＩＱ４・Ｒ６・・・・・・（２２） 式（２２）は、抵抗Ｒ５の抵抗値変動ａに対する差動増
幅回路１の動作電流ＩＱ３を一定に保つためのトランジ
スタＱ４のベース電圧変化を表したものである。Here, Expressions (17) and (18) are replaced by Expression (1).
Substituting into 6) gives the following equation: IQ4d-IQ4 = (1-a) VBE3 / (aR6) (19) Here, since the currents IQ4 and IQ4d are set by the base voltage Vb4 of the transistor Q4, the following equations (2)
0) and (21). Vb4 = VBE4 + IQ4 · R6 (20) Vb4d = VBE4d + IQ4d · aR6 (21) where Vb4 and Vb4d are The base voltage of the transistor Q4, VBE4, VBE4d, is the base-emitter voltage of the transistor Q4. When IQ4d in Expression (19) is deleted from Expressions (20) and (21), the following Expression (22) is obtained. Vb4d-Vb4 = VT.ln (IQ4d / IQ4) + (aIQ4d-IQ4) R6 Vb4d-Vb4 = VT.ln [{(1-a) VBE3 / (aIQ4R6)} + 1] + (1-a) VBE3 + ( a-1) IQ4 · R6 (22) Equation (22) represents the base voltage of the transistor Q4 for keeping the operating current IQ3 of the differential amplifier circuit 1 constant with respect to the resistance variation a of the resistor R5. It represents a change.
【００２９】ここで、式（２２）の第１項のＶＴは常温
で２６ｍＶと小さい値であるため、この第１項を省略す
ると、トランジスタＱ４のベース電圧変化は次式で表さ
れる。 Ｖｂ４ｄ−Ｖｂ４ （ａ−１）（ＩＱ４・Ｒ６−ＶＢＥ３）・・・・（２３） すなわち、抵抗Ｒ５の抵抗値が高い方向に変動するとト
ランジスタＱ４のベース電圧は高い方向に変動する必要
がある。Here, since VT in the first term of the equation (22) is a small value of 26 mV at room temperature, if this first term is omitted, the change in the base voltage of the transistor Q4 is expressed by the following equation. Vb4d−Vb4 (a−1) (IQ4 · R6-VBE3) (23) That is, when the resistance value of the resistor R5 changes in the high direction, the base voltage of the transistor Q4 needs to change in the high direction.
【００３０】式（２３）より、トランジスタＱ４のベー
ス電圧変化Ｖｂ４ｄ−Ｖｂ４の値が決まれば、他の変数
は中心値で式（２３）の条件を満たすように各変数値を
設定する。When the value of the base voltage change Vb4d-Vb4 of the transistor Q4 is determined from the equation (23), the values of the other variables are set so that the center value satisfies the condition of the equation (23).
【００３１】次に、温度抵抗補償回路４のトランジスタ
Ｑ４のベース電圧変化Ｖｂ４ｄ−Ｖｂ４を求める。Next, a base voltage change Vb4d-Vb4 of the transistor Q4 of the temperature resistance compensating circuit 4 is obtained.
【００３２】ＶＢＥ６，ＶＢＥ９を温度抵抗補償回路４
のトランジスタＱ６，Ｑ９の各々のベースエミッタ間電
圧、ＩＱ６，ＩＱ７，ＩＱ８をトランジスタＱ６，Ｑ
７，Ｑ８の各々の電流とすると、トランジスタＱ４の変
化前後の各々のベース電圧Ｖｂ４，Ｖｂ４ｄは、次式
（２４），（２５）で表される。 Ｖｂ４＝ＶＢＥ６＋ＶＢＥ９＋（Ｒ９／Ｒ１０）ＶＴｌｎ（Ｒ９／Ｒ８）・・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・（２４） Ｖｂ４ｄ＝ＶＢＥ６ｄ＋ＶＢＥ９ｄ＋｛ａＲ９／（ａＲ１０）｝ＶＴｌｎ（ａＲ ９／ａＲ８） ＝ＶＢＥ６ｄ＋ＶＢＥ９ｄ＋（Ｒ９／Ｒ１０）ＶＴｌｎ（Ｒ９／Ｒ８）・・・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・（２５） ここで、（Ｒ９／Ｒ１０）ＶＴｌｎ（Ｒ９／Ｒ８）＝Ｘ
とおくと、トランジスタＱ８，Ｑ７の各々の電流ＩＱ
８，ＩＱ７は次式（２６），（２７）で表される。 ＩＱ８＝（１／Ｒ１０）ＶＴｌｎ（Ｒ９／Ｒ８）・・・・・・・・・（２６） ＩＱ７＝｛Ｒ８／（Ｒ９Ｒ１０）｝ＶＴｌｎ（Ｒ９／Ｒ８）・・・・（２７） ＩＱ６＝ＩＱ７＋ＩＱ８＋ＩＱ９・・・・・・・・・・・・・・・・（２８） 式（２８）を式（２６），（２７）に代入すると、電流
Ｉ３は次式で表される。 ＩＱ９＝ＩＱ６−ＩＱ７＋ＩＱ８ ＝ＩＱ６−｛（Ｒ９＋Ｒ８）／（Ｒ９Ｒ１０）｝ＶＴｌｎ（Ｒ９／Ｒ８）・・・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・（２９） 次に、トランジスタＱ５のベースエミッタ間電圧ＶＢＥ
５を用い、式（２９）を代入して、トランジスタＱ６に
流れる電流ＩＱ６ｄ，ＩＱ６を求める。VBE6 and VBE9 are connected to the temperature resistance compensating circuit 4
And the base-emitter voltage of each of the transistors Q6, Q9, IQ6, IQ7, IQ8
Assuming that the currents are respectively Q7 and Q8, the base voltages Vb4 and Vb4d before and after the change of the transistor Q4 are expressed by the following equations (24) and (25). Vb4 = VBE6 + VBE9 + (R9 / R10) VTln (R9 / R8) (24) Vb4d = VBE6d + VBE9d + {aR9 / (aR10)} VTln (aR9 / aR8) = VBE6d + VBE9d + (R9 / R10) VTln (R9 / R8) (25) where (R9 / R10) VTln (R9 / R8) = X
In other words, the current IQ of each of the transistors Q8 and Q7
8, IQ7 are represented by the following equations (26) and (27). IQ8 = (1 / R10) VTln (R9 / R8) (26) IQ7 = {R8 / (R9R10)} VTln (R9 / R8) (27) IQ6 = IQ7 + IQ8 + IQ9 (28) When the equation (28) is substituted into the equations (26) and (27), the current I3 is expressed by the following equation. IQ9 = IQ6-IQ7 + IQ8 = IQ6-{(R9 + R8) / (R9R10)} VTln (R9 / R8) (29) Next, the base-emitter voltage VBE of the transistor Q5
5, the currents IQ6d and IQ6 flowing through the transistor Q6 are obtained by substituting the equation (29).
【００３３】 ＶＣＣ１＝ＶＢＥ５＋Ｒ７・ＩＱ６＋Ｖｂ４ ＝ＶＢＥ５＋Ｒ７・ＩＱ６＋ＶＴｌｎ（ＩＱ６・ＩＱ９／ＩＳ2 ）＋Ｘ ＝ＶＢＥ５＋Ｒ７・ＩＱ６＋ＶＴｌｎ［（ＩＱ６／ＩＳ2 ）〔ＩＱ６−｛（Ｒ８ ＋Ｒ９）／（Ｒ９Ｒ１０）｝｛ＶＴｌｎ（Ｒ９／Ｒ８）｝〕］・・・（３０） 式（３０）の両項に指数をかけると、次式が得られる。The VCC1 = VBE5 + R7 · IQ6 + Vb4 = VBE5 + R7 · IQ6 + VTln (IQ6 · IQ9 / IS 2) + X = VBE5 + R7 · IQ6 + VTln [(IQ6 / IS 2) [IQ6 - {(R8 + R9) / (R9R10)} {VTln (R9 / R8)｝]] (30) By multiplying both terms of equation (30) by an index, the following equation is obtained.
【００３４】 ＥＸＰ（ＶＣＣ１−ＶＢＥ５−Ｒ７・ＩＱ６−Ｘ） ＝（ＩＱ６2 ／ＩＳ2 ）−（ＩＱ６／ＩＳ2 ）｛（Ｒ８＋Ｒ９）／（Ｒ９Ｒ１０ ）｝｛ＶＴｌｎ（Ｒ９／Ｒ８）｝・・・・・・・・・・・・・・（３１） 指数を級数展開をして近似値を求めると、次式が得られ
る。 ＩＱ６2 −〔｛（Ｒ８＋Ｒ９）／（Ｒ９Ｒ１０）｝｛ＶＴｌｎ（Ｒ９／Ｒ８）｝ −（ＩＳ2 Ｒ７／ＶＴ）〕ＩＱ６−ＩＳ2 ｛１＋（ＶＣＣ１−ＶＢＥ５−Ｘ）／ ＶＴ｝・・・・・・・・・・・・・・・・・・・・・・・・・・（３２） 式（３２）から、ＩＱ６は次式で表される。 ＩＱ６＝［〔｛（Ｒ８＋Ｒ９）／（Ｒ９Ｒ１０）｝｛ＶＴｌｎ（Ｒ９／Ｒ８）｝ −（ＩＳ2 Ｒ７／ＶＴ）〕／２］ ±［〔｛（Ｒ８＋Ｒ９）／（Ｒ９Ｒ１０）｝｛ＶＴｌｎ（Ｒ９／Ｒ８）｝−（Ｉ Ｓ2 Ｒ７／ＶＴ）〕2 ＋４ＩＳ2｛１＋（ＶＣＣ１−ＶＢＥ５−Ｘ）／ＶＴ｝］1 /2 ／２・・・・・・・・・・・・・（３３） 同様にＩＱ６ｄを求めると、次式で表される。 ＩＱ６ｄ＝［〔｛ａ（Ｒ８＋Ｒ９）／ａ2 （Ｒ９Ｒ１０）｝｛ＶＴｌｎ（ａＲ９ ／ａＲ８）｝−（ＩＳ2 ａＲ７／ＶＴ）〕／２］ ±［〔｛ａ（Ｒ８＋Ｒ９）／ａ2 （Ｒ９Ｒ１０）｝｛ＶＴｌｎ（ａＲ９／ａＲ８ ）｝−（ＩＳ2 ａＲ７／ＶＴ）〕2 ＋４ＩＳ2｛１＋（ＶＣＣ１−ＶＢＥ５−Ｘ ）／ＶＴ｝］1/2 ／２ ＝［〔｛（Ｒ８＋Ｒ９）／ａ（Ｒ９Ｒ１０）｝｛ＶＴｌｎ（Ｒ９／Ｒ８）｝−（ ＩＳ2 ａＲ７／ＶＴ）〕／２］ ±［〔｛（Ｒ８＋Ｒ９）／ａ（Ｒ９Ｒ１０）｝｛ＶＴｌｎ（ａＲ９／ａＲ８）｝ −（ＩＳ2 ａＲ７／ＶＴ）〕2 ＋４ＩＳ2｛１＋（ＶＣＣ１−ＶＢＥ５−Ｘ）／ ＶＴ｝］1/2 ／２・・・・・・・・・・・・・・・・・・・・・・（３４） ＩＳが十分小さい値とすると式（３３）と式（３４）は
ＩＱ６ ａ・ＩＱ６ｄとなり、電流ＩＱ６は抵抗Ｒ７，
Ｒ８，Ｒ９，Ｒ１０の抵抗値が増加すると減少する。[0034] EXP (VCC1-VBE5-R7 · IQ6-X) = (IQ6 2 / IS 2) - (IQ6 / IS 2) {(R8 + R9) / (R9R10)} {VTln (R9 / R8)} ··· (31) When an exponent is subjected to series expansion to obtain an approximate value, the following equation is obtained. IQ6 2 - [{(R8 + R9) / ( R9R10)} {VTln (R9 / R8)} - (IS 2 R7 / VT) ] IQ6-IS 2 {1+ (VCC1 -VBE5-X) / VT} ···· (32) From equation (32), IQ6 is represented by the following equation. IQ6 = [[{(R8 + R9) / (R9R10)｝ ｛VTln (R9 / R8)} − (IS 2 R7 / VT)] / 2] ± [[｛(R8 + R9) / (R9R10)｝ ｛VTln (R9 / R8)} - (I S 2 R7 / VT) ] 2 + 4IS 2 {1+ (VCC1 -VBE5-X) / VT}] 1/2/2 ············· (33) Similarly, when IQ6d is obtained, it is expressed by the following equation. IQ6d = [[{a (R8 + R9) / a 2 (R9R10)} {VTln (aR9 / aR8)} - (IS 2 aR7 / VT) ] / 2] ± [[{a (R8 + R9) / a 2 (R9R10) } {VTln (aR9 / aR8) } - (IS 2 aR7 / VT) ] 2 + 4IS 2 {1+ (VCC1 -VBE5-X) / VT}] 1/2 / 2 = [ [{(R8 + R9) / a (R9R10 )} {VTln (R9 / R8 )} - (IS 2 aR7 / VT) ] / 2] ± [[{(R8 + R9) / a (R9R10)} {VTln (aR9 / aR8)} - (IS 2 aR7 / VT )] 2 + 4IS 2 {1+ (VCC1 -VBE5-X) / VT}] is 1/2 / 2 ······················ (34) iS Assuming that the value is sufficiently small, equations (33) and (34) can be expressed as IQ6a · IQ6d. And the current IQ6 is the resistance R7,
It decreases as the resistance of R8, R9, R10 increases.
【００３５】 ＶＣＣ１＝ＶＢＥ５＋Ｒ７・ＩＱ６＋Ｖｂ４・・・・・・・・・（３５） ＶＣＣ１＝ＶＢＥ５ｄ＋ａＲ７・ＩＱ６ｄ＋Ｖｂ４ｄ・・・・・（３６） Ｖｂ４ｄ−Ｖｂ４＝ＶＢＥ５−ＶＢＥ５ｄ＋Ｒ７・ＩＱ６−ａＲ７・ＩＱ６ｄ ＝ＶＢＥ５−ＶＢＥ５ｄ ＝ＶＴｌｎ｛（ＩＱ４＋ＩＱ６）／（ＩＱ４ｄ＋ＩＱ６ｄ）｝・・・・（３７） 電流ＩＱ４及びＩＱ６は、抵抗値が増加すると電流は減
少する。したがって、抵抗値が高い方向に変動するとト
ランジスタＱ４のベース電圧は高い方向に変動する。VCC1 = VBE5 + R7.IQ6 + Vb4 (35) VCC1 = VBE5d + aR7.IQ6d + Vb4d (36) Vb4d-Vb4 = VBE5-VBE5d + R7.IQ6-aR7.IQ5-dVE5 = VE5 = VTln {(IQ4 + IQ6) / (IQ4d + IQ6d)} (37) As for the currents IQ4 and IQ6, the current decreases as the resistance value increases. Therefore, when the resistance value changes in a higher direction, the base voltage of the transistor Q4 changes in a higher direction.
【００３６】以上により、式（２２）で論じたとおり抵
抗Ｒ６〜Ｒ１０の抵抗値変動に対して、差動増幅回路１
の動作電流ＩＱ３の変動を低減することができる。As described above, the differential amplifier circuit 1 does not respond to the fluctuation of the resistance values of the resistors R6 to R10 as discussed in the equation (22).
Of the operating current IQ3 can be reduced.
【００３７】また、Δは温度変動の値とすると、温度特
性は次式で表される。 ΔＩＱ３＝〔ΔＶＢＥ６＋ΔＶＢＥ９＋（Ｒ９／Ｒ１０）｛ＶＴｌｎ（Ｒ９／Ｒ ８）｝−ΔＶＢＥ４−ΔＶＢＥ３〕／ΔＲ５・・・・・・・・（３８） 各トランジスタのＶＢＥの温度変動を同一と考えると、
式（３９）が得られ、式（３９）が最小となるように抵
抗Ｒ８，Ｒ９，Ｒ１０の値を設定する。 ΔＩＱ３＝〔（Ｒ９／Ｒ１０）｛ＶＴｌｎ（Ｒ９／Ｒ８）｝〕／ΔＲ５・・・・ ・・・・・・・・・・・・・・・・・・・・・・・・・（３９） 次に、本実施の形態の発振回路の特性を従来と対比して
それぞれグラフで示す図２を参照して、特性改善効果に
ついて説明すると、まず、図２（Ａ）は、各抵抗の抵抗
値の％で表した変動率に対する差動増幅回路１の動作電
流の変動率を％で示す。この図において、実線Ａで示す
本実施の形態の発振回路の抵抗値変動に対する動作電流
の変動は、点線Ｂで示す従来の発振回路の動作電流の変
動よりも小さい。If Δ is a value of temperature fluctuation, the temperature characteristic is expressed by the following equation. ΔIQ3 = [ΔVBE6 + ΔVBE9 + (R9 / R10) ｛VTln (R9 / R8)｝ − ΔVBE4-ΔVBE3] / ΔR5 (38) Assuming that the temperature fluctuation of the VBE of each transistor is the same,
Equation (39) is obtained, and the values of the resistors R8, R9, and R10 are set so that the equation (39) is minimized. ΔIQ3 = [(R9 / R10) {VTln (R9 / R8)}] / ΔR5 (39) Next, the effect of improving the characteristics of the oscillation circuit of the present embodiment will be described with reference to FIG. 2 which shows the characteristics of the oscillation circuit in comparison with the prior art, and FIG. 2 (A) first shows the resistance of each resistor. The rate of change of the operating current of the differential amplifier circuit 1 with respect to the rate of change expressed in% of the value is shown in%. In this figure, the fluctuation of the operating current with respect to the fluctuation of the resistance value of the oscillation circuit of the present embodiment indicated by the solid line A is smaller than the fluctuation of the operation current of the conventional oscillation circuit indicated by the dotted line B.
【００３８】次に、図２（Ｂ）は、各抵抗の抵抗値の変
動に対する発振周波数の各々の変化を示す。この図にお
いて、実線Ｃで示す本実施の形態の発振回路の抵抗値変
動に対する発振周波数の変動は、点線Ｄで示す従来の発
振回路の発振周波数の変動よりも小さい。Next, FIG. 2B shows a change in the oscillation frequency with respect to a change in the resistance value of each resistor. In this figure, the fluctuation of the oscillation frequency with respect to the fluctuation of the resistance value of the oscillation circuit of the present embodiment indicated by the solid line C is smaller than the fluctuation of the oscillation frequency of the conventional oscillation circuit indicated by the dotted line D.
【００３９】したがって、本実施の形態の発振回路は従
来より抵抗値変動に対する動作電流変化が小さく、発振
周波数変動も小さい安定な発振回路ということができ
る。Therefore, the oscillation circuit according to the present embodiment can be said to be a stable oscillation circuit in which the operating current change with respect to the resistance value fluctuation is small and the oscillation frequency fluctuation is small as compared with the conventional case.
【００４０】次に、本発明の第２の実施の形態を図１と
共通の構成要素には共通の参照文字／数字を付して同様
に回路図で示す図３を参照すると、この図に示す本実施
の形態の発振回路の第１の実施の形態との相違点は、差
動増幅回路１の代わりにコレクタ接地型の増幅器を有す
る増幅回路５と、温度抵抗補償回路４の代わりにコレク
タとベースを短絡してトランジスタＱ５のエミッタにエ
ミッタをトランジスタＱ４のコレクタにそれぞれ接続し
たトランジスタＱ１５をさらに備えた温度抵抗補償回路
４Ａとを備えることである。Next, a second embodiment of the present invention will be described with reference to FIG. 3, which is also shown in a circuit diagram with common reference characters / numerals attached to constituent elements common to FIG. The difference between the oscillation circuit according to the present embodiment and the first embodiment is that an amplifier circuit 5 having a common collector type amplifier in place of the differential amplifier circuit 1 and a collector instead of the temperature resistance compensating circuit 4 are provided. And a temperature resistance compensating circuit 4A further provided with a transistor Q15 in which the base is short-circuited and the emitter is connected to the emitter of the transistor Q5 and the emitter is connected to the collector of the transistor Q4.
【００４１】増幅回路５は、コレクタを電源ＶＣＣにベ
ースを帰還回路２のコンデンサＣ１の一端にエミッタを
コンデンサＣ２の一端にそれぞれ接続したＮＰＮ型のト
ランジスタＱ１０と、コレクタをトランジスタＱ１０の
エミッタにベースを温度抵抗補償回路４Ａのトランジス
タＱ４のエミッタにそれぞれ接続したＮＰＮ型のトラン
ジスタＱ１１と、一端をトランジスタＱ１０のベースに
他端をバイアス電源ＶＢ１にそれぞれ接続した抵抗Ｒ１
１と、一端をトランジスタＱ１１のエミッタに他端を接
地にそれぞれ接続した抵抗Ｒ１２とを備える。The amplifier circuit 5 has an NPN transistor Q10 having a collector connected to the power supply VCC, a base connected to one end of the capacitor C1 of the feedback circuit 2, and an emitter connected to one end of the capacitor C2, and a collector connected to the emitter of the transistor Q10. An NPN transistor Q11 connected to the emitter of the transistor Q4 of the temperature resistance compensation circuit 4A, and a resistor R1 connected at one end to the base of the transistor Q10 and the other end to the bias power supply VB1.
1 and a resistor R12 having one end connected to the emitter of the transistor Q11 and the other end connected to ground.
【００４２】次に、図３を参照して本実施の形態の動作
について説明すると、増幅回路５はトランジスタＱ１０
単体で発振し、トランジスタＱ１０のベースには、コン
デンサＣ１，Ｃ２を介してトランジスタＱ１０のエミッ
タから正帰還をかけている。トランジスタＱ１０に流れ
る電流ＩＱ１０は、トランジスタＱ１１のベース電圧と
抵抗Ｒ１２により設定される。Next, the operation of the present embodiment will be described with reference to FIG.
It oscillates by itself, and positive feedback is applied to the base of the transistor Q10 from the emitter of the transistor Q10 via the capacitors C1 and C2. The current IQ10 flowing through the transistor Q10 is set by the base voltage of the transistor Q11 and the resistor R12.
【００４３】第１の実施の形態と同様に式を解くと電流
ＩＱ１０の抵抗変動による電流安定性は次式（４０）で
表される。ここで、ＶＢＥ１１はトランジスタＱ１１の
ベースエミッタ間電圧を示す。 Ｖｂ４ｄ−Ｖｂ４＝ＶＴｌｎ〔｛（１−ａ）ＶＢＥ１１／（ａＩＱ４Ｒ６）｝＋ １〕＋（１−ａ）ＶＢＥ１１＋（１−ａ）ＩＱ４Ｒ６・・・・・・・（４０） 温度抵抗補償回路４Ａは、温度抵抗補償回路４のトラン
ジスタＱ５の代わりにトランジスタＱ５，Ｑ１５を２段
直列に接続した回路となっており、ＶＢＥ５，ＶＢＥ１
５を、トランジスタＱ５，Ｑ１４のベースエミッタ間電
圧、ＩＱ６，ＩＱ４をトランジスタＱ５，Ｑ４の各々の
電流とすると、式（４０）は次式のようになる。 Ｖｂ４ｄ−Ｖｂ４＝ＶＢＥ５＋ＶＢＥ１５−（ＶＢＥ５ｄ＋ＶＢＥ１５）＋Ｒ７ ・ＩＱ５−ａＲ７・ＩＱ６ｄ・・・・・・・・・・・・・・・・・（４１） トランジスタＱ５，Ｑ１５が同一特性のトランジスタで
あるとすると第１の実施の形態の倍の変動幅を得る事が
できる。 Ｖｂ４ｄ−Ｖｂ４＝２ＶＢＥ−２ＶＢＥ５ｄ ＝２ＶＴｌｎ｛（ＩＱ４＋ＩＱ６）／（ＩＱ４ｄ＋ＩＱ６ｄ）｝・・（４２） 次に、本発明の第３の実施の形態を図１と共通の構成要
素には共通の参照文字／数字を付して同様に回路図で示
す図４を参照すると、この図に示す本実施の形態の発振
回路の第１の実施の形態との相違点は、差動増幅回路１
の代わりに電流源用トランジスタＱ３、抵抗Ｒ１及びベ
ースバイアス電源ＶＢ１を省略しトランジスタＱ１，Ｑ
２の各々のベース抵抗Ｒ３，Ｒ４の他端を温度抵抗補償
回路４ＢのトランジスタＱ４のエミッタに接続した差動
増幅回路１Ａと、温度抵抗補償回路４の代わりにコレク
タとベースを短絡してトランジスタＱ６のエミッタにエ
ミッタを抵抗Ｒ８，Ｒ９の一端にそれぞれ接続したトラ
ンジスタＱ１６をさらに備えた温度抵抗補償回路４Ｂと
を備えることである。When the equation is solved in the same manner as in the first embodiment, the current stability due to the resistance fluctuation of the current IQ10 is expressed by the following equation (40). Here, VBE11 indicates a base-emitter voltage of the transistor Q11. Vb4d-Vb4 = VTln [{(1-a) VBE11 / (aIQ4R6)} + 1] + (1-a) VBE11 + (1-a) IQ4R6 (40) The temperature resistance compensation circuit 4A And a circuit in which transistors Q5 and Q15 are connected in series in two stages instead of the transistor Q5 of the temperature resistance compensating circuit 4, and VBE5 and VBE1
If 5 is the base-emitter voltage of the transistors Q5 and Q14, and IQ6 and IQ4 are the currents of the transistors Q5 and Q4, the equation (40) becomes as follows. Vb4d−Vb4 = VBE5 + VBE15− (VBE5d + VBE15) + R7 · IQ5-aR7 · IQ6d (41) Assuming that the transistors Q5 and Q15 have the same characteristics, A variation width twice as large as that of the first embodiment can be obtained. Vb4d−Vb4 = 2VBE−2VBE5d = 2VTln {(IQ4 + IQ6) / (IQ4d + IQ6d)} (42) Next, the third embodiment of the present invention will be described with reference characters / components common to those in FIG. Referring to FIG. 4, which is also shown in a circuit diagram with numerals, the difference between the oscillation circuit of the present embodiment and the first embodiment shown in FIG.
, The current source transistor Q3, the resistor R1, and the base bias power supply VB1 are omitted, and the transistors Q1, Q
2, a differential amplifier circuit 1A in which the other end of each of the base resistors R3 and R4 is connected to the emitter of the transistor Q4 of the temperature resistance compensating circuit 4B; And a temperature resistance compensating circuit 4B further provided with a transistor Q16 having an emitter connected to one end of each of the resistors R8 and R9.
【００４４】次に、図４を参照して本実施の形態の動作
について説明すると、差動増幅器１Ａは、トランジスタ
Ｑ２のコレクタに発生する信号をコンデンサＣ１，Ｃ２
を介してトランジスタＱ１のベースに正帰還をかけてい
る。差動増幅器１Ａの動作電流はトランジスタＱ１，Ｑ
２のベース電位とこれらトランジスタＱ１，Ｑ２のエミ
ッタに接続された抵抗Ｒ５とで設定される。Next, the operation of the present embodiment will be described with reference to FIG. 4. Differential amplifier 1A transmits signals generated at the collector of transistor Q2 to capacitors C1 and C2.
, A positive feedback is applied to the base of the transistor Q1. The operating current of the differential amplifier 1A is determined by transistors Q1 and Q
2 and a resistor R5 connected to the emitters of the transistors Q1 and Q2.
【００４５】本実施の形態の差動回路１Ａの動作電流Ｉ
Ｒ５の抵抗値変動による電流安定性は、第１の実施の形
態と同様に式を解くと式（４３）で表される。Operation current I of differential circuit 1A of the present embodiment
The current stability due to the change in the resistance value of R5 is expressed by equation (43) by solving the equation as in the first embodiment.
【００４６】ここで、Ｖｂ４はトランジスタＱ４のベー
ス電圧、ＶＢＥ２，ＶＢＥ５はトランジスタＱ２、Ｑ５
のベースエミッタ電圧、ＩＱ４，ＩＱ６はトランジスタ
Ｑ４，Ｑ６の電流である。 Ｖｂ４ｄ−Ｖｂ４＝ＶＴｌｎ〔｛（１−ａ）ＶＢＥ２／（ａＩＱ４Ｒ６）｝＋１ 〕＋（１−ａ）ＶＢＥ４＋（１−ａ）ＩＱ４Ｒ６・・・・・・・（４３） Ｖｂ４ｄ−Ｖｂ４＝ＶＴｌｎ｛（ＩＱ４＋ＩＱ６）／（ＩＱ４ｄ＋ＩＱ６ｄ）・ ・・・・・・・・・・・・・・・・・・・・・・・・・・・・・（４４） また、Δは温度変動の値とすると、差動増幅回路１Ａの
動作電流ＩＲ５の温度特性は、次式で表される。 ΔＩＲ５＝〔ΔＶＢＥ６＋ΔＶＢＥ１６＋ΔＶＢＥ９＋（Ｒ９／Ｒ１０）｛ＶＴ ｌｎ（Ｒ９／Ｒ８）｝−ΔＶＢＥ４〕／ΔＲ５・・・・・・・・（４５） 各トランジスタのベースエミッタ電圧ＶＢＥの温度変動
を同一と考えると、式（４６）が得られ、式（４６）の
分子が最小となるように抵抗Ｒ８，Ｒ９，Ｒ１０の値を
設定する。 ΔＩＲ５＝〔ΔＶＢＥ＋（Ｒ９／Ｒ１０）｛ＶＴｌｎ（Ｒ９／Ｒ８）｝〕／ΔＲ ５・・・・・・・・・・・・・・・・・・・・・・・・・・・・・（４６） Here, Vb4 is the base voltage of the transistor Q4, and VBE2 and VBE5 are the transistors Q2 and Q5.
, The base-emitter voltages IQ4 and IQ6 are the currents of the transistors Q4 and Q6. Vb4d-Vb4 = VTln [{(1-a) VBE2 / (aIQ4R6)} + 1] + (1-a) VBE4 + (1-a) IQ4R6 (43) Vb4d-Vb4 = VTln} ( IQ4 + IQ6) / (IQ4d + IQ6d) (44) Further, when Δ is a value of temperature fluctuation, The temperature characteristic of the operating current IR5 of the differential amplifier circuit 1A is expressed by the following equation. ΔIR5 = [ΔVBE6 + ΔVBE16 + ΔVBE9 + (R9 / R10) ｛VT In (R9 / R8)｝ − ΔVBE4] / ΔR5 (45) Assuming that the temperature fluctuation of the base-emitter voltage VBE of each transistor is the same, Equation (46) is obtained, and the values of the resistors R8, R9, and R10 are set so that the numerator of the equation (46) is minimized. ΔIR5 = [ΔVBE + (R9 / R10) ｛VTln (R9 / R8)｝] / ΔR5 (46)
【００４７】[0047]
【発明の効果】以上説明したように、本発明の発振回路
は、温度変動及び製造工程に起因する抵抗素子の絶対抵
抗値のばらつきに対して補償電圧を発生し増幅回路の動
作電流の変動を抑圧する温度抵抗補償手段を備えること
により、絶対抵抗値のばらつきがあっても、従来より動
作電流変化及び発振周波数変動を大幅に抑圧でき安定な
動作を行うことができるという効果がある。As described above, the oscillation circuit of the present invention generates a compensation voltage for the variation in the absolute resistance value of the resistance element due to the temperature variation and the manufacturing process, and suppresses the variation in the operating current of the amplifier circuit. By providing the temperature resistance compensating means for suppressing, even if there is a variation in the absolute resistance value, there is an effect that a change in the operating current and a change in the oscillating frequency can be significantly suppressed and a stable operation can be performed.
【図１】本発明の発振回路の第１の実施の形態を示す回
路図である。FIG. 1 is a circuit diagram showing a first embodiment of an oscillation circuit according to the present invention.
【図２】本実施の形態の発振回路における動作の一例を
従来と比較して示す特性図である。FIG. 2 is a characteristic diagram showing an example of an operation of the oscillation circuit of the present embodiment in comparison with a conventional example.
【図３】本発明の発振回路の第２の実施の形態を示す回
路図である。FIG. 3 is a circuit diagram showing a second embodiment of the oscillation circuit of the present invention.
【図４】本発明の発振回路の第３の実施の形態を示す回
路図である。FIG. 4 is a circuit diagram showing a third embodiment of the oscillation circuit of the present invention.
【図５】従来の発振回路の一例を示すブロック図であ
る。FIG. 5 is a block diagram illustrating an example of a conventional oscillation circuit.
【図６】図５の帰還回路の等価回路を示す回路図であ
る。FIG. 6 is a circuit diagram showing an equivalent circuit of the feedback circuit of FIG.
１，１Ａ 差動増幅回路 ２ 帰還回路 ３ 温度補償回路 ４，４Ａ，４Ｂ 温度抵抗補償回路 ５ 増幅回路 ３１ 演算増幅器 Ｃ１〜Ｃ３，Ｃ１２，Ｃｏ１ コンデンサ Ｌｏ１ インダクタンス Ｑ１〜Ｑ１０，Ｑ１５，Ｑ１６，Ｑ３１〜Ｑ３５ ト
ランジスタ Ｒ１〜Ｒ１０，Ｒ３１〜Ｒ３６ 抵抗1, 1A Differential amplifier circuit 2 Feedback circuit 3 Temperature compensation circuit 4, 4A, 4B Temperature resistance compensation circuit 5 Amplifier circuit 31 Operational amplifier C1 to C3, C12, Co1 Capacitor Lo1 Inductance Q1 to Q10, Q15, Q16, Q31 to Q35 Transistors R1 to R10, R31 to R36 Resistance
Claims (6)
と第１の抵抗素子とを有する増幅回路とこの増幅回路の
出力信号の所定の周波数成分を正帰還し前記増幅回路の
入力に供給する帰還回路とを有する発振回路において、 前記集積回路基板上に形成された複数の第２の抵抗素子
の絶対抵抗値のばらつきに対応する補償電圧を発生し温
度変動及び製造工程に起因する前記抵抗素子の絶対抵抗
値のばらつきに対して前記増幅回路の動作電流の変動を
抑圧する温度抵抗補償手段を備えることを特徴とする発
振回路。An amplifier circuit formed on an integrated circuit substrate and having a transistor and a first resistance element, and a feedback circuit for positively feeding back a predetermined frequency component of an output signal of the amplifier circuit and supplying the signal to an input of the amplifier circuit An oscillation circuit having a plurality of second resistance elements formed on the integrated circuit substrate, generating a compensation voltage corresponding to a variation in absolute resistance value, and generating a compensation voltage corresponding to a temperature variation and a manufacturing process. An oscillation circuit, comprising: a temperature resistance compensator for suppressing a variation in an operation current of the amplifier circuit with respect to a variation in a resistance value.
の電源に接続された第１の抵抗にベースを前記帰還回路
の出力端と一端がバイアス用電源に接続された第３の抵
抗の他端にそれぞれ接続した第１のトランジスタと、 コレクタを一端が第１の電源に接続された第２の抵抗と
前記帰還回路の入力端にベースを前記帰還回路の入力端
と一端が前記バイアス用電源に接続された第４の抵抗の
他端にエミッタを前記第１のトランジスタのエミッタに
それぞれ接続した第２のトランジスタと、 コレクタを前記第１，第２のトランジスタの共通接続し
たエミッタに接続しエミッタを一端が第２の電源に接続
され前記第１の抵抗素子対応の第５の抵抗の他端にそれ
ぞれ接続しベースに前記補償電圧の供給を受ける第３の
トランジスタとを有する差動増幅回路を備え、 前記温度抵抗補償手段が、エミッタを前記第３のトラン
ジスタのベースに接続した第４のトランジスタと、 ベースとコレクタとを第１の電源にエミッタを前記第４
のトランジスタのコレクタにそれぞれ接続した第５のト
ランジスタと、 コレクタとベースとを短絡して前記第４のトランジスタ
のベースに接続した第６のトランジスタと、 ベースとコレクタとを短絡しエミッタを第２の電源に接
続した第７のトランジスタと、 ベースを前記第７のトランジスタのべーに接続した第８
のトランジスタと、 コレクタを前記第６のトランジスタのエミッタにベース
を前記第８のトランジスタのコレクタにエミッタを前記
第２の電源にそれぞれ接続した第９のトランジスタと、 一端を前記第４のトランジスタのエミッタに他端を前記
第２の電源にそれぞれ接続した第６の抵抗と、 一端を前記第５のトランジスタのエミッタに他端を前記
第４のトランジスタのベースにそれぞれ接続し前記第２
の抵抗素子に対応する第７の抵抗と、 一端を前記第６のトランジスタのエミッタに他端を前記
第７のトランジスタのコレクタにそれぞれ接続し前記第
２の抵抗素子に対応する第８の抵抗と、 一端を前記第６のトランジスタのエミッタに他端を前記
第８のトランジスタのコレクタにそれぞれ接続し前記第
２の抵抗素子に対応する第９の抵抗と、 一端を前記第８のトランジスタのエミッタに他端を前記
第２の電源にそれぞれ接続し前記第２の抵抗素子に対応
する第１０の抵抗とを備えることを特徴とする請求項１
記載の発振回路。2. The amplifying circuit according to claim 1, wherein the collector has a first end connected to the first end.
A first transistor having a base connected to the first resistor connected to the power supply of the first circuit, and a first transistor having one end connected to the output end of the feedback circuit and one end connected to the other end of the third resistor connected to the bias power supply; The second resistor connected to the first power supply and the input terminal of the feedback circuit have a base connected to the input terminal of the feedback circuit and the emitter connected to the other end of the fourth resistor connected at one end to the bias power supply. A second transistor connected to an emitter of the first transistor, a collector connected to a commonly connected emitter of the first and second transistors, an emitter connected to a second power supply at one end, and a first resistor connected to a second power supply; A differential amplifier circuit having a third transistor connected to the other end of the fifth resistor corresponding to the element and receiving the compensation voltage at a base, wherein the temperature resistance compensating means includes an emitter connected to a front end of the fifth resistor. Third and fourth transistors connected to the base of the transistor, the base and collector and a first of the emitters 4 to the power supply
A fifth transistor connected to the collector of the fourth transistor, a sixth transistor connected to the base of the fourth transistor by short-circuiting the collector and base, and a fifth transistor connected to the base of the fourth transistor by short-circuiting the emitter to the second transistor. A seventh transistor connected to a power supply, and an eighth transistor connected to a base of the seventh transistor.
A ninth transistor having a collector connected to the emitter of the sixth transistor, a base connected to the collector of the eighth transistor, and an emitter connected to the second power supply, and one end connected to the emitter of the fourth transistor. A sixth resistor having the other end connected to the second power supply, one end connected to the emitter of the fifth transistor, and the other end connected to the base of the fourth transistor, respectively.
A seventh resistor corresponding to the second resistor element, and an eighth resistor corresponding to the second resistor element having one end connected to the emitter of the sixth transistor and the other end connected to the collector of the seventh transistor. A ninth resistor having one end connected to the emitter of the sixth transistor and the other end connected to the collector of the eighth transistor, and one end connected to the emitter of the eighth transistor; 2. The semiconductor device according to claim 1, further comprising: a tenth resistor connected to the second power source at the other end, the tenth resistor corresponding to the second resistance element.
Oscillation circuit as described.
にベースを前記帰還回路の出力端と一端に前記補償電圧
の供給を受ける第３の抵抗の他端にそれぞれ接続した第
１のトランジスタと、 コレクタを一端が第１の電源に接続された第２の抵抗と
前記帰還回路の入力端にベースを前記帰還回路の入力端
と一端を前記第３の抵抗の一端に接続した第４の抵抗の
他端にエミッタを前記第１のトランジスタのエミッタに
それぞれ接続した第２のトランジスタと、 一端を第２の電源に他端を前記第１，第２のトランジス
タのエミッタにそれぞれ接続した第５の抵抗とを有する
差動増幅回路であることを特徴とする請求項１記載の発
振回路。A first transistor having a collector connected to a first power supply and a base connected to an output terminal of the feedback circuit and one end of a third resistor receiving the supply of the compensation voltage at one end thereof; A second resistor having one end connected to the first power supply, a base connected to the input end of the feedback circuit, a base connected to the input end of the feedback circuit, and one end connected to one end of the third resistance; A second transistor having the other end connected to the emitter of the first transistor, and a fifth transistor having one end connected to the second power supply and the other end connected to the emitters of the first and second transistors, respectively. 2. The oscillation circuit according to claim 1, wherein the oscillation circuit is a differential amplifier circuit having the following resistors.
にベースを前記帰還回路の出力端と一端がバイアス用電
源に接続された第３の抵抗の他端にエミッタを前記帰還
回路の入力端にそれぞれ接続した第１のトランジスタ
と、 コレクタを前記第１のトランジスタのエミッタに一端が
第２の電源に接続された第５の抵抗の他端にそれぞれ接
続しベースに前記補償電圧の供給を受ける第３のトラン
ジスタとを備えることを特徴とする請求項１記載の発振
回路。4. The amplifier circuit has a collector connected to a first power supply, a base connected to an output terminal of the feedback circuit and an emitter connected to the other end of a third resistor having one end connected to a bias power supply and an input terminal of the feedback circuit. A first transistor connected to an end of the first transistor, a collector connected to the emitter of the first transistor, and one end connected to the other end of a fifth resistor connected to a second power supply, and supplying the compensation voltage to a base. 2. The oscillation circuit according to claim 1, further comprising a third transistor for receiving.
た同一特性の２個のトランジスタから構成されることを
特徴とする請求項２記載の発振回路。5. The oscillation circuit according to claim 2, wherein said fifth transistor comprises two transistors connected in series and having the same characteristic.
た同一特性の２個のトランジスタから構成されることを
特徴とする請求項２記載の発振回路。6. The oscillation circuit according to claim 2, wherein said sixth transistor comprises two transistors connected in series and having the same characteristic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07939598A JP3204387B2 (en) | 1998-03-26 | 1998-03-26 | Oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07939598A JP3204387B2 (en) | 1998-03-26 | 1998-03-26 | Oscillation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11274852A true JPH11274852A (en) | 1999-10-08 |
| JP3204387B2 JP3204387B2 (en) | 2001-09-04 |
Family
ID=13688679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07939598A Expired - Fee Related JP3204387B2 (en) | 1998-03-26 | 1998-03-26 | Oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3204387B2 (en) |
-
1998
- 1998-03-26 JP JP07939598A patent/JP3204387B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3204387B2 (en) | 2001-09-04 |
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