JPH11274082A - Group iii nitride semiconductor and fabrication thereof, and group iii nitride semiconductor device - Google Patents
Group iii nitride semiconductor and fabrication thereof, and group iii nitride semiconductor deviceInfo
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- JPH11274082A JPH11274082A JP7544198A JP7544198A JPH11274082A JP H11274082 A JPH11274082 A JP H11274082A JP 7544198 A JP7544198 A JP 7544198A JP 7544198 A JP7544198 A JP 7544198A JP H11274082 A JPH11274082 A JP H11274082A
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- Prior art keywords
- nitride semiconductor
- group iii
- iii nitride
- substrate
- layer
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】Ｓｉ基板とその上にエピタキ
シャル成長された III族窒化物半導体およびこのIII族
窒化物半導体を構成要素とする特に発光素子などの III
族窒化物半導体半導体装置、およびそれらの製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention A Si substrate, a group III nitride semiconductor epitaxially grown thereon, and a group III nitride semiconductor including the group III nitride semiconductor, particularly a light emitting device.
The present invention relates to a group III nitride semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】直接遷移で、しかも光学エネルギーギャ
ップが１．９〜６．２eVの範囲で制御可能なＡｌx Ｇａ
y Ｉｎ1-x-y Ｎ系材料用いたレーザーダイオードや発光
ダイオードが試作されている。Ａｌx Ｇａy Ｉｎ1-x-y
Ｎ系材料を使った上記発光素子は、格子や熱膨張係数の
整合性の良さから、主としてサファイア基板やスピネル
（ＭｇＡｌ2 Ｏ4 ）基板等が広く使われている。そし
て、シリコン（Ｓｉ）やマグネシウム（Ｍｇ）を添加す
ることによるｎ型やｐ型の価電子制御や、Ａｌx Ｇａy
Ｉｎ1-x-y Ｎにおけるｘやｙの値を変えることによる光
学エネルギーギャップの制御が実現され、ダブルへテロ
（ＤＨ）構造のレーザが試作されている。しかし、絶縁
性基板を使用するので基板裏面に電極を取り付けること
ができないため、直列抵抗分が大きく、投入電力当たり
の発光効率が低く、信頼性も高くない。2. Description of the Related Art Al x Ga which is a direct transition and whose optical energy gap can be controlled in the range of 1.9 to 6.2 eV.
Laser diodes and light-emitting diodes using y In 1-xy N-based materials have been experimentally manufactured. Al x Ga y In 1-xy
As the light emitting element using an N-based material, a sapphire substrate, a spinel (MgAl 2 O 4 ) substrate, or the like is widely used mainly because of good matching of lattice and thermal expansion coefficient. Then, silicon (Si) and n-type or p-type and the valence control by addition of magnesium (Mg), Al x Ga y
Control of the optical energy gap by changing the values of x and y in In 1-xy N has been realized, and a laser having a double hetero (DH) structure has been prototyped. However, since an insulating substrate is used, electrodes cannot be attached to the back surface of the substrate, so that the series resistance is large, the luminous efficiency per input power is low, and the reliability is not high.
【０００３】また、炭化ケイ素（ＳｉＣ）基板を使って
基板に電極を有するダブルへテロ（ＤＨ）構造のレーザ
が試作されているが、ＳｉＣ基板は高価である。Further, a laser having a double hetero (DH) structure having an electrode on a substrate using a silicon carbide (SiC) substrate has been experimentally manufactured, but the SiC substrate is expensive.
【０００４】[0004]
【発明が解決しようとする課題】そこで、最も一般的で
基板の劈開により III族窒化物半導体の劈開面も出せ、
また熱膨張係数も近くしかも安価なＳｉ基板上へＧａＮ
などの III族窒化物からなるＤＨ構造を形成することが
望まれている。Ｓｉ基板上に形成された III族窒化物層
はその表面の結晶性の向上のため１ないし数μm 厚さが
必要である。しかしＳｉ基板上に厚さが１μm 以上のエ
ピタキシャル膜を成長すると、割れが生じてしまう。そ
の原因として次の２点が考えられる。Therefore, a cleavage plane of a group III nitride semiconductor can be obtained by cleavage of the most common substrate,
In addition, GaN is deposited on an inexpensive Si substrate with a close thermal expansion coefficient.
It is desired to form a DH structure made of a group III nitride such as The group III nitride layer formed on the Si substrate needs to be 1 to several μm thick in order to improve the crystallinity of the surface. However, when an epitaxial film having a thickness of 1 μm or more is grown on a Si substrate, cracks occur. The following two points can be considered as the cause.
【０００５】１）Ｓｉの格子定数は０．５４３１nmであ
り、Ｓｉ｛1,1,1 ｝面上での原子間隔は０．３８４０nm
（＝５．４３１／√２）となる。これに対して、ＧａＮ
の格子定数は０．３１８９nmであり、格子間隔はＧａＮ
の方が狭く、約１７％の格子不整合が存在し、Ｓｉ｛1,
1,1 ｝面上にヘテロエピタキシャル成長したＧａＮ膜に
は引っ張り応力が発生する。 ２）線膨張係数はＳｉが２．６×１０-6Ｋ-1であるのに
対して、ＧａＮは５．６×１０-6Ｋ-1と大きく、温度を
下げるとＧａＮの収縮の方が大きく、成長温度から室温
に降温する際にＧａＮに引っ張り応力が発生する。1) The lattice constant of Si is 0.5431 nm, and the atomic spacing on the Si {1,1,1} plane is 0.3840 nm.
(= 5.4311 / √2). In contrast, GaN
Has a lattice constant of 0.3189 nm and a lattice spacing of GaN.
Are narrower, there is a lattice mismatch of about 17%, and Si ｛1,
A tensile stress is generated in the GaN film heteroepitaxially grown on the 1,1｝ plane. 2) The coefficient of linear expansion of Si is 2.6 × 10 −6 K −1 , whereas that of GaN is 5.6 × 10 −6 K −1. When the temperature is decreased from the growth temperature to room temperature, tensile stress is generated in GaN.
【０００６】さらにＳｉ基板上にエピタキシャル成長し
たＧａＮエピタキシャル膜には、Ｓｉ基板とＧａＮ層と
の格子不整合によって生じた、基板に垂直方向に成長す
る貫通転位がデバイス特性を劣化させるという問題点も
ある。本発明の目的は、Ｓｉ基板を用いても、貫通転位
が少なく、表面が平坦であり、また割れの生じていない
厚さ１μm 以上のエピタキシャル層を有する III族窒化
物半導体およびその製造方法および III族窒化物半導体
装置を提供することにある。Further, the GaN epitaxial film epitaxially grown on the Si substrate has a problem that threading dislocations growing in a direction perpendicular to the substrate caused by lattice mismatch between the Si substrate and the GaN layer deteriorate device characteristics. . SUMMARY OF THE INVENTION An object of the present invention is to provide a group III nitride semiconductor having an epitaxial layer having a thickness of 1 μm or more which has a small number of threading dislocations, has a flat surface, and has no crack even when a Si substrate is used. An object of the present invention is to provide a group III nitride semiconductor device.
【０００７】[0007]
【課題を解決するための手段】上記の目的を達成するた
めに、Ｓｉ基板上へのＡｌx Ｇａy Ｉｎ1-x-y Ｎ（但
し、０≦ｘ，ｙ≦１、０≦ｘ＋ｙ≦１）からなる III族
窒化物半導体のエピタキシャル成長工程を含む III族窒
化物半導体および半導体装置の製造方法において、前記
Ｓｉ基板上にＳｉの熱酸化膜からなるマスクを形成し、
Ｓｉの露出部に前記 III族窒化物半導体の選択エピタキ
シャル成長を開始し、選択エピタキシャル成長した III
族窒化物層が横方向にも成長して前記マスクを被覆し、
III族窒化物半導体層の表面が平坦になるまでエピタキ
シャル成長を続けることとする。To achieve the above object, according to the solution to ## from Al x Ga y In 1-xy N on Si substrate (where, 0 ≦ x, y ≦ 1,0 ≦ x + y ≦ 1) In the method for manufacturing a group III nitride semiconductor and a semiconductor device including a step of epitaxially growing a group III nitride semiconductor, a mask made of a thermal oxide film of Si is formed on the Si substrate,
Selective epitaxial growth of the group III nitride semiconductor is started on the exposed portion of Si,
A group-nitride layer also grows laterally to cover the mask,
Epitaxial growth is continued until the surface of the group III nitride semiconductor layer becomes flat.
【０００８】前記エピタキシャル成長は、ＭＯＶＰＥま
たはＨＶＰＥにより行われると良い。前記 III族窒化物
層の表面の平坦度は、表面の凹凸は１０nmオーダー以下
であると良い。前記マスクは互いに平行に配置された短
冊状であると良い。The epitaxial growth is preferably performed by MOVPE or HVPE. Regarding the flatness of the surface of the group III nitride layer, the surface irregularities are preferably on the order of 10 nm or less. The masks are preferably strip-shaped arranged in parallel with each other.
【０００９】前記Ｓｉ基板面は｛1,1,1 ｝面であり、前
記短冊状のマスクの長手方向は前記Ｓｉ基板の<1,1,0>
方向であると良い。III族窒化物半導体は上記の III族
窒化物半導体の製造方法により製造されると良い。ま
た、 III族窒化物半導体装置は上記の III族窒化物半導
体を有すると良い。The surface of the Si substrate is a {1,1,1} plane, and the longitudinal direction of the strip-shaped mask is <1,1,0> of the Si substrate.
The direction should be good. The group III nitride semiconductor is preferably manufactured by the method for manufacturing a group III nitride semiconductor described above. Further, the group III nitride semiconductor device preferably includes the above group III nitride semiconductor.
【００１０】前記 III族窒化物半導体装置は発光ダイオ
ードまたはレーザダイオードであると良い。本発明の製
造方法によれば、 III族窒化物半導体は露出しているＳ
ｉ基板表面に選択成長を始め、成長して厚さが増加する
と熱酸化膜の上で基板表面に平行な方向（横方向）への
成長を始める。選択成長部には貫通転移が生じるが、熱
酸化膜の上の横方向成長部には貫通転移は生じない。横
方向成長が進みマスクが被覆され尽くすと、エピタキシ
ャル成長は全体を平坦化するように進む。こうして、１
μm 以上の厚さに達すると、表面は平坦化され、転移の
平均密度は小さくなり、例えば発光素子等の III族窒化
物半導体装置の形成に適した状態になっている。The group III nitride semiconductor device is preferably a light emitting diode or a laser diode. According to the manufacturing method of the present invention, the group III nitride semiconductor is exposed
Selective growth is started on the i-substrate surface, and when the thickness is increased by growth, the growth starts on the thermal oxide film in a direction (lateral direction) parallel to the substrate surface. A threading dislocation occurs in the selective growth portion, but no threading dislocation occurs in the lateral growth portion on the thermal oxide film. As the lateral growth progresses and the mask is completely covered, the epitaxial growth proceeds to planarize the whole. Thus, 1
When the thickness reaches μm or more, the surface is flattened, and the average density of dislocations becomes small, which is suitable for forming a group III nitride semiconductor device such as a light emitting element.
【００１１】このようなエピタキシャル成長には有機金
属気相エピタキシー（ＭＯＶＰＥ）またはハイドライド
気相エピタキシー（ＨＶＰＥ）などが適している。ま
た、熱酸化膜のマスクはＳｉ基板全面に形成しやすく、
短冊状のマスクは長方形の場合が多い半導体装置の形成
には適しており、特にマスクの長手方向が前記Ｓｉ基板
の<1,1,0> 方向であれば、これは劈開面の法線と一致し
ており劈開面を利用する III族窒化物半導体の発光素子
には適している。For such epitaxial growth, metal organic vapor phase epitaxy (MOVPE) or hydride vapor phase epitaxy (HVPE) is suitable. In addition, the thermal oxide film mask is easily formed on the entire surface of the Si substrate,
The strip-shaped mask is suitable for forming a semiconductor device that is often rectangular, and particularly when the longitudinal direction of the mask is the <1,1,0> direction of the Si substrate, this is the normal to the cleavage plane. This is consistent, and is suitable for a group III nitride semiconductor light emitting device using a cleavage plane.
【００１２】[0012]
【発明の実施の形態】実施例１ 図１は本発明に係るＳｉ基板上への III族窒化物半導体
の製造工程後の断面図であり、（ａ）は熱酸化工程後、
（ｂ）は酸化膜のパターニング工程後であり、（ｃ）は
III族窒化物半導体のエピタキシャル成長後である。Embodiment 1 FIG. 1 is a cross-sectional view after a manufacturing process of a group III nitride semiconductor on a Si substrate according to the present invention, and FIG.
(B) after the oxide film patterning step, (c)
After the epitaxial growth of the group III nitride semiconductor.
【００１３】Ｓｉ基板１の基板表面は (1,1,1)面であ
り、断面はＳｉ基板１の (1,0,0)面である。先ず、Ｓｉ
基板１の全面を熱酸化して厚さ１００nmの熱酸化膜２を
形成した（図１（ａ））。フォトリソグラフィにより、
フッ酸溶液エッチングを行い、互いに平行な幅５μm 、
間隔１４μm の短冊状の熱酸化膜のマスク２ａをパター
ニングした（図１（ｂ））。The substrate surface of the Si substrate 1 is the (1,1,1) plane, and the cross section is the (1,0,0) plane of the Si substrate 1. First, Si
The entire surface of the substrate 1 was thermally oxidized to form a thermal oxide film 2 having a thickness of 100 nm (FIG. 1A). By photolithography,
Perform hydrofluoric acid solution etching, width 5 μm parallel to each other,
A strip-shaped thermal oxide film mask 2a with an interval of 14 μm was patterned (FIG. 1B).
【００１４】次に有機金属気相エピタキシー（ＭＯＶＰ
Ｅ）によりＧａＮのエピタキシャル成長を行った。キャ
リアガスとして水素とチッ素の混合ガスを用いた。先
ず、トリメチルアルミニウム（以下ＴＭＡと略記する）
とアンモニア（ＮＨ3 ）で厚さ２０nmのＡｌＮ層を基板
温度６００℃で形成しバッファ層４とした。このとき、
Ｓｉ基板１表面の窒化を防止するためにＴＭＡをＮＨ3
の導入よりも先行して流し始めた。バッファ層４は薄く
してあり、Ｓｉの露出した部分のみに選択的に成長させ
た。次に基板を１０５０℃に昇温し、トリメチルガリウ
ム（以下ＴＭＧと略記する）とＮＨ3 を流して、 III族
窒化物膜５としてＧａＮを形成した（図１（ｃ））。Ｔ
ＭＡやＴＭＧは熱酸化膜上では分解しないので、バッフ
ァ層４上でのみ選択成長が開始され、エピタキシャル成
長が進むと縦方向と同時に基板面に平行に（横方向に）
エピタキシャル成長も進むので、厚さ４μm 程度の成長
を行うと熱酸化膜のマスク２ａの上で段差のない平坦な
表面を有するエピタキシャル層５が得られた。また全面
に亀裂は生じなかった。基板面に垂直方向の貫通転移の
密度は約１０7 ／cm2 個であった。Next, metal organic vapor phase epitaxy (MOVP)
E) epitaxial growth of GaN was performed. A mixed gas of hydrogen and nitrogen was used as a carrier gas. First, trimethyl aluminum (hereinafter abbreviated as TMA)
And an AlN layer having a thickness of 20nm was formed buffer layer 4 at a substrate temperature of 600 ° C. with ammonia (NH 3). At this time,
In order to prevent nitriding of the surface of the Si substrate 1, TMA is NH 3
Began to flow before the introduction of. The buffer layer 4 was made thin, and was selectively grown only on exposed portions of Si. Next, the temperature of the substrate was raised to 1050 ° C., and trimethylgallium (hereinafter abbreviated as TMG) and NH 3 were flowed to form GaN as the group III nitride film 5 (FIG. 1C). T
Since MA and TMG do not decompose on the thermal oxide film, selective growth is started only on the buffer layer 4, and as epitaxial growth proceeds, the epitaxial growth proceeds in the vertical direction and at the same time as the substrate surface (in the horizontal direction).
Since the epitaxial growth proceeds, the epitaxial layer 5 having a flat surface with no steps was obtained on the thermal oxide film mask 2a when the growth was performed to a thickness of about 4 μm. No cracks were formed on the entire surface. The density of threading dislocations in the direction perpendicular to the substrate surface was about 10 7 / cm 2 .
【００１５】比較のため、熱酸化膜の形成されていない
Ｓｉ基板面全面に同じ条件で成膜したところ、ＧａＮの
厚さが１μm 程度に達すると亀裂が生じた。また、基板
面に垂直方向の貫通転移の密度は約１０10／cm2 個であ
り、本発明に係るエピタキシャル層では１／１０００程
度に減少していることが判った。従って、このような貫
通転移密度の低いＧａＮ膜は発光素子に限らずどのよう
な半導体装置にも用いることができる。 実施例２ 図３は本発明に係るＳｉ基板上への III族窒化物半導体
の形成のための短冊状の熱酸化膜の斜視図である。この
場合、短冊状の熱酸化膜マスク２ｍの長手方向はＳｉ基
板１の[1/2,1/2,1] 方向Ｎに平行であり、ＧａＮの劈開
方向[2,-1,-1,0] と一致するＳｉの劈開方向[1,1,0] に
対して垂直となるようにした。また、マスク２ｍの間隔
（Ｓｉ基板面の露出幅）を５μm とした。この上に、実
施例１と同じ条件で、エピタキシャル成長させたバッフ
ァ層４上の厚さ３μm のＧａＮ膜（次の図３ではコンタ
クト層５ａとなる）上に、さらに次の各層をエピタキシ
ャル成長させ、ダブルヘテロ構造を作製した。For comparison, when a film was formed under the same conditions on the entire surface of the Si substrate on which the thermal oxide film was not formed, cracks occurred when the thickness of GaN reached about 1 μm. In addition, the density of threading dislocations in the direction perpendicular to the substrate surface was about 10 10 / cm 2 , which was found to be reduced to about 1/1000 in the epitaxial layer according to the present invention. Therefore, such a GaN film having a low threading dislocation density can be used not only for a light emitting element but also for any semiconductor device. Example 2 FIG. 3 is a perspective view of a strip-shaped thermal oxide film for forming a group III nitride semiconductor on a Si substrate according to the present invention. In this case, the longitudinal direction of the strip-shaped thermal oxide film mask 2m is parallel to the [1 / 2,1 / 2,1] direction N of the Si substrate 1, and the GaN cleavage direction [2, -1, -1,1]. 0] and perpendicular to the cleavage direction [1,1,0] of Si. The interval between the masks 2 m (the exposed width of the Si substrate surface) was set to 5 μm. On this, under the same conditions as in Example 1, the following layers are further epitaxially grown on a 3 μm-thick GaN film on the buffer layer 4 (which will be the contact layer 5a in FIG. 3) on the epitaxially grown buffer layer 4, and A heterostructure was fabricated.
【００１６】図３は本発明に係る外部狭窄構造のレーザ
ダイオードの劈開面での断面図である。層構成は、上記
のＧａＮのコンタクト層上の、厚さ３００nmのｎ型Ａｌ
0.2Ｇａ0.8 Ｎからなる第１のクラッド層５ｂ、厚さ５
０nmのＩｎ0.1 Ｇａ0.9 Ｎからなる活性層５ｃ、厚さ３
００nmのｐ型Ａｌ0.2 Ｇａ0.8 Ｎからなる第２のクラッ
ド層５ｄおよび厚さ３００nmのｐ型ＧａＮからなるコン
タクト層５ｅである。FIG. 3 is a sectional view of a laser diode having an external confinement structure according to the present invention, taken along a cleavage plane. The layer structure is 300 nm thick n-type Al on the GaN contact layer.
First cladding layer 5b of 0.2 Ga 0.8 N, thickness 5
Active layer 5c made of 0nm of In 0.1 Ga 0.9 N, a thickness of 3
A second cladding layer 5d of p-type Al 0.2 Ga 0.8 N of 00 nm and a contact layer 5e of p-type GaN of 300 nm thickness.
【００１７】そして、コンタクト層５ｅには外部電流狭
窄層６としてＳｉＯ2 膜をパターニングした後、Ａｕ／
Ｎｉからなる上部電極７ａを形成した。また、基板１の
裏面にはＡｌ／Ｔｉからなる下部電極７ｂを形成した。 実施例３ 図４は本発明に係る他の実施例を示し、（ａ）は窒化ケ
イ素マスクパターニング工程後、（ｂ）は熱酸化工程
後、（ｃ）は窒化ケイ素マスク除去工程後であり、
（ｄ）は III族窒化物半導体のエピタキシャル成長後で
ある。After patterning a SiO 2 film as the external current confinement layer 6 on the contact layer 5e, Au /
An upper electrode 7a made of Ni was formed. A lower electrode 7b made of Al / Ti was formed on the back surface of the substrate 1. Example 3 FIG. 4 shows another example according to the present invention, wherein (a) is after a silicon nitride mask patterning step, (b) is after a thermal oxidation step, (c) is after a silicon nitride mask removing step,
(D) is after the epitaxial growth of the group III nitride semiconductor.
【００１８】先ず、短冊状のチッ化ケイ素（Ｓｉ
3 Ｎ4 ）層を形成し、パターニングしてマスク３ｍとし
た後（図４（ａ））、マスク３ｍの周縁に潜り込んだ段
差がなく勾配の付いた周縁部（この断面形状を一般にバ
ーズビークという）を有する熱酸化膜のマスク２ｎを選
択酸化により形成し（図４（ｂ））、マスク３ｍを除去
した（図４（ｃ））。そして、実施例１と同じくＡｌＮ
バッファ層４および III族窒化物膜５としてＧａＮをＭ
ＯＶＰＥにより横方向のエピタキシャル成長を行った
（図４（ｄ））。実施例１と同様に、貫通転位密度は低
く、厚さ４μm 程度までは亀裂は生じていなかった。First, strip-shaped silicon nitride (Si)
After forming a 3N 4 ) layer and patterning it to form a mask 3m (FIG. 4 (a)), there is a stepped edge and a sloping edge portion which penetrates the edge of the mask 3m (this cross-sectional shape is generally called bird's beak). Is formed by selective oxidation (FIG. 4B), and the mask 3m is removed (FIG. 4C). Then, as in the first embodiment, AlN
GaN is used as the buffer layer 4 and the group III nitride film 5.
Lateral epitaxial growth was performed by OVPE (FIG. 4D). As in Example 1, the threading dislocation density was low, and no cracks occurred up to a thickness of about 4 μm.
【００１９】[0019]
【発明の効果】本発明によれば、Ｓｉ基板上へのＡｌx
Ｇａy Ｉｎ1-x-y Ｎ（但し、０≦ｘ，ｙ≦１、０≦ｘ＋
ｙ≦１）からなる III族窒化物半導体のエピタキシャル
成長工程を含む III族窒化物半導体および半導体装置の
製造方法において、前記Ｓｉ基板上にＳｉの熱酸化膜か
らなるマスクを形成し、Ｓｉの露出部に前記 III族窒化
物半導体の選択エピタキシャル成長を開始し、選択エピ
タキシャル成長した III族窒化物層が横方向にも成長し
て前記マスクを被覆し、 III族窒化物半導体層の表面が
平坦になるまでエピタキシャル成長を続けるようにした
ため、 III族窒化物半導体はＳｉ基板表面に選択成長
し、成長して厚さが増加すると熱酸化膜の上で基板表面
に平行な方向（横方向）への成長が始まる。選択成長部
には貫通転移が生じるが、熱酸化膜の上の横方向成長部
には貫通転移は生じない。横方向成長が進みマスクが被
覆され尽くすと、エピタキシャル成長は全体を平坦化す
るように進む。こうして、１μm 以上の厚さに達する
と、表面は平坦であり、転移の平均密度は小さくなり、
III族窒化物半導体装置の形成に適した状態になってい
る。その結果、ＤＨ構造や多重量子井戸構造などのレー
ザダイオードの試作が可能になった。According to the present invention, Al x on Si substrate
Ga y In 1-xy N (where, 0 ≦ x, y ≦ 1,0 ≦ x +
In the method for manufacturing a group III nitride semiconductor and a semiconductor device, the method including a step of epitaxially growing a group III nitride semiconductor, wherein y ≦ 1), a mask made of a thermal oxide film of Si is formed on the Si substrate, Then, selective epitaxial growth of the group III nitride semiconductor is started, and the selectively epitaxially grown group III nitride layer also grows in the lateral direction to cover the mask, and is epitaxially grown until the surface of the group III nitride semiconductor layer becomes flat. The group III nitride semiconductor is selectively grown on the surface of the Si substrate, and when it grows and the thickness increases, growth in the direction parallel to the substrate surface (lateral direction) starts on the thermal oxide film. A threading dislocation occurs in the selective growth portion, but no threading dislocation occurs in the lateral growth portion on the thermal oxide film. As the lateral growth progresses and the mask is completely covered, the epitaxial growth proceeds to planarize the whole. Thus, when the thickness reaches 1 μm or more, the surface is flat and the average density of dislocations is low,
It is in a state suitable for forming a group III nitride semiconductor device. As a result, a prototype of a laser diode having a DH structure or a multiple quantum well structure has become possible.
【図１】本発明に係るＳｉ基板上への III族窒化物半導
体の製造工程後の断面図であり、（ａ）は熱酸化工程
後、（ｂ）は酸化膜のパターニング工程後であり、
（ｃ）は III族窒化物半導体のエピタキシャル成長後で
ある。FIG. 1 is a cross-sectional view after a step of manufacturing a group III nitride semiconductor on a Si substrate according to the present invention, (a) after a thermal oxidation step, (b) after a patterning step of an oxide film,
(C) is after the epitaxial growth of the group III nitride semiconductor.
【図２】本発明に係るＳｉ基板上への III族窒化物半導
体の形成のための短冊状の熱酸化膜の斜視図である。FIG. 2 is a perspective view of a strip-shaped thermal oxide film for forming a group III nitride semiconductor on a Si substrate according to the present invention.
【図３】本発明に係る外部狭窄構造のレーザダイオード
の劈開面での断面図である。FIG. 3 is a cross-sectional view along a cleavage plane of a laser diode having an external constriction structure according to the present invention.
【図４】本発明に係る他の実施例の断面図を示し、
（ａ）は窒化ケイ素マスクパターニング工程後、（ｂ）
は熱酸化工程後、（ｃ）は窒化ケイ素マスク除去工程後
であり、（ｄ）は III族窒化物半導体のエピタキシャル
成長後である。FIG. 4 shows a sectional view of another embodiment according to the present invention,
(A) after the silicon nitride mask patterning step, (b)
Shows a state after the thermal oxidation step, (c) shows a state after the silicon nitride mask removing step, and (d) shows a state after the epitaxial growth of the group III nitride semiconductor.
１ シリコン基板 ２ 熱酸化膜 ２ｍ 熱酸化膜マスク ３ｍ 窒化ケイ素膜マスク ４ バッファ層 ５ III族窒化物層 ５ａ コンタクト層 ５ｂ 第１のクラッド層 ５ｃ 活性層 ５ｄ 第２のクラッド層 ５ｅ キャップ層 ６ 外部狭窄層 ７ａ 上部電極 ７ｂ 下部電極 Ｎ Ｓｉ基板の[1,1,1] 方向 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Thermal oxide film 2m Thermal oxide film mask 3m Silicon nitride film mask 4 Buffer layer 5 Group III nitride layer 5a Contact layer 5b First cladding layer 5c Active layer 5d Second cladding layer 5e Cap layer 6 External constriction Layer 7a Upper electrode 7b Lower electrode [1,1,1] direction of N Si substrate
Claims (8)
（但し、０≦ｘ，ｙ≦１、０≦ｘ＋ｙ≦１）からなる I
II族窒化物半導体のエピタキシャル成長工程を含む III
族窒化物半導体および半導体装置の製造方法において、
前記Ｓｉ基板上にＳｉの熱酸化膜からなるマスクを形成
し、Ｓｉの露出部に前記 III族窒化物半導体の選択エピ
タキシャル成長を開始し、選択エピタキシャル成長した
III族窒化物層が横方向にも成長して前記マスクを被覆
し、 III族窒化物半導体層の表面が平坦になるまでエピ
タキシャル成長を続けることを特徴とする III族窒化物
半導体の製造方法。1. A Si Al x Ga y In 1- xy N on a substrate
(Where 0 ≦ x, y ≦ 1, 0 ≦ x + y ≦ 1)
Including epitaxial growth process of group II nitride semiconductor III
In a method for manufacturing a group III nitride semiconductor and a semiconductor device,
A mask made of a thermal oxide film of Si was formed on the Si substrate, selective epitaxial growth of the group III nitride semiconductor was started on the exposed portion of Si, and selective epitaxial growth was performed.
A method for manufacturing a group III nitride semiconductor, comprising: growing a group III nitride layer in the lateral direction to cover the mask; and continuing epitaxial growth until the surface of the group III nitride semiconductor layer becomes flat.
エピタキシー（以下ＭＯＶＰＥと略記）またはハイドラ
イド気相エピタキシー（以下ＨＶＰＥと略記）により行
われることを特徴とする請求項１に記載の III族窒化物
半導体の製造方法。2. The group III nitride semiconductor according to claim 1, wherein said epitaxial growth is performed by metal organic vapor phase epitaxy (hereinafter abbreviated as MOVPE) or hydride vapor phase epitaxy (hereinafter abbreviated as HVPE). Manufacturing method.
面の凹凸は１０nmオーダー以下であることを特徴とする
請求項１または２に記載の III族窒化物半導体の製造方
法。3. The method of manufacturing a group III nitride semiconductor according to claim 1, wherein the surface flatness of the group III nitride layer is such that surface irregularities are on the order of 10 nm or less.
状であることを特徴とする請求項１ないし３に記載の I
II族窒化物半導体の製造方法。4. The method according to claim 1, wherein the mask has a strip shape arranged in parallel with each other.
A method for producing a group II nitride semiconductor.
記短冊状のマスクの長手方向は前記Ｓｉ基板の<1,1,0>
方向であることを特徴とする請求項１ないし４に記載の
III族窒化物半導体の製造方法。5. The Si substrate surface is a {1,1,1} plane, and the longitudinal direction of the strip-shaped mask is <1,1,0> of the Si substrate.
5. The method according to claim 1, wherein the direction is a direction.
A method for producing a group III nitride semiconductor.
導体の製造方法により製造されたことを特徴とする III
族窒化物半導体。6. A group III nitride semiconductor manufactured by the method for manufacturing a group III nitride semiconductor according to claim 1.
Group nitride semiconductor.
することを特徴とする III族窒化物半導体装置。7. A group III nitride semiconductor device comprising the group III nitride semiconductor according to claim 6.
ードまたはレーザダイオードであることを特徴とする請
求項７に記載の III族窒化物半導体装置。8. The group III nitride semiconductor device according to claim 7, wherein said group III nitride semiconductor device is a light emitting diode or a laser diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7544198A JPH11274082A (en) | 1998-03-24 | 1998-03-24 | Group iii nitride semiconductor and fabrication thereof, and group iii nitride semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7544198A JPH11274082A (en) | 1998-03-24 | 1998-03-24 | Group iii nitride semiconductor and fabrication thereof, and group iii nitride semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11274082A true JPH11274082A (en) | 1999-10-08 |
Family
ID=13576341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7544198A Pending JPH11274082A (en) | 1998-03-24 | 1998-03-24 | Group iii nitride semiconductor and fabrication thereof, and group iii nitride semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11274082A (en) |
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