JPH11214540A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH11214540A JPH11214540A JP10009866A JP986698A JPH11214540A JP H11214540 A JPH11214540 A JP H11214540A JP 10009866 A JP10009866 A JP 10009866A JP 986698 A JP986698 A JP 986698A JP H11214540 A JPH11214540 A JP H11214540A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- film
- semiconductor device
- manufacturing
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発名は、半導体装置の製造
方法に関する。The present invention relates to a method for manufacturing a semiconductor device.
【０００２】[0002]
【従来の技術】従来の半導体装置の製造方法は、図２
（ａ）から図２（ｃ）のようであった。2. Description of the Related Art A conventional method of manufacturing a semiconductor device is shown in FIG.
From (a) to FIG. 2 (c).
【０００３】まず、図２（ａ）の如く、半導体基板２０
１上にフィールド絶縁膜２０２を形成し、犠牲酸化膜２
０３を熱酸化法により形成する。[0003] First, as shown in FIG.
1. A field insulating film 202 is formed on the
03 is formed by a thermal oxidation method.
【０００４】次に図２（ｂ）の如く、前記犠牲酸化膜２
０３を除去した後、熱酸化法により、トンネル酸化膜
（もしくはゲート絶縁膜）２０４を形成する。そして、
前記トンネル酸化膜（もしくはゲート絶縁膜）２０４上
に多結晶シリコン膜２０５を形成する。そして、前記多
結晶シリコン膜２０５を低抵抗化させる為に、例えば５
族の元素（燐元素や砒素など撞電性不純物）をイオン打
ち込み法を用いて、１×１０15〜１×１０16ａｔｏｍｓ
・ｃｍ-2程度注入する。Next, as shown in FIG. 2B, the sacrificial oxide film 2 is formed.
After removing 03, a tunnel oxide film (or gate insulating film) 204 is formed by a thermal oxidation method. And
A polycrystalline silicon film 205 is formed on the tunnel oxide film (or gate insulating film) 204. In order to lower the resistance of the polycrystalline silicon film 205, for example, 5
Group 10 elements (consistent impurities such as phosphorus element and arsenic) by ion implantation at 1 × 10 15 to 1 × 10 16 atoms
・ Inject about cm -2 .
【０００５】そして、図２（ｃ）の如く、フォト及びエ
ッチング法により、前記多結晶シリコン膜２０５を所定
形に形成する。以上が従来技術の半導体装置の製造方法
である。Then, as shown in FIG. 2C, the polycrystalline silicon film 205 is formed in a predetermined shape by a photo and etching method. The above is the method of manufacturing a semiconductor device according to the related art.
【０００６】[0006]
【発明が解決しようとする課題】しかし、前述の従来技
術では、トンネル酸化膜の信頼性が悪く、ＥＥＰＲＯＭ
等の不揮発性メモリのデータ書き換え可能な回数が少な
いという問題点やゲート酸化膜のＴＤＤＢ特性が悪く、
製品が早く壊れてしまうという問題点があった。However, in the prior art described above, the reliability of the tunnel oxide film is poor, and
And the TDDB characteristic of the gate oxide film is poor,
There was a problem that the product was broken quickly.
【０００７】そこで、本発明はこの様な問題点を解決す
るもので、その目的とすることは、長期信頼性が高いト
ンネル酸化膜やゲート絶縁膜を提供するところにある。Therefore, the present invention solves such a problem, and an object of the present invention is to provide a tunnel oxide film and a gate insulating film having high long-term reliability.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体装置の製造方法は、半導体基板上に
ゲート絶縁膜を形成する工程、前記ゲート絶縁上に多結
晶シリコンを形成する工程、前記多結晶シリコン中にイ
オン注入を行い、前記多結晶シリコンの一部もしくは全
てをアモルファスシリコン化する工程からなることを特
徴とする。In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a gate insulating film on a semiconductor substrate, and forming polycrystalline silicon on the gate insulating. Forming a part or all of the polycrystalline silicon into amorphous silicon by implanting ions into the polycrystalline silicon.
【０００９】また、本発明の半導体装置の製造方法は、
半導体基板上にトンネル絶縁膜を形成する工程、前記ト
ンネル絶縁上に多結晶シリコンを形成する工程、前記多
結晶シリコン中にイオン注入を行い、前記多結晶シリコ
ンの一部もしくは全てをアモルファスシリコン化する工
程からなることを特徴とする。Further, a method for manufacturing a semiconductor device according to the present invention
Forming a tunnel insulating film on a semiconductor substrate, forming polycrystalline silicon on the tunnel insulating film, performing ion implantation into the polycrystalline silicon, and converting part or all of the polycrystalline silicon to amorphous silicon It is characterized by comprising a process.
【００１０】[0010]
【発明の実施の形態】以下図面により、本発明の実施例
を説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１１】図１は、本発明の半導体装置の製造方法の
一例を表わす断面図である。FIG. 1 is a sectional view showing an example of a method for manufacturing a semiconductor device according to the present invention.
【００１２】なお、実施例の全図において、同一の記号
を有するものには、同一の符号を付け、その繰り返しの
説明は省略する。In all the drawings of the embodiments, those having the same symbols are given the same reference numerals and their repeated explanation is omitted.
【００１３】まず、図１（ａ）の如く、半導体基板１０
１上にシリコン窒化膜を所定形に形成する。そして、熱
酸化を行い、フィールド絶縁膜１０２を形成する。前記
フィールド絶縁膜１０２は、４００ｎｍから８００ｎｍ
程度形成する。前記シリコン窒化膜を除去し、熱酸化法
により前記半導体基板１０１上に犠牲酸化膜１０３を１
５ｎｍから４０ｎｍ程度形成する。First, as shown in FIG.
A silicon nitride film is formed in a predetermined shape on 1. Then, thermal oxidation is performed to form the field insulating film 102. The field insulating film 102 has a thickness of 400 nm to 800 nm.
Degree formed. The silicon nitride film is removed, and a sacrificial oxide film 103 is formed on the semiconductor substrate 101 by thermal oxidation.
It is formed to a thickness of about 5 nm to 40 nm.
【００１４】次に図１（ｂ）の如く、前記犠牲酸化膜１
０３を除去した後、前記半導体基板１０１上にトンネル
酸化膜（もしくは、ゲート絶縁膜）１０４を１０ｎｍ程
度形成する。そして、前記トンネル酸化膜（もしくは、
ゲート絶縁膜）１０４及び、前記フィールド絶縁膜１０
２上に多結晶シリコン膜１０５を形成する。通常モノシ
ランガスを６２０度前後で熱分解させ、前記多結晶シリ
コン膜１０５を堆積させる。そして、前記多結晶シリコ
ン膜１０５中にイオン注入法１０６を用い、前記多結晶
シリコン膜中にＡｒ等の不活性物質もしくは、ガリウム
やゲルマニウム等の物質を１×１０13〜1×１０16ａｔ
ｏｍｓ・ｃｍ-2程度注入する。そして、前記多結晶シリ
コン膜１０５を低抵抗化させる為に、例えば５族の元素
（燐元素や砒素など導電性不純物）をイオン打ち込み法
を用いて、１×１０15〜１×１０16ａｔｏｍｓ・ｃｍ-2
程度注入する。Next, as shown in FIG. 1B, the sacrificial oxide film 1 is formed.
After removing 03, a tunnel oxide film (or gate insulating film) 104 is formed on the semiconductor substrate 101 to a thickness of about 10 nm. And the tunnel oxide film (or
Gate insulating film) 104 and the field insulating film 10
A polycrystalline silicon film 105 is formed on 2. Normally, monosilane gas is thermally decomposed at about 620 degrees to deposit the polycrystalline silicon film 105. Then, an inert substance such as Ar or a substance such as gallium or germanium is introduced into the polycrystalline silicon film 105 by an ion implantation method 106 into the polycrystalline silicon film 105 at 1 × 10 13 to 1 × 10 16 at.
oms · cm −2 is implanted. Then, in order to lower the resistance of the polycrystalline silicon film 105, for example, an element of group V (conductive impurity such as phosphorus element or arsenic) is ion-implanted to a concentration of 1 × 10 15 to 1 × 10 16 atoms. cm -2
About to inject.
【００１５】そして、図１（ｃ）の如く、フォト及びエ
ッチング法により、前記多結晶シリコン膜１０５を所定
形に形成することによりゲート電極もしくは、フローテ
ィングゲートを形成する。Then, as shown in FIG. 1C, a gate electrode or a floating gate is formed by forming the polycrystalline silicon film 105 into a predetermined shape by a photo and etching method.
【００１６】以上が本発明の半導体装置の製造方法であ
る。The above is the method of manufacturing a semiconductor device according to the present invention.
【００１７】このように、トンネル酸化膜もしくは、ゲ
ート絶縁膜上に多結晶シリコン膜を形成した後、アルゴ
ン等の不純物を前記多結晶シリコン膜に注入することに
より、前記多結晶シリコン膜がアモルファスシリコン化
される。そして、このイオン注入を行ってから、前記多
結晶シリコン膜を低抵抗化すると、従来技術で形成した
トンネル酸化膜やゲート絶縁膜に比べ、ＴＤＤＢ特性や
Ｑｂｄ特性が著しく向上することが実験により明らかに
なった。As described above, after the polycrystalline silicon film is formed on the tunnel oxide film or the gate insulating film, an impurity such as argon is implanted into the polycrystalline silicon film so that the polycrystalline silicon film becomes amorphous silicon. Be transformed into Experiments have revealed that when the resistance of the polycrystalline silicon film is reduced after the ion implantation, the TDDB characteristics and the Qbd characteristics are remarkably improved as compared with the tunnel oxide film and the gate insulating film formed by the conventional technique. Became.
【００１８】以上本発明を実施例に基ずき、具体的に説
明したが、本発明は、前記実施例に限定されるものでは
なく、その要旨を逸脱しない範囲において、変形し得る
ことは無論である。例えば、本発明の半導体装置の製造
方法の実施では、ゲート電極に多結晶シリコン膜を用い
たが、高融点金属シリサイド等を用いた場合でも有効で
あることはいうまでもない。Although the present invention has been described in detail with reference to the embodiments, the present invention is not limited to the above-described embodiments, but may be modified without departing from the scope of the invention. It is. For example, in the method of manufacturing a semiconductor device according to the present invention, a polycrystalline silicon film is used for the gate electrode.
【００１９】[0019]
【発明の効果】本発明によれば、トンネル酸化膜もしく
は、ゲート絶縁膜上の多結晶シリコン膜を形成した後、
前記多結晶シリコン膜中にアルゴン等の不純物を注入す
ることにより、前記多結晶シリコン膜がアモルファス化
され、従来に比べ、著しく長期信頼性が良いトンネル酸
化膜やゲート絶縁膜を持つ半導体装置を提供することが
可能になる。According to the present invention, after forming a tunnel oxide film or a polycrystalline silicon film on a gate insulating film,
By implanting an impurity such as argon into the polycrystalline silicon film, the polycrystalline silicon film is made amorphous to provide a semiconductor device having a tunnel oxide film or a gate insulating film having significantly longer-term reliability than conventional ones. It becomes possible to do.
【図１】本発明の半導体装置の製造方法の一実施例を工
程順に説明する為の主要断面図である。FIG. 1 is a main cross-sectional view for describing one embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps.
【図２】従来の半導体装置の製造方法を説明する為の主
要断面図である。FIG. 2 is a main cross-sectional view for describing a conventional method for manufacturing a semiconductor device.
１０1 半導体基板 １０２ フィールド絶縁膜 １０３ 犠牲酸化膜 １０４ ゲート絶縁膜（もしくはトンネル酸化膜） １０５ 多結晶シリコン膜 １０６ イオン注入 ２０1 半導体基板 ２０２ フィールド絶縁膜 ２０３ 犠牲酸化膜 ２０４ ゲート絶縁膜（もしくはトンネル酸化膜） ２０５ 多結晶シリコン Reference Signs List 101 semiconductor substrate 102 field insulating film 103 sacrificial oxide film 104 gate insulating film (or tunnel oxide film) 105 polycrystalline silicon film 106 ion implantation 201 semiconductor substrate 202 field insulating film 203 sacrificial oxide film 204 gate insulating film (or tunnel oxide film) 205 Polycrystalline silicon
Claims (8)
程、前記ゲート絶縁膜上に多結晶シリコンを形成する工
程、前記多結晶シリコン中にイオン注入を行い前記多結
晶シリコンの一部もしくは全てをアモルファスシリコン
化する工程からなることを特徴とする半導体装置の製造
方法。A step of forming a gate insulating film on a semiconductor substrate; a step of forming polycrystalline silicon on the gate insulating film; and a part or all of the polycrystalline silicon by implanting ions into the polycrystalline silicon. A method for manufacturing a semiconductor device, comprising: converting silicon into amorphous silicon.
いて、前記イオン注入をアルゴン等の不活性物質を用い
て行うことを特徴とする半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein said ion implantation is performed using an inert substance such as argon.
いて、前記イオン注入をガリウム等の３属の元素を用い
て行うことを特徴とする半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein said ion implantation is performed using a Group 3 element such as gallium.
いて、前記イオン注入をゲルマニウム等の４属の元素を
用いて行うことを特徴とする半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein said ion implantation is performed using an element belonging to Group 4 such as germanium.
工程、前記トンネル絶縁膜上に多結晶シリコンを形成す
る工程、前記多結晶シリコン中にイオン注入を行い前記
多結晶シリコンの一部もしくは全てをアモルファスシリ
コン化する工程からなることを特徴とする半導体装置の
製造方法。5. A step of forming a tunnel insulating film on a semiconductor substrate, a step of forming polycrystalline silicon on the tunnel insulating film, and a part or all of the polycrystalline silicon by implanting ions into the polycrystalline silicon. A method for manufacturing a semiconductor device, comprising: converting silicon into amorphous silicon.
いて、前記イオン注入をアルゴン等の不活性物質を用い
て行うことを特徴とする半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 5, wherein said ion implantation is performed using an inert substance such as argon.
いて、前記イオン注入をガリウム等の３属の元素を用い
て行うことを特徴とする半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 5, wherein said ion implantation is performed using a Group 3 element such as gallium.
いて、前記イオン注入をゲルマニウム等の４属の元素を
用いて行うことを特徴とする半導体装置の製造方法。8. The method for manufacturing a semiconductor device according to claim 5, wherein said ion implantation is performed using an element belonging to Group 4 such as germanium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10009866A JPH11214540A (en) | 1998-01-21 | 1998-01-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10009866A JPH11214540A (en) | 1998-01-21 | 1998-01-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11214540A true JPH11214540A (en) | 1999-08-06 |
Family
ID=11732072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10009866A Withdrawn JPH11214540A (en) | 1998-01-21 | 1998-01-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11214540A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100431300B1 (en) * | 2001-12-22 | 2004-05-12 | 주식회사 하이닉스반도체 | method for fabricating flash memory cell |
-
1998
- 1998-01-21 JP JP10009866A patent/JPH11214540A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100431300B1 (en) * | 2001-12-22 | 2004-05-12 | 주식회사 하이닉스반도체 | method for fabricating flash memory cell |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
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