JPH11204801A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH11204801A JPH11204801A JP20564998A JP20564998A JPH11204801A JP H11204801 A JPH11204801 A JP H11204801A JP 20564998 A JP20564998 A JP 20564998A JP 20564998 A JP20564998 A JP 20564998A JP H11204801 A JPH11204801 A JP H11204801A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- element isolation
- region
- substrate
- oxidized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Element Separation (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＳＯＩ（絶縁体層
上に半導体層を積層した）基板を用いた半導体集積回
路、またはＴＦＴ（薄膜トランジスタ）半導体集積回路
の素子分離構造に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit using a SOI (insulating layer with a semiconductor layer) substrate or an element isolation structure of a TFT (thin film transistor) semiconductor integrated circuit.
【０００２】[0002]
【従来の技術】絶縁体層の上にシリコンなどの半導体層
を形成したＳＯＩ（シリコン・オン・インシュレータ）
基板上にＭＯＳトランジスタなどの半導体素子を集積し
たＳＯＩ集積回路は、素子の能動領域以外を選択酸化し
て形成する素子分離用酸化膜が下層の絶縁体層に接する
形を取るか、または素子の能動領域以外をエッチングに
て除去した後に側壁を酸化することによって、素子を構
成する半導体部分の外側を３次元的に絶縁物が取り囲む
構造を特徴とする。この素子分離構造を取ることによっ
て、ＳＯＩ集積回路は、半導体基板表面に素子を集積す
る通常の集積回路に比べ、寄生容量や接合リークが小さ
く、バイアス印加方向の自由度が高いなどの多くの利点
を持つ。しかし同時に、ＭＯＳトランジスタのチャネル
領域が絶縁物に取り囲まれて電気的に孤立することに起
因して、チャネル領域を流れる電流で発生した多数キャ
リアが、孤立したチャネル領域に蓄積され、該チャネル
領域の電位、即ちＭＯＳトランジスタの基板電位を変動
させて寄生バイポーラデバイスをオンさせることで電気
特性を劣化させる、いわゆる基板電位浮遊効果を有する
という弊害をも併せ持つ。2. Description of the Related Art An SOI (silicon on insulator) in which a semiconductor layer such as silicon is formed on an insulator layer.
An SOI integrated circuit in which a semiconductor element such as a MOS transistor is integrated on a substrate takes a form in which an element isolation oxide film formed by selectively oxidizing an area other than the active area of the element is in contact with a lower insulating layer, or The structure is characterized in that the sidewalls are oxidized after the portions other than the active region are removed by etching, so that the insulator three-dimensionally surrounds the outside of the semiconductor portion forming the element. By adopting this element isolation structure, the SOI integrated circuit has many advantages, such as smaller parasitic capacitance and junction leakage and a higher degree of freedom in the direction of bias application, as compared with a normal integrated circuit in which elements are integrated on the surface of a semiconductor substrate. have. At the same time, however, majority carriers generated by current flowing in the channel region are accumulated in the isolated channel region due to the fact that the channel region of the MOS transistor is electrically isolated by being surrounded by the insulator, and Turning on the parasitic bipolar device by changing the potential, that is, the substrate potential of the MOS transistor, degrades the electrical characteristics, and also has a problem of having a so-called substrate potential floating effect.
【０００３】これを回避する手段として、配線層とのコ
ンタクトホールを設けた、チャネル領域と同じ導電型の
濃い拡散領域をチャネル領域に隣接させて形成したり、
半導体層下部の絶縁体層に予め開口してチャネル領域が
下側に導通できるような構造をとるなど、キャリアの蓄
積を防ぎ、基板電位浮遊効果を抑制する構造が、特開平
H07273340、H05075124、H05075123、H06085262、H08153
775などの他、多くの文献に提案されている。As a means for avoiding this, a dense diffusion region having the same conductivity type as the channel region and having a contact hole with the wiring layer is formed adjacent to the channel region.
A structure that prevents carrier accumulation and suppresses the substrate potential floating effect, for example, by adopting a structure in which an opening is formed in an insulator layer below a semiconductor layer in advance so that a channel region can be conducted to a lower side, is disclosed in Japanese Patent Application Laid-Open No. H10-163873.
H07273340, H05075124, H05075123, H06085262, H08153
It has been proposed in many documents such as 775.
【０００４】図３は、これら従来技術に基づく、ＳＯＩ
基板上のＭＯＳトランジスタの基板電位浮遊効果抑制構
造のうち最も代表的なものを、平面図及びチャネル方向
の断面図として表したものである。図において、１は支
持基板、２は絶縁体層、３は素子分離領域または素子分
離用選択酸化膜、５はドレイン拡散領域、６はソース拡
散領域、７はゲート金属、８はチャネル領域、９は基板
電位拡散層、１１はＰ型・Ｎ型拡散境界線をそれぞれ表
す。以下、図に沿って従来のＳＯＩ基板上のＭＯＳトラ
ンジスタの基板電位浮遊効果抑制構造を簡単に説明す
る。FIG. 3 shows an SOI based on these prior arts.
The most typical structure of the substrate potential floating effect suppressing structure of the MOS transistor on the substrate is shown as a plan view and a sectional view in the channel direction. In the figure, 1 is a supporting substrate, 2 is an insulator layer, 3 is an element isolation region or a selective oxide film for element isolation, 5 is a drain diffusion region, 6 is a source diffusion region, 7 is a gate metal, 8 is a channel region, 9 Denotes a substrate potential diffusion layer, and 11 denotes a P-type / N-type diffusion boundary line. Hereinafter, a conventional structure for suppressing the floating effect of the substrate potential of a MOS transistor on an SOI substrate will be briefly described with reference to the drawings.
【０００５】図３（ｃ）は、図３（ａ）と図３（ｂ）に
示した二つの代表的構造の平面図に共通する、Ａ−Ａに
おける断面図である。前述の通り、素子分離領域の半導
体層を選択酸化することで形成された素子分離用選択酸
化膜３が下部の絶縁体層２の深さまで達しており、素子
を形成する半導体部分５、６、８は、絶縁物に囲まれて
いる。当然、ソース６とドレイン５はコンタクトホール
を介してそれぞれ配線層に接続されるが、チャネル領域
８はソース６・ドレイン５と接合に隔てられ、図３
（ｃ）の断面図を見る限り、周囲から電気的に孤立して
いることがわかる。FIG. 3 (c) is a cross-sectional view taken along the line AA which is common to the plan views of the two representative structures shown in FIGS. 3 (a) and 3 (b). As described above, the selective oxide film 3 for element isolation formed by selectively oxidizing the semiconductor layer in the element isolation region reaches the depth of the lower insulator layer 2, and the semiconductor portions 5, 6, and 8 is surrounded by an insulator. Naturally, the source 6 and the drain 5 are connected to the wiring layers via the contact holes, respectively. However, the channel region 8 is separated from the source 6 and the drain 5 by the junction, and the structure shown in FIG.
As can be seen from the cross-sectional view of (c), it is electrically isolated from the surroundings.
【０００６】図３（ａ）は、チャネル領域８をチャネル
幅方向に延長し、基板電位拡散層９をチャネル領域８を
隣接させることによって、チャネル領域８と電気的接触
をとれるように改善したものである。基板電位拡散層９
は、チャネル領域８と同極性の不純物拡散が行われるよ
うにするためにＰＮ境界線１１で囲まれており、かつ、
異極性不純物が拡散されるソース６・ドレイン５とはＴ
字型に変形したゲート金属によって隔てられることで、
相応の耐圧を持つように工夫されている。この構造によ
って、基板電位拡散層９はソース６・ドレイン５と独立
の電位を与えることができ、基板電位浮遊効果が抑制で
きる。FIG. 3 (a) shows a structure in which the channel region 8 is extended in the channel width direction, and the substrate potential diffusion layer 9 is improved so that the channel region 8 can be brought into electrical contact with the channel region 8 by adjoining the channel region. It is. Substrate potential diffusion layer 9
Are surrounded by a PN boundary line 11 so that impurity diffusion of the same polarity as that of the channel region 8 is performed, and
The source 6 and the drain 5 where the impurity of the opposite polarity is diffused are T
By being separated by the gate metal transformed into a letter shape,
It is devised to have a corresponding pressure resistance. With this structure, the substrate potential diffusion layer 9 can apply a potential independent of the source 6 and the drain 5, and the substrate potential floating effect can be suppressed.
【０００７】図３（ｂ）は図３（ａ）の変形で、ソース
６との分離を省略して短絡させたものであり、基板電位
がソース電位と短絡されて差し支えないような使い方に
おいては、図３（ａ）の場合より専有面積を小さくで
き、基板電位浮遊効果の抑制については、図３（ａ）と
ほぼ同等である。FIG. 3 (b) is a modification of FIG. 3 (a), which is short-circuited by omitting the separation from the source 6, and is used in such a way that the substrate potential may be short-circuited to the source potential. 3A, the occupied area can be made smaller than in the case of FIG. 3A, and the suppression of the substrate potential floating effect is almost the same as that of FIG.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、上記図
３（ａ）記載の従来のＳＯＩ基板上のＭＯＳトランジス
タの基板電位浮遊効果抑制構造においては、集積回路を
構成する全てのＭＯＳトランジスタについて１個ずつ基
板電位拡散層９を設置する必要があり、素子の専有面積
の増大による集積度の大幅低下を招くという問題点のみ
ならず、通常の半導体基板表面での集積回路設計に比べ
てパターンレイアウト上の差異が大きいために、過去に
蓄積した設計資産を活用できないという問題点を有して
いた。また、上記図３（ｂ）記載の従来のＳＯＩ基板上
のＭＯＳトランジスタの基板電位浮遊効果抑制構造にお
いては、素子の専有面積増大は基板電位拡散層９の存在
によるチャネル幅の減少分を補うだけで済むため、図３
（ａ）に比べて面積増加分を小さく抑えられる反面、基
板電位が常にソース６の電位に固定されるため、NANDゲ
ートなどに多用される複数のトランジスタを直列に配置
したレイアウトなどに使用できない。さらに、前述の過
去の設計資産を活用できないという問題点はそのまま残
る。However, in the conventional structure for suppressing the floating of the substrate potential of the MOS transistor on the SOI substrate shown in FIG. 3A, one MOS transistor is provided for every MOS transistor constituting the integrated circuit. It is necessary to provide the substrate potential diffusion layer 9, which causes not only a problem that the degree of integration is greatly reduced due to an increase in the occupied area of the element, but also a pattern layout as compared with an integrated circuit design on a normal semiconductor substrate surface. Due to the large difference, there was a problem that design resources accumulated in the past could not be used. Further, in the conventional structure for suppressing the substrate potential floating effect of the MOS transistor on the SOI substrate shown in FIG. 3B, the increase in the occupied area of the element only compensates for the decrease in the channel width due to the presence of the substrate potential diffusion layer 9. Figure 3
Although the increase in area can be suppressed smaller than that in FIG. 7A, the substrate potential is always fixed to the potential of the source 6, and therefore cannot be used in a layout in which a plurality of transistors frequently used in NAND gates and the like are arranged in series. Further, the problem that the past design resources cannot be utilized remains as it is.
【０００９】そこで、本発明は、ＳＯＩ基板上のＭＯＳ
トランジスタの基板電位浮遊効果を抑制し、かつ、素子
の専有面積の増大を抑えて集積度の低下を防ぎ、さらに
既存の設計資産を有効活用を可能にするＳＯＩ基板上の
素子分離構造を提供することを目的とする。Therefore, the present invention provides a MOS transistor on an SOI substrate.
Provided is an element isolation structure on an SOI substrate that suppresses a substrate potential floating effect of a transistor, suppresses an increase in the occupied area of an element, prevents a decrease in integration degree, and enables effective use of existing design resources. The purpose is to:
【００１０】[0010]
【課題を解決するための手段】本発明の請求項１記載の
半導体装置は、基板上の絶縁膜上に形成された半導体層
上に複数の素子を集積した半導体装置において、選択酸
化により前記半導体層の第１の選択領域を酸化して該選
択領域の半導体層の厚さ分が全て酸化された第１の素子
分離領域と、やはり選択酸化により前記半導体層の第２
の選択領域を酸化して該選択領域の半導体層の厚さ分の
一部が該酸化膜と前記絶縁膜との間に残存する範囲で酸
化された第２の素子分離領域とが、同一基板上に混在す
ることを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor device in which a plurality of elements are integrated on a semiconductor layer formed on an insulating film on a substrate. A first element isolation region in which the thickness of the semiconductor layer in the first selected region is oxidized by oxidizing the first selected region of the layer;
And a second element isolation region oxidized to the extent that a portion of the thickness of the semiconductor layer in the selected region remains between the oxide film and the insulating film. It is characterized by being mixed above.
【００１１】また、本発明の請求項２記載の半導体装置
は、基板上の絶縁膜上に形成された半導体層上に複数の
素子を集積した半導体装置において、前記半導体層の第
１の選択領域を除去して形成される第１の素子分離領域
と、選択酸化により前記半導体層の第２の選択領域を酸
化して該選択領域の半導体層の厚さ分の一部が該酸化膜
と前記絶縁膜との間に残存する範囲で酸化された第２の
素子分離領域とが、同一基板上に混在することを特徴と
する。According to a second aspect of the present invention, in the semiconductor device in which a plurality of elements are integrated on a semiconductor layer formed on an insulating film on a substrate, the first selected region of the semiconductor layer is provided. A first element isolation region formed by removing the oxide film, and a portion corresponding to the thickness of the semiconductor layer in the selected region by oxidizing a second selected region of the semiconductor layer by selective oxidation. The second element isolation region oxidized in a range remaining between the insulating film and the insulating film is mixed on the same substrate.
【００１２】また、本発明の請求項３記載の半導体装置
は、基板上の絶縁膜上に形成された半導体層上に複数の
素子を集積した半導体装置において、前記半導体層の厚
さを素子分離酸化によって該半導体層の厚さ分が全て酸
化される程度に薄くした第１の領域と、前記半導体層の
厚さを、素子分離酸化によって該半導体層の厚さ分の一
部が該酸化膜と前記絶縁膜との間に残存する範囲で酸化
される程度の厚さにした第２の領域とが、同一基板上に
混在することを特徴とする。According to a third aspect of the present invention, in a semiconductor device in which a plurality of elements are integrated on a semiconductor layer formed on an insulating film on a substrate, the thickness of the semiconductor layer is separated by an element. A first region thinned to such an extent that the entire thickness of the semiconductor layer is oxidized by oxidation, and a part of the semiconductor layer having a thickness corresponding to the thickness of the semiconductor layer formed by element isolation oxidation. And a second region having a thickness such that it is oxidized in a range remaining between the insulating film and the insulating film is present on the same substrate.
【００１３】この発明によれば、前記絶縁体層上の半導
体層にＭＯＳトランジスタなどの基板電位を持つ素子を
集積する際に、請求項１・２記載の第１の素子分離領域
または請求項３記載の第１の領域内の素子分離領域に囲
まれた能動領域内の複数の素子の半導体層内の基板部分
が、請求項１・２記載の第２の素子分離領域または請求
項３記載の第２の領域内の素子分離領域の酸化膜の下側
に残存する半導体層を通じて導通可能な状態をとること
ができ、これら複数の素子間を包含する該能動領域内に
基板電位拡散層を最低１個設けることで、複数の素子間
に共通な基板電位を固定することが可能になるため、素
子ごとに基板電位拡散層を設ける必要のある従来の技術
に比べて素子面積を小さくして集積度を向上させること
ができ、さらに半導体基板表面に素子を集積する通常の
集積回路に近い素子レイアウトが可能となることによっ
て過去の設計資産の有効活用も可能にするという効果を
奏する。According to the present invention, when an element having a substrate potential such as a MOS transistor is integrated on the semiconductor layer on the insulator layer, the first element isolation region according to claim 1 or 2 or claim 3. 4. The second element isolation region according to claim 1 or 2, wherein the substrate portion in the semiconductor layer of the plurality of elements in the active region surrounded by the element isolation region in the first region according to claim 1. A conductive state can be established through a semiconductor layer remaining below the oxide film in the element isolation region in the second region, and a substrate potential diffusion layer is formed at least in the active region including the plurality of elements. By providing one, it becomes possible to fix a common substrate potential between a plurality of elements, so that the element area can be reduced and integrated compared to the conventional technology in which a substrate potential diffusion layer must be provided for each element. Degree can be improved, and even a half An effect that also allows effective use of the past design resources by conventional integrated circuit close element layout for integrating element to the body surface of the substrate becomes possible.
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１５】図１は、請求項１記載の発明に係る半導体
装置の実施の形態の構造を示す図である。図１(ａ)は構
造の平面図で、この図のＡ−Ａに沿った断面図を図１
(b)に、Ｂ−Ｂに沿った断面図を図１(ｃ)に示す。図に
おいて、１は支持基板、２は絶縁体層、３は第１の素子
分離領域または第１の素子分離用選択酸化膜、４は第２
の素子分離領域または第２の素子分離用選択酸化膜、５
はドレイン拡散領域、６はソース拡散領域、７はゲート
金属、８はチャネル領域、９は基板電位拡散層、１１は
Ｐ型・Ｎ型拡散境界線をそれぞれ表す。FIG. 1 is a diagram showing a structure of an embodiment of a semiconductor device according to the present invention. FIG. 1A is a plan view of the structure, and FIG. 1A is a sectional view taken along the line AA in FIG.
FIG. 1B is a cross-sectional view taken along the line BB in FIG. In the drawing, 1 is a support substrate, 2 is an insulator layer, 3 is a first element isolation region or a first selective oxide film for element isolation, and 4 is a second element isolation oxide film.
Element isolation region or second element isolation selective oxide film, 5
Is a drain diffusion region, 6 is a source diffusion region, 7 is a gate metal, 8 is a channel region, 9 is a substrate potential diffusion layer, and 11 is a P-type / N-type diffusion boundary line.
【００１６】図１(ａ)の構造をチャネル長方向、即ちＡ
−Ａに沿った方向に見た断面図、図１（ｂ）を見ると、
従来の技術による構造の断面図（図３）と同様に、第１
の素子分離領域の半導体層を選択酸化することで形成さ
れた第１の素子分離用選択酸化膜３が下部の絶縁体層２
の深さまで達することで、素子を形成する半導体部分
５、６、８は、絶縁物に囲まれており、断面図上のチャ
ネル領域８は、周囲から電気的に孤立していることがわ
かる。しかし、図１（ａ）に短破線で示した第２の素子
分離用選択酸化膜４の下部には、図１（ｃ）に示したよ
うに半導体層が残存しているため、チャネル領域８はこ
の部分を通じて基板電位拡散層９と隣接する。この基板
電位拡散層９は、Ｐ型・Ｎ型拡散境界線１１に囲まれて
おり、ソース６・ドレイン５とは異なる導電型、即ちチ
ャネル領域８と同じ導電型の不純物拡散がされているこ
とによってチャネル領域８と電気的に接続されており、
かつ、第２の素子分離用選択酸化膜４によってソース６
・ドレイン５から隔てられ、相応の耐圧を持つことによ
ってソース６・ドレイン５と独立に電位を与えることが
できる。この構造によって、基板電位拡散層９にコンタ
クトホールを介して接続された配線を通じて、チャネル
領域８の電位を外部から決定することができる。即ち、
チャネル領域８に多数キャリアが蓄積されて電位が変動
して特性に影響を与える基板電位浮遊効果を抑制するこ
とができる。FIG. 1A shows the structure in the channel length direction, that is, A
Looking at the cross-sectional view in the direction along -A, FIG.
As in the cross-sectional view of the structure according to the prior art (FIG. 3), the first
The first selective oxide film 3 for element isolation formed by selectively oxidizing the semiconductor layer in the element isolation region of FIG.
It can be seen that the semiconductor portions 5, 6, and 8 forming the element are surrounded by the insulator, and the channel region 8 on the cross-sectional view is electrically isolated from the periphery. However, as shown in FIG. 1C, the semiconductor layer remains below the second element isolation selective oxide film 4 indicated by the short dashed line in FIG. Is adjacent to the substrate potential diffusion layer 9 through this portion. The substrate potential diffusion layer 9 is surrounded by a P-type / N-type diffusion boundary line 11 and has an impurity diffusion different from that of the source 6 and the drain 5, that is, of the same conductivity type as the channel region 8. And is electrically connected to the channel region 8 by
In addition, the source 6 is formed by the second selective oxide film 4 for element isolation.
The potential can be given independently of the source 6 and the drain 5 by being separated from the drain 5 and having a corresponding withstand voltage. With this structure, the potential of the channel region 8 can be externally determined through the wiring connected to the substrate potential diffusion layer 9 via the contact hole. That is,
It is possible to suppress the floating effect of the substrate potential, which causes the majority carriers to be accumulated in the channel region 8 and fluctuates the potential to affect the characteristics.
【００１７】図２は、請求項２記載の発明に係る半導体
装置の実施の形態の構造を示す図である。図２(ａ)は構
造の平面図で、この図のＡ−Ａに沿った断面図を図２
(b)に、Ｂ−Ｂに沿った断面図を図２(ｃ)に示す。図に
おいて、１は支持基板、２は絶縁体層、３は第１の素子
分離領域または第１の素子分離用半導体層除去部、４は
第２の素子分離領域または第２の素子分離用選択酸化
膜、５はドレイン拡散領域、６はソース拡散領域、７は
ゲート金属、８はチャネル領域、９は基板電位拡散層、
１１はＰ型・Ｎ型拡散境界線をそれぞれ表す。この構造
は、前述の図１に示した構造に対して、第１の素子分離
用選択酸化膜を半導体層除去領域に変更した他はほぼ同
じ構造となっている。図１で説明した構造と同様に、チ
ャネル領域８は第２の素子分離用選択酸化膜４の下部に
残存する半導体層を通じて基板電位拡散層９と隣接し、
該基板電位拡散層９がチャネル領域８と同極性の不純物
が拡散されていることから電気的に接続される。よっ
て、図２に示す構造は、図１の構造と同様に、基板電位
拡散層９の電位を制御することによって基板電位浮遊効
果を抑制することができる。FIG. 2 is a diagram showing the structure of an embodiment of the semiconductor device according to the second aspect of the present invention. FIG. 2A is a plan view of the structure, and FIG. 2A is a sectional view taken along the line AA in FIG.
FIG. 2C is a cross-sectional view taken along the line BB in FIG. In the figure, reference numeral 1 denotes a support substrate, 2 denotes an insulator layer, 3 denotes a first element isolation region or a first element isolation semiconductor layer removed portion, and 4 denotes a second element isolation region or a second element isolation selection. An oxide film, 5 a drain diffusion region, 6 a source diffusion region, 7 a gate metal, 8 a channel region, 9 a substrate potential diffusion layer,
Reference numeral 11 denotes a P-type / N-type diffusion boundary line. This structure is substantially the same as the structure shown in FIG. 1 except that the first selective oxide film for element isolation is changed to a semiconductor layer removal region. As in the structure described with reference to FIG. 1, the channel region 8 is adjacent to the substrate potential diffusion layer 9 through the semiconductor layer remaining under the second isolation oxide film 4, and
The substrate potential diffusion layer 9 is electrically connected because an impurity having the same polarity as that of the channel region 8 is diffused. Therefore, the structure shown in FIG. 2 can suppress the substrate potential floating effect by controlling the potential of the substrate potential diffusion layer 9 as in the structure of FIG.
【００１８】図５は、請求項３記載の発明に係る半導体
装置の実施の形態の構造を示す図である。図５(ａ)は構
造の平面図で、この図のＡ−Ａに沿った断面図を図５
(b)に、Ｂ−Ｂに沿った断面図を図５(ｃ)に示す。図に
おいて、１は支持基板、２は絶縁体層、３は第１の領域
または第１の素子分離用選択酸化膜、４は第２の領域ま
たは第２の素子分離用選択酸化膜、５はドレイン拡散領
域、６はソース拡散領域、７はゲート金属、８はチャネ
ル領域、９は基板電位拡散層、１１はＰ型・Ｎ型拡散境
界線をそれぞれ表す。FIG. 5 is a diagram showing the structure of an embodiment of the semiconductor device according to the third aspect of the present invention. FIG. 5A is a plan view of the structure, and FIG. 5A is a sectional view taken along the line AA of FIG.
FIG. 5B shows a cross-sectional view along the line BB in FIG. In the figure, 1 is a support substrate, 2 is an insulator layer, 3 is a first region or first element isolation selective oxide film, 4 is a second region or second element isolation selective oxide film, 5 is A drain diffusion region, 6 is a source diffusion region, 7 is a gate metal, 8 is a channel region, 9 is a substrate potential diffusion layer, and 11 is a P-type / N-type diffusion boundary line.
【００１９】この構造も、前述の図１に示した構造に対
して、第２の領域４の半導体層を素子分離用選択酸化に
おいて、全ての厚みが酸化されない程度の厚さに変更し
た他はほぼ同じ構造となっている。即ち、第１の領域３
の半導体層は素子分離用選択酸化によって全て酸化され
る程度に薄いため、図５(ｂ)・(ｃ)では酸化膜のみを示
してあるが、これに対して第２の領域４の半導体層は第
１の領域より厚いために、前述の第１の領域を酸化した
と同一の素子分離用選択酸化によって、その厚みの全て
が酸化されきらず、酸化膜の下側に半導体層が残存する
ことになる。この残存部分の様子を図５(ｃ)に示す。図
１で説明した構造と同様に、チャネル領域８は第２の素
子分離用選択酸化膜４の下部に残存する半導体層を通じ
て基板電位拡散層９と隣接し、該基板電位拡散層９がチ
ャネル領域８と同極性の不純物が拡散されていることか
ら電気的に接続される。よって、図５に示す構造は、図
１の構造と同様に、基板電位拡散層９の電位を制御する
ことによって基板電位浮遊効果を抑制することができ
る。This structure also differs from the structure shown in FIG. 1 in that the thickness of the semiconductor layer in the second region 4 is changed to such a degree that all the thickness is not oxidized in the selective oxidation for element isolation. It has almost the same structure. That is, the first area 3
5 (b) and 5 (c) show only the oxide film, whereas the semiconductor layer in the second region 4 is thin enough to be oxidized by the selective oxidation for element isolation. Is thicker than the first region. Therefore, the entire thickness cannot be completely oxidized by the same selective oxidation for element isolation as when the first region is oxidized, and the semiconductor layer remains under the oxide film. become. The state of the remaining portion is shown in FIG. As in the structure described with reference to FIG. 1, the channel region 8 is adjacent to the substrate potential diffusion layer 9 through the semiconductor layer remaining under the second selective oxide film 4 for element isolation. 8 are electrically connected because the impurity of the same polarity as 8 is diffused. Therefore, the structure shown in FIG. 5 can suppress the substrate potential floating effect by controlling the potential of the substrate potential diffusion layer 9 as in the structure of FIG.
【００２０】さて、素子の専有面積という点を単独の素
子について見れば、本発明による図１、図２、図５の構
造は、従来技術による図３の構造とさほど変わらない。
しかし、複数の素子について比較すると、その差は歴然
とする。この点について、図４に示した請求項１または
２または３記載の発明に係る半導体装置の第２の実施の
形態を用いて以下に説明する。Now, looking at the occupied area of the element for a single element, the structure of FIGS. 1, 2 and 5 according to the present invention is not much different from the structure of FIG. 3 according to the prior art.
However, when comparing a plurality of elements, the difference is obvious. This point will be described below using a second embodiment of the semiconductor device according to the first, second, or third aspect of the present invention shown in FIG.
【００２１】図４は、本発明による構造を用いて、３つ
のＭＯＳトランジスタを集積した実施の形態を平面図と
して表したものである。図において、３は第１の素子分
離領域、４は第２の素子分離領域、５ａ・５ｂはドレイ
ン拡散領域、６ａ・６ｂはソース拡散領域、７ａ１・７
ａ２・７ｂはゲート金属、９は基板電位拡散層、１１は
Ｐ型・Ｎ型拡散境界線をそれぞれ表す。図４において、
これら３つのＭＯＳトランジスタは、第１の素子分離領
域３に囲まれたひとつの大きな能動領域内に集積され、
各々のトランジスタ間は第２の素子分離領域４によって
さらに個々のトランジスタに分離されている。図１の説
明で前述したように、図４中の３つのＭＯＳトランジス
タのチャネル領域は全て、第２の素子分離領域４を通じ
て基板電位拡散層９に電気的に接続され、そこでまとめ
て電位を決定されることになる。これと同じ素子レイア
ウトを、従来技術による図３の構造で実現するには、３
つのＭＯＳトランジスタの１個ずつについて各々基板電
位拡散層を設ける必要があり、素子の占有面積が大幅に
増えてしまうことが判り、本発明による専有面積の節減
の効果がはっきりする。さらに、第１の素子分離領域３
に囲まれたひとつの大きな能動領域を、半導体基板表面
に素子を集積する通常の集積回路、特に相補型ＭＯＳ集
積回路におけるウェルに見立てることによって、通常の
集積回路用の素子レイアウトをわずかな変更で流用でき
ることが判る。即ち、過去に蓄積された膨大な設計資産
を有効に活用できる効果も奏する。FIG. 4 is a plan view showing an embodiment in which three MOS transistors are integrated using the structure according to the present invention. In the drawing, 3 is a first element isolation region, 4 is a second element isolation region, 5a and 5b are drain diffusion regions, 6a and 6b are source diffusion regions, 7a1 and 7
a2 and 7b are gate metals, 9 is a substrate potential diffusion layer, and 11 is a P-type / N-type diffusion boundary line. In FIG.
These three MOS transistors are integrated in one large active area surrounded by the first element isolation region 3,
Each transistor is further separated into individual transistors by a second element isolation region 4. As described above with reference to FIG. 1, all the channel regions of the three MOS transistors in FIG. 4 are electrically connected to the substrate potential diffusion layer 9 through the second element isolation region 4, and collectively determine the potential there. Will be done. In order to realize the same element layout with the structure of FIG.
It is necessary to provide a substrate potential diffusion layer for each of the MOS transistors, and it is found that the occupied area of the element is greatly increased, and the effect of saving the occupied area according to the present invention becomes clear. Further, the first element isolation region 3
One large active area surrounded by the above is regarded as a well in a conventional integrated circuit for integrating devices on the surface of a semiconductor substrate, particularly in a complementary MOS integrated circuit, so that the device layout for a normal integrated circuit can be slightly changed. It turns out that it can be diverted. That is, there is an effect that the huge design resources accumulated in the past can be effectively used.
【００２２】[0022]
【発明の効果】以上述べたように、本発明の半導体装置
は、基板上の絶縁膜上に形成された半導体層上に複数の
素子を集積した半導体装置において、選択酸化により前
記半導体層の第１の選択領域を酸化して該選択領域の半
導体層の厚さ分が全て酸化されるか、または半導体層の
除去による第１の素子分離領域と、選択酸化により前記
半導体層の第２の選択領域を酸化して該選択領域の半導
体層の厚さ分の一部が該酸化膜と前記絶縁膜との間に残
存する範囲で酸化された第２の素子分離領域とが、同一
基板上に混在することを特徴とし、第１の素子分離領域
に囲まれた複数の半導体素子の基板領域を第２の素子分
離領域の下に残存する半導体層によって電気的に接続す
ることができ、複数の素子の基板電位をまとめて１カ所
でとることによって、素子面積の増大、言い換えれば集
積度を犠牲にすることなく、また過去の通常の半導体集
積回路の設計資産を有効に活用できる形で、ＳＯＩ基板
上のＭＯＳトランジスタの基板電位浮遊効果を抑制する
ことができるという効果を奏する。As described above, according to the semiconductor device of the present invention, in a semiconductor device in which a plurality of elements are integrated on a semiconductor layer formed on an insulating film on a substrate, the semiconductor layer of the semiconductor layer is selectively oxidized. One selected region is oxidized to oxidize the entire thickness of the semiconductor layer in the selected region, or a first element isolation region by removing the semiconductor layer and a second selection of the semiconductor layer by selective oxidation A second element isolation region, which is oxidized in a range where a portion of the thickness of the semiconductor layer in the selected region is oxidized and remains between the oxide film and the insulating film, is formed on the same substrate; The substrate regions of the plurality of semiconductor elements surrounded by the first element isolation region can be electrically connected by a semiconductor layer remaining under the second element isolation region. By collecting the substrate potential of the device at one place, In order to suppress the floating effect of the MOS transistor on the SOI substrate, the effect of increasing the element area, in other words, without sacrificing the degree of integration and effectively utilizing the past design resources of the ordinary semiconductor integrated circuit. It has the effect of being able to do so.
【図１】本発明の請求項１に係る実施の形態の構造を示
す平面図、及び断面図であり、(a)は平面図、(b)はＡ−
Ａ断面図、(c)はＢ−Ｂ断面図である。FIGS. 1A and 1B are a plan view and a sectional view showing a structure according to an embodiment of the present invention, wherein FIG. 1A is a plan view, and FIG.
A sectional view, and (c) is a BB sectional view.
【図２】本発明の請求項２に係る実施の形態の構造を示
す平面図、及び断面図であり、(a)は平面図、(b)はＡ−
Ａ断面図、(c)はＢ−Ｂ断面図である。FIGS. 2A and 2B are a plan view and a sectional view showing a structure according to an embodiment of the present invention, wherein FIG. 2A is a plan view and FIG.
A sectional view, and (c) is a BB sectional view.
【図３】従来のＳＯＩ基板上のＭＯＳトランジスタの基
板電位浮遊効果抑制構造を表す平面図、及び断面図であ
り、(a)はソース・ドレイン電位に独立に基板電位を決
定するための構造の平面図で、(b)は基板電位をソース
電位と同じ値に固定する構造の平面図、(c)は(a)と(b)
に共通のＡ−Ａ断面図である。FIGS. 3A and 3B are a plan view and a cross-sectional view showing a conventional structure for suppressing the floating of the substrate potential of a MOS transistor on an SOI substrate, and FIG. 3A shows a structure for determining the substrate potential independently of the source / drain potential. In the plan view, (b) is a plan view of a structure in which the substrate potential is fixed at the same value as the source potential, and (c) is (a) and (b)
FIG. 2 is a sectional view taken along line AA of FIG.
【図４】本発明の実施の形態に基づき、複数の素子を集
積した場合を示す平面図である。FIG. 4 is a plan view showing a case where a plurality of elements are integrated based on an embodiment of the present invention.
【図５】本発明の請求項３に係る実施の形態の構造を示
す平面図、及び断面図であり、(a)は平面図、(b)はＡ−
Ａ断面図、(c)はＢ−Ｂ断面図である。FIGS. 5A and 5B are a plan view and a cross-sectional view showing a structure according to a third embodiment of the present invention, wherein FIG. 5A is a plan view and FIG.
A sectional view, and (c) is a BB sectional view.
１． 支持基板 ２． 絶縁体層 ３． 第１の素子分離領域または第１の素子分離用選択
酸化膜（半導体層除去部） ４． 第２の素子分離領域または第２の素子分離用選択
酸化膜 ５． ドレイン拡散層（５ａ，５ｂも同じ） ６． ソース拡散層（６ａ，６ｂも同じ） ７． ゲート金属（７ａ１，７ａ２，７ｂも同じ） ８． ＭＯＳトランジスタのチャネル部 ９． 基板電位拡散層 １１． Ｐ型・Ｎ型拡散境界線1. Support substrate 2. 2. Insulator layer 3. First element isolation region or first element isolation selective oxide film (semiconductor layer removed portion) 4. Second element isolation region or second element isolation selective oxide film 5. Drain diffusion layer (same for 5a and 5b) 6. Source diffusion layer (same for 6a and 6b) 7. Gate metal (same for 7a1, 7a2 and 7b) 8. Channel portion of MOS transistor 10. Substrate potential diffusion layer P-type / N-type diffusion boundary
Claims (5)
に複数の素子を集積した半導体装置において、選択酸化
により前記半導体層の第１の選択領域を酸化して該選択
領域の半導体層の厚さ分が全て酸化された第１の素子分
離領域と、やはり選択酸化により前記半導体層の第２の
選択領域を酸化して該選択領域の半導体層の厚さ分の一
部が該酸化膜と前記絶縁膜との間に残存する範囲で酸化
された第２の素子分離領域とが、同一基板上に混在する
ことを特徴とする半導体装置。In a semiconductor device in which a plurality of elements are integrated on a semiconductor layer formed on an insulating film on a substrate, a first selected region of the semiconductor layer is oxidized by selective oxidation to form a semiconductor in the selected region. A first element isolation region in which the entire thickness of the layer is oxidized; and a second selective region of the semiconductor layer, which is also oxidized by selective oxidation, and a part of the thickness of the semiconductor layer in the selected region becomes part of the first element isolation region. A semiconductor device, wherein a second element isolation region oxidized in a range remaining between an oxide film and the insulating film is mixed on the same substrate.
に複数の素子を集積した半導体装置において、前記半導
体層の第１の選択領域を除去して形成される第１の素子
分離領域と、選択酸化により前記半導体層の第２の選択
領域を酸化して該選択領域の半導体層の厚さ分の一部が
該酸化膜と前記絶縁膜との間に残存する範囲で酸化され
た第２の素子分離領域とが、同一基板上に混在すること
を特徴とする半導体装置。2. A semiconductor device in which a plurality of elements are integrated on a semiconductor layer formed on an insulating film on a substrate, a first element isolation formed by removing a first selected region of the semiconductor layer. The region and the second selected region of the semiconductor layer are oxidized by selective oxidation, and a portion corresponding to the thickness of the semiconductor layer in the selected region is oxidized within a range remaining between the oxide film and the insulating film. Wherein the second element isolation region and the second element isolation region coexist on the same substrate.
に複数の素子を集積した半導体装置において、前記半導
体層の厚さを素子分離酸化によって該半導体層の厚さ分
が全て酸化される程度に薄くした第１の領域と、前記半
導体層の厚さを、素子分離酸化によって該半導体層の厚
さ分の一部が該酸化膜と前記絶縁膜との間に残存する範
囲で酸化される程度の厚さにした第２の領域とが、同一
基板上に混在することを特徴とする半導体装置。3. In a semiconductor device in which a plurality of elements are integrated on a semiconductor layer formed on an insulating film on a substrate, the thickness of the semiconductor layer is entirely oxidized by element isolation oxidation. And the thickness of the semiconductor layer is reduced so that part of the thickness of the semiconductor layer remains between the oxide film and the insulating film due to element isolation oxidation. A semiconductor device, wherein a second region having a thickness to be oxidized is mixed on the same substrate.
いて、前記半導体層が単結晶シリコンであることを特徴
とする半導体装置。4. The semiconductor device according to claim 1, wherein said semiconductor layer is single crystal silicon.
いて、前記半導体層が多結晶または非晶質シリコンであ
ることを特徴とする半導体装置。5. The semiconductor device according to claim 1, wherein said semiconductor layer is made of polycrystalline or amorphous silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20564998A JPH11204801A (en) | 1997-11-13 | 1998-07-21 | Semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31211897 | 1997-11-13 | ||
| JP9-312118 | 1997-11-13 | ||
| JP20564998A JPH11204801A (en) | 1997-11-13 | 1998-07-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11204801A true JPH11204801A (en) | 1999-07-30 |
Family
ID=26515182
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20564998A Withdrawn JPH11204801A (en) | 1997-11-13 | 1998-07-21 | Semiconductor device |
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| Country | Link |
|---|---|
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100363554B1 (en) * | 2001-03-30 | 2002-12-05 | 삼성전자 주식회사 | Soi type semiconductor device and method of forming the same |
| US6693329B2 (en) | 2001-01-19 | 2004-02-17 | Seiko Epson Corporation | Semiconductor devices having a field effect transistor and a bi-polar transistor |
| US6734500B2 (en) | 2000-12-15 | 2004-05-11 | Seiko Epson Corporation | Semiconductor devices including a bi-polar transistor and a field effect transistor |
| US6762465B2 (en) | 2001-01-19 | 2004-07-13 | Seiko Epson Corporation | BiCMOS inverter |
| JP2011109130A (en) * | 2011-01-27 | 2011-06-02 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| US8148215B2 (en) | 2001-04-24 | 2012-04-03 | Semiconductor Energy Laboratory Co., Ltd. | Non-volatile memory and method of manufacturing the same |
-
1998
- 1998-07-21 JP JP20564998A patent/JPH11204801A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6734500B2 (en) | 2000-12-15 | 2004-05-11 | Seiko Epson Corporation | Semiconductor devices including a bi-polar transistor and a field effect transistor |
| US6693329B2 (en) | 2001-01-19 | 2004-02-17 | Seiko Epson Corporation | Semiconductor devices having a field effect transistor and a bi-polar transistor |
| US6762465B2 (en) | 2001-01-19 | 2004-07-13 | Seiko Epson Corporation | BiCMOS inverter |
| KR100363554B1 (en) * | 2001-03-30 | 2002-12-05 | 삼성전자 주식회사 | Soi type semiconductor device and method of forming the same |
| US8148215B2 (en) | 2001-04-24 | 2012-04-03 | Semiconductor Energy Laboratory Co., Ltd. | Non-volatile memory and method of manufacturing the same |
| JP2011109130A (en) * | 2011-01-27 | 2011-06-02 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
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