JPH11176890A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH11176890A
JPH11176890A JP9343045A JP34304597A JPH11176890A JP H11176890 A JPH11176890 A JP H11176890A JP 9343045 A JP9343045 A JP 9343045A JP 34304597 A JP34304597 A JP 34304597A JP H11176890 A JPH11176890 A JP H11176890A
Authority
JP
Japan
Prior art keywords
hole
solder
wiring
semiconductor device
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP9343045A
Other languages
Japanese (ja)
Inventor
Morihiko Ikemizu
守彦 池水
Tokuaki Negishi
徳昭 根岸
Hiroaki Kishi
博明 岸
Noboru Takashima
昇 高島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Shinko Electric Industries Co Ltd
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Shinko Electric Industries Co Ltd
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Shinko Electric Industries Co Ltd, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP9343045A priority Critical patent/JPH11176890A/en
Publication of JPH11176890A publication Critical patent/JPH11176890A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To facilitate the escape of flux when a solder ball is soldered and to prevent defective connections of solder bumps in a BGA semiconductor device. SOLUTION: This semiconductor device is provided with a hole 10 formed at the specified position of an insulating resin film 9. In a wiring film, a wiring 11 such as a via land 11b is formed on one main surface, and a semiconductor element is deposited and mounted on a wiring film. A resin sealing layer 14 seals the mounting part of the semiconductor element, and a solder bump 15 is buried in the hole 10 and connected to the via land 11b. Furthermore, since the hole 10 is of square cross-sectional shape and the gap is present between the inner wall surface of the hole and the inserted solder ball at the time of solder reflow, the flux for soldering readily escapes through the gap to the outside, and the filling of the solder in the hole is performed satisfactorily.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に係
り、さらに詳しくは、絶縁性フィルムをベースとする配
線フィルムを基板とし、ボールグリッドアレイ（ＢＧ
Ａ）構造を有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a ball grid array (BG) using a wiring film based on an insulating film as a substrate.
A) The present invention relates to a semiconductor device having a structure.

【０００２】[0002]

【従来の技術】従来から、半導体装置におけるコストの
低減と構成の簡略化等を目的として、インナーリード等
の配線を有するキャリアテープに半導体素子を搭載・実
装し、その実装領域を、絶縁性樹脂により被覆・封止し
たＴＣＰ（テープキャリアパッケージ）が開発されてい
る。そしてこのようなＴＣＰでは、入出力端子数の増
加、外形の小型化、実装の容易性等の観点から、はんだ
等のボールを格子（アレイ）状に配列して外部接続端子
とした、ボールグリッドアレイ（以下、ＢＧＡと示
す。）と呼ばれる構造が採られている。2. Description of the Related Art Conventionally, a semiconductor element has been mounted and mounted on a carrier tape having wiring such as inner leads for the purpose of reducing the cost and simplifying the configuration of a semiconductor device, and the mounting area is insulated by an insulating resin. A TCP (tape carrier package) coated and sealed by the company has been developed. In such a TCP, balls of solder or the like are arranged in a grid (array) to form external connection terminals from the viewpoints of an increase in the number of input / output terminals, miniaturization of the outer shape, and ease of mounting. A structure called an array (hereinafter, referred to as BGA) is employed.

【０００３】このようなＢＧＡ型半導体装置の中でも、
特に端子間のピッチの狭いＦＢＧＡ（ファインピッチボ
ールグリッドアレイ）型のものでは、所定の位置にヴィ
アホール用の孔が開けられ、片面に所要の配線が形成さ
れた配線フィルム上に、半導体素子がフェースアップ型
に配設され、ワイヤボンディング等により電気的に接続
されており、その外側に絶縁性樹脂の封止層が形成され
ている。また、配線フィルムの他面側に、はんだボール
のバンプが形成されている。[0003] Among such BGA type semiconductor devices,
In particular, in the case of an FBGA (fine pitch ball grid array) type having a narrow pitch between terminals, a hole for a via hole is formed at a predetermined position, and a semiconductor element is mounted on a wiring film having required wiring formed on one side. They are arranged face-up and are electrically connected by wire bonding or the like, and a sealing layer of an insulating resin is formed outside thereof. In addition, solder ball bumps are formed on the other surface of the wiring film.

【０００４】ここで、はんだバンプの形成は、以下に示
すようにして行なわれている。すなわち、図５に示すよ
うに、ポリイミド系樹脂フィルムのような絶縁性樹脂フ
ィルム１に形成されたヴィアホール用の孔２の内部に、
ランド（ヴィアランド）３等の配線の形成面と反対の面
側から、ペースト状のはんだフラックス４を塗布した
後、はんだ（例えばＰｂ／Ｓｎ系の共晶はんだ）ボール
５を孔内に挿嵌する。ここで、はんだフラックス４は、
はんだおよびはんだが接合される金属層表面の酸化を防
止し、これらの表面を活性化するために塗布されるもの
であり、樹脂系のものなどが使用される。Here, the formation of the solder bumps is performed as follows. That is, as shown in FIG. 5, the inside of a via hole 2 formed in an insulating resin film 1 such as a polyimide resin film,
After applying a paste-like solder flux 4 from the side opposite to the wiring formation surface such as a land (via land) 3, a solder (for example, Pb / Sn-based eutectic solder) ball 5 is inserted into the hole. I do. Here, the solder flux 4 is
It is applied in order to prevent the oxidation of the solder and the surface of the metal layer to which the solder is joined and to activate these surfaces, and a resin-based material is used.

【０００５】次いで、加熱によりはんだボール５をリフ
ローさせて孔に充填した後、フラックス等を洗浄して除
去する。こうして、リフローしたはんだが、ヴィアラン
ド３を構成する銅等と共晶を形成して接合し、はんだバ
ンプが形成される。なお、図中、符号は６は接着剤層、
７はヴィアランド３等の配線を保護するための絶縁レジ
スト層、８は樹脂封止層をそれぞれ示している。Next, after the solder balls 5 are reflowed by heating and filled in the holes, the flux and the like are removed by washing. In this way, the reflowed solder forms a eutectic with copper or the like constituting the via land 3 and joins to form a solder bump. In the drawing, reference numeral 6 denotes an adhesive layer,
Reference numeral 7 denotes an insulating resist layer for protecting wiring such as via land 3 and the like, and reference numeral 8 denotes a resin sealing layer.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、このよ
うなはんだバンプの形成においては、ヴィアホール用孔
２が、断面円形で径が小さいため、孔内に挿嵌したはん
だボール５をリフローさせる際に、予め孔内に塗布され
たはんだフラックス４が、孔の底部のヴィアランド３と
はんだボール５との間に閉じ込められ、孔の内壁面全体
に濡れ広がりにくい。その結果、リフローしたはんだが
ヴィアランド３に接触しない事態が生じ、はんだ付け不
良が発生しやすいという問題があった。However, in the formation of such a solder bump, since the via hole 2 has a circular cross section and a small diameter, it is necessary to reflow the solder ball 5 inserted into the hole. The solder flux 4 previously applied to the inside of the hole is confined between the via land 3 at the bottom of the hole and the solder ball 5, so that it is difficult to wet and spread over the entire inner wall surface of the hole. As a result, a situation occurs in which the reflowed solder does not come into contact with the via land 3, and there is a problem that a soldering failure easily occurs.

【０００７】具体的数値を挙げて説明すると、ヴィアホ
ール用孔２は、 0.8mmピッチでは直径 0.3〜 0.5mm、
0.5mmピッチでは直径 0.2〜 0.4mmと、極めて小径に孔
加工されている。そして、はんだリフロー時のフラック
ス４の逃げを容易にするため、孔の径を大きくすること
も考えられるが、高密度配線という時代の要請に逆行す
るため、好ましくなかった。すなわち、半導体装置の多
ピン化に対応して、配線フィルムのランド間には高密度
に配線がなされるため、ヴィアホール用孔２の大きさ
は、はんだボール５の大きさに合わせ、かつできるだけ
小さく設定されることが望ましく、孔径の拡大は、半導
体装置の多ピン化に逆行し、好ましくなかった。[0007] Explaining by giving specific numerical values, the via hole 2 has a diameter of 0.3 to 0.5 mm at a pitch of 0.8 mm.
The hole is drilled to a very small diameter of 0.2 to 0.4 mm at 0.5 mm pitch. In order to facilitate the escape of the flux 4 at the time of solder reflow, it is conceivable to increase the diameter of the hole. However, this is not preferable because it goes against the demand of the era of high-density wiring. That is, wiring is performed between the lands of the wiring film at a high density in response to the increase in the number of pins of the semiconductor device. Therefore, the size of the via hole 2 is adjusted to the size of the solder ball 5 and as much as possible. It is desirable that the diameter be set small, and the enlargement of the hole diameter is not preferable because it goes against the increase in the number of pins of the semiconductor device.

【０００８】本発明はこのような問題を解決するために
なされたもので、ＢＧＡ型の半導体装置において、はん
だボール取付けの際のフラックスの逃げを容易にし、外
部接続端子であるはんだバンプの接続不良を防止するこ
とを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and in a BGA type semiconductor device, it facilitates the escape of a flux when mounting a solder ball, and a connection failure of a solder bump as an external connection terminal. The purpose is to prevent.

【０００９】[0009]

【課題を解決するための手段】本発明の半導体装置は、
絶縁性フィルムの所定の位置に導通用の孔が形成され、
かつ一主面に所要の配線が形成された配線フィルムと、
前記配線フィルムの配線形成面上に搭載され実装された
半導体素子と、前記半導体素子の実装部を被覆し封止す
る樹脂封止層と、前記配線フィルムの他主面側から前記
導通用孔内に埋め込まれ、前記配線に接続されたはんだ
バンプとを備えた半導体装置において、前記導通用孔
が、前記はんだバンプ形成のためのはんだリフロー時
に、該孔の内壁面と孔内に挿嵌されたはんだボールの外
周面との間に、はんだ付け用フラックスが流通する隙間
を持つ形状を有することを特徴とする。According to the present invention, there is provided a semiconductor device comprising:
A hole for conduction is formed at a predetermined position of the insulating film,
And a wiring film having required wiring formed on one main surface,
A semiconductor element mounted and mounted on the wiring forming surface of the wiring film, a resin sealing layer for covering and sealing a mounting portion of the semiconductor element, and the inside of the conduction hole from the other main surface side of the wiring film. In the semiconductor device having a solder bump embedded in the wiring and connected to the wiring, the conduction hole is inserted and fitted into the inner wall surface of the hole and the hole during the solder reflow for forming the solder bump. It is characterized by having a shape having a gap through which the soldering flux flows between the solder ball and the outer peripheral surface of the solder ball.

【００１０】本発明において、絶縁性フィルムとして
は、例えばポリイミド系、ポリエステル系などの絶縁性
樹脂フィルムや、ガラス繊維にエポキシ樹脂を含浸させ
硬化させたガラスエポキシフィルムなどが挙げられ、そ
の厚さは、構成する半導体装置の品種、形状、大きさ等
にもよるが、一般的には50〜 125μm 程度とすることが
好ましい。In the present invention, examples of the insulating film include a polyimide-based or polyester-based insulating resin film, and a glass epoxy film obtained by impregnating glass fiber with an epoxy resin and curing the glass fiber. In general, the thickness is preferably about 50 to 125 μm, though it depends on the kind, shape, size, and the like of the semiconductor device to be constituted.

【００１１】本発明においては、このような絶縁性フィ
ルムの所定の位置に、すなわち後述するはんだバンプの
形成位置に相当する位置に、以下に示す形状を有する導
通用（ヴィアホール形成用）の孔が、パンチング等の機
械的方法により形成される。In the present invention, a conductive (via hole) hole having the following shape is formed at a predetermined position of the insulating film, that is, at a position corresponding to a solder bump forming position described later. Are formed by a mechanical method such as punching.

【００１２】すなわち、本発明における導通用の孔は、
はんだバンプ形成のためのはんだリフロー時に、孔の内
壁面とこの孔内に挿嵌されたはんだボールの外周面との
間に、はんだ付け用のフラックスの逃げ路となる隙間が
存在するような形状を有している。このような孔の形状
としては、四角形や五角形、六角形あるいはそれ以上の
多角形の断面（横断面）形状が挙げられる。また、絶縁
性フィルムのはんだバンプ形成面側に開口し、かつフィ
ルム厚にほぼ等しい深さを有する１個または２個以上の
溝を、断面円形の孔の側部に連接して形成しても良い。That is, the hole for conduction in the present invention is:
A shape in which there is a gap between the inner wall surface of the hole and the outer peripheral surface of the solder ball inserted in this hole during solder reflow for forming the solder bumps, which serves as an escape path for the flux for soldering. have. Examples of the shape of such a hole include a quadrangular, pentagonal, hexagonal or polygonal cross section (transverse cross section). Further, one or two or more grooves which are opened on the solder bump forming surface side of the insulating film and have a depth substantially equal to the film thickness may be formed so as to be connected to the side of the hole having a circular cross section. good.

【００１３】本発明において、このような導通用孔が形
成された絶縁性フィルムの一主面上に配設される配線
は、半導体素子の接続用パッド、信号線、ヴィアランド
などを有し、これらは、例えば絶縁性フィルムの片面に
張り付けられた銅箔を、光学的にパターニングすること
により形成される。In the present invention, the wiring provided on one main surface of the insulating film in which such a conduction hole is formed has connection pads for a semiconductor element, signal lines, via lands, and the like. These are formed, for example, by optically patterning a copper foil adhered to one surface of an insulating film.

【００１４】また、このような配線が形成された配線フ
ィルムに実装された半導体素子を被覆・封止する樹脂封
止層は、エポキシ樹脂等の絶縁性樹脂から構成される。
そして、このような樹脂封止層の形成には、トランスフ
ァモールドのような金型を用いたモールド成形やポッテ
ィング（注型）などの方法が採られる。The resin sealing layer for covering and sealing the semiconductor element mounted on the wiring film having such wiring formed thereon is made of an insulating resin such as an epoxy resin.
In order to form such a resin sealing layer, a method such as molding using a mold such as transfer molding or potting (casting) is employed.

【００１５】さらに本発明において、配線フィルムの樹
脂封止面と反対側の主面に、外部接続端子として形成さ
れるバンプは、Ｐｂ／Ｓｎ系のはんだを素材としたもの
であり、特にＳｎ62％とＰｂ38％から成る共晶はんだに
より構成することが望ましい。このようなはんだバンプ
の形成は、前記した形状を有する導通用の孔内に、ペー
スト状のはんだフラックスを塗布した後、はんだボール
を挿入して嵌め込み、しかる後、加熱してハンダボール
をリフローさせることにより行なわれる。Further, in the present invention, the bump formed as an external connection terminal on the main surface opposite to the resin sealing surface of the wiring film is made of a Pb / Sn-based solder. And eutectic solder composed of Pb 38%. The formation of such a solder bump is performed by applying a paste-like solder flux into the conduction hole having the above-described shape, inserting and fitting a solder ball, and then heating to reflow the solder ball. It is done by doing.

【００１６】そして本発明の半導体装置では、導通用の
孔が、四角形、六角形等の多角形の断面形状を有するよ
うに加工されており、あるいは断面円形で側部に孔の底
部に達する溝が連接形成されており、前記したハンダボ
ールのリフロー時に、孔の内壁面とはんだボールの外周
面との間に、はんだフラックスの逃げ路となる隙間が存
在しているので、加熱によりリフローしたはんだが孔内
に充填するより先に、あるいはリフローはんだの充填と
同時に、孔の底部に溜まったはんだフラックスが、隙間
を通って外部に流れ出る。In the semiconductor device of the present invention, the conduction hole is processed so as to have a polygonal cross section such as a quadrangle or a hexagon, or a groove having a circular cross section reaching the bottom of the hole on the side. Are formed continuously, and at the time of the reflow of the solder ball, there is a clearance between the inner wall surface of the hole and the outer peripheral surface of the solder ball as an escape path for the solder flux. Prior to filling in the hole or simultaneously with the reflow solder filling, the solder flux accumulated at the bottom of the hole flows out through the gap to the outside.

【００１７】したがって、はんだフラックスが導通用孔
の底部に溜まった状態で閉じ込められることがなく、孔
内に充填されたリフローはんだにより、ヴィアランドと
の良好な接続が得られる。[0017] Therefore, the solder flux is not trapped in a state of being accumulated at the bottom of the conduction hole, and a good connection with the via land can be obtained by the reflow solder filled in the hole.

【００１８】[0018]

【発明の実施の形態】以下、本発明の実施例を図面に基
づいて説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１９】図１は、本発明の一実施例に係る半導体装
置の構造を断面的に示したものである。また、図２は実
施例の要部を拡大して示す図であり、（ａ）は平面図で
あり、（ｂ）は（ａ）におけるＡ−Ａ断面図である。FIG. 1 is a sectional view showing the structure of a semiconductor device according to one embodiment of the present invention. FIG. 2 is an enlarged view showing a main part of the embodiment, in which (a) is a plan view, and (b) is a cross-sectional view along AA in (a).

【００２０】これらの図において、符号９は、ポリイミ
ド樹脂フィルムのような絶縁性樹脂フィルムを示し、こ
の絶縁性樹脂フィルム９の所定の位置に、四角形の断面
形状を有する導通用の孔１０がアレイ状に配列されて形
成されている。また、このような導通用孔１０が開けら
れた絶縁性樹脂フィルム９の一主面上には、半導体素子
の接続用パッド１１ａや外部接続端子の接続用ランド
（ヴィアランド）１１ｂ、信号線などの配線１１群が、
銅箔のフォトパターニングにより形成されている。ここ
で、半導体素子の接続用パッド１１ａは、搭載される半
導体素子の電極端子に対応して配設されており、ヴィア
ランド１１ｂは、導通用孔１０の上に孔を塞ぐように設
けられている。In these figures, reference numeral 9 denotes an insulating resin film such as a polyimide resin film. At predetermined positions of the insulating resin film 9, conductive holes 10 having a rectangular cross section are arrayed. They are arranged in a shape. Further, on one main surface of the insulating resin film 9 in which the conduction holes 10 are formed, connection pads 11a for semiconductor elements, connection lands (via lands) 11b for external connection terminals, signal lines, etc. The wiring 11 group of
It is formed by photo patterning of a copper foil. Here, the connection pads 11a of the semiconductor element are provided corresponding to the electrode terminals of the semiconductor element to be mounted, and the via lands 11b are provided on the conduction holes 10 so as to close the holes. I have.

【００２１】また、このような配線フィルムの配線１１
形成面上には、フェースアップに配置された半導体素子
１２が接着されており、この半導体素子１２の各電極端
子１２ａは対応する接続用パッド１１ａに、それぞれ金
線のようなボンディングワイヤ１３により電気的に接続
されている。そして、このような半導体素子１２とボン
ディングワイヤ１３およびこれらの接合部の外側には、
エポキシ樹脂等の樹脂封止層１４がトランスファモール
ドにより形成されている。The wiring 11 of such a wiring film
On the formation surface, a semiconductor element 12 arranged face-up is bonded, and each electrode terminal 12a of the semiconductor element 12 is electrically connected to a corresponding connection pad 11a by a bonding wire 13 such as a gold wire. Connected. The semiconductor element 12 and the bonding wire 13 and the outside of the joint between them are
A resin sealing layer 14 such as an epoxy resin is formed by transfer molding.

【００２２】さらに、このような配線フィルムの樹脂封
止層１４と反対側の面には、Ｐｂ／Ｓｎ系の共晶はんだ
から成るバンプ１５が、導通用孔１０内にはんだボール
を挿嵌し加熱してリフローさせることにより、取り付け
られている。そして、これらのはんだバンプ１５の基部
は、断面四角形の導通用孔１０内に嵌め込まれて、孔１
０の他面側に設けられヴィアランド１１ｂに直接接触し
ており、はんだと銅との共晶形成による強固な接合がな
されている。なお、図２において、符号１６は絶縁性樹
脂フィルム９の片面に設けられた接着剤層を示し、符号
１７はヴィアランド１１ｂ等を保護するための絶縁レジ
スト層を示している。Further, a bump 15 made of a Pb / Sn-based eutectic solder is inserted on the surface of the wiring film opposite to the resin sealing layer 14 by inserting a solder ball into the conduction hole 10. It is attached by heating and reflowing. Then, the bases of these solder bumps 15 are fitted into the conductive holes 10 having a rectangular cross section,
0 is provided on the other surface side and is in direct contact with the via land 11b, and a strong joint is formed by eutectic formation of solder and copper. In FIG. 2, reference numeral 16 denotes an adhesive layer provided on one surface of the insulating resin film 9, and reference numeral 17 denotes an insulating resist layer for protecting the via land 11b and the like.

【００２３】このように構成される実施例の半導体装置
においては、導通用孔１０が、四角形の断面形状を有し
ているので、導通用孔１０内に挿嵌されたはんだボール
をリフローしてはんだバンプ１５を形成する際に、先に
孔内に塗布されたはんだフラックスが、四角柱状の孔の
内壁面とはんだボールの外周面との間の隙間を通り、容
易に外部に流れ出る。したがって、はんだフラックスが
導通用孔１０の底部に溜まった状態で閉じ込められるこ
とがなく、リフローしたはんだボールが孔内に充填し
て、はんだバンプ１５とヴィアランド１１ｂとの良好な
接続が達成される。In the semiconductor device of the embodiment configured as described above, since the conduction hole 10 has a square cross-sectional shape, the solder ball inserted into the conduction hole 10 is reflowed. When the solder bumps 15 are formed, the solder flux previously applied to the holes easily flows out through the gap between the inner wall surface of the square pillar-shaped hole and the outer peripheral surface of the solder ball. Therefore, the solder flux is not trapped in a state of being collected at the bottom of the conduction hole 10, and the reflowed solder ball fills the hole, thereby achieving a good connection between the solder bump 15 and the via land 11b. .

【００２４】次に、本発明の別の実施例について説明す
る。Next, another embodiment of the present invention will be described.

【００２５】図３および図４は、それぞれ本発明の第２
の実施例および第３の実施例に係る半導体装置の要部を
示し、各図において、（ａ）は平面図であり、（ｂ）は
（ａ）におけるＡ−Ａ断面図である。なお、図３および
図４において、図２と同一の部分には同一の符号を付し
て説明を省略する。FIGS. 3 and 4 show the second embodiment of the present invention, respectively.
FIGS. 3A and 3B show main parts of a semiconductor device according to the third embodiment and the third embodiment. In each of the drawings, FIG. 4A is a plan view, and FIG. In FIGS. 3 and 4, the same parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

【００２６】第２の実施例の半導体装置では、図３
（ａ）および（ｂ）にそれぞれ示すように、絶縁性樹脂
フィルム９の所定の位置に、六角形の断面形状を有する
導通用孔１０がアレイ状に配列されて形成されており、
このような導通用孔１０が設けられた絶縁性樹脂フィル
ム９の一主面上に、接続用パッド１１ａやヴィアランド
１１ｂ等の配線１１群が形成され、半導体素子１２が実
装されている。そして、この配線フィルムの樹脂封止層
１４と反対側の面には、Ｐｂ／Ｓｎ系の共晶はんだのバ
ンプ１５が、断面六角形の導通用孔１０を埋めるように
取り付けられており、はんだバンプ１５とヴィアランド
１１ｂとが、はんだと銅との共晶形成により強固に接合
されている。In the semiconductor device of the second embodiment, FIG.
As shown in (a) and (b), conductive holes 10 having a hexagonal cross-sectional shape are formed at predetermined positions of the insulating resin film 9 in an array.
On one main surface of the insulating resin film 9 provided with such conduction holes 10, a group of wirings 11 such as connection pads 11a and via lands 11b are formed, and a semiconductor element 12 is mounted. A bump 15 made of a Pb / Sn-based eutectic solder is attached to a surface of the wiring film opposite to the resin sealing layer 14 so as to fill the conduction hole 10 having a hexagonal cross section. The bump 15 and the via land 11b are firmly joined by eutectic formation of solder and copper.

【００２７】第３の実施例の半導体装置では、図４
（ａ）および（ｂ）にそれぞれ示すように、絶縁性樹脂
フィルム９の所定の位置に、以下に示す側溝１８を有す
る導通用孔１０が形成されている。すなわち、側溝１８
は三角錐形でフィルム厚に等しい深さを有しており、こ
のような側溝１８が、断面円形の孔本体１０ａの側部に
連接して形成されている。そして、このような導通用孔
１０が設けられた絶縁性樹脂フィルム９の一主面（側溝
１８の開口面と反対側の面）上に、接続用パッド１１ａ
やヴィアランド１１ｂ等の配線１１群が形成され、半導
体素子１２が実装されている。また、この配線フィルム
の樹脂封止層１４と反対側の面には、Ｐｂ／Ｓｎ系の共
晶はんだのバンプ１５が、導通用孔１０を埋めて取り付
けられており、はんだバンプ１５とヴィアランド１１ｂ
とは強固に接合されている。In the semiconductor device of the third embodiment, FIG.
As shown in (a) and (b), a conduction hole 10 having a side groove 18 described below is formed at a predetermined position of the insulating resin film 9. That is, the side groove 18
Has a depth equal to the film thickness in a triangular pyramid shape, and such a side groove 18 is formed so as to be connected to a side portion of the hole main body 10a having a circular cross section. Then, on one main surface (the surface opposite to the opening surface of the side groove 18) of the insulating resin film 9 provided with such conduction holes 10, the connection pads 11a are provided.
And a group of wirings 11 such as via land 11b are formed, and a semiconductor element 12 is mounted. A bump 15 made of a Pb / Sn-based eutectic solder is attached to the surface of the wiring film opposite to the resin sealing layer 14 so as to fill the conduction hole 10. 11b
And are firmly joined.

【００２８】このように構成される第２の実施例および
第３の実施例の半導体装置においては、導通用孔１０の
内壁面と孔１０内に挿嵌されたはんだボールの外周面と
の間に隙間が生じるようになっているので、はんだボー
ルをリフローしてはんだバンプ１５を形成する際に、先
に孔内に塗布されたはんだフラックスが、この隙間を通
って容易に外部に流れ出ることができる。したがって、
はんだフラックスが導通用孔１０の底部に溜まった状態
で閉じ込められることがなく、リフローしたはんだボー
ルが孔内に充填し、はんだバンプ１５とヴィアランド１
１ｂとの良好な接続が得られる。In the semiconductor devices of the second and third embodiments configured as described above, the gap between the inner wall surface of the conduction hole 10 and the outer peripheral surface of the solder ball inserted into the hole 10 is set. When the solder balls are reflowed to form the solder bumps 15, the solder flux previously applied to the holes may easily flow to the outside through the gaps. it can. Therefore,
The solder flux is not trapped in a state where it has accumulated at the bottom of the conduction hole 10, and the reflowed solder balls fill the hole, and the solder bump 15 and the via land 1
Good connection with 1b is obtained.

【００２９】[0029]

【発明の効果】以上の説明から明らかなように、本発明
の半導体装置においては、はんだフラックスの流通路と
なる隙間が、導通用孔の内壁面と孔内に嵌め込まれるは
んだボールとの間に存在しているので、はんだリフロー
時のフラックスの逃げが容易である。したがって、外部
接続端子であるはんだバンプとヴィアランドとの接続不
良が防止され、良好な接続が得られる。As is apparent from the above description, in the semiconductor device of the present invention, the gap serving as the flow path of the solder flux is formed between the inner wall surface of the conduction hole and the solder ball fitted in the hole. Since it is present, it is easy for the flux to escape during solder reflow. Therefore, poor connection between the solder bumps serving as the external connection terminals and the via land is prevented, and good connection is obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体装置の一実施例を示す断面図。FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention.

【図２】同実施例の要部を拡大して示す図であり、
（ａ）は平面図、（ｂ）は（ａ）におけるＡ−Ａ断面
図。FIG. 2 is an enlarged view showing a main part of the embodiment;
(A) is a top view, (b) is AA sectional drawing in (a).

【図３】本発明の第２の実施例に係る半導体装置の要部
を示し、（ａ）は平面図、（ｂ）は（ａ）におけるＡ−
Ａ断面図。FIGS. 3A and 3B show a main part of a semiconductor device according to a second embodiment of the present invention, wherein FIG. 3A is a plan view, and FIG.
A sectional drawing.

【図４】本発明の第３の実施例に係る半導体装置の要部
を示し、（ａ）は平面図、（ｂ）は（ａ）におけるＡ−
Ａ断面図。FIGS. 4A and 4B show a main part of a semiconductor device according to a third embodiment of the present invention, wherein FIG. 4A is a plan view, and FIG.
A sectional drawing.

【図５】従来の半導体装置において、はんだリフロー時
のフラックスの状態を説明するための断面図。FIG. 5 is a cross-sectional view illustrating a state of a flux at the time of solder reflow in a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

９………絶縁性樹脂フィルム １０………導通用孔 １１………配線 １１ｂ………ヴィアランド １２………半導体素子 １３………ボンディングワイヤ １４………樹脂封止層 １５………はんだバンプ １８………側溝 9 Insulating resin film 10 Conducting hole 11 Wiring 11b Vialand 12 Semiconductor element 13 Bonding wire 14 Resin sealing layer 15 Solder bump 18 ... Side groove

───────────────────────────────────────────────────── フロントページの続き (72)発明者 根岸 徳昭 神奈川県川崎市川崎区駅前本町25番地１ 東芝マイクロエレクトロニクス株式会社内 (72)発明者 岸 博明 神奈川県川崎市川崎区駅前本町25番地１ 東芝マイクロエレクトロニクス株式会社内 (72)発明者 高島 昇 長野県長野市大字栗田字舎利田711番地 新光電気工業株式会社内 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tokuaki Negishi 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Inside (72) Inventor Hiroaki Kishi 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki-ku, Kanagawa Prefecture Toshiba Microelectronics Co., Ltd. (72) Inventor Noboru Takashima Nagano City, Nagano Pref.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 絶縁性フィルムの所定の位置に導通用の
孔が形成され、かつ一主面に所要の配線が形成された配
線フィルムと、 前記配線フィルムの配線形成面上に搭載され実装された
半導体素子と、 前記半導体素子の実装部を被覆し封止する樹脂封止層
と、 前記配線フィルムの他主面側から前記導通用孔内に埋め
込まれ、前記配線に接続されたはんだバンプとを備えた
半導体装置において、 前記導通用孔が、前記はんだバンプ形成のためのはんだ
リフロー時に、該孔の内壁面と孔内に挿嵌されたはんだ
ボールの外周面との間に、はんだ付け用フラックスが流
通する隙間を持つ形状を有することを特徴とする半導体
装置。1. A wiring film in which a hole for conduction is formed at a predetermined position of an insulating film and a required wiring is formed on one main surface; and a wiring film is mounted and mounted on a wiring forming surface of the wiring film. A semiconductor element, a resin sealing layer that covers and seals a mounting portion of the semiconductor element, and a solder bump embedded in the conduction hole from the other main surface side of the wiring film and connected to the wiring. In the semiconductor device, the conductive hole is provided between the inner wall surface of the hole and the outer peripheral surface of the solder ball inserted in the hole during solder reflow for forming the solder bump. A semiconductor device having a shape having a gap through which a flux flows. 【請求項２】 前記導通用孔が、多角形の断面形状を有
することを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said conduction hole has a polygonal cross-sectional shape. 【請求項３】 前記導通用孔が、前記配線フィルムの他
主面側に開口した溝を、該孔の内壁面に連接して有する
ことを特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the conduction hole has a groove opened on the other main surface side of the wiring film and connected to an inner wall surface of the hole. 【請求項４】 前記はんだバンプが、Ｐｂ／Ｓｎ系の共
晶はんだから成り、かつ前記配線フィルムの他主面に格
子状に配列されていることを特徴とする請求項１乃至３
のいずれか１項記載の半導体装置。4. The solder bump according to claim 1, wherein the solder bumps are made of a Pb / Sn eutectic solder, and are arranged in a grid pattern on the other main surface of the wiring film.
The semiconductor device according to claim 1.
JP9343045A 1997-12-12 1997-12-12 Semiconductor device Abandoned JPH11176890A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9343045A JPH11176890A (en) 1997-12-12 1997-12-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9343045A JPH11176890A (en) 1997-12-12 1997-12-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH11176890A true JPH11176890A (en) 1999-07-02

Family

ID=18358521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9343045A Abandoned JPH11176890A (en) 1997-12-12 1997-12-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH11176890A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1303171A2 (en) * 2001-10-11 2003-04-16 Alps Electric Co., Ltd. Electronic circuit unit suitable for miniaturization
US8115290B2 (en) 2008-02-29 2012-02-14 Kabushiki Kaisha Toshiba Storage medium and semiconductor package

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1303171A2 (en) * 2001-10-11 2003-04-16 Alps Electric Co., Ltd. Electronic circuit unit suitable for miniaturization
EP1303171A3 (en) * 2001-10-11 2005-11-16 Alps Electric Co., Ltd. Electronic circuit unit suitable for miniaturization
US8115290B2 (en) 2008-02-29 2012-02-14 Kabushiki Kaisha Toshiba Storage medium and semiconductor package
USRE48110E1 (en) 2008-02-29 2020-07-21 Toshiba Memory Corporation Storage medium and semiconductor package
USRE49332E1 (en) 2008-02-29 2022-12-13 Kioxia Corporation Storage medium and semiconductor package

Similar Documents

Publication Publication Date Title
US6528869B1 (en) Semiconductor package with molded substrate and recessed input/output terminals
KR100244580B1 (en) Method for manufacturing circuit board having matal bump and semiconductor chip package
US6734557B2 (en) Semiconductor device
US5900676A (en) Semiconductor device package structure having column leads and a method for production thereof
TWI478254B (en) Bump-on-lead flip chip interconnection
JP5095074B2 (en) Package stacking structure
US7662672B2 (en) Manufacturing process of leadframe-based BGA packages
US7420814B2 (en) Package stack and manufacturing method thereof
JPH11204720A (en) Semiconductor device and its manufacture
US6590286B2 (en) Land grid array semiconductor device
JP3486872B2 (en) Semiconductor device and manufacturing method thereof
JP2003092376A (en) Method and structure of mounting semiconductor device, and semiconductor device and method of manufacturing the same
JPH11176890A (en) Semiconductor device
KR100247508B1 (en) Semiconductor package for a flip chip and its manufacturing method
US20020125568A1 (en) Method Of Fabricating Chip-Scale Packages And Resulting Structures
KR100575858B1 (en) Chip scale package and method of fabricating the same
KR20010061784A (en) Chip scale package and method of fabricating the same
KR20030012994A (en) Tape ball grid array semiconductor chip package having ball land pad which is isolated with adhesive and manufacturing method thereof and multi chip package
KR100246367B1 (en) Semiconductor package and manufacturing method
JP3563170B2 (en) Method for manufacturing semiconductor device
KR100481424B1 (en) Method for manufacturing chip scale package
JP3707639B2 (en) Structure of area array package type semiconductor device
KR100648044B1 (en) Method for manufacturing semiconductor package
KR100303363B1 (en) wafer level package and method of fabricating the same
KR100331386B1 (en) Wafer level package

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040722

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050518

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050524

A762 Written abandonment of application

Free format text: JAPANESE INTERMEDIATE CODE: A762

Effective date: 20050720