JPH11168306A - Element provided with thin film multi-layer electrode and manufacture therefor - Google Patents
Element provided with thin film multi-layer electrode and manufacture thereforInfo
- Publication number
- JPH11168306A JPH11168306A JP9331885A JP33188597A JPH11168306A JP H11168306 A JPH11168306 A JP H11168306A JP 9331885 A JP9331885 A JP 9331885A JP 33188597 A JP33188597 A JP 33188597A JP H11168306 A JPH11168306 A JP H11168306A
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- Prior art keywords
- film
- thin
- flattening
- multilayer electrode
- dielectric substrate
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、主として高周波領
域において使用される薄膜多層電極を有する素子および
その製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device having a thin-film multilayer electrode mainly used in a high-frequency region and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】近年、電子部品の小型化が進む中、マイ
クロ波、準ミリ波またはミリ波などの高周波帯において
も、高誘電率材料を用いることによってデバイスの小型
化が図られている。しかし、高誘電率材料を用いること
によって形状を縮小すると、体積の立方根に反比例して
エネルギー損失が増大するという問題点があった。この
高周波デバイスのエネルギー損失は、表皮効果による導
体損失と、誘電体材料による誘電体損失とに大きく分類
することができるが、近年では、高誘電率のものでも低
損失な特性を有する誘電体材料が実用化されており、従
って、誘電体損失よりも導体損失の方がエネルギー損失
において支配的な割合を占めるようになっている。2. Description of the Related Art In recent years, as electronic components have been miniaturized, devices have been miniaturized by using high dielectric constant materials even in high frequency bands such as microwaves, quasi-millimeter waves or millimeter waves. However, when the shape is reduced by using the high dielectric constant material, there is a problem that the energy loss increases in inverse proportion to the cubic root of the volume. The energy loss of this high-frequency device can be broadly classified into a conductor loss due to the skin effect and a dielectric loss due to a dielectric material. In recent years, a dielectric material having a high dielectric constant and having a low loss characteristic has been developed. Has been put into practical use, and therefore, conductor loss occupies a more dominant proportion in energy loss than dielectric loss.
【０００３】以上のような状況の下、本出願人は国際出
願公開第ＷＯ９５／０６３３６号公報において、高周波
帯での導体損失を低減しうる電極として、誘電体基板上
に薄膜導体層と薄膜誘電体層とを接着層を介して交互に
積層して構成した薄膜多層電極を提案した。なお、ここ
で提案されている薄膜多層電極は、平坦な表面を有する
誘電体基板（鏡面研磨の施されたアルミナの単結晶から
なるサファイア基板が例示されている）上に形成される
ことを前提として薄膜導体層と薄膜誘電体層の各膜厚が
設定されている。Under the circumstances described above, the applicant of the present application has disclosed in International Patent Application Publication No. WO95 / 06336 as a thin film conductor layer and a thin film dielectric on a dielectric substrate as electrodes capable of reducing conductor loss in a high frequency band. A thin-film multilayer electrode composed of a body layer and an adhesive layer alternately stacked is proposed. It is assumed that the thin-film multilayer electrode proposed here is formed on a dielectric substrate having a flat surface (a sapphire substrate made of a single crystal of alumina subjected to mirror polishing is exemplified). The thickness of each of the thin-film conductor layer and the thin-film dielectric layer is set.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、例えば
誘電体基板としてセラミック基板を用いるような場合、
通常その基板表面はポア等の存在により凹凸を有してい
る。この凹凸は、表面研磨処理等によってある程度平坦
化することが可能である。しかし、ポアは基板表面のみ
ならず基板内部にも多数存在するため、研磨処理によっ
て新たなポアが表面に顕在化することになり、基板表面
を充分には平坦化することができない。ここで、ポアを
有する誘電体基板上に薄膜多層電極を形成した場合の膜
構造を示す断面図を、図３に示す。図３に示すように、
誘電体基板３２上に薄膜導体層３５および薄膜誘電体層
３６がそれぞれ積層されて薄膜多層電極３４が形成され
ているが、薄膜導体層３５および薄膜誘電体層３６は基
板３２のポア３７に対応して凹凸を有するものとなる。
このように各層が凹凸を持って形成されると、当初の設
計通りの低損失動作を実現できなくなる。また、ポアを
有する基板上に薄膜を積層する場合、成膜プロセス上、
隣接する薄膜導体層同士が短絡する恐れが非常に高くな
る。これらの事態は、いずれも薄膜多層電極の有する表
皮効果の抑制効果を大幅に劣化させてしまう。However, for example, when a ceramic substrate is used as a dielectric substrate,
Usually, the substrate surface has irregularities due to the presence of pores and the like. These irregularities can be flattened to some extent by surface polishing or the like. However, since a large number of pores exist not only on the substrate surface but also inside the substrate, new pores become apparent on the surface by the polishing treatment, and the substrate surface cannot be sufficiently planarized. Here, FIG. 3 is a cross-sectional view showing a film structure when a thin film multilayer electrode is formed on a dielectric substrate having pores. As shown in FIG.
The thin-film conductor layer 35 and the thin-film dielectric layer 36 are respectively laminated on the dielectric substrate 32 to form the thin-film multilayer electrode 34. The thin-film conductor layer 35 and the thin-film dielectric layer 36 correspond to the pores 37 of the substrate 32. As a result, it has irregularities.
If each layer is formed with irregularities in this way, it is impossible to realize a low-loss operation as originally designed. In addition, when a thin film is laminated on a substrate having pores,
The risk of short-circuiting between adjacent thin film conductor layers is very high. All of these situations greatly deteriorate the effect of suppressing the skin effect of the thin-film multilayer electrode.
【０００５】このような問題に対処して本願出願人は、
特願平８−１４００５６および特願平９−２８８７４８
において、誘電体基板と薄膜多層電極との間に基板の凹
凸を平坦化するための平坦化膜を介在させる方法を提案
し、これらの問題点の解決を図った。In response to such a problem, the present applicant has
Japanese Patent Application Nos. 8-140056 and 9-288748.
Proposed a method of interposing a flattening film for flattening the unevenness of the substrate between the dielectric substrate and the thin-film multilayer electrode, and solved these problems.
【０００６】しかしながらこれらの方法によった場合で
あっても、新たに以下のような問題点が発生していた。
すなわち平坦化膜を成膜するにあたっては、図４（ａ）
〜（ｄ）に示すように、誘電体基板３２上に例えばスパ
ッタリング等の手法で平坦化膜３３の表面が平坦になる
まで成膜を続け、その後に薄膜多層電極３４を形成して
いた。このため、平坦化膜３３の成膜完了までに多くの
時間がかかり量産には不向きであった。また平坦化膜３
３の膜厚が厚くなるため、その上に形成される薄膜多層
電極３４の電気的特性に与える影響が大きくなる等の問
題があった。However, even in the case of using these methods, the following problems newly occur.
That is, in forming the planarizing film, the film shown in FIG.
As shown in (d), film formation was continued on the dielectric substrate 32 by, for example, a technique such as sputtering until the surface of the flattening film 33 became flat, and then the thin film multilayer electrode 34 was formed. Therefore, it takes a lot of time to complete the formation of the flattening film 33, which is not suitable for mass production. Also, the planarizing film 3
Since the film thickness of No. 3 is increased, there is a problem that the influence on the electrical characteristics of the thin-film multilayer electrode 34 formed thereon is increased.
【０００７】従って本発明の目的は、上述の技術的問題
点を解決するためになされたものであって、基板の凹凸
の影響を受けにくい構造を有する薄膜多層電極を有する
素子、及びその製造方法を提供することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned technical problems, and it is an object to provide a device having a thin-film multilayer electrode having a structure that is hardly affected by unevenness of a substrate, and a method of manufacturing the same. Is to provide.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に、本発明の薄膜多層電極を有する素子においては、誘
電体基板と、誘電体基板上に薄膜導体層と薄膜誘電体層
とを接着層を介して交互に積層した薄膜多層電極と、誘
電体基板と薄膜多層電極との間に介在された平坦化膜と
を備えてなる薄膜多層電極を有する素子であって、前記
平坦化膜の薄膜多層電極と接する面に、その表面を平坦
化するための研磨処理が施されている。In order to achieve the above object, in an element having a thin-film multilayer electrode according to the present invention, a dielectric substrate and a thin-film conductor layer and a thin-film dielectric layer are bonded on the dielectric substrate. An element having a thin-film multilayer electrode comprising a thin-film multilayer electrode alternately stacked with layers and a planarizing film interposed between a dielectric substrate and a thin-film multilayer electrode, wherein the flattening film has A surface in contact with the thin-film multilayer electrode is subjected to a polishing treatment for flattening the surface.
【０００９】このように、平坦化膜に研磨処理を施して
基板の平坦化に寄与していない部分の平坦化膜は積極的
に除去することにより、誘電体基板と薄膜多層電極との
間に介在する平坦化膜の膜厚を薄くすることができる。
これにより平坦化膜が薄膜多層電極に及ぼす影響を低く
抑えることができる。また従来と異なり、研磨処理によ
って平坦化するので、平坦化されるまで成膜し続ける必
要がなくなり、成膜時間の短縮を図ることができる。As described above, the flattening film is polished, and the portion of the flattening film not contributing to the flattening of the substrate is positively removed. The thickness of the intervening flattening film can be reduced.
Thus, the influence of the flattening film on the thin-film multilayer electrode can be suppressed. Further, unlike the related art, since the surface is flattened by the polishing process, it is not necessary to continuously form the film until the surface is flattened, and the film formation time can be reduced.
【００１０】なお、平坦化膜にはＴｉ、Ｔａ、Ｗ、Ｃ
ｒ、Ｚｒ、Ｎｂ、Ｈｆ、Ｖ、Ｍｏ、Ｔｉ−Ｎ、Ｔａ−
Ｎ、あるいはこれらを２種以上混合して得られる材料、
あるいはこれらに添加物を加えた材料などを使用するこ
とが好ましい。これらの材料は、誘電体基板や薄膜多層
電極を構成する薄膜導体層と結合しやすく、その接着作
用により誘電体基板と薄膜多層電極との密着度を高める
ことができるからである。またこれらの材料は、薄膜多
層電極を構成する薄膜導体層と薄膜誘電体層との接着の
ためにも用いられており、使用する材料を共通化でき成
膜の効率化を図ることができる。Note that Ti, Ta, W, C
r, Zr, Nb, Hf, V, Mo, Ti-N, Ta-
N, or a material obtained by mixing two or more of these,
Alternatively, it is preferable to use a material in which an additive is added to these. This is because these materials are easily bonded to the dielectric substrate and the thin-film conductor layer forming the thin-film multilayer electrode, and the adhesion thereof can increase the degree of adhesion between the dielectric substrate and the thin-film multilayer electrode. These materials are also used for bonding the thin-film conductor layer and the thin-film dielectric layer constituting the thin-film multilayer electrode, so that the materials used can be made common and the efficiency of film formation can be increased.
【００１１】また、本発明の薄膜多層電極を有する素子
の製造方法は、誘電体基板上に薄膜導体層と薄膜誘電体
層とを接着層を介して交互に積層した薄膜多層電極を形
成してなる薄膜多層電極を有する素子の製造方法におい
て、誘電体基板を準備する工程と、誘電体基板表面に、
基板表面の凹凸を平坦化する平坦化膜を形成する工程
と、平坦化膜の表面が平坦になるように不要部分を除去
する除去工程と、除去工程後の平坦化膜上に薄膜多層電
極を形成する工程とを有する。Further, according to the method of manufacturing an element having a thin-film multilayer electrode of the present invention, a thin-film multilayer electrode in which thin-film conductor layers and thin-film dielectric layers are alternately laminated on a dielectric substrate via an adhesive layer is formed. In the method for manufacturing an element having a thin-film multilayer electrode, a step of preparing a dielectric substrate, and on the surface of the dielectric substrate,
A step of forming a flattening film for flattening irregularities on the substrate surface, a removing step of removing unnecessary portions so that the surface of the flattening film becomes flat, and forming a thin-film multilayer electrode on the flattening film after the removing step. Forming.
【００１２】なお除去工程は、薄膜多層電極を安定して
低損失動作させるために、平坦化膜の表面粗さＲａが
０．０５μｍ以下となるように研磨処理を施す工程を含
むことが望ましい。The removing step desirably includes a step of performing a polishing treatment so that the surface roughness Ra of the flattening film is 0.05 μm or less in order to stably operate the thin-film multilayer electrode with low loss.
【００１３】また、特に平面研削やバフ研磨などの研磨
方法によった場合、研磨処理中に平坦化膜の表面が酸化
して加工変質層となり導電性の悪化を招く場合がある。
従って、ウェットエッチング等により、この加工変質層
を除去することが望ましい。Further, in particular, when a polishing method such as surface grinding or buff polishing is used, the surface of the flattening film may be oxidized during the polishing process to become a work-affected layer, resulting in deterioration of conductivity.
Therefore, it is desirable to remove the affected layer by wet etching or the like.
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施の形態を図を
参照して詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１５】［第１実施例、図１〜図２］第１実施例の
薄膜多層電極を有する素子１を、図１に示す。図１は素
子１の断面図であり、誘電体基板２上に平坦化膜３およ
び薄膜多層電極４が形成されて構成されている。誘電体
基板２にはポア７が存在しているが、平坦化膜３によっ
て、誘電体基板２の表面は平坦化されている。平坦化膜
３上には薄膜導体層５と薄膜誘電体層６とを交互に積層
して構成された薄膜多層電極４が形成されている。薄膜
多層電極４を構成する各層は、ポア７の影響を受けるこ
となくそれぞれ平坦に形成されている。[First Embodiment, FIGS. 1 and 2] FIG. 1 shows an element 1 having a thin-film multilayer electrode according to the first embodiment. FIG. 1 is a cross-sectional view of an element 1, which is configured by forming a planarizing film 3 and a thin-film multilayer electrode 4 on a dielectric substrate 2. Although the pores 7 exist in the dielectric substrate 2, the surface of the dielectric substrate 2 is planarized by the planarization film 3. On the flattening film 3, a thin-film multilayer electrode 4 formed by alternately stacking thin-film conductor layers 5 and thin-film dielectric layers 6 is formed. Each layer constituting the thin film multilayer electrode 4 is formed flat without being affected by the pores 7.
【００１６】次に、本実施例の素子１の製造方法につい
て図２（ａ）〜（ｄ）を用いて説明する。Next, a method for manufacturing the element 1 of this embodiment will be described with reference to FIGS.
【００１７】まず誘電体基板２を準備し、該基板上にス
パッタリング法によってＴｉからなる平坦化膜３を形成
する。平坦化膜３はポア７の窪んだ部分が十分に埋まる
程度以上に厚く成膜する（図２（ａ）、（ｂ））。つぎ
に、必要以上に厚く成膜された平坦化膜３の不要部分
（すなわち平坦化膜のうち、誘電体基板の平坦化に寄与
していない部分）を研磨処理によって除去する（図２
（ｃ））。そして、研磨処理の施された平坦化膜３上に
薄膜多層電極４を所定の膜厚設計値に基づいて形成する
（図２（ｄ））。以上のようにして素子１を製造する。First, a dielectric substrate 2 is prepared, and a flattening film 3 made of Ti is formed on the dielectric substrate 2 by a sputtering method. The flattening film 3 is formed thick enough to sufficiently fill the recessed part of the pore 7 (FIGS. 2A and 2B). Next, unnecessary portions of the flattening film 3 formed more than necessary (that is, portions of the flattening film that do not contribute to the flattening of the dielectric substrate) are removed by polishing (FIG. 2).
(C)). Then, a thin-film multilayer electrode 4 is formed on the polished planarizing film 3 based on a predetermined film thickness design value (FIG. 2D). The element 1 is manufactured as described above.
【００１８】ところで、本実施例において平坦化膜３の
材料としてＴｉを使用したのは、ＴｉがＳｉＯ２などか
らなる誘電体基板２およびＣｕなどからなる薄膜導体層
５の双方に対して高い密着度を有するからである。この
ように密着性の高い材料を使用することにより、経時劣
化や熱膨張係数の差によって生じる膜剥がれを効果的に
抑制することができる。誘電体基板２および薄膜導体層
５の双方に対して高い密着度を有する材料としては、Ｔ
ｉの他にＴａ、Ｗ、Ｃｒ、Ｚｒ、Ｎｂ、Ｈｆ、Ｖ、Ｍ
ｏ、Ｔｉ−Ｎ、Ｔａ−Ｎ、あるいはこれらを２種以上混
合して得られる材料、あるいはこれらに添加物を加えた
材料を考慮しうる。なお、これらの材料は薄膜多層電極
４を構成する薄膜導体層５と薄膜誘電体層６との間にも
接着層として介在させる場合が多いが、この接着層と平
坦化膜の材料は成膜効率を向上させるために共通化する
ことが好ましい。In the present embodiment, the reason why Ti is used as the material of the planarizing film 3 is that Ti has a high adhesion to both the dielectric substrate 2 made of SiO2 or the like and the thin film conductor layer 5 made of Cu or the like. This is because By using such a material having high adhesiveness, it is possible to effectively suppress film peeling caused by deterioration over time and a difference in thermal expansion coefficient. Materials having high adhesion to both the dielectric substrate 2 and the thin film conductor layer 5 include T
In addition to i, Ta, W, Cr, Zr, Nb, Hf, V, M
o, Ti-N, Ta-N, a material obtained by mixing two or more of these, or a material obtained by adding an additive to these materials can be considered. In many cases, these materials are also interposed between the thin film conductor layer 5 and the thin film dielectric layer 6 constituting the thin film multilayer electrode 4 as an adhesive layer. It is preferable to share them in order to improve efficiency.
【００１９】以上で平坦化膜に好適な材料について説明
したが、これに限定するものではなく、成膜の用に供す
ることのできる材料であれば既知の種々の材料を使用す
ることができる。例えば、薄膜導体層として使用するＣ
ｕ、Ａｇ、Ａｕ、Ａｌや、Ｙ−Ｂａ−Ｃｕ−Ｏに代表さ
れる超伝導体、また薄膜誘電体層として使用するＳｉＯ
2、Ａｌ2Ｏ3、Ｓｉ3Ｎ4、Ｔａ2Ｏ5等の使用が可能であ
る。Although the materials suitable for the flattening film have been described above, the present invention is not limited to these materials, and various known materials can be used as long as they can be used for film formation. For example, C used as a thin film conductor layer
superconductors represented by u, Ag, Au, Al, and Y—Ba—Cu—O, and SiO used as a thin film dielectric layer
2 , Al 2 O 3 , Si 3 N 4 , Ta 2 O 5 and the like can be used.
【００２０】なお本実施例において、平坦化膜３の成膜
にスパッタリング法を用いたのは、ポアを平坦化するた
めに要する膜厚が比較的薄く済むからである。これによ
り、成膜時間の短縮化が図れ同時に研磨処理に要する時
間も短縮することができる。また、平坦化膜３上に形成
する薄膜多層電極４は通常スパッタリング法によって形
成されるので、成膜手法の共通化をはかれる。もっとも
成膜方法はこれに限定するものではなく、蒸着法、ＭＯ
−ＣＶＤ法等の真空成膜法、印刷焼成法、電解メッキ法
および無電解メッキ法などの種々の成膜法を使用するこ
とができる。In this embodiment, the reason why the sputtering method is used for forming the flattening film 3 is that the film thickness required for flattening the pores is relatively small. Thereby, the film formation time can be shortened, and at the same time, the time required for the polishing process can be shortened. Further, since the thin-film multilayer electrode 4 formed on the flattening film 3 is usually formed by a sputtering method, a common film-forming method can be used. However, the film formation method is not limited to this, and the vapor deposition method, MO
-Various film forming methods such as a vacuum film forming method such as a CVD method, a printing and baking method, an electrolytic plating method, and an electroless plating method can be used.
【００２１】また本実施例の平坦化膜３の研磨処理の具
体的方法としては、平面研削、バフ研磨、斜め方向から
のミリング、ウェットエッチング等の種々の研磨方法を
用いることができる。なお、平坦化膜の表面粗さＲａが
０．０５μｍ以下となるように研磨処理を施すと、薄膜
多層電極４を構成する薄膜導体層５や薄膜誘電体層６
を、薄膜多層電極４が当初の設計値通りに安定して低損
失動作をする程度に平坦に形成することができることが
確認されている。As a specific method of polishing the flattening film 3 of this embodiment, various polishing methods such as surface grinding, buff polishing, milling from an oblique direction, and wet etching can be used. When the polishing treatment is performed so that the surface roughness Ra of the flattening film becomes 0.05 μm or less, the thin film conductor layer 5 and the thin film dielectric layer 6 constituting the thin film multilayer electrode 4 are formed.
It has been confirmed that the thin film multilayer electrode 4 can be formed flat enough to perform stable and low-loss operation as originally designed.
【００２２】［第２実施例］本発明の第２実施例の薄膜
多層電極を有する素子は、平坦化膜の不要部分を研磨処
理によって除去した後に、さらに以下で説明する加工変
質層をウェットエッチングによって除去することを特徴
とする。[Second Embodiment] In a device having a thin-film multilayer electrode according to a second embodiment of the present invention, after an unnecessary portion of a flattening film is removed by polishing, a damaged layer to be described below is further wet-etched. Characterized by the following:
【００２３】すなわち、平面研削やバフ研磨などの物理
的な研削方法で研磨処理を施す場合には、一般に、摩擦
により研磨表面が比較的高温となったり、研磨工程中に
研磨する表面を水洗する。このような状況下においては
研磨表面が非常に酸化しやすくなるが、研磨表面が酸化
されると平坦化膜３の導電性の悪化を引き起こし、その
上に形成される薄膜多層電極の特性に悪影響を及ぼす。
また、研磨表面が酸化すると平坦化膜３の有する密着性
が悪化するので、平坦化膜３の有する膜剥がれの抑制効
果を十分に実現できなくなる。That is, when the polishing process is performed by a physical grinding method such as surface grinding or buffing, the surface to be polished generally becomes relatively high due to friction or the surface to be polished during the polishing process is washed with water. . In such a situation, the polished surface is very easily oxidized. However, if the polished surface is oxidized, the conductivity of the flattening film 3 is deteriorated, and the characteristics of the thin-film multilayer electrode formed thereon are adversely affected. Effect.
In addition, when the polished surface is oxidized, the adhesion of the planarizing film 3 is deteriorated, so that the effect of suppressing the film peeling of the planarizing film 3 cannot be sufficiently realized.
【００２４】そこで加工変質層、すなわち平坦化膜の表
面に形成された酸化物の層を、平坦化膜３表面の表面粗
さを所望の値に保ちつつ酸化物層を除去しうるウェット
エッチングによって改めて除去したものである。Therefore, the work-affected layer, that is, the oxide layer formed on the surface of the flattening film is subjected to wet etching capable of removing the oxide layer while maintaining the surface roughness of the surface of the flattening film 3 at a desired value. It has been removed again.
【００２５】なお、その他の点においては素子の構造、
製造方法のいづれにおいても第１実施例の素子１と変わ
るところはないので、その説明を省略する。In other respects, the structure of the element,
Since there is no difference from the element 1 of the first embodiment in any of the manufacturing methods, the description is omitted.
【００２６】[0026]
【発明の効果】以上の説明からも明らかなように、本発
明の薄膜多層電極を有する素子やその製造方法によった
場合、以下の優れた効果が得られる。As is apparent from the above description, the following excellent effects can be obtained by the device having the thin film multilayer electrode of the present invention and the method of manufacturing the same.
【００２７】すなわち、平坦化膜に研磨処理を施して基
板の平坦化に寄与していない部分の平坦化膜は積極的に
除去することにより、誘電体基板と薄膜多層電極との間
に介在する平坦化膜の膜厚を薄くすることができる。こ
れにより平坦化膜が薄膜多層電極の特性に及ぼす影響を
低く抑えることができる。また従来と異なり、研磨処理
によって平坦化するので、ポア部分が埋まる程度まで成
膜すれば足り、平坦化膜表面が完全に平坦化されるまで
成膜し続ける必要がなくなるので、成膜時間の短縮を図
ることができる。That is, the flattening film is polished, and the portion of the flattening film not contributing to the flattening of the substrate is positively removed, so that the flattening film is interposed between the dielectric substrate and the thin-film multilayer electrode. The thickness of the planarizing film can be reduced. As a result, the effect of the flattening film on the characteristics of the thin-film multilayer electrode can be reduced. Also, unlike the conventional method, since the surface is planarized by polishing, it is sufficient to form the film until the pore portion is buried, and it is not necessary to continuously form the film until the surface of the planarized film is completely planarized. Shortening can be achieved.
【００２８】また、平坦化膜にＴｉ、Ｔａ、Ｗ、Ｃｒ、
Ｚｒ、Ｎｂ、Ｈｆ、Ｖ、Ｍｏ、Ｔｉ−Ｎ、Ｔａ−Ｎ、あ
るいはこれらを２種以上混合して得られる材料、あるい
はこれらに添加物を加えた材料を使用することにより、
その接着作用により誘電体基板と薄膜多層電極との密着
度を高めることができ、経時劣化や熱膨張係数の差によ
って生じる膜剥がれを効果的に抑制することができる。
またこれらの材料は、薄膜多層電極を構成する薄膜導体
層と薄膜誘電体層との接着のためにも用いられており、
使用する材料を共通化でき成膜の効率化を図ることがで
きる。Further, Ti, Ta, W, Cr,
By using a material obtained by mixing Zr, Nb, Hf, V, Mo, Ti-N, Ta-N, or a mixture of two or more thereof, or a material obtained by adding an additive thereto,
Due to the adhesive action, the degree of adhesion between the dielectric substrate and the thin-film multilayer electrode can be increased, and film peeling caused by deterioration with time and a difference in thermal expansion coefficient can be effectively suppressed.
These materials are also used for bonding the thin film conductor layer and the thin film dielectric layer constituting the thin film multilayer electrode,
A common material can be used, and the efficiency of film formation can be improved.
【００２９】さらに、除去工程において平坦化膜の表層
に生じた加工変質層をウェットエッチングにより除去す
ることにより、平坦化膜の導電性および密着性を良好に
保つことができる。Furthermore, by removing the damaged layer formed on the surface of the flattening film in the removing step by wet etching, the conductivity and adhesion of the flattening film can be kept good.
【図１】 本発明の第１実施例の薄膜多層電極を有する
素子の断面図であるFIG. 1 is a sectional view of an element having a thin-film multilayer electrode according to a first embodiment of the present invention.
【図２】（ａ）〜（ｄ） 素子の製造方法を示す図であ
る。2 (a) to 2 (d) are views showing a method for manufacturing an element.
【図３】 従来例の薄膜多層電極を有する素子の断面図
である。FIG. 3 is a cross-sectional view of a conventional device having a thin-film multilayer electrode.
【図４】（ａ）〜（ｄ） 異なる従来例の薄膜多層電極
の製造方法を示す図である。4 (a) to 4 (d) are views showing a method of manufacturing a different conventional thin film multilayer electrode.
１、３１ ・・・ 薄膜多層電極を有する素子 ２、３２ ・・・ 誘電体基板 ３、３３ ・・・ 平坦化膜 ４、３４ ・・・ 薄膜多層電極 ５、３５ ・・・ 薄膜導体層 ６、３６ ・・・ 薄膜誘電体層 ７、３７ ・・・ ポア 1, 31 element having thin film multilayer electrode 2, 32 dielectric substrate 3, 33 flattening film 4, 34 thin film multilayer electrode 5, 35 thin film conductor layer 6, 36: Thin film dielectric layer 7, 37: Pore
Claims (5)
層と薄膜誘電体層とを接着層を介して交互に積層した薄
膜多層電極と、誘電体基板と薄膜多層電極との間に介在
された平坦化膜とを備えてなる薄膜多層電極を有する素
子であって、 前記平坦化膜の薄膜多層電極と接する面に、その表面を
平坦化するための研磨処理が施されていることを特徴と
する薄膜多層電極を有する素子。1. A dielectric substrate, a thin-film multilayer electrode in which thin-film conductor layers and thin-film dielectric layers are alternately laminated on a dielectric substrate via an adhesive layer, and a dielectric substrate and a thin-film multilayer electrode. An element having a thin-film multilayer electrode including an intervening flattening film, wherein a surface of the flattening film in contact with the thin-film multilayer electrode has been subjected to a polishing treatment for flattening the surface. An element having a thin-film multilayer electrode, characterized in that:
ｒ、Ｚｒ、Ｎｂ、Ｈｆ、Ｖ、Ｍｏ、Ｔｉ−Ｎ、Ｔａ−
Ｎ、あるいはこれらを２種以上混合して得られる材料、
あるいはこれらに添加物を加えた材料からなることを特
徴とする請求項１に記載の薄膜多層電極を有する素子。2. The flattening film is made of Ti, Ta, W, C
r, Zr, Nb, Hf, V, Mo, Ti-N, Ta-
N, or a material obtained by mixing two or more of these,
2. The device having a thin-film multilayer electrode according to claim 1, wherein the device comprises a material obtained by adding an additive thereto.
層とを交互に積層した薄膜多層電極を形成してなる薄膜
多層電極を有する素子の製造方法において、 誘電体基板を準備する工程と、 誘電体基板表面に、基板表面の凹凸を平坦化する平坦化
膜を形成する工程と、 平坦化膜の表面が平坦になるように不要部分を除去する
除去工程と、 除去工程後の平坦化膜上に薄膜多層電極を形成する工程
と、を有することを特徴とする薄膜多層電極を有する素
子の製造方法。3. A method of manufacturing a device having a thin-film multilayer electrode formed by alternately laminating thin-film conductor layers and thin-film dielectric layers on a dielectric substrate, comprising the steps of: preparing a dielectric substrate. Forming a flattening film on the surface of the dielectric substrate to flatten the unevenness of the substrate surface; removing the unnecessary portion so that the surface of the flattening film becomes flat; and flattening after the removing process. Forming a thin film multi-layer electrode on the passivation film.
た加工変質層をウェットエッチングにより除去する工程
を含むことを特徴とする請求項３に記載の薄膜多層電極
を有する素子の製造方法。4. The method for manufacturing a device having a thin-film multilayered electrode according to claim 3, wherein the removing step includes a step of removing a damaged layer formed on a surface layer of the flattening film by wet etching. .
ａが０．０５μｍ以下となるように研磨処理を施す工程
を含むことを特徴とする請求項３または請求項４に記載
の薄膜多層電極を有する素子の製造方法。5. The method according to claim 1, wherein the removing step includes:
5. The method according to claim 3, further comprising a step of performing a polishing treatment so that a is 0.05 μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33188597A JP3750324B2 (en) | 1997-12-02 | 1997-12-02 | Device having thin film multilayer electrode and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33188597A JP3750324B2 (en) | 1997-12-02 | 1997-12-02 | Device having thin film multilayer electrode and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11168306A true JPH11168306A (en) | 1999-06-22 |
| JP3750324B2 JP3750324B2 (en) | 2006-03-01 |
Family
ID=18248720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33188597A Expired - Fee Related JP3750324B2 (en) | 1997-12-02 | 1997-12-02 | Device having thin film multilayer electrode and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3750324B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1193790A2 (en) * | 2000-09-29 | 2002-04-03 | Robert Bosch Gmbh | Substrate with a smoothed surface and method of manufacturing thereof |
| US7608881B2 (en) | 2005-11-28 | 2009-10-27 | Tdk Corporation | Thin-film device and method of manufacturing same |
-
1997
- 1997-12-02 JP JP33188597A patent/JP3750324B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1193790A2 (en) * | 2000-09-29 | 2002-04-03 | Robert Bosch Gmbh | Substrate with a smoothed surface and method of manufacturing thereof |
| EP1193790A3 (en) * | 2000-09-29 | 2003-05-14 | Robert Bosch Gmbh | Substrate with a smoothed surface and method of manufacturing thereof |
| US7608881B2 (en) | 2005-11-28 | 2009-10-27 | Tdk Corporation | Thin-film device and method of manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3750324B2 (en) | 2006-03-01 |
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