JPH11160388A - Ic tester - Google Patents
Ic testerInfo
- Publication number
- JPH11160388A JPH11160388A JP9329345A JP32934597A JPH11160388A JP H11160388 A JPH11160388 A JP H11160388A JP 9329345 A JP9329345 A JP 9329345A JP 32934597 A JP32934597 A JP 32934597A JP H11160388 A JPH11160388 A JP H11160388A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- test
- relay
- circuit
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、ＩＣ試験装置に
関する。[0001] The present invention relates to an IC test apparatus.
【０００２】[0002]
【従来の技術】従来のＩＣ試験装置の被測定デバイスへ
の電源供給部分の構成図を図２に示す。この図におい
て、符号１は低周波用コンデンサ、２は高周波用コンデ
ンサ、３は被測定デバイス（以下ＤＵＴと略称する）、
４はリレー、５は電源回路、６はリレー駆動回路であ
る。2. Description of the Related Art FIG. 2 shows a configuration diagram of a power supply portion for a device under test of a conventional IC test apparatus. In this figure, reference numeral 1 denotes a low-frequency capacitor, 2 denotes a high-frequency capacitor, 3 denotes a device under test (hereinafter abbreviated as DUT),
4 is a relay, 5 is a power supply circuit, and 6 is a relay drive circuit.
【０００３】通常、ＤＵＴ３の直流試験を行う場合、低
周波用コンデンサ１は大容量であるため漏れ電流が大き
いので、測定誤差を生ずることを避けるため前記ＤＵＴ
３の電源から切り離し、リレー４はＯＦＦさせた状態で
試験をおこない、交流試験をおこなうときのみ、前記Ｄ
ＵＴ３に印加される電源の変動による影響を抑えるため
に前記リレー４をＯＮさせ、前記ＤＵＴ３の電源に前記
低周波用コンデンサ１を接続した状態で試験をおこなっ
ている。Usually, when a DC test of the DUT 3 is performed, since the low-frequency capacitor 1 has a large capacitance and a large leakage current, the DUT 3 is used to avoid a measurement error.
3 is disconnected from the power supply and the test is performed with the relay 4 turned off.
The test is performed with the relay 4 turned on and the low frequency capacitor 1 connected to the power supply of the DUT 3 in order to suppress the influence of the fluctuation of the power supply applied to the UT 3.
【０００４】[0004]
【発明が解決しようとする課題】上述の方法では、通常
ＤＵＴの交流試験を行う場合と、直流試験をおこなう場
合とで、低周波用コンデンサに接続されたリレーをＯＮ
／ＯＦＦさせることにより、交流試験を行うときは電源
に低周波用コンデンサが接続された状態とし、直流試験
を行うときは電源に低周波用コンデンサが接続されない
状態として試験を行っている。In the above-described method, the relay connected to the low-frequency capacitor is normally turned on when performing the AC test of the DUT and when performing the DC test.
By performing / OFF, the test is performed with the low-frequency capacitor connected to the power supply when performing the AC test, and without the low-frequency capacitor connected to the power supply when performing the DC test.
【０００５】ところで、リレー４のＯＮ／ＯＦＦの制御
は、リレー駆動回路５でおこなっているが、一つのＤＵ
Ｔ毎に一つのリレーを設けているため、数十個のＤＵＴ
の試験を同時に行うとき、ＩＣ試験装置全体ではリレー
の数は数十個にもなり、リレー駆動回路もその数だけ必
要になり、回路規模が膨大なものになってしまうという
ことが課題となっていた。[0005] The ON / OFF control of the relay 4 is performed by the relay drive circuit 5, but one DU is controlled.
Since one relay is provided for each T, several tens DUT
When performing the tests at the same time, the number of relays in the IC test equipment as a whole becomes several tens, and the number of relay drive circuits is required, and the circuit scale becomes enormous. I was
【０００６】この発明は上記の課題を解決するためにな
されたもので、リレーを駆動する駆動回路を用意しなく
ても、リレーをＯＮ／ＯＦＦでき、低周波用コンデンサ
のＯＮ／ＯＦＦを行うことができ、装置を簡略化できる
ＩＣ試験装置の提供を目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to turn on / off a relay without providing a drive circuit for driving the relay, and to turn on / off a low-frequency capacitor. And to provide an IC test apparatus that can simplify the apparatus.
【０００７】[0007]
【課題を解決するための手段】上記の課題を解決するた
めに、この発明の請求項１は、複数の被測定デバイスの
電源端子毎に個別に電源を供給する複数の電源回路と、
前記各電源回路に並列に接続された低周波用コンデンサ
と、該コンデンサ毎に設けられ、接点が該コンデンサに
それぞれ直列に接続されたリレーと、テストボード上の
負荷回路のための負荷用電源回路とを具備し、前記負荷
用電源回路の電圧によって前記リレーの励磁コイルを駆
動することを特徴とするＩＣ試験装置を提供する。In order to solve the above-mentioned problems, a first aspect of the present invention is to provide a plurality of power supply circuits for individually supplying power to respective power supply terminals of a plurality of devices under test;
A low-frequency capacitor connected in parallel to each of the power supply circuits, a relay provided for each of the capacitors, and a contact connected in series to the capacitor, and a load power supply circuit for a load circuit on a test board; And driving the exciting coil of the relay with the voltage of the load power supply circuit.
【０００８】請求項２に記載の発明は、前記複数のリレ
ーの接点が、前記被測定デバイスの交流試験を行うとき
閉成され、前記被測定デバイスの直流試験を行うとき開
放されることを特徴とする請求項１に記載のＩＣ試験装
置を提供する。According to a second aspect of the present invention, the contacts of the plurality of relays are closed when performing an AC test on the device under test, and are opened when performing a DC test on the device under test. An IC test apparatus according to claim 1 is provided.
【０００９】請求項３に記載の発明は、前記低周波用コ
ンデンサが、電解コンデンサであることを特徴とする請
求項１または２に記載のＩＣ試験装置を提供する。The invention according to claim 3 provides the IC test apparatus according to claim 1 or 2, wherein the low-frequency capacitor is an electrolytic capacitor.
【００１０】請求項４に記載の発明は、前記複数の電源
回路にそれぞれ並列に小容量の高周波用コンデンサを接
続したことを特徴とする請求項１ないし３のいずれかに
記載のＩＣ試験装置を提供する。According to a fourth aspect of the present invention, there is provided an IC test apparatus according to any one of the first to third aspects, wherein a small-capacity high-frequency capacitor is connected in parallel to each of the plurality of power supply circuits. provide.
【００１１】[0011]
【発明の実施の形態】以下、この発明の一実施形態につ
いて、図を参照しながら説明する。図１はこの発明の一
実施形態によるＩＣ試験装置の電源供給部分の構成を示
すブロック図である。この図において、符号１は交流試
験のとき電源の電圧変動を抑えるため電源に並列に接続
される低周波用コンデンサ、２は電源の高周波ノイズを
カットするため電源に並列に接続された高周波用コンデ
ンサ、３は被測定デバイス（以下ＤＵＴと略称する）、
４は前記低周波コンデンサ１をＯＮ／ＯＦＦするための
リレーである。この符号１から４の構成がＤＵＴの数だ
け用意され、同時に試験を行うことができる。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a power supply portion of an IC test apparatus according to one embodiment of the present invention. In this figure, reference numeral 1 denotes a low-frequency capacitor connected in parallel to the power supply to suppress voltage fluctuation of the power supply during an AC test, and 2 denotes a high-frequency capacitor connected in parallel to the power supply to cut high-frequency noise of the power supply. 3 is a device under test (hereinafter abbreviated as DUT),
Reference numeral 4 denotes a relay for turning on / off the low-frequency capacitor 1. The configurations of the reference numerals 1 to 4 are prepared by the number of DUTs, and the test can be performed at the same time.
【００１２】符号５は電源回路であり、この電源回路５
によって前記ＤＵＴ３の電源端子に電源が供給される。
また、符号７はテストボード上の負荷回路を接続すると
き使用される負荷用電源回路である。しかしながら、前
記低周波用コンデンサ１を電源５に接続することが必要
となる高速ＤＵＴを試験する場合は前記負荷回路は使用
しないため、前記電源回路７は未使用となっている。Reference numeral 5 denotes a power supply circuit.
Thus, power is supplied to the power supply terminal of the DUT 3.
Reference numeral 7 denotes a load power supply circuit used when connecting a load circuit on the test board. However, when testing a high-speed DUT that requires connecting the low-frequency capacitor 1 to the power supply 5, the load circuit is not used, and the power supply circuit 7 is unused.
【００１３】通常、ＤＵＴ３の直流試験を行う場合、低
周波用コンデンサ１は大容量であるため漏れ電流が大き
いので、測定誤差を避けるため前記ＤＵＴ３の電源から
切り離し、リレー４はＯＦＦさせた状態で前記ＤＵＴ３
に電源を供給し、試験をおこなう。また、交流試験をお
こなう場合、前記ＤＵＴ３に与えられる電源電圧の変動
による影響を抑えるために、前記リレー４をＯＮさせて
前記低周波用コンデンサ１を接続させた状態で前記ＤＵ
Ｔ３に電源を供給し、試験をおこなう。Normally, when a DC test of the DUT 3 is performed, since the low-frequency capacitor 1 has a large capacity and a large leakage current, it is disconnected from the power supply of the DUT 3 and the relay 4 is turned off to avoid a measurement error. The DUT3
Supply power to the tester. When performing an AC test, the relay 4 is turned on and the DU is connected with the low-frequency capacitor 1 in order to suppress the influence of the fluctuation of the power supply voltage applied to the DUT 3.
Power is supplied to T3 and a test is performed.
【００１４】このとき、前記リレー４のＯＮ／ＯＦＦ制
御は、もう一つの電源回路である未使用の負荷用電源回
路７によっておこなうが、この方式の動作について具体
的に説明する。通常、ＩＣ試験装置は複数の電源回路を
備えており、ＤＵＴ用の電源回路５の他にＤＵＴを搭載
しているテストボード上の負荷回路用として、プログラ
ムにより任意にＯＮ／ＯＦＦすることができる負荷用電
源回路７が用意されている。At this time, the ON / OFF control of the relay 4 is performed by an unused load power supply circuit 7, which is another power supply circuit. The operation of this method will be specifically described. Normally, the IC test apparatus is provided with a plurality of power supply circuits, and can be arbitrarily turned on / off by a program for a load circuit on a test board on which the DUT is mounted in addition to the power supply circuit 5 for the DUT. A load power supply circuit 7 is provided.
【００１５】しかし、本条件のように前記低周波用コン
デンサ１を電源に接続して試験するような高速ＤＵＴを
試験する場合、テストボード上の負荷回路は使用しない
ため、前記負荷用電源７は未使用となっている。この未
使用の負荷用電源７を前記リレー４の駆動コイルに接続
し、前記負荷用電源７のプログラムによるＯＮ／ＯＦＦ
制御によって、前記リレー４のＯＮ／ＯＦＦ制御をおこ
なうことができ、前記低周波用コンデンサ１のＯＮ／Ｏ
ＦＦを行うことができる。このリレー駆動方法により、
個別のリレー駆動回路は不要となる。However, when testing a high-speed DUT in which the low-frequency capacitor 1 is connected to a power supply for testing under the above conditions, the load power supply 7 is not used because the load circuit on the test board is not used. It is unused. The unused load power supply 7 is connected to the drive coil of the relay 4 and the load power supply 7 is turned on / off by a program.
The ON / OFF control of the relay 4 can be performed by the control, and the ON / O of the low-frequency capacitor 1 can be controlled.
FF can be performed. With this relay driving method,
No separate relay drive circuit is required.
【００１６】以上、本発明の一実施形態の動作を図面を
参照して詳述してきたが、本発明はこの実施形態に限ら
れるものではなく、本発明の要旨を逸脱しない範囲の設
計変更等があっても本発明に含まれる。The operation of one embodiment of the present invention has been described above in detail with reference to the drawings. However, the present invention is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. The present invention is also included in the present invention.
【００１７】[0017]
【発明の効果】これまでに説明したように、この発明に
よれば、ＩＣ試験装置において負荷用電源回路のＯＮ／
ＯＦＦによってリレーのＯＮ／ＯＦＦを行い、低周波用
コンデンサのＯＮ／ＯＦＦ制御を行うようにしたので、
ＤＵＴの交流試験をする場合と、直流試験をおこなう場
合とで、リレーを駆動させるための回路を用意しなくて
も、リレーをＯＮ／ＯＦＦさせ、低周波用コンデンサの
ＯＮ／ＯＦＦを行うことができるという効果が得られ
る。As described above, according to the present invention, the ON / OFF of the load power supply circuit in the IC test apparatus is achieved.
Since the relay is turned on / off by turning off and the low frequency capacitor is turned on / off,
The relay can be turned on and off and the low-frequency capacitor can be turned on and off without preparing a circuit to drive the relay between the DUT AC test and the DC test. The effect that it can be obtained is obtained.
【図１】 本発明の一実施形態によるＩＣ試験装置の被
測定デバイスへの電源供給部分の構成を示す図FIG. 1 is a diagram showing a configuration of a power supply portion to a device under test of an IC test apparatus according to an embodiment of the present invention.
【図２】 従来の技術によるＩＣ試験装置の被測定デバ
イスへの電源供給部分の構成を示す図FIG. 2 is a diagram showing a configuration of a power supply portion to a device under test of an IC test apparatus according to a conventional technique.
１ 低周波用コンデンサ ２ 高周波用コンデンサ ３ 被測定デバイス（ＤＵＴ） ４ リレー ５ 電源回路 ６ リレー駆動回路 ７ 負荷用電源回路 DESCRIPTION OF SYMBOLS 1 Low frequency capacitor 2 High frequency capacitor 3 Device under test (DUT) 4 Relay 5 Power supply circuit 6 Relay drive circuit 7 Load power supply circuit
Claims (4)
別に電源を供給する複数の電源回路と、 前記各電源回路に並列に接続された低周波用コンデンサ
と、 該コンデンサ毎に設けられ、接点が該コンデンサにそれ
ぞれ直列に接続されたリレーと、 テストボード上の負荷回路のための負荷用電源回路とを
具備し、前記負荷用電源回路の電圧によって前記リレー
の励磁コイルを駆動することを特徴とするＩＣ試験装置A plurality of power supply circuits for individually supplying power to power supply terminals of a plurality of devices under test; a low-frequency capacitor connected in parallel to each of the power supply circuits; A relay having contacts connected in series to the capacitor, and a load power supply circuit for a load circuit on a test board, wherein the excitation coil of the relay is driven by the voltage of the load power supply circuit. Characteristic IC test equipment
とを特徴とする請求項１に記載のＩＣ試験装置2. The contact according to claim 1, wherein the contacts of the plurality of relays are closed when performing an AC test on the device under test and are opened when performing a DC test on the device under test. IC testing equipment
ンサであることを特徴とする請求項１または２に記載の
ＩＣ試験装置3. The IC test apparatus according to claim 1, wherein the low frequency capacitor is an electrolytic capacitor.
容量の高周波用コンデンサを接続したことを特徴とする
請求項１ないし３のいずれかに記載のＩＣ試験装置4. The IC test apparatus according to claim 1, wherein a small-capacity high-frequency capacitor is connected in parallel to each of the plurality of power supply circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9329345A JPH11160388A (en) | 1997-11-28 | 1997-11-28 | Ic tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9329345A JPH11160388A (en) | 1997-11-28 | 1997-11-28 | Ic tester |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11160388A true JPH11160388A (en) | 1999-06-18 |
Family
ID=18220424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9329345A Withdrawn JPH11160388A (en) | 1997-11-28 | 1997-11-28 | Ic tester |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11160388A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10059142B4 (en) * | 1999-11-30 | 2004-05-19 | Ando Electric Co., Ltd., Kawasaki | Current limiting apparatus |
| US7560949B2 (en) | 2006-03-31 | 2009-07-14 | Renesas Technology Corp. | Manufacturing method of semiconductor device and semiconductor device corresponding to loop back test |
| JP2009204329A (en) * | 2008-02-26 | 2009-09-10 | Nec Electronics Corp | Circuit board inspecting system and inspection method |
-
1997
- 1997-11-28 JP JP9329345A patent/JPH11160388A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10059142B4 (en) * | 1999-11-30 | 2004-05-19 | Ando Electric Co., Ltd., Kawasaki | Current limiting apparatus |
| US7560949B2 (en) | 2006-03-31 | 2009-07-14 | Renesas Technology Corp. | Manufacturing method of semiconductor device and semiconductor device corresponding to loop back test |
| JP2009204329A (en) * | 2008-02-26 | 2009-09-10 | Nec Electronics Corp | Circuit board inspecting system and inspection method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20050201 |