JPH1114709A - Test method of integrated circuit device - Google Patents
Test method of integrated circuit deviceInfo
- Publication number
- JPH1114709A JPH1114709A JP9165798A JP16579897A JPH1114709A JP H1114709 A JPH1114709 A JP H1114709A JP 9165798 A JP9165798 A JP 9165798A JP 16579897 A JP16579897 A JP 16579897A JP H1114709 A JPH1114709 A JP H1114709A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- test
- terminals
- circuit device
- test method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Non-Volatile Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は集積回路装置の試験
方法に関し、特にＤＲＡＭ，ＳＲＡＭ，フラッシュＥＰ
ＲＯＭ等を含む大規模論理集積回路の試験方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing an integrated circuit device, and more particularly to a DRAM, an SRAM, and a flash EP.
The present invention relates to a method for testing a large-scale logic integrated circuit including a ROM and the like.
【０００２】[0002]
【従来の技術】近年、論理集積回路装置は、ＬＳＩの微
細化技術やＣＡＤ技術により、大規模集積回路であるフ
ラッシュメモリ（ＦｌａｓｈＥＰＲＯＭ）やＤＲＡＭを
含み、高機能を実現している。2. Description of the Related Art In recent years, a logic integrated circuit device has realized high functions including a flash memory (Flash EPROM) or a DRAM which is a large-scale integrated circuit by a technology of miniaturizing an LSI or a CAD technology.
【０００３】このような大規模論理集積回路の試験は、
一般にＩＣテスタを用いて実施されており、ＩＣテスタ
用の言語を用いて各機能試験やＤＣ試験などが、各試験
項目ごとに細かく記述された手続プログラムを用いて自
動的に測定される。この試験は、各試験項目ごとに、被
試験ＩＣ回路に入力される信号値や回路から出力される
期待値が記述されているテストパターンが用意されてお
り、これら全てのテストパターンのテストをパスすれ
ば、全機能を満足する良品であると判定されるようにな
っている。A test of such a large-scale logic integrated circuit is performed as follows.
Generally, the test is performed using an IC tester, and each functional test, DC test, and the like are automatically measured using a procedure program that is described in detail for each test item using a language for the IC tester. In this test, test patterns are prepared for each test item that describe the signal values input to the IC circuit under test and the expected values output from the circuit. Then, it is determined that the product is a good product satisfying all functions.
【０００４】このＩＣテスタは、大規模論理集積回路の
ウェハー段階で、ウェハーの接続点とプローブで接触し
て試験をするウェハーテスト、チップをパッケージに実
装した段階でのパッケージテスト、製品段階でのテスト
など各段階で試験ができるようになっているが、これら
を組合せて効率的に試験が行われる必要がある。このＩ
Ｃテスタの接続ピン数は、最近のＩＣテスタでは５００
ピンと多数のものもあるが、接続ピン数が多くなれば、
システムとして高価なものとなってしまう。This IC tester is used in a wafer stage of a large-scale logic integrated circuit to perform a test by contacting a connection point of a wafer with a probe, a package test in a stage in which a chip is mounted on a package, and a product stage. Testing can be performed at each stage such as testing, but it is necessary to perform testing efficiently by combining them. This I
The number of connection pins of the C tester is 500 for a recent IC tester.
There are many pins and many, but if the number of connection pins increases,
It becomes expensive as a system.
【０００５】マイクロコンピュータ（マイコン）は、そ
の機能がプログラムされてＲＯＭに格納されており、従
来はＵＶＥＰＲＯＭを内蔵するマイコンが用いられてい
た。最近ではフラッシュメモリが、ハードディスクに置
き替るべきものとして実用化されており、マイコンのプ
ログラムは、デバッグのために何回も書きかえられる必
要があり、このマイコンのメモリとして、このフラッシ
ュメモリが適当と考えられてきた。A microcomputer (microcomputer) has its function programmed and stored in a ROM, and a microcomputer having a built-in UVEPROM has conventionally been used. In recent years, flash memory has been put into practical use as a replacement for hard disks. Microcomputer programs need to be rewritten many times for debugging, and this flash memory is appropriate for this microcomputer. Has been considered.
【０００６】図４は従来例のＵＶＥＰＲＯＭを内蔵する
マイコンの論理集積回路の試験時の接続図である。１個
の被測定素子ＤＵＴ（Ｄｅｖｉｃｅ Ｕｎｄｅｒ Ｔｅ
ｓｔ）４の入出力接続ピン（Ｉ01〜Ｉ40，Ｏ1 〜Ｏ40）
が１台のＩＣテスタ３の接続ピンＪ01〜Ｊ80と接続され
て試験を行う。ここではＤＵＴ４の入出力接続ピンＪ01
〜Ｊ80が８０個となっており、ＩＣテスタ３として、８
０ピンの接続ピンをもつテスタが使用される。このＤＵ
Ｔ４の入力端子Ｉ01〜Ｉ40には、ＩＣテスタ３の出力端
子Ｊ01〜Ｊ40のドライバ（ＤＲＶ）からの信号が入力さ
れ、ＤＵＴ４の出力端子Ｏ01〜Ｏ40からの信号がＩＣテ
スタ３の入力端子Ｊ41〜Ｊ80のコンパレータ（ＣＭＰ）
内で、所定の期待値と比較されて、このＤＵＴ４の良品
・不良品の判定がなされる。この場合、ＤＵＴ４の全て
の端子はＩＣテスタ３のＤＲＶ，ＣＭＰ，ＢＳ（バイア
ス・ソース），ＧＮＤ（接地）のいずれかに接続されて
いる。FIG. 4 is a connection diagram for testing a conventional logic integrated circuit of a microcomputer having a built-in UVEPROM. One device under test DUT (Device Under Te
st) 4 input / output connection pins (I01 to I40, O1 to O40)
Are connected to the connection pins J01 to J80 of one IC tester 3 to perform a test. Here, the input / output connection pin J01 of the DUT 4
~ 80 of J80 and 8 as IC tester 3
A tester with 0 connection pins is used. This DU
The signals from the drivers (DRV) of the output terminals J01 to J40 of the IC tester 3 are input to the input terminals I01 to I40 of the T4, and the signals from the output terminals O01 to O40 of the DUT 4 are input to the input terminals J41 to J40 of the IC tester 3. J80 comparator (CMP)
The DUT 4 is compared with a predetermined expected value to determine whether the DUT 4 is good or defective. In this case, all terminals of the DUT 4 are connected to one of the DRV, CMP, BS (bias source), and GND (ground) of the IC tester 3.
【０００７】このＤＵＴ４には、ＣＰＵ１１，ＲＡＭ１
２，ＵＶＥＰＲＯＭ１５が含まれるが、ＣＰＵ１１，Ｒ
ＡＭ１２の試験は総合的に試験されるが、ＵＶＥＰＲＯ
Ｍ１５は、信頼性確保のため、単体としての試験も実施
する必要があり、その試験としては、図５に示すフロー
図のように、ＵＶＥＰＲＯＭの単体試験としてウェハー
テスト（ステップＳ１１〜Ｓ１４）およびパッケージテ
スト（ステップＳ１６〜Ｓ２０）が含まれる。The DUT 4 includes a CPU 11 and a RAM 1
2, UVEPROM 15 is included, but CPU 11, R
AM12 testing is comprehensively tested, but UVEPRO
M15 also needs to perform a test as a single unit in order to ensure reliability. As the test, a wafer test (steps S11 to S14) and a package test are performed as a unit test of the UVEPROM as shown in the flowchart of FIG. A test (steps S16 to S20) is included.
【０００８】まず、ステップＳ１１のＵＶＥＰＲＯＭの
ウェハーテストとして、ＵＶＥＰＲＯＭへのデータ書込
みが行われ、ステップＳ１２で、書込んだデータの保存
状態をチェックするため、ベークによりウェハーを２５
０°Ｃに加熱する。次に、ステップＳ１３でステップＳ
１１で書込んだデータを読込み、機能試験を行ない、こ
の試験が終了すると、ステップＳ１４でこのＵＶＥＰＲ
ＯＭに紫外線ぽ照射して試験用に書込んだデータを消去
する。First, as a wafer test of the UVEPROM in step S11, data is written to the UVEPROM. In step S12, the wafer is baked to check the storage state of the written data.
Heat to 0 ° C. Next, in Step S13, Step S
11 to read the written data and perform a functional test. When this test is completed, in step S14, the UVEPR
The OM is irradiated with ultraviolet rays to erase the data written for the test.
【０００９】次に、ステップＳ１５でＵＶＥＰＲＯＭを
チップに組込んでパッケージとし、ステップＳ１６の１
回目のパッケージテストとして、ＵＶＥＰＲＯＭへのデ
ータ書込みが行われ、ステップＳ１７でエージングによ
る負荷試験として、パッケージを１２５°Ｃに加熱す
る。さらに、ステップＳ１８で、ステップＳ１６で書込
んだデータを読込み、機能試験を行ない、この試験が終
了すると、ステップＳ１９でこのＵＶＥＰＲＯＭに紫外
線ぽ照射して試験用に書込んだデータを消去する。さら
に、ステップＳ２０で、ＣＰＵ，ＲＡＭを含めた最終試
験が抜き取りにより実施される。Next, in step S15, the UVEPROM is assembled into a chip to form a package,
As a second package test, data is written to the UVEPROM, and the package is heated to 125 ° C. as a load test by aging in step S17. Further, in step S18, the data written in step S16 is read and a functional test is performed. When this test is completed, in step S19, the UVEPROM is irradiated with ultraviolet rays to erase the data written for the test. Further, in step S20, a final test including the CPU and the RAM is performed by sampling.
【００１０】[0010]
【発明が解決しようとする課題】上述した従来のＵＶＥ
ＰＲＯＭを内蔵するマイコンの論理集積回路の試験方法
では、ＩＣテスタ３に接続される全ての接続端子に論理
集積回路であるＤＵＴ４の全ての接続ピンが接続される
ため、ＩＣテスタ３の端子数により同時に測定するＤＵ
Ｔ４の個数が制限されてしまうことになる。従って、端
子数の多い論理集積回路の場合には、同時に試験てきる
ＤＵＴの個数が制限されると共に、その試験時間も長く
かかることになる。前述の図４の場合には、８０個の接
続端子をもつＩＣテスタに対して、８０個の接続ピンを
もつ論理集積回路を接続しているので、１個しか試験す
ることができず、メモリ（ＵＶＥＰＲＯＭ）のように多
数の入出力端子を必要とし、その試験時間が長くかかる
論理集積回路では、試験時間が極めて長くなり、製造コ
ストが大幅に増大してしまうという問題がある。SUMMARY OF THE INVENTION The above-mentioned conventional UVE
In the method for testing a logic integrated circuit of a microcomputer having a built-in PROM, all connection pins of the logic integrated circuit DUT 4 are connected to all connection terminals connected to the IC tester 3. DU measuring at the same time
This will limit the number of T4. Therefore, in the case of a logic integrated circuit having a large number of terminals, the number of simultaneously tested DUTs is limited, and the test time is long. In the case of FIG. 4 described above, a logic integrated circuit having 80 connection pins is connected to an IC tester having 80 connection terminals, so that only one test can be performed. A logic integrated circuit that requires a large number of input / output terminals and requires a long test time like a (UVEPROM) has a problem that the test time is extremely long and the manufacturing cost is greatly increased.
【００１１】本発明の目的は、試験時間が長くかかるメ
モリを含む論理集積回路や、端子数の多い集積回路の試
験時間を短縮した集積回路装置の試験方法を提供するこ
とにある。An object of the present invention is to provide a test method for a logic integrated circuit including a memory that requires a long test time, and an integrated circuit device in which the test time for an integrated circuit having a large number of terminals is reduced.
【００１２】[0012]
【課題を解決するための手段】本発明の構成は、複数の
特定機能をもつ大規模集積回路群からなり、複数の外部
接続端子をもつ論理集積回路装置を複数回にわたって試
験する集積回路装置の試験方法において、前記大規模集
積回路群のうちの特定の大規模集積回路の機能を、前記
複数の外部接続端子のうちの一部の端子を用いて、前記
複数回のうち一部を並列に試験することを特徴とする。According to the present invention, there is provided an integrated circuit device comprising a large-scale integrated circuit group having a plurality of specific functions and testing a logic integrated circuit device having a plurality of external connection terminals a plurality of times. In the test method, a function of a specific large-scale integrated circuit in the large-scale integrated circuit group is performed by using a part of the plurality of external connection terminals and performing a part of the plurality of parallel operations in parallel. It is characterized by testing.
【００１３】本発明において、複数回の試験のうちの前
半を前記特定の大規模集積回路を複数個並列に試験し、
また並列の試験を、複数の前記特定の大規模集積回路の
各接続端子を全て、前記複数の外部接続端子にそれぞれ
接続して行なったり、複数の前記特定の大規模集積回路
の入力側の対応する各接続端子を並列接続して並列に試
験を行なうこともできる。さらに、特定の大規模集積回
路として記憶回路、特にフラッシュ型ＥＰＲＯＭを用い
ることができる。In the present invention, the first half of the plurality of tests is performed by testing a plurality of the specific large-scale integrated circuits in parallel.
In addition, a parallel test may be performed by connecting all of the connection terminals of the plurality of specific large-scale integrated circuits to the plurality of external connection terminals, respectively, or may be performed on the input side of the plurality of specific large-scale integrated circuits. The test can also be performed in parallel by connecting the respective connection terminals in parallel. Further, a storage circuit, in particular, a flash type EPROM can be used as a specific large-scale integrated circuit.
【００１４】本発明によれば、大規模集積回路の試験項
目を、特定の（メモリ）機能のみに限定して、その際に
必要な接続端子のみをＩＣテスタに接続するので、同時
に試験することのできる大規模集積回路の個数を増やす
ことができ、全体として試験時間を短縮することがで
き、この試験コストを削減することができる。According to the present invention, the test items of a large-scale integrated circuit are limited to a specific (memory) function, and only necessary connection terminals are connected to the IC tester at that time. The number of large-scale integrated circuits that can be used can be increased, the test time can be shortened as a whole, and the test cost can be reduced.
【００１５】[0015]
【発明の実態の形態】次に本発明の実態形態を図により
説明する。図１は本発明の一実態形態を説明するフラッ
シュ型ＥＰＲＯＭを内蔵したマイコンの試験フロー図で
あり、図２は図１のフラッシュ型ＥＰＲＯＭを内蔵した
マイコンの論理集積回路の前半試験であるウェハーテス
トおよび一部のパッケージテストを行う時の接続図であ
る。本実態形態では、図２に示すように、図４のＵＶＥ
ＰＲＯＭ１５を内蔵した１個のＤＵＴ４の代りに、フラ
ッシュ型ＥＰＲＯＭ１３を内蔵した２個のＤＵＴ１，２
を用いている。ここ場合、２個の被測定素子ＤＵＴ１，
２の入出力接続ピン（Ｉ1 〜Ｉ40，Ｏ1 〜Ｏ40）のう
ち、フラッシュ型ＥＰＲＯＭ１３と接続される接続ピン
Ｉ26〜Ｉ40，Ｏ26〜Ｏ40が１台のＩＣテスタ３の接続ピ
ンＪ01〜15、Ｊ26〜40，Ｊ41〜55，Ｊ66〜80と接続され
て試験を行う。ここではＤＵＴ１，２の入出力接続ピン
数が６０個となっており、ＩＣテスタ３の８０本の接続
ピンを余裕をもって使用できる。Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a test flow chart of a microcomputer having a built-in flash EPROM for explaining one embodiment of the present invention, and FIG. 2 is a wafer test which is a first half test of a logic integrated circuit of the microcomputer having a built-in flash EPROM of FIG. FIG. 4 is a connection diagram when performing a partial package test. In this embodiment, as shown in FIG.
Instead of one DUT 4 with a built-in PROM 15, two DUTs 1 and 2 with a built-in flash EPROM 13
Is used. In this case, two devices under test DUT1,
Of the two input / output connection pins (I1 to I40, O1 to O40), connection pins I26 to I40 and O26 to O40 connected to the flash EPROM 13 are connection pins J01 to J15 and J26 to one IC tester 3. 40, J41-55 and J66-80 are connected and tested. Here, the number of input / output connection pins of the DUTs 1 and 2 is 60, and the 80 connection pins of the IC tester 3 can be used with a margin.
【００１６】これらＤＵＴ１，２の入力端子Ｉ26〜Ｉ40
には、ＩＣテスタ３の出力端子Ｊ01〜15，Ｊ26〜40のド
ライバ（ＤＲＶ）からの信号が入力され、ＤＵＴ１，２
の出力端子Ｏ26〜Ｏ40からの信号がＩＣテスタ３の入力
端子Ｊ41〜55，Ｊ66〜80のコンパレータ（ＣＭＰ）内
で、所定の期待値と比較されて、これらＤＵＴ１，２の
良品・不良品の判定がなされる。Input terminals I26 to I40 of these DUTs 1 and 2
, Signals from output terminals J01 to 15 and drivers (DRV) of J26 to 40 of the IC tester 3 are input to the DUTs 1 and 2,
The signals from the output terminals O26 to O40 are compared with predetermined expected values in comparators (CMP) of the input terminals J41 to 55 and J66 to 80 of the IC tester 3 to determine whether the DUTs 1 and 2 are good or defective. A determination is made.
【００１７】これらＤＵＴ１，２には、ＣＰＵ１１，Ｒ
ＡＭ１２の他にフラッシュ型ＥＰＲＯＭ１３が含まれる
が、ＣＰＵ１１，ＲＡＭ１２の試験は総合的に試験され
るが、フラッシュ型ＥＰＲＯＭ１３は、信頼性確保のた
め、単体としての試験も実施する必要があり、その試験
としては、図２に示すフロー図のように、フラッシュ型
ＥＰＲＯＭの単体試験としてウェハーテスト（ステップ
Ｓ１〜Ｓ３）および１回目のパッケージテスト（ステッ
プＳ５）が含まれる。The DUTs 1 and 2 include a CPU 11 and an R
A flash EPROM 13 is included in addition to the AM 12. The tests of the CPU 11 and the RAM 12 are comprehensively tested. However, the flash EPROM 13 also needs to be tested as a single unit in order to ensure reliability. As shown in the flowchart of FIG. 2, a wafer test (steps S1 to S3) and a first package test (step S5) are included as unit tests of the flash EPROM.
【００１８】まず、ステップＳ１のフラッシュＥＰＲＯ
Ｍのウェハーテストとして、２個のＤＵＴ１，２のフラ
ッシュＥＰＲＯＭへのデータ書込み・消去試験が行わ
れ、ステップＳ２で、加熱時の状態をみるため、ベーク
によりウェハーを２５０°Ｃに加熱する。次にステップ
Ｓ３で、加熱後の２回目のウェハーテストとして、同様
にデータ書込み・消去機能試験が行われ、この試験が終
了すると、次にステップＳ４でフラッシュＥＰＲＯＭを
チップに組込んでパッケージとする。First, the flash EPRO in step S1
As a wafer test for M, a test for writing / erasing data to / from the flash EPROM of the two DUTs 1 and 2 is performed. In step S2, the wafer is heated to 250 ° C. by baking to check the state at the time of heating. Next, in step S3, a data writing / erasing function test is similarly performed as a second wafer test after heating, and when this test is completed, in step S4, the flash EPROM is assembled into a chip to form a package. .
【００１９】次に、ステップＳ５の１回目のパッケージ
テストとして、２個のＤＵＴ１，２のフラッシュＥＰＲ
ＯＭへのデータ書込み・消去試験が行われ、ステップＳ
６で、加熱時の状態をみるため、エージングによ負荷試
験としてパッケージ１２５°Ｃに加熱する。さらにステ
ップＳ７で、加熱後の２回目のパッケージテストとし
て、２個のＤＵＴ１，２のフラッシュＥＰＲＯＭへのデ
ータ書込み・消去試験が行われる。その後、ステップＳ
８で、ＣＰＵ，ＲＡＭを含めた総合最終試験が抜き取り
により実施される。Next, as the first package test in step S5, the flash EPR of the two DUTs 1 and 2
A test for writing / erasing data to / from the OM is performed.
In step 6, the package is heated to 125 ° C. as a load test by aging to see the state at the time of heating. Further, in step S7, a data write / erase test is performed on the flash EPROM of the two DUTs 1 and 2 as a second package test after heating. Then, step S
At 8, a comprehensive final test including the CPU and RAM is executed by sampling.
【００２０】本実施形態において、ウェハーテストやパ
ッケージテスト等で複数回の試験を必要とする場合に、
多くの入出力端子をもったマイコンのＤＵＴの機能の一
部、すなわちフラッシュ型ＥＰＲＯＭの部分だけを接続
して試験をすれば、メモリ部分の３０端子分の接続でよ
く、他の部分の接続を必要としないので、２個のフラッ
シュ型ＥＰＲＯＭの部分だけを接続して試験すれば、６
０端子の接続で済むことになる。従って、同時に２個の
ＤＵＴの試験が可能となり、試験時間の長くかかるフラ
ッシュＥＰＲＯＭ内蔵の製品や、多端子数をもつ他の不
揮発性メモリ内蔵の製品の試験が、１台のＩＣテスタに
より短時間でできることになる。例えば、従来の試験方
法では素子１個当り６０秒かかっていたものが、本実施
形態の場合には２個で６０秒、すなわち素子１個当り３
０秒で済むことになる。In this embodiment, when a plurality of tests are required in a wafer test, a package test, or the like,
If a part of the function of the DUT of the microcomputer having many input / output terminals, that is, the test is performed by connecting only the flash type EPROM portion, the connection of 30 terminals of the memory portion is sufficient, and the connection of the other portions is not required. Since it is not necessary, if only two flash EPROMs are connected and tested, 6
It is sufficient to connect the 0 terminal. Therefore, two DUTs can be tested at the same time, and a product with a built-in flash EPROM, which requires a long test time, and another product with a built-in nonvolatile memory having a large number of terminals can be tested in a short time by one IC tester You can do it in For example, it took 60 seconds per element in the conventional test method, but in the present embodiment, two elements took 60 seconds, that is, 3 seconds per element.
It takes only 0 seconds.
【００２１】図３は本発明の他の実態形態を説明するフ
ラッシュ型ＥＰＲＯＭを内蔵したマイコンの試験接続図
である。この実態形態では、ＤＵＴ１，２の入力端子Ｉ
26〜Ｉ40が共通接続されて、ＩＣテスタ３の出力端子Ｊ
26〜40のドライバ（ＤＲＶ）からの信号が入力されるよ
うになっており、ＤＵＴ１，２の出力端子Ｏ26〜Ｏ40か
らの信号がＩＣテスタ３の入力端子Ｊ41〜55，Ｊ66〜80
のコンパレータ（ＣＭＰ）内に接続されている。FIG. 3 is a test connection diagram of a microcomputer having a built-in flash EPROM for explaining another embodiment of the present invention. In this embodiment, the input terminals I of the DUTs 1 and 2
26 to I40 are connected in common and output terminal J of IC tester 3
Signals from drivers 26 to 40 (DRVs) are input, and signals from output terminals O26 to O40 of DUTs 1 and 2 are input to input terminals J41 to 55 and J66 to 80 of IC tester 3.
In the comparator (CMP).
【００２２】この実態形態では、ＤＵＴ１，２に同時に
入力信号が供給されるので、出力信号の識別をソフトウ
ェアで工夫する必要があるかもしれないが、接続端子数
６０とすると、３個のＤＵＴを同時に接続して試験する
ことができるという特徴がある。In this embodiment, the input signals are supplied to the DUTs 1 and 2 at the same time. Therefore, the identification of the output signals may need to be devised by software. However, when the number of connection terminals is 60, three DUTs are used. It has the feature that it can be connected and tested at the same time.
【００２３】[0023]
【発明の効果】以上説明したように、本発明の集積回路
装置の試験方法によれば、複数の試験段階の前半で、一
部の機能の集積回路だけを、その部分の接続に限って試
験するので、一度に多くの製品の試験が可能となり、全
体として試験時間を短縮でき、試験コストを低減できる
という効果がある。As described above, according to the test method for an integrated circuit device of the present invention, in the first half of a plurality of test steps, only the integrated circuit having a part of the function is limited to the connection of the part. Therefore, many products can be tested at one time, so that the test time can be shortened as a whole and the test cost can be reduced.
【図１】本発明の一実施形態の試験方法を説明するフロ
ー図。FIG. 1 is a flowchart illustrating a test method according to an embodiment of the present invention.
【図２】本実施形態のＩＣの接続状態を示す回路図。FIG. 2 is a circuit diagram showing a connection state of the IC according to the embodiment.
【図３】本発明の他の実施形態のＩＣの接続状態を示す
回路図。FIG. 3 is a circuit diagram showing a connection state of an IC according to another embodiment of the present invention.
【図４】従来例のＵＶＥＰＲＯＭを含むＩＣの試験方法
を説明するフロー図。FIG. 4 is a flowchart for explaining a conventional method for testing an IC including a UVEPROM.
【図５】従来例のＩＣの接続状態を示す回路図。FIG. 5 is a circuit diagram showing a connection state of a conventional IC.
１，２，４ ＤＵＴ ３ ＩＣテスタ １１ ＣＰＵ １２ ＲＡＭ １３ フラッシュメモリ １５ ＵＶＥＰＲＯＭ Ｉ01〜Ｉ40 ＤＵＴの入力端子 Ｏ01〜Ｏ40 ＤＵＴの出力端子 Ｊ01〜Ｊ80 ＩＣテスタの入出力ピン Ｓ１〜Ｓ２０ 処理ステップ 1, 2, 4 DUT 3 IC tester 11 CPU 12 RAM 13 Flash memory 15 UVEPROM I01 to I40 Input terminal of DUT O01 to O40 Output terminal of DUT J01 to J80 Input / output pins of IC tester S1 to S20 Processing steps
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 21/8247 Ｈ０１Ｌ 29/78 ３７１ 29/788 29/792 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification code FI H01L 21/8247 H01L 29/78 371 29/29/788 29/792
Claims (6)
からなり、複数の外部接続端子をもつ論理集積回路装置
を複数回にわたって試験する集積回路装置の試験方法に
おいて、前記大規模集積回路群のうちの特定の大規模集
積回路の機能を、前記複数の外部接続端子のうちの一部
の端子を用いて、前記複数回のうち一部を並列に試験す
ることを特徴とする集積回路装置の試験方法。1. A method for testing a logic integrated circuit device comprising a plurality of large-scale integrated circuits having a plurality of specific functions and having a plurality of external connection terminals a plurality of times, wherein the large-scale integrated circuit group is provided. Testing a function of a specific large-scale integrated circuit among the plurality of times by using a part of the plurality of external connection terminals in parallel. Test method.
定の大規模集積回路を複数個並列に試験する請求項１記
載の集積回路装置の試験方法。2. The test method of an integrated circuit device according to claim 1, wherein a plurality of said specific large-scale integrated circuits are tested in parallel in a first half of said plurality of tests.
規模集積回路の各接続端子を全て、前記複数の外部接続
端子にそれぞれ接続して行なう請求項１または２記載の
集積回路装置の試験方法。3. The integrated circuit device according to claim 1, wherein the parallel test is performed by connecting all of the connection terminals of the plurality of specific large-scale integrated circuits to the plurality of external connection terminals, respectively. Test method.
規模集積回路の入力側の対応する各接続端子を並列接続
して並列に試験を行なう請求項１または２記載の集積回
路装置の試験方法。4. The integrated circuit device according to claim 1, wherein the parallel test is performed in parallel by connecting corresponding connection terminals on the input side of the plurality of specific large-scale integrated circuits in parallel. Test method.
ある請求項１乃至４記載の集積回路装置の試験方法。5. The test method for an integrated circuit device according to claim 1, wherein the specific large-scale integrated circuit is a storage circuit.
である請求項５記載の集積回路装置の試験方法。6. The flash EPROM according to claim 6, wherein said storage circuit is a flash type EPROM.
6. The test method for an integrated circuit device according to claim 5, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9165798A JPH1114709A (en) | 1997-06-23 | 1997-06-23 | Test method of integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9165798A JPH1114709A (en) | 1997-06-23 | 1997-06-23 | Test method of integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1114709A true JPH1114709A (en) | 1999-01-22 |
Family
ID=15819202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9165798A Pending JPH1114709A (en) | 1997-06-23 | 1997-06-23 | Test method of integrated circuit device |
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| Country | Link |
|---|---|
| JP (1) | JPH1114709A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108351380A (en) * | 2015-10-29 | 2018-07-31 | 北欧半导体公司 | microprocessor interface |
-
1997
- 1997-06-23 JP JP9165798A patent/JPH1114709A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108351380A (en) * | 2015-10-29 | 2018-07-31 | 北欧半导体公司 | microprocessor interface |
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