JPH11135676A - Package board - Google Patents
Package boardInfo
- Publication number
- JPH11135676A JPH11135676A JP31268697A JP31268697A JPH11135676A JP H11135676 A JPH11135676 A JP H11135676A JP 31268697 A JP31268697 A JP 31268697A JP 31268697 A JP31268697 A JP 31268697A JP H11135676 A JPH11135676 A JP H11135676A
- Authority
- JP
- Japan
- Prior art keywords
- package substrate
- layer
- solder
- chip
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、ＩＣチップを載
置させるためのパッケージ基板に関し、更に詳細には、
上面及び下面に、ＩＣチップへの接続用の半田パッド
と、マザーボード、サブボード等の基板への接続用の半
田パッドとが形成されたパッケージ基板に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package substrate on which an IC chip is mounted.
The present invention relates to a package substrate in which solder pads for connection to an IC chip and solder pads for connection to a substrate such as a mother board and a sub board are formed on upper and lower surfaces.
【０００２】[0002]
【従来の技術】高集積ＩＣチップは、パッケージ基板に
載置され、マザーボード、サブボード等の基板へ接続さ
れている。このパッケージ基板の構成について、図２４
を参照して説明する。図２４（Ａ）は、パッケージ基板
３００の断面図を示し、図２４（Ｂ）は、該パッケージ
基板３００にＩＣチップ８０を載置して、マザーボード
９０へ取り付けた状態を示す断面図である。該パッケー
ジ基板３００は、コア基板３３０の両面に層間樹脂絶縁
層３５０を介在させて複数層の導体回路３５８を形成し
てなり、ＩＣチップ８０側の表面（上面）には、ＩＣチ
ップ側のパッド８２と接続するための半田バンプ３７６
Ｕが形成され、サブボード９０側の表面（下面）には、
マザーボード側のパッド９２と接続するための半田バン
プ３７６Ｄが形成されている。該半田バンプ３７６Ｕ
は、半田パッド３７５Ｕ上に形成され、又、半田バンプ
３７６Ｄは、半田パッド３７５Ｄ上に形成されている。2. Description of the Related Art A highly integrated IC chip is mounted on a package substrate and connected to a substrate such as a motherboard or a sub board. FIG. 24 shows the structure of this package substrate.
This will be described with reference to FIG. FIG. 24A is a cross-sectional view of the package substrate 300, and FIG. 24B is a cross-sectional view showing a state where the IC chip 80 is mounted on the package substrate 300 and attached to the motherboard 90. The package substrate 300 includes a plurality of conductor circuits 358 formed on both surfaces of a core substrate 330 with an interlayer resin insulating layer 350 interposed therebetween. A surface (upper surface) on the IC chip 80 side has pads on the IC chip side. Solder bump 376 for connection with
U is formed, and on the surface (lower surface) on the sub-board 90 side,
Solder bumps 376D for connection to pads 92 on the motherboard are formed. The solder bump 376U
Are formed on the solder pad 375U, and the solder bump 376D is formed on the solder pad 375D.
【０００３】上述したようにパッケージ基板３００は、
高集積ＩＣチップ８０とマザーボード９０とを接続する
ために用いられている。即ち、ＩＣチップ８０のパッド
８２は直径１３３〜１７０μｍと小さく、マザーボード
９０側のパッド９２は直径６００μｍと大きいので、Ｉ
Ｃチップをマザーボードへ直接取り付けることができな
いため、パッケージ基板にて中継を行っている。As described above, the package substrate 300 is
It is used to connect the highly integrated IC chip 80 and the motherboard 90. That is, the pad 82 of the IC chip 80 has a small diameter of 133 to 170 μm, and the pad 92 on the motherboard 90 has a large diameter of 600 μm.
Since the C chip cannot be directly mounted on the motherboard, the relay is performed on the package substrate.
【０００４】[0004]
【発明が解決しようとする課題】パッケージ基板は、Ｉ
Ｃチップ側半田パッド３７５Ｕ及びマザーボード側半田
パッド３７５Ｄを、それぞれ上述したＩＣチップ側のパ
ッド８２及びマザーボード側のパッド９２の大きさに対
応させて形成してある。このため、パッケージ基板３０
０のＩＣチップ側の表面に占める半田パッド３７５Ｕの
面積の割合と、マザーボード側の表面に占める半田パッ
ド３７５Ｄの面積の割合とが異なっている。ここで、層
間樹脂絶縁層３５０及びコア基板３３０は、樹脂により
形成されており、半田パッド３７５Ｕ、３７５Ｄは、ニ
ッケル等の金属で形成されている。このため、製造工程
において、層間樹脂絶縁層３５０の硬化、乾燥等により
当該樹脂部分を収縮させた際に、上述したＩＣチップ側
の表面に占める半田パッド３７５Ｙの面積の割合と、マ
ザーボード側の表面に占める半田パッド３７５Ｄの面積
の割合との差から、パッケージ基板に、ＩＣチップ側へ
の反りを発生させることがあった。更に、ＩＣチップを
載置させて実際に使用される際にも、ＩＣチップに発生
する熱により収縮を繰り返した際に、該樹脂部分と金属
部分である半田パッドとの収縮率の差から、反りを生じ
させることがあった。The package substrate is I
The C-chip-side solder pad 375U and the motherboard-side solder pad 375D are formed so as to correspond to the sizes of the IC chip-side pad 82 and the motherboard-side pad 92, respectively. Therefore, the package substrate 30
The ratio of the area of the solder pad 375U to the surface of the IC chip side of the IC chip 0 is different from that of the solder pad 375D to the surface of the mother board side. Here, the interlayer resin insulating layer 350 and the core substrate 330 are formed of resin, and the solder pads 375U and 375D are formed of metal such as nickel. Therefore, in the manufacturing process, when the resin portion is shrunk by curing, drying, etc. of the interlayer resin insulating layer 350, the ratio of the area of the solder pad 375Y to the surface of the IC chip side and the surface of the motherboard side From the ratio of the area of the solder pad 375D to the package substrate, the package substrate may be warped toward the IC chip. Furthermore, even when the IC chip is mounted and actually used, when the shrinkage is repeated due to the heat generated in the IC chip, the difference in the shrinkage ratio between the resin portion and the solder pad as the metal portion indicates that Warping may occur.
【０００５】本発明は、上述した課題を解決するために
なされたものであり、その目的とするところは、半田バ
ンプを有する反りのないパッケージ基板を提供すること
にある。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a warped package substrate having solder bumps.
【０００６】[0006]
【課題を解決するための手段】上述した目的を達成する
ため本発明は、コア基板の両面に、層間樹脂絶縁層を介
在させて導体回路を形成して成り、ＩＣチップの搭載さ
れる側の表面に半田パッドが形成され、他の基板に接続
される側の表面に、前記ＩＣチップ搭載側の半田パッド
よりも相対的に大きな半田パッドが形成されたパッケー
ジ基板であって、前記コア基板のＩＣチップが搭載され
る側に形成される導体回路のパターン間に、ダミーパタ
ーンを形成したことを技術的特徴とする。In order to achieve the above-mentioned object, the present invention comprises a conductor circuit formed on both surfaces of a core substrate with an interlayer resin insulating layer interposed therebetween. A package substrate in which solder pads are formed on the surface and solder pads relatively larger than the solder pads on the IC chip mounting side are formed on the surface connected to another substrate, A technical feature is that a dummy pattern is formed between the patterns of the conductor circuits formed on the side on which the IC chip is mounted.
【０００７】本発明においては、パッケージ基板のＩＣ
チップ側は、半田パッドが小さいため、半田パッドによ
る金属部分の占める割合が小さく、マザーボード等の基
板側は、半田パッドが大きいため、金属部分の割合が大
きい。ここで、パッケージ基板のＩＣチップ側の導体回
路のパターン間に、ダミーパターンを形成することで、
金属部分を増やし、該ＩＣチップ側とマザーボード側と
の金属部分の比率を調整し、パッケージ基板に反りを発
生させないようにしている。ここで、ダミーパターンと
は、電気接続或いはコンデンサ等の意味を持たず、単に
機械的な意味合いで形成されるパターンを言う。In the present invention, an IC on a package substrate is used.
On the chip side, the proportion of the metal portion occupied by the solder pad is small because the solder pad is small. On the substrate side such as the motherboard, the proportion of the metal portion is large because the solder pad is large. Here, by forming a dummy pattern between the patterns of the conductor circuits on the IC chip side of the package substrate,
The number of metal parts is increased, and the ratio of the metal parts on the IC chip side and the motherboard side is adjusted to prevent the package substrate from warping. Here, the dummy pattern has no meaning such as an electrical connection or a capacitor, and is a pattern formed simply with a mechanical meaning.
【０００８】[0008]
【発明の実施の形態】本発明の第１実施形態に係るパッ
ケージ基板の構成について図２２を参照して説明する。
図２２に断面を示す第１実施形態のパッケージ基板は、
上面に集積回路（図示せず）を載置した状態で、マザー
ボード（図示せず）に取り付けるためのいわゆる集積回
路パッケージを構成するものである。該パッケージ基板
は、上面に集積回路のバンプ側に接続するための半田バ
ンプ７６Ｕが設けられ、下面側にマザーボードのバンプ
に接続するための半田バンプ７６Ｄが配設され、該集積
回路−マザーボード間の信号等の受け渡し、及び、マザ
ーボード側からの電源供給を中継する役割を果たしてい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a package substrate according to a first embodiment of the present invention will be described with reference to FIG.
The package substrate according to the first embodiment whose cross section is shown in FIG.
A so-called integrated circuit package for mounting on a motherboard (not shown) with an integrated circuit (not shown) mounted on the upper surface is configured. The package substrate is provided on its upper surface with solder bumps 76U for connection to the bump side of the integrated circuit, and on the lower surface side is provided with solder bumps 76D for connection to the bumps on the motherboard. It plays a role of passing signals and the like and relaying power supply from the motherboard.
【０００９】パッケージ基板のコア基板３０の上面及び
下面には、グランド層となる内層銅パターン３４Ｕ、３
４Ｄが形成されている。また、内層銅パターン３４Ｕの
上層には、層間樹脂絶縁層５０を介在させて信号線を形
成する導体回路５８Ｕ及びダミーパターン５８Ｍが、
又、該層間樹脂絶縁層５０を貫通してバイアホール６０
Ｕ形成されている。導体回路５８Ｕ及びダミーパターン
５８Ｍの上層には、層間樹脂絶縁層１５０を介して最外
層の導体回路１５８Ｕ及び該層間樹脂絶縁層１５０を貫
通するバイアホール１６０Ｕが形成され、該導体回路１
５８Ｕ、バイアホール１６０Ｕには半田バンプ７６Ｕを
支持する半田パッド７５Ｕが形成されている。ここで、
ＩＣチップ側の半田パッド７５Ｕは、直径１３３〜１７
０μｍに形成されている。On the upper and lower surfaces of the core substrate 30 of the package substrate, inner layer copper patterns 34U, 3
4D is formed. In the upper layer of the inner copper pattern 34U, a conductor circuit 58U and a dummy pattern 58M for forming a signal line with the interlayer resin insulating layer 50 interposed therebetween are provided.
Also, the via holes 60 penetrate through the interlayer resin insulation layer 50.
U is formed. In the upper layer of the conductor circuit 58U and the dummy pattern 58M, a conductor circuit 158U of the outermost layer and a via hole 160U penetrating the interlayer resin insulation layer 150 via the interlayer resin insulation layer 150 are formed.
At 58U and via holes 160U, solder pads 75U for supporting solder bumps 76U are formed. here,
The solder pad 75U on the IC chip side has a diameter of 133 to 17
It is formed at 0 μm.
【００１０】一方、コア基板３０の下面側のグランド層
（内層銅パターン）３４Ｄの上層（ここで、上層とは基
板３０を中心として上面については上側を、基板の下面
については下側を意味する）には、層間樹脂絶縁層５０
を介して信号線を形成する導体回路５８Ｄが形成されて
いる。該導体回路５８Ｄの上層には、層間樹脂絶縁層１
５０を介して最外層の導体回路１５８Ｄ及び該層間樹脂
絶縁層１５０を貫通するバイアホール１６０Ｄが形成さ
れ、該導体回路１５８Ｄ、バイアホール１６０Ｄには半
田バンプ７６Ｄを支持する半田パッド７５Ｄが形成され
ている。ここで、マザーボード側の半田パッド７５Ｄ
は、直径６００μｍに形成されている。On the other hand, the upper layer of the ground layer (inner layer copper pattern) 34D on the lower surface side of the core substrate 30 (here, the upper layer means the upper side with respect to the substrate 30 as the center and the lower side with respect to the lower surface of the substrate). ) Includes an interlayer resin insulation layer 50
, A conductor circuit 58D forming a signal line is formed. On the upper layer of the conductor circuit 58D, an interlayer resin insulating layer 1 is provided.
A via hole 160D is formed through the outermost conductor circuit 158D and the interlayer resin insulation layer 150 via the via hole 50, and a solder pad 75D for supporting a solder bump 76D is formed in the conductor circuit 158D and the via hole 160D. I have. Here, the solder pad 75D on the motherboard side
Has a diameter of 600 μm.
【００１１】図２２のＸ１−Ｘ１断面を図２３に示す。
即ち、図２３は、パッケージ基板の横断面を示し、図２
３中のＸ１−Ｘ１縦断面が図２２に相当する。図２３中
に示すように、信号線を構成する導体回路５８Ｕ−導体
回路５８Ｕ間には、ダミーパターン５８Ｍが形成されて
いる。ここで、ダミーパターンとは、電気接続或いはコ
ンデンサ等の意味を持たず、単に機械的な意味合いで形
成されるパターンを言う。FIG. 23 shows a cross section taken along line X1-X1 of FIG.
That is, FIG. 23 shows a cross section of the package substrate, and FIG.
X1-X1 longitudinal section in 3 corresponds to FIG. As shown in FIG. 23, a dummy pattern 58M is formed between a conductor circuit 58U constituting a signal line and a conductor circuit 58U. Here, the dummy pattern has no meaning such as an electrical connection or a capacitor, and is a pattern formed simply with a mechanical meaning.
【００１２】図２４を参照して上述した従来技術のパッ
ケージ基板と同様に、第１実施形態に係るパッケージ基
板において、ＩＣチップ側の表面（上面）は、配設され
る半田パッドが小さいため（直径１３３〜１７０μ
ｍ）、半田パッドによる金属部分の占める割合が小さ
い。一方、マザーボード等の表面（下面）は、半田パッ
ドが大きいため（直径６００μｍ）、金属部分の割合が
大きい。ここで、本実施形態のパッケージ基板では、パ
ッケージ基板のＩＣチップ側の信号線を形成する導体回
路５８Ｕ、５８Ｕ間に、ダミーパターン５８Ｍを形成す
ることで、パッケージ基板のＩＣチップ側の金属部分を
増やし、該ＩＣチップ側とマザーボード側との金属部分
の比率を調整し、後述するパッケージ基板の製造工程、
及び、使用中において反りを発生させないようにしてあ
る。As in the case of the conventional package substrate described above with reference to FIG. 24, in the package substrate according to the first embodiment, the surface (upper surface) on the IC chip side has small solder pads provided thereon (see FIG. 133-170μ in diameter
m), the proportion of the metal portion occupied by the solder pads is small. On the other hand, the surface (lower surface) of the motherboard or the like has a large solder pad (600 μm in diameter), so that the ratio of the metal portion is large. Here, in the package substrate of the present embodiment, a metal pattern on the IC chip side of the package substrate is formed by forming a dummy pattern 58M between the conductor circuits 58U, 58U forming signal lines on the IC chip side of the package substrate. The ratio of the metal portion between the IC chip side and the motherboard side is adjusted, and a package substrate manufacturing process described later,
In addition, warpage is not generated during use.
【００１３】引き続き、図２２に示すパッケージ基板の
製造工程について図１〜図２２を参照して説明する。 （１）厚さ１ｍｍのガラスエポキシ樹脂またはＢＴ（ビ
スマレイミドトリアジン）樹脂からなるコア基板３０の
両面に１８μｍの銅箔３２がラミネートされている銅張
積層板３０Ａを出発材料とする（図１参照）。まず、こ
の銅張積層板３０Ａをドリル削孔し、無電解めっき処理
を施し、パターン状にエッチングすることにより、基板
３０の両面に内層銅パターン３４Ｕ、３４Ｄとスルーホ
ール３６を形成する（図２参照）。Next, a manufacturing process of the package substrate shown in FIG. 22 will be described with reference to FIGS. (1) The starting material is a copper-clad laminate 30A in which 18 μm copper foils 32 are laminated on both sides of a core substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm (see FIG. 1). ). First, the copper-clad laminate 30A is drilled, subjected to an electroless plating process, and etched in a pattern to form inner layer copper patterns 34U and 34D and through holes 36 on both surfaces of the substrate 30 (FIG. 2). reference).
【００１４】（２）さらに、内層銅パターン３４Ｕ、３
４Ｄおよびスルーホール３６を形成した基板３０を、水
洗いして乾燥した後、酸化一還元処理し、内層銅パター
ン３４Ｕ、３４Ｄおよびスルーホール３６の表面に粗化
層３８を設ける（図３参照）。(2) Further, the inner layer copper patterns 34U, 3U
The substrate 30 having the 4D and the through-hole 36 formed thereon is washed with water and dried, and then subjected to an oxidation-reduction treatment to provide a roughened layer 38 on the surfaces of the inner copper patterns 34U and 34D and the through-hole 36 (see FIG. 3).
【００１５】（３）一方、基板表面を平滑化するための
樹脂充填剤を調整する。ここでは、ビスフェノールＦ型
エポキシモノマー（油化シェル製、分子量３１０、ＹＬ
９８３Ｕ）１００重量部、イミダゾール硬化剤（四国化
成製、２Ｅ４ＭＺ−ＣＮ）６重量部を混合し、これらの
混合物に対し、表面にシランカップリング剤がコーティ
ングされた平均粒径１．６μｍのＳｉＯ2 球状粒子（ア
ドマテック製、ＣＲＳ１１０１−ＣＥ、ここで、最大粒
子の大きさは後述する内層銅パターンの厚み（１５μ
ｍ）以下とする）１７０重量部、消泡剤（サンノプコ
製、ペレノールＳ４）０．５重量部を混合し、３本ロー
ルにて混練することにより、その混合物の粘度を２３±
１℃で４５，０００〜４９，０００ｃｐｓに調整して、
樹脂充填剤を得る。この樹脂充填剤は無溶剤である。も
し溶剤入りの樹脂充填剤を用いると、後工程において層
間剤を塗布して加熱・乾燥させる際に、樹脂充填剤の層
から溶剤が揮発して、樹脂充填剤の層と層間材との間で
剥離が発生するからである。(3) On the other hand, a resin filler for smoothing the substrate surface is adjusted. Here, bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL)
983U) 100 parts by weight of imidazole curing agent (made by Shikoku Kasei Co., 2E4MZ-CN) 6 parts by weight of 1, for these mixtures, SiO having an average particle size of 1.6μm silane coupling agent to the surface-coated 2 Spherical particles (manufactured by Admatech, CRS1101-CE, where the maximum particle size is the thickness of the inner layer copper pattern described later (15 μm).
m) or less) 170 parts by weight, and 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, Perenol S4), and kneading with a three-roll mill to reduce the viscosity of the mixture to 23 ±
Adjust to 45,000-49,000 cps at 1 ° C,
Obtain resin filler. This resin filler is solventless. If a resin filler containing a solvent is used, the solvent is volatilized from the resin filler layer when the interlayer agent is applied, heated and dried in a later step, so that a gap between the resin filler layer and the interlayer material is generated. This causes peeling.
【００１６】（４）上記（３）で得た樹脂充填剤４０
を、基板３０の両面にロールコータを用いて塗布するこ
とにより、上面の導体回路（内層銅パターン）３４Ｕ間
あるいはスルーホール３６内に充填し、７０℃，２０分
間で乾燥させ、下面についても同様にして樹脂充填剤４
０を導体回路３４Ｄ間あるいはスルーホール３６内に充
填し、７０℃，２０分間で乾燥させる（図４参照）。(4) The resin filler 40 obtained in the above (3)
Is applied to both surfaces of the substrate 30 using a roll coater to fill the space between the conductor circuits (inner copper patterns) 34U on the upper surface or in the through holes 36, and is dried at 70 ° C. for 20 minutes. And resin filler 4
0 is filled between the conductor circuits 34D or in the through holes 36 and dried at 70 ° C. for 20 minutes (see FIG. 4).
【００１７】（５）上記（４）の処理を終えた基板３０
の片面を、♯６００のベルト研磨紙（三共理化学製）を
用いたベルトサンダー研磨により、内層銅パターン３４
Ｕ、３４Ｄの表面やスルーホール３６のランド表面に樹
脂充填剤４０が残らないように研磨し、次いで、上記ベ
ルトサンダー研磨による傷を取り除くためのバフ研磨を
行う（図５参照）。次いで、１００℃で１時間、１２０
℃で３時間、１５０℃で１時間、１８０℃で７時間の加
熱処理を行って樹脂充填剤４０を硬化させる。(5) The substrate 30 after the processing of the above (4)
Of the inner layer copper pattern 34 by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku).
Polishing is performed so that the resin filler 40 does not remain on the surfaces of the U and 34D and the land surface of the through hole 36, and then buffing is performed to remove the scratches caused by the belt sander polishing (see FIG. 5). Then, at 100 ° C. for 1 hour, 120
The resin filler 40 is cured by performing a heat treatment at a temperature of 3 hours at 150 ° C. for 1 hour and at 180 ° C. for 7 hours.
【００１８】このようにして、スルーホール３６等に充
填された樹脂充填剤４０の表層部および導体回路３４
Ｕ、３４Ｄ上面の粗化層３８を除去して基板両面を平滑
化することで、樹脂充填剤４０と導体回路３４Ｕ、３４
Ｄの側面とが粗化層３８を介して強固に密着し、またス
ルーホール３６の内壁面と樹脂充填剤４０とが粗化層３
８を介して強固に密着した配線基板を得る。即ち、この
工程により、掛脂充填剤４０の表面と内層銅パターン３
４Ｕ、３４Ｄの表面とを同一平面にする。ここで、充填
した硬化樹脂のＴｇ点は１５５．６℃、線熱膨張係数は
４４．５×１０-6／℃であった。In this manner, the surface layer of the resin filler 40 filled in the through holes 36 and the like and the conductor circuit 34
By removing the roughened layer 38 on the upper surface of the U and 34D and smoothing both surfaces of the substrate, the resin filler 40 and the conductor circuits 34U and 34D are removed.
D is firmly adhered to the side surface of the roughened layer 38 via the roughened layer 38, and the inner wall surface of the through hole 36 and the resin filler 40 are bonded to the roughened layer 3.
Thus, a wiring board firmly adhered to the wiring board is obtained. That is, by this process, the surface of the grease filler 40 and the inner layer copper pattern 3
The surfaces of 4U and 34D are flush with each other. Here, the filled resin had a Tg point of 155.6 ° C. and a linear thermal expansion coefficient of 44.5 × 10 −6 / ° C.
【００１９】（６）上記（５）の処理で露出した導体回
路３４Ｕ、３４Ｄおよびスルーホール３６のランド上面
に、厚さ２．５μｍのＣｕ−Ｎｉ−Ｐ合金からなる粗化
層（凹凸層）４２を形成し、さらに、その粗化層４２の
表面に厚さ０．３μｍのＳｎ層を設ける（図６参照、但
し、Ｓｎ層については図示しない）。その形成方法は以
下のようである。即ち、基板３０を酸性脱脂してソフト
エッチングし、次いで、塩化パラジウムと有機酸からな
る触媒溶液で処理して、Ｐｄ触媒を付与し、この触媒を
活性化した後、硫酸銅８ｇ／ｌ、硫酸ニッケル０．６ｇ
／ｌ、クエン酸１５ｇ／ｌ、次亜リン酸ナトリウム２９
ｇ／ｌ、ホウ酸３１ｇ／ｌ、界面活性剤０．１ｇ／ｌ、
ｐＨ＝９からなる無電解めっき浴にてめっきを施し、銅
導体回路４およびスルーホール９のランド上面にＣｕ−
Ｎｉ−Ｐ合金の粗化層４２を形成する。ついで、ホウフ
ッ化スズ０．１ｍｏｌ／ｌ、チオ尿素１．０ｍｏｌ／
ｌ、温度５０℃、ｐＨ＝１．２の条件でＣｕ−Ｓｎ置換
反応させ、粗化層４２の表面に厚さ０．３μｍのＳｎ層
を設ける（Ｓｎ層については図示しない）。(6) On the upper surface of the lands of the conductor circuits 34U, 34D and the through holes 36 exposed in the processing of (5), a roughened layer (concavo-convex layer) made of a Cu—Ni—P alloy having a thickness of 2.5 μm Then, an Sn layer having a thickness of 0.3 μm is provided on the surface of the roughened layer 42 (see FIG. 6, but the Sn layer is not shown). The formation method is as follows. That is, the substrate 30 is acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst. After activating this catalyst, copper sulfate 8 g / l, sulfuric acid Nickel 0.6g
/ L, citric acid 15g / l, sodium hypophosphite 29
g / l, boric acid 31 g / l, surfactant 0.1 g / l,
Plating is performed in an electroless plating bath having a pH of 9 and Cu-
The roughened layer 42 of the Ni-P alloy is formed. Then, tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l
1, a Cu-Sn substitution reaction is performed under the conditions of a temperature of 50 ° C. and a pH of 1.2 to form a 0.3 μm thick Sn layer on the surface of the roughened layer 42 (the Sn layer is not shown).
【００２０】引き続き、絶縁層を形成する感光性接着剤
（上層用）及び層間樹脂絶縁剤（下層用）を用意する。 （７）感光性接着剤（上層用）は、ＤＭＤＧ（ジエチレ
ングリコールジメチルエーテル）に溶解した濃度８０ｗ
ｔ％のクレゾールノボラック型エポキシ樹脂（日本化薬
製、分子量２５００）の２５％アクリル化物を３５重量
部、ポリエーテルスルフォン（ＰＥＳ）１２重量部、イ
ミダゾール硬化剤（四国化成製、２Ｅ４ＭＺ−ＣＮ）２
重量部、感光性モノマー（東亜合成製、アロニックスＭ
３１５）４重量部、光開始剤（チバガイギー製、イルガ
キュアＩ−９０７）２重量部、光増感剤（日本化薬製、
ＤＥＴＸ−Ｓ）０．２重量部を混合し、これらの混合物
に対し、エポキシ樹脂粒子（三洋化成製、ポリマーポー
ル）の平均粒径１．０μｍのものを７．２重量部、平均
粒経０．５μｍのものを３．０９重量部、消泡剤（サン
ノプコ製 Ｓ−６５）０．５重量部を混合した後、さら
にＮＭＰ３０重量部を添加しながら混合して粘度７Ｐａ
・ｓの感光性接着剤（上層用）を得る。Subsequently, a photosensitive adhesive (for an upper layer) and an interlayer resin insulator (for a lower layer) for forming an insulating layer are prepared. (7) The photosensitive adhesive (for the upper layer) is dissolved in DMDG (diethylene glycol dimethyl ether) at a concentration of 80 w
35% by weight of 25% acrylate of t% cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500), 12 parts by weight of polyether sulfone (PES), imidazole curing agent (2E4MZ-CN) 2
Parts by weight, photosensitive monomer (Toa Gosei Co., Aronix M
315) 4 parts by weight, 2 parts by weight of a photoinitiator (manufactured by Ciba Geigy, Irgacure I-907), a photosensitizer (manufactured by Nippon Kayaku,
0.2 parts by weight of DETX-S) were mixed, and 7.2 parts by weight of epoxy resin particles (manufactured by Sanyo Chemical Industries, polymer pole) having an average particle diameter of 1.0 μm were added to these mixtures, and the average particle diameter was 0%. After mixing 3.09 parts by weight of a 0.5 μm-thick and 0.5 parts by weight of an antifoaming agent (S-65 manufactured by San Nopco), the mixture was further mixed while adding 30 parts by weight of NMP to obtain a viscosity of 7 Pa.
・ S photosensitive adhesive (for upper layer) is obtained.
【００２１】（８）一方、層間樹脂絶縁剤（下層用）
は、ＤＭＤＧ（ジエチレングリコールジメチルエーテ
ル）に溶解した濃度８０ｗｔ％のクレゾールノボラック
型エポキシ樹脂（日本化薬製、分子量２５００）の２５
％アクリル化物を３５重量部、ポリエーテルスルフォン
（ＰＥＳ）１２重量部、イミダゾール硬化剤（四国化成
製、２Ｅ４ＭＺ−ＣＮ）２重量部、感光性モノマー（東
亜合成製、アロニックスＭ３１５）４重量部、光開始剤
（チバガイギー製、イルガキュアI −９０７）２重量
部、光増感剤（日本化薬製、ＤＥＴＥ−Ｓ）０．２重量
部を混合し、これらの混合物に対し、エポキシ樹脂粒子
（三洋化成製、ポリマーポール）の平均粒経０．５μｍ
のものを１４．４９重量部、消泡剤（サンノプコ製、Ｓ
−６５）０．５重量部を混合した後、さらにＮＭＰ３０
重量部を添加しながら混合して粘度１．５Ｐａ・ｓの層
間樹脂絶縁剤（下層用）を得る。(8) On the other hand, interlayer resin insulating agent (for lower layer)
Is a 25% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku, molecular weight 2500) dissolved in DMDG (diethylene glycol dimethyl ether).
% Acrylate, 35 parts by weight of polyethersulfone (PES), 12 parts by weight of imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 4 parts by weight of photosensitive monomer (Aronix M315, manufactured by Toa Gosei), light 2 parts by weight of an initiator (Circa Geigy, Irgacure I-907) and 0.2 part by weight of a photosensitizer (DETE-S, Nippon Kayaku) were mixed, and the mixture was mixed with epoxy resin particles (Sanyo Chemical Co., Ltd.). 0.5μm average particle size
14.49 parts by weight of an antifoaming agent (manufactured by San Nopco, S
-65) After mixing 0.5 part by weight, NMP30
By mixing while adding parts by weight, an interlayer resin insulating agent (for lower layer) having a viscosity of 1.5 Pa · s is obtained.
【００２２】（９）基板３０の両面に、上記（７）で得
られた粘度１．５Ｐａ・ｓの層間樹脂絶縁剤（下層用）
をロールコ一夕で塗布し、水平状態で２０分間放置して
から、６０℃で３０分の乾燥（プリベーク）を行い、絶
縁剤層４４を形成する。さらにこの絶縁剤層４４の上に
上記（８）で得られた粘度７Ｐａ・ｓの感光性接着剤
（上層用）をロールコ一タを用いて塗布し、水平状態で
２０分間放置してから、６０℃で３０分の乾燥を行い、
接着剤層４６を形成する（図７参照）。(9) On both sides of the substrate 30, an interlayer resin insulating material having a viscosity of 1.5 Pa · s obtained in the above (7) (for lower layer)
Is applied on a roll roll overnight, left for 20 minutes in a horizontal state, and then dried (prebaked) at 60 ° C. for 30 minutes to form an insulating layer 44. Further, the photosensitive adhesive (for the upper layer) having a viscosity of 7 Pa · s obtained in the above (8) is applied on the insulating layer 44 using a roll coater, and left for 20 minutes in a horizontal state. Dry at 60 ° C for 30 minutes,
An adhesive layer 46 is formed (see FIG. 7).
【００２３】上述したように導体回路３４Ｕ、３４Ｄ
は、粗化層（凹凸層）４２が形成され、即ち、粗化処理
が施されることで、上層の絶縁剤層４４との密着性が高
められている。As described above, the conductor circuits 34U and 34D
The roughening layer (irregular layer) 42 is formed, that is, by performing a roughening process, the adhesion to the upper insulating layer 44 is enhanced.
【００２４】（１０）上記（９）で絶縁剤層４４および
接着剤層４６を形成した基板３０の両面に、１００μｍ
φの黒円が印刷されたフォトマスクフィルムを密着さ
せ、超高圧水銀灯により５００ｍＪ／ｃｍ2 で露光す
る。これをＤＭＤＧ溶液でスプレー現像し、さらに、当
該基板を超高圧水銀灯により３０００ｍＪ／ｃｍ2 で露
光し、１００℃で１時間、その後１５０℃で５時間の加
熱処理（ポストベーク）をすることにより、フォトマス
クフィルムに相当する寸法精度に優れた１００μｍφの
開口（バイアホール形成用開口４８）を有する厚さ３５
μｍの層間樹脂絶縁層（２層構造）５０を形成する（図
８参照）。なお、バイアホールとなる開口４８には、ス
ズめっき層を部分的に露出させる。(10) On both sides of the substrate 30 on which the insulating layer 44 and the adhesive layer 46 are formed in the above (9), 100 μm
The photomask film on which the black circle of φ is printed is brought into close contact with the photomask film, and exposed at 500 mJ / cm 2 using an ultra-high pressure mercury lamp. This is spray-developed with a DMDG solution, and further, the substrate is exposed to 3000 mJ / cm 2 by an ultra-high pressure mercury lamp, and is subjected to a heat treatment (post-bake) at 100 ° C. for 1 hour, and then at 150 ° C. for 5 hours. Thickness 35 having 100 μmφ opening (via hole forming opening 48) having excellent dimensional accuracy equivalent to a photomask film
A μm interlayer resin insulating layer (two-layer structure) 50 is formed (see FIG. 8). Note that the tin plating layer is partially exposed in the opening 48 serving as a via hole.
【００２５】（１１）開口４８が形成された基板３０
を、クロム酸に１分間浸漬し、接着剤層４６の表面のエ
ポキシ樹脂粒子を溶解除去することにより、層間樹脂絶
縁層５０の表面を粗面とし、その後、中和溶液（シプレ
イ社製）に浸漬してから水洗いする（図９参照）。さら
に、粗面化処理した該基板の表面に、パラジウム触媒
（アトテック製）を付与することにより、層間樹脂絶縁
層５０の表面およびバイアホール用開口４８の内壁面に
触媒核を付ける。(11) The substrate 30 having the opening 48 formed
Is immersed in chromic acid for 1 minute to dissolve and remove the epoxy resin particles on the surface of the adhesive layer 46 to make the surface of the interlayer resin insulating layer 50 rough, and then to a neutralizing solution (manufactured by Shipley). After immersion, it is washed with water (see FIG. 9). Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate subjected to the surface roughening treatment, a catalyst nucleus is attached to the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48.
【００２６】（１２）以下の組成の無電解銅めっき浴中
に基板を浸漬して、粗面全体に厚さ１．６μｍの無電解
銅めっき膜５２を形成する（図１０参照）。 〔無電解めっき液〕 ＥＤＴＡ １５０ ｇ／ｌ 硫酸銅 ２０ ｇ／ｌ ＨＣＨＯ ３０ｍｌ／ｌ ＮａＯＨ ４０ ｇ／ｌ α、α’−ビピリジル ８０ ｍｇ／ｌ ＰＥＧ ０．１ｇ／ｌ 〔無電解めっき条件〕 ７０℃の液温度で３０分(12) The substrate is immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 52 having a thickness of 1.6 μm on the entire rough surface (see FIG. 10). [Electroless plating solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at liquid temperature
【００２７】（１３）上記（１２）で形成した無電解銅
めっき膜５２上に市販の感光性ドライフィルムを張り付
け、マスクを載置して、１００ｍＪ／ｃｍ2 で露光、
０．８％炭酸ナトリウムで現像処理し、図２３を参照し
て上述したように信号線となる導体回路５８Ｕ−５８Ｕ
間に、ダミーパターン５８Ｍを形成するように厚さ１５
μｍのめっきレジスト５４を設ける（図１１参照）。(13) A commercially available photosensitive dry film is stuck on the electroless copper plating film 52 formed in the above (12), a mask is placed, and exposure is performed at 100 mJ / cm 2 .
Conductive circuits 58U-58U which are developed with 0.8% sodium carbonate and become signal lines as described above with reference to FIG.
A thickness of 15 mm is formed so as to form a dummy pattern 58M.
A plating resist 54 of μm is provided (see FIG. 11).
【００２８】（１４）ついで、レジスト非形成部分に以
下の条件で電解銅めっきを施し、厚さ１５μｍの電解銅
めっき膜５６を形成する（図１２参照）。 (14) Next, electrolytic copper plating is applied to the non-resist-formed portion under the following conditions to form an electrolytic copper plating film 56 having a thickness of 15 μm (see FIG. 12).
【００２９】（１５）めっきレジスト５４を５％ＫＯＨ
で剥離除去した後、そのめっきレジスト５４下の無電解
めっき膜５２を硫酸と過酸化水素の混合液でエッチング
処理して溶解除去し、無電解銅めっき膜５２と電解銅め
っき膜５６からなる厚さ１８μｍの導体回路５８Ｕ、５
８Ｄ及びバイアホール６０Ｕ、６０Ｄを形成する（図１
３参照）。引き続き、その基板３０を８００ｇ／ｌのク
ロム酸中に３分間浸漬して粗化面上に残留しているパラ
ジウム触媒核を除去する。(15) 5% KOH plating resist 54
Then, the electroless plating film 52 under the plating resist 54 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to form a film comprising the electroless copper plating film 52 and the electrolytic copper plating film 56. 58 μm conductor circuit 58U, 5
8D and via holes 60U, 60D are formed (FIG. 1).
3). Subsequently, the substrate 30 is immersed in 800 g / l chromic acid for 3 minutes to remove the palladium catalyst nuclei remaining on the roughened surface.
【００３０】（１６）導体回路５８Ｕ、５８Ｄ及びバイ
アホール６０Ｕ、６０Ｄを形成した基板３０を、硫酸銅
８ｇ／ｌ、硫酸ニッケル０．６ｇ／ｌ、クエン酸１５ｇ
／ｌ、次亜リン酸ナトリウム２９ｇ／ｌ、ホウ酸３１ｇ
／ｌ、界面活性剤０．１ｇ／ｌからなるｐＨ＝９の無電
解めっき液に浸漬し、該導体回路５８Ｕ、５８Ｄ及びバ
イアホール６０Ｕ、６０Ｄの表面に厚さ３μｍの銅−ニ
ッケル−リンからなる粗化層６２を形成する（図１４参
照）。さらに、ホウフッ化スズ０．１ｍｏｌ／ｌ、チオ
尿素１．０ｍｏｌ／ｌ、温度５０℃、ｐＨ＝１．２の条
件でＣｕ−Ｓｎ置換反応を行い、上記粗化層６２の表面
に厚さ０．３μｍのＳｎ層を設ける（Ｓｎ層については
図示しない）。(16) The substrate 30 on which the conductor circuits 58U and 58D and the via holes 60U and 60D are formed is replaced with copper sulfate 8 g / l, nickel sulfate 0.6 g / l, and citric acid 15 g.
/ L, sodium hypophosphite 29g / l, boric acid 31g
/ L, a surfactant of 0.1 g / l, immersed in an electroless plating solution having a pH of 9 and a surface of the conductor circuits 58U, 58D and via holes 60U, 60D formed of copper-nickel-phosphorus having a thickness of 3 μm. A roughened layer 62 is formed (see FIG. 14). Further, a Cu—Sn substitution reaction was performed under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50 ° C., and pH = 1.2, and a thickness of 0 A Sn layer of 0.3 μm is provided (the Sn layer is not shown).
【００３１】（１７）上記（２）〜（１６）の工程を繰
り返すことにより、さらに上層の導体回路を形成する。
即ち、基板３０の両面に、層間樹脂絶縁剤（下層用）を
ロールコ一夕で塗布し、絶縁剤層１４４を形成する。ま
た、この絶縁剤層１４４の上に感光性接着剤（上層用）
をロールコ一タを用いて塗布し、接着剤層１４６を形成
する（図１５参照）。絶縁剤層１４４および接着剤層１
４６を形成した基板３０の両面に、フォトマスクフィル
ムを密着させ、露光・現像し、開口（バイアホール形成
用開口１４８）を有する層間樹脂絶縁層１５０を形成し
た後、該層間樹脂絶縁層１５０の表面を粗面とする（図
１６参照）。その後、該粗面化処理した該基板３０の表
面に、無電解銅めっき膜１５２を形成する（図１７参
照）。引き続き、無電解銅めっき膜１５２上にめっきレ
ジスト１５４を設けた後、レジスト非形成部分に電解銅
めっき膜１５６を形成する（図１８参照）。そして、め
っきレジスト１５４をＫＯＨで剥離除去した後、そのめ
っきレジスト５４下の無電解めっき膜１５２を溶解除去
し導体回路１５８Ｕ、１５８Ｄ及びバイアホール１６０
Ｕ、１６０Ｄを形成する（図１９参照）。さらに、該導
体回路１５８Ｕ、１５８Ｄ及びバイアホール１６０Ｕ、
１６０Ｄの表面に粗化層１６２を形成し、パッケージ基
板を完成する（図２０参照）。(17) By repeating the above steps (2) to (16), a conductor circuit in a further upper layer is formed.
That is, an interlayer resin insulating agent (for the lower layer) is applied to both surfaces of the substrate 30 with a roller to form an insulating agent layer 144. Also, a photosensitive adhesive (for the upper layer) is provided on the insulating layer 144.
Is applied using a roll coater to form an adhesive layer 146 (see FIG. 15). Insulating agent layer 144 and adhesive layer 1
A photomask film is brought into close contact with both surfaces of the substrate 30 on which the 46 has been formed, and exposed and developed to form an interlayer resin insulating layer 150 having an opening (via hole forming opening 148). The surface is made rough (see FIG. 16). Thereafter, an electroless copper plating film 152 is formed on the surface of the substrate 30 subjected to the surface roughening treatment (see FIG. 17). Subsequently, after a plating resist 154 is provided on the electroless copper plating film 152, an electrolytic copper plating film 156 is formed on a portion where no resist is formed (see FIG. 18). Then, after the plating resist 154 is peeled off with KOH, the electroless plating film 152 under the plating resist 54 is dissolved and removed, and the conductor circuits 158U and 158D and the via holes 160 are removed.
U, 160D are formed (see FIG. 19). Further, the conductor circuits 158U, 158D and via holes 160U,
A roughened layer 162 is formed on the surface of 160D, and a package substrate is completed (see FIG. 20).
【００３２】（１９）そして、上述したパッケージ基板
にはんだバンプを形成する。先ず、はんだバンプ用のソ
ルダーレジスト組成物の調整について説明する。ここで
は、ＤＭＤＧに溶解させた６０重量％のクレゾールノボ
ラック型エポキシ樹脂（日本化薬製）のエポキシ基５０
％をアクリル化した感光性付与のオリゴマー（分子量４
０００）を４６．６７ｇ、メチルエチルケトンに溶解さ
せた８０重量％のビスフェノールＡ型エポキシ樹脂（油
化シェル製、エピコート１００１）１５．０ｇ、イミダ
ゾール硬化剤（四国化成製、２Ｅ４ＭＺ−ＣＮ）１．６
ｇ、感光性モノマーである多価アクリルモノマー（日本
化薬製、Ｒ６０４）３ｇ、同じく多価アクリルモノマー
（共栄社化学製、ＤＰＥ６Ａ）１．５ｇ、分散系消泡剤
（サンノプコ社製、Ｓ−６５）０．７１ｇを混合し、さ
らにこれらの混合物に対し、光開始剤としてのべンゾフ
ェノン（関東化学製）を２ｇ、光増感剤としてのミヒラ
ーケトン（関東化学製）を０．２ｇ加えて、粘度を２５
℃で２．０Ｐａ・ｓに調整したソルダーレジスト組成物
を得る。(19) Then, solder bumps are formed on the above-mentioned package substrate. First, adjustment of the solder resist composition for a solder bump will be described. Here, the epoxy group 50 of a 60% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG is used.
% Of acrylated oligomer (molecular weight 4
000) was dissolved in methyl ethyl ketone, and 15.0 g of a 80% by weight bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001), and an imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN) 1.6.
g, 3 g of a polyacrylic monomer (R604, manufactured by Nippon Kayaku) which is a photosensitive monomer, 1.5 g of a polyvalent acrylic monomer (DPE6A, manufactured by Kyoeisha Chemical Co., Ltd.), and an antifoaming agent (S-65, manufactured by San Nopco) ), And 2 g of benzophenone as a photoinitiator (manufactured by Kanto Kagaku) and 0.2 g of Michler's ketone as a photosensitizer (manufactured by Kanto Kagaku) were added to the mixture. 25
A solder resist composition adjusted to 2.0 Pa · s at ° C is obtained.
【００３３】（２０）上記（１８）で得た配線板の両面
に、上記ソルダーレジスト組成物を２０μｍの厚さで塗
布する。次いで、７０℃で２０分間、７０℃で３０分間
の乾燥処理を行った後、円パターン（マスクパターン）
が描画された厚さ５ｍｍのフォトマスクフィルムを密着
させて載置し、１０００ｍＪ／ｃｍ2 の紫外線で露光
し、ＤＭＴＧ現像処理する。そしてさらに、８０℃で１
時間、１００℃で１時間、１２０℃で１時間、１５０℃
で３時間の条件で加熱処理し、はんだパッド部分（バイ
アホールとそのランド部分を含む）７１が開口した（上
面側の開口径２００μｍ、下面側の開口径８００μｍ）
ソルダーレジスト層（厚み２０μｍ）７０を形成する
（図２１参照）。(20) The solder resist composition is applied to both sides of the wiring board obtained in (18) in a thickness of 20 μm. Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a circular pattern (mask pattern)
Is placed in close contact with a 5 mm thick photomask film on which is drawn, exposed to ultraviolet light of 1000 mJ / cm 2 , and subjected to DMTG development processing. And at 80 ° C for 1
Time, 1 hour at 100 ° C, 1 hour at 120 ° C, 150 ° C
And a heat treatment was performed under the condition of 3 hours, and a solder pad portion (including a via hole and its land portion) 71 was opened (opening diameter on the upper surface side 200 μm, opening diameter on the lower surface side 800 μm).
A solder resist layer (thickness: 20 μm) 70 is formed (see FIG. 21).
【００３４】（２１）次に、ソルダーレジスト層７０を
形成した基板３０を、塩化ニッケル３０ｇ／ｌ、次亜リ
ン酸ナトリウム１０ｇ／ｌ、クエン酸ナトリウム１０ｇ
／ｌからなるｐＨ＝５の無電解ニッケルめっき液に２０
分間浸漬して、開口部７１に厚さ５μｍのニッケルめっ
き層７２を形成する（図２２参照）。さらに、その基板
３０を、シアン化金カリウム２ｇ／ｌ、塩化アンモニウ
ム７５ｇ／ｌ、クエン酸ナトリウム５０ｇ／ｌ、次亜リ
ン酸ナトリウム１０ｇ／ｌからなる無電解金めっき液に
９３℃の条件で２３秒間浸漬して、ニッケルめっき層７
２上に厚さ０．０３μｍの金めっき層７４を析出し、上
面に直径１３３〜１７０μｍの半田パッド７５Ｕを、下
面に直径６００μｍの半田パッド７５Ｄを形成する。(21) Next, the substrate 30 on which the solder resist layer 70 is formed is replaced with nickel chloride 30 g / l, sodium hypophosphite 10 g / l, and sodium citrate 10 g.
/ L of electroless nickel plating solution of pH = 5
Then, a nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 (see FIG. 22). Further, the substrate 30 was immersed in an electroless gold plating solution comprising 2 g / l of potassium gold cyanide, 75 g / l of ammonium chloride, 50 g / l of sodium citrate, and 10 g / l of sodium hypophosphite at 93 ° C. for 23 hours. Immersion for 2 seconds, nickel plating layer 7
A gold plating layer 74 having a thickness of 0.03 μm is deposited on the substrate 2, and a solder pad 75 U having a diameter of 133 to 170 μm is formed on the upper surface, and a solder pad 75 D having a diameter of 600 μm is formed on the lower surface.
【００３５】（２２）そして、ソルダーレジスト層７０
の開口部７１内の半田パッド７５Ｕ、７５Ｄに、はんだ
ペーストを印刷して２００℃でリフローすることにより
はんだバンプ７６Ｕ、７６Ｄを形成し、はんだバンプ７
６Ｕ、７６Ｄを有するパッケージ基板を完成する。(22) The solder resist layer 70
Solder paste is printed on the solder pads 75U and 75D in the opening 71, and reflowed at 200 ° C. to form solder bumps 76U and 76D.
A package substrate having 6U and 76D is completed.
【００３６】なお、上述した実施形態では、セミアディ
ティブ法により形成するパッケージ基板を例示したが、
本発明の構成は、フルアディティブ法により形成するパ
ッケージ基板にも適用し得ることは言うまでもない。ま
た、上述した実施形態では、層間樹脂絶縁層５０と層間
樹脂絶縁層１５０との間に形成される導体回路５８Ｕ間
にダミーパターン５８Ｍを形成したが、この代わりに、
コア基板３０上に形成される内層銅パターン３４Ｄ、或
いは、最外層の導体回路１５８Ｕ間にダミーパターン５
８Ｍを形成することも可能である。また、上述した実施
形態では、パッケージ基板をマザーボードに直接取り付
ける例を挙げたが、パッケージ基板をサブボード等を介
してマザーボードに接続する場合にも、本発明のパッケ
ージ基板を好適に使用することができる。In the above-described embodiment, the package substrate formed by the semi-additive method has been exemplified.
Needless to say, the configuration of the present invention can be applied to a package substrate formed by a full additive method. In the above-described embodiment, the dummy pattern 58M is formed between the conductor circuits 58U formed between the interlayer resin insulating layer 50 and the interlayer resin insulating layer 150.
The inner copper pattern 34D formed on the core substrate 30 or the dummy pattern 5 between the outermost conductive circuits 158U.
It is also possible to form 8M. Further, in the above-described embodiment, the example in which the package substrate is directly attached to the motherboard has been described.However, even when the package substrate is connected to the motherboard via a sub board or the like, the package substrate of the present invention can be preferably used. it can.
【００３７】[0037]
【発明の効果】以上説明したように本発明のパッケージ
基板において、ＩＣチップ側の表面は、配設される半田
パッドが小さいため、半田パッドによる金属部分の占め
る割合が小さく、マザーボード等の表面は、半田パッド
が大きいため、金属部分の割合が大きい。ここで、パッ
ケージ基板のＩＣチップ側の信号線を形成する導体回路
間に、ダミーパターンを形成し、パッケージ基板のＩＣ
チップ側の金属部分を増やし、該ＩＣチップ側とマザー
ボード側との金属部分の比率を調整してあるため、本発
明の構成によれば、パッケージ基板の製造工程、及び、
使用中において反りを発生させることがない。As described above, in the package substrate of the present invention, since the solder pads provided on the surface of the IC chip side are small, the proportion of the metal portion occupied by the solder pads is small, and the surface of the motherboard or the like is small. Since the size of the solder pad is large, the ratio of the metal portion is large. Here, a dummy pattern is formed between the conductor circuits forming the signal lines on the IC chip side of the package substrate, and the IC of the package substrate is formed.
Since the number of metal parts on the chip side is increased and the ratio of the metal parts on the IC chip side and the motherboard side is adjusted, according to the configuration of the present invention, the manufacturing process of the package substrate, and
No warpage occurs during use.
【図１】本発明の第１実施形態に係るパッケージ基板の
製造工程を示す図である。FIG. 1 is a diagram illustrating a manufacturing process of a package substrate according to a first embodiment of the present invention.
【図２】本発明の第１実施形態に係るパッケージ基板の
製造工程を示す図である。FIG. 2 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図３】本発明の第１実施形態に係るパッケージ基板の
製造工程を示す図である。FIG. 3 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図４】本発明の第１実施形態に係るパッケージ基板の
製造工程を示す図である。FIG. 4 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図５】本発明の第１実施形態に係るパッケージ基板の
製造工程を示す図である。FIG. 5 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図６】本発明の第１実施形態に係るパッケージ基板の
製造工程を示す図である。FIG. 6 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図７】本発明の第１実施形態に係るパッケージ基板の
製造工程を示す図である。FIG. 7 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図８】本発明の第１実施形態に係るパッケージ基板の
製造工程を示す図である。FIG. 8 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図９】本発明の第１実施形態に係るパッケージ基板の
製造工程を示す図である。FIG. 9 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図１０】本発明の第１実施形態に係るパッケージ基板
の製造工程を示す図である。FIG. 10 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図１１】本発明の第１実施形態に係るパッケージ基板
の製造工程を示す図である。FIG. 11 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図１２】本発明の第１実施形態に係るパッケージ基板
の製造工程を示す図である。FIG. 12 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図１３】本発明の第１実施形態に係るパッケージ基板
の製造工程を示す図である。FIG. 13 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図１４】本発明の第１実施形態に係るパッケージ基板
の製造工程を示す図である。FIG. 14 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図１５】本発明の第１実施形態に係るパッケージ基板
の製造工程を示す図である。FIG. 15 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図１６】本発明の第１実施形態に係るパッケージ基板
の製造工程を示す図である。FIG. 16 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図１７】本発明の第１実施形態に係るパッケージ基板
の製造工程を示す図である。FIG. 17 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図１８】本発明の第１実施形態に係るパッケージ基板
の製造工程を示す図である。FIG. 18 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図１９】本発明の第１実施形態に係るパッケージ基板
の製造工程を示す図である。FIG. 19 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図２０】本発明の第１実施形態に係るパッケージ基板
の製造工程を示す図である。FIG. 20 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図２１】本発明の第１実施形態に係るパッケージ基板
の製造工程を示す図である。FIG. 21 is a diagram illustrating a manufacturing process of the package substrate according to the first embodiment of the present invention.
【図２２】本発明の第１実施形態に係るパッケージ基板
を示す断面図である。FIG. 22 is a cross-sectional view illustrating the package substrate according to the first embodiment of the present invention.
【図２３】図２２に示すパッケージ基板のＸ１−Ｘ１横
断面図である。23 is a cross-sectional view of the package substrate shown in FIG. 22, taken along line X1-X1.
【図２４】図２４（Ａ）は、従来技術に係るパッケージ
基板の断面図であり、図２４（Ｂ）は、従来技術のパッ
ケージ基板にＩＣチップを載置し、マザーボードに取り
付けた状態を示す断面図である。FIG. 24A is a cross-sectional view of a conventional package substrate, and FIG. 24B shows a state where an IC chip is mounted on a conventional package substrate and attached to a motherboard. It is sectional drawing.
【符号の説明】 ３０ コア基板 ３４Ｕ、３４Ｄ 内層銅パターン（内層導体回路） ３５ 導体非形成部分 ３８ 粗化層 ４０ 樹脂充填剤 ４２ 粗化層 ４８ バイアホール用開口 ５０ 層間樹脂絶縁層 ５８Ｕ、５８Ｄ 導体回路 ５８Ｍ ダミーパターン ６０Ｕ、６０Ｄ バイアホール ７６Ｕ、７６Ｄ 半田バンプ １５０ 層間樹脂絶縁層[Description of Signs] 30 Core substrate 34U, 34D Inner layer copper pattern (inner layer conductor circuit) 35 Non-conductor-formed portion 38 Roughened layer 40 Resin filler 42 Roughened layer 48 Via hole opening 50 Interlayer resin insulating layer 58U, 58D Conductor Circuit 58M Dummy pattern 60U, 60D Via hole 76U, 76D Solder bump 150 Interlayer resin insulation layer
Claims (1)
在させて導体回路を形成して成り、ＩＣチップの搭載さ
れる側の表面に半田パッドが形成され、他の基板に接続
される側の表面に、前記ＩＣチップ搭載側の半田パッド
よりも相対的に大きな半田パッドが形成されたパッケー
ジ基板であって、 前記コア基板のＩＣチップが搭載される側に形成される
導体回路のパターン間に、ダミーパターンを形成したこ
とを特徴とするパッケージ基板。1. A conductor circuit is formed on both surfaces of a core substrate with an interlayer resin insulating layer interposed therebetween. Solder pads are formed on a surface on a side on which an IC chip is mounted, and are connected to another substrate. A package substrate having a solder pad relatively larger than the solder pad on the IC chip mounting side formed on the surface on the side thereof, and a conductive circuit pattern formed on the core board mounting side of the IC chip. A package substrate, wherein a dummy pattern is formed therebetween.
Priority Applications (21)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31268697A JP3126330B2 (en) | 1997-10-29 | 1997-10-29 | Package substrate |
| PCT/JP1998/004350 WO1999021224A1 (en) | 1997-10-17 | 1998-09-28 | Package substrate |
| CN200610101902XA CN1971899B (en) | 1997-10-17 | 1998-09-28 | Package substrate |
| EP07122506A EP1895589A3 (en) | 1997-10-17 | 1998-09-28 | Semiconductor package substrate |
| KR1020007004062A KR100691296B1 (en) | 1997-10-17 | 1998-09-28 | Package substrate |
| CN 200610100699 CN101013685B (en) | 1997-10-17 | 1998-09-28 | Package substrate |
| EP07122509A EP1895587A3 (en) | 1997-10-17 | 1998-09-28 | Semiconductor package substrate |
| EP07122502A EP1895586A3 (en) | 1997-10-17 | 1998-09-28 | Semiconductor package substrate |
| US10/850,584 USRE41242E1 (en) | 1997-10-17 | 1998-09-28 | Package substrate |
| US09/529,597 US6392898B1 (en) | 1997-10-17 | 1998-09-28 | Package substrate |
| CNB988102153A CN1161838C (en) | 1997-10-17 | 1998-09-28 | Package substrate |
| CN 200610094490 CN1909226B (en) | 1997-10-17 | 1998-09-28 | Package substrate |
| EP98944278A EP1030365A4 (en) | 1997-10-17 | 1998-09-28 | Package substrate |
| CNB2004100456190A CN100426491C (en) | 1997-10-17 | 1998-09-28 | Package substrate |
| TW087117123A TW398162B (en) | 1997-10-17 | 1998-10-15 | Package substrate board |
| MYPI98004731A MY128327A (en) | 1997-10-17 | 1998-10-16 | Package board |
| US09/906,078 US6487088B2 (en) | 1997-10-17 | 2001-07-17 | Package substrate |
| US09/905,973 US6490170B2 (en) | 1997-10-17 | 2001-07-17 | Package substrate |
| US09/906,076 US20010054513A1 (en) | 1997-10-17 | 2001-07-17 | Package substrate |
| US09/905,974 US6411519B2 (en) | 1997-10-17 | 2001-07-17 | Package substrate |
| US10/876,287 USRE41051E1 (en) | 1997-10-17 | 2004-06-25 | Package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31268697A JP3126330B2 (en) | 1997-10-29 | 1997-10-29 | Package substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11135676A true JPH11135676A (en) | 1999-05-21 |
| JP3126330B2 JP3126330B2 (en) | 2001-01-22 |
Family
ID=18032212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31268697A Expired - Lifetime JP3126330B2 (en) | 1997-10-17 | 1997-10-29 | Package substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3126330B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012124537A (en) * | 2012-03-26 | 2012-06-28 | Renesas Electronics Corp | Semiconductor device |
| US9661762B2 (en) | 2013-11-05 | 2017-05-23 | Ibiden Co., Ltd. | Printed wiring board |
-
1997
- 1997-10-29 JP JP31268697A patent/JP3126330B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012124537A (en) * | 2012-03-26 | 2012-06-28 | Renesas Electronics Corp | Semiconductor device |
| US9661762B2 (en) | 2013-11-05 | 2017-05-23 | Ibiden Co., Ltd. | Printed wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3126330B2 (en) | 2001-01-22 |
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