JPH1092970A - Substrate module - Google Patents
Substrate moduleInfo
- Publication number
- JPH1092970A JPH1092970A JP8247797A JP24779796A JPH1092970A JP H1092970 A JPH1092970 A JP H1092970A JP 8247797 A JP8247797 A JP 8247797A JP 24779796 A JP24779796 A JP 24779796A JP H1092970 A JPH1092970 A JP H1092970A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- resin
- semiconductor package
- resin injection
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＣＳＰ（Chip Sca
le Package）やベアチップなどを実装する基板モジュー
ルに関する。The present invention relates to a CSP (Chip Sca)
le Package) and a board module on which bare chips are mounted.
【０００２】[0002]
【従来の技術】従来から、ＣＳＰやベアチップのような
半導体パッケージをフリップチップボンディングなどに
より基板に直接接続して基板モジュールを形成する場
合、その接続部を保護するために樹脂による封止を行う
ことが一般的である。2. Description of the Related Art Conventionally, when a semiconductor package such as a CSP or a bare chip is directly connected to a substrate by flip chip bonding or the like to form a substrate module, sealing with a resin is performed to protect the connection portion. Is common.
【０００３】ここで、封止の際には基板上への不要な樹
脂の流出を防ぐ必要がある。そのため、例えば図６の断
面図に示されるように、基板１０１上のパッド１０４と
半導体パッケージ１０２のパッドとを接続するはんだボ
ール１０３による接続部を樹脂１０７で封止する場合に
は、予め基板１０１上に接続部の周囲、具体的には半導
体パッケージ１０２の周囲にダムフレーム１０６と呼ば
れる囲いを設けて樹脂１０７を流し込むようにしてい
た。Here, at the time of sealing, it is necessary to prevent unnecessary outflow of resin onto the substrate. For this reason, as shown in the cross-sectional view of FIG. 6, for example, when the connection portion of the solder ball 103 connecting the pad 104 on the substrate 101 and the pad of the semiconductor package 102 is sealed with the resin 107, the substrate 101 is An enclosure called a dam frame 106 is provided around the connection portion, specifically, around the semiconductor package 102, so that the resin 107 is poured.
【０００４】[0004]
【発明が解決しようとする課題】上述したように、従来
は樹脂による封止を行う場合には半導体パッケージの周
囲を囲むダムフレームを基板上に設けていたため、この
ダムフレームを設置した分だけ基板の面積が増加してし
まうという問題があった。本発明は、樹脂封止に必要な
面積の少ない基板モジュールを提供することを目的とす
る。As described above, conventionally, when sealing with a resin, a dam frame surrounding the periphery of a semiconductor package is provided on a substrate. However, there is a problem that the area increases. An object of the present invention is to provide a board module having a small area required for resin sealing.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
本発明は、半導体パッケージと、半導体パッケージが実
装される凹部を有する基板と、凹部の周辺から連続して
形成される樹脂注入部と、樹脂注入部を介して凹部内に
充填される樹脂とを具備する。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a semiconductor package, a substrate having a concave portion on which the semiconductor package is mounted, a resin injection portion formed continuously from the periphery of the concave portion, Resin filled in the recess through the resin injection portion.
【０００６】このような基板モジュールでは、基板の凹
部に半導体パッケージが埋め込まれるように実装され、
この凹部内に樹脂を充填することにより封止が行われ
る。この場合、樹脂封止に必要な基板面積は、樹脂注入
部のみで従来のようにダムフレームを設ける場合に比べ
て大幅に少なくなる。In such a board module, a semiconductor package is mounted so as to be embedded in a concave portion of the board.
Sealing is performed by filling the concave portion with a resin. In this case, the substrate area required for resin sealing is significantly reduced as compared with a conventional case where a dam frame is provided only at the resin injection portion.
【０００７】凹部に半導体パッケージが埋め込まれるよ
うに実装されることにより、基板からの半導体パッケー
ジの抜け落ち等が少なくなって製造時の歩留りが向上す
る。また、基板モジュール自体も薄くなって高密度実装
が可能となる。By mounting the semiconductor package so as to be embedded in the recess, the semiconductor package is less likely to fall off from the substrate, and the yield in manufacturing is improved. Further, the thickness of the substrate module itself is reduced, and high-density mounting is enabled.
【０００８】さらに、樹脂注入部を介して樹脂を注入し
ているので、凹部に直接樹脂を注入する場合に比べて樹
脂が凹部内に効果的に拡散して封止を確実に行うことが
できる。なお、この樹脂注入部を複数個設けるようにす
れば、例えば各樹脂注入部からの樹脂の注入量等を制御
してさらに効果的に樹脂の充填を行うことができる。Further, since the resin is injected through the resin injection portion, the resin can be more effectively diffused into the recess and the sealing can be reliably performed as compared with the case where the resin is directly injected into the recess. . If a plurality of resin injection portions are provided, for example, the amount of resin injected from each resin injection portion can be controlled to more effectively fill the resin.
【０００９】ここで、本発明では半導体パッケージの底
面には複数の電極が設けられ、凹部の底面部には半導体
パッケージの電極にそれぞれ電気的に接続されるパッド
が設けられ、この複数のパッドは基板の信号層に電気的
に接続されるように構成することができる。この場合、
信号層は基板の内層に設けられて、パッドがスルーホー
ルを介して信号層に電気的に接続されるようにすること
が望ましい。また、本発明では半導体パッケージの底面
に複数の電極が設けられ、凹部の底面には電極にそれぞ
れ電気的に接続する信号層が露出するようにしてもよ
い。Here, in the present invention, a plurality of electrodes are provided on the bottom surface of the semiconductor package, and pads electrically connected to the electrodes of the semiconductor package are provided on the bottom surface of the concave portion, respectively. It can be configured to be electrically connected to the signal layer of the substrate. in this case,
Preferably, the signal layer is provided on an inner layer of the substrate so that the pad is electrically connected to the signal layer via a through hole. In the present invention, a plurality of electrodes may be provided on the bottom surface of the semiconductor package, and signal layers electrically connected to the electrodes may be exposed on the bottom surface of the concave portion.
【００１０】[0010]
（第１の実施形態）図１は、本発明の第１の実施形態に
係る基板モジュールの構成を示す図で、（ａ）はこの基
板モジュールの実装構造を示す断面図、（ｂ）はこの基
板モジュールを半導体パッケージ（半導体チップ）の実
装側から見た図である。(First Embodiment) FIGS. 1A and 1B are diagrams showing a configuration of a board module according to a first embodiment of the present invention, wherein FIG. 1A is a cross-sectional view showing a mounting structure of the board module, and FIG. FIG. 3 is a view of the substrate module as viewed from a mounting side of a semiconductor package (semiconductor chip).
【００１１】基板１は、ガラス・エポキシ樹脂などの絶
縁性基材で形成される。この基板１には半導体パッケー
ジ２が実装される凹部１２が設けられている。凹部１２
は、半導体パッケージ２が実装されたときその半導体パ
ッケージ２の各周辺と自身の各周辺との間隔（以下、隙
間と称する）が１ｍｍ程度になるように形成されること
が望ましい。The substrate 1 is formed of an insulating substrate such as a glass epoxy resin. The substrate 1 is provided with a concave portion 12 in which the semiconductor package 2 is mounted. Recess 12
Is preferably formed such that when the semiconductor package 2 is mounted, an interval (hereinafter, referred to as a gap) between each periphery of the semiconductor package 2 and each periphery thereof is about 1 mm.
【００１２】また、凹部１２は半導体パッケージ２の厚
さと同程度の深さを有することが望ましい。ただし、基
板１の強度低下を防ぐために基板１の厚さの半分以上の
深さにはしないようにすることが好ましい。例えば、基
板１の厚さを１．２８ｍｍ、半導体パッケージ２の厚さ
を０．６ｍｍとすると、凹部１２の厚さは０．６ｍｍ前
後にする。It is desirable that the recess 12 has a depth substantially equal to the thickness of the semiconductor package 2. However, in order to prevent the strength of the substrate 1 from decreasing, it is preferable that the depth is not more than half the thickness of the substrate 1. For example, assuming that the thickness of the substrate 1 is 1.28 mm and the thickness of the semiconductor package 2 is 0.6 mm, the thickness of the recess 12 is about 0.6 mm.
【００１３】樹脂注入部９は、基板１において凹部１２
の周辺から連続するように形成されており、この樹脂注
入部９を介して樹脂６の注入が行われる。この樹脂注入
部９は、注入された樹脂６が基板１と半導体パッケージ
２との各接続部に効果的に拡散するような位置に設けら
れ、その形状は樹脂６の性質、量および樹脂６の注入に
用いるディスペンサの口径等に応じて定められる。The resin injection portion 9 is provided in the substrate 1
The resin 6 is injected through the resin injection portion 9. The resin injection portion 9 is provided at a position where the injected resin 6 is effectively diffused into each connection portion between the substrate 1 and the semiconductor package 2. It is determined according to the diameter of the dispenser used for injection.
【００１４】図１においては、樹脂注入部９は（ａ）の
ように凹部１２と同じ深さで、（ｂ）のように基板１の
表面から見て四角形状の凹部として形成されている。樹
脂注入部９を基板１の表面から見て四角形状に形成する
場合、その縦横の長さを上述した隙間以上の長さにする
と効果的に樹脂６の充填を行うことができる。例えば、
隙間が１ｍｍである場合は、樹脂注入部９を縦横５ｍｍ
程度に形成する。In FIG. 1, the resin injection portion 9 is formed as a concave portion having the same depth as the concave portion 12 as shown in FIG. 1A and a rectangular shape as viewed from the surface of the substrate 1 as shown in FIG. When the resin injection portion 9 is formed in a rectangular shape when viewed from the surface of the substrate 1, the resin 6 can be effectively filled by setting the length and width of the resin injection portion 9 to be equal to or greater than the above-described gap. For example,
When the gap is 1 mm, the resin injection part 9 is
Formed to the extent.
【００１５】凹部１２の底面部には、半導体パッケージ
２の底面に設けられている図示されていない複数の電極
に対応させて複数のパッド４が形成されている。これら
複数のパッド４は、それぞれスルーホール５を介して基
板１の裏面の複数のパッド７に電気的に接続されてい
る。基板１の裏面には複数のパッド７および所定の配線
パターン８による信号層が形成されている。A plurality of pads 4 are formed on the bottom surface of the recess 12 so as to correspond to a plurality of electrodes (not shown) provided on the bottom surface of the semiconductor package 2. The plurality of pads 4 are electrically connected to the plurality of pads 7 on the back surface of the substrate 1 through the through holes 5, respectively. A signal layer including a plurality of pads 7 and a predetermined wiring pattern 8 is formed on the back surface of the substrate 1.
【００１６】半導体パッケージ２は、マイクロプロセッ
サやメモリなど所定の機能を有するＣＳＰやベアチップ
などであり、底面には図示されていない複数の電極が設
けられている。The semiconductor package 2 is a CSP or a bare chip having a predetermined function such as a microprocessor or a memory, and has a plurality of electrodes (not shown) provided on a bottom surface.
【００１７】基板１に半導体パッケージ２を実装する場
合、半導体パッケージ２の複数の電極と凹部１２の底面
部の複数のパッド４とをはんだボール３を介してそれぞ
れ電気的に接続する。When the semiconductor package 2 is mounted on the substrate 1, a plurality of electrodes of the semiconductor package 2 are electrically connected to a plurality of pads 4 on the bottom of the recess 12 via the solder balls 3.
【００１８】具体的には、半導体パッケージ２の各電極
にはんだボール３を形成し、凹部１２における各パッド
４にフラックスを塗り、対応する各はんだボール３と各
パッド４を接触させてリフローで加熱することで接続を
行う。Specifically, solder balls 3 are formed on the respective electrodes of the semiconductor package 2, a flux is applied to the respective pads 4 in the concave portions 12, the corresponding respective solder balls 3 and the respective pads 4 are brought into contact with each other, and heated by reflow. To make a connection.
【００１９】このように基板１に半導体パッケージ２を
実装した後、適当なディスペンサを用いてエポキシなど
の樹脂６を樹脂注入部９を介して注入し、凹部１２内に
樹脂６を充填させることにより基板１と半導体パッケー
ジ２との接続部を封止する。After the semiconductor package 2 is mounted on the substrate 1 as described above, a resin 6 such as epoxy is injected through a resin injection portion 9 using an appropriate dispenser, and the resin 6 is filled in the concave portion 12. The connection between the substrate 1 and the semiconductor package 2 is sealed.
【００２０】以上述べたように、この基板モジュールは
基板１に凹部１２を形成しておき、この凹部１２に半導
体パッケージ２を実装したあと樹脂６を充填することに
より封止を行う。従って、樹脂封止に必要とされる基板
１の面積は、樹脂注入部９のみで従来のようにダムフレ
ームを用いる場合に比べてはるかに少なくなる。As described above, in this substrate module, the concave portion 12 is formed in the substrate 1, the semiconductor package 2 is mounted in the concave portion 12, and then the resin 6 is filled to perform sealing. Therefore, the area of the substrate 1 required for resin sealing is much smaller than that of a conventional case using a dam frame with only the resin injection portion 9.
【００２１】また、半導体パッケージ２が凹部１２に埋
め込まれるように実装されるので、外部からの衝撃に対
して確実に保護され、保護基板１からの半導体パッケー
ジ２の抜け落ち等が少なくなって製造時の歩留りが向上
する。また、半導体パッケージ２が埋め込めれた分だけ
基板モジュール自体も薄くなって高密度実装が可能にな
るため、この基板モジュールを搭載する電子機器等を小
型化することができるようになる。Further, since the semiconductor package 2 is mounted so as to be embedded in the concave portion 12, the semiconductor package 2 is reliably protected against external impact, and the semiconductor package 2 is less likely to fall out of the protective substrate 1 and is manufactured. Yield is improved. Further, the substrate module itself is thinned by the amount in which the semiconductor package 2 is embedded, and high-density mounting can be performed. Therefore, the size of an electronic device or the like on which the substrate module is mounted can be reduced.
【００２２】さらに、樹脂注入部９を介して樹脂６を注
入しているため、樹脂６が凹部１２内に効果的に拡散
し、接続部の隅々まで樹脂６が行き渡るので封止を確実
に行うことができる。Further, since the resin 6 is injected through the resin injection portion 9, the resin 6 is effectively diffused into the concave portion 12, and the resin 6 spreads to every corner of the connection portion, so that the sealing is reliably performed. It can be carried out.
【００２３】ところで、上記実施形態では樹脂注入部９
が一つの場合について説明したが、凹部１２の周辺に複
数個設けるようにしてもよい。図２に示されるように、
凹部１２の周辺を構成する４辺に樹脂注入部１０ａ〜１
０ｄを設けた場合、基板１と半導体パッケージ２との接
続部に応じて各樹脂注入部１０ａ〜１０ｄの樹脂注入量
等を制御して、より効果的に樹脂６の充填を行うことが
できる。また、樹脂注入部９の形状および設置位置は任
意であり、例えば図３に示されるように基板１の表面か
ら見て円形状の樹脂注入部１１ａ〜１１ｄを凹部１２の
周辺の頂点にそれぞれ設けるようにしてもよい。この
他、樹脂注入部９の設置位置、形状および数は必要に応
じて適当に変えることができる。なお、図２および図３
はそれぞれ基板モジュールを半導体パッケージの実装側
から見た図である。In the above embodiment, the resin injection portion 9
Has been described, but a plurality may be provided around the recess 12. As shown in FIG.
The resin injection portions 10a to 10a-1
When 0d is provided, the amount of resin injected into each of the resin injection sections 10a to 10d can be controlled in accordance with the connection between the substrate 1 and the semiconductor package 2, so that the resin 6 can be more effectively filled. The shape and installation position of the resin injection portion 9 are arbitrary. For example, as shown in FIG. 3, circular resin injection portions 11a to 11d as viewed from the surface of the substrate 1 are provided at vertexes around the concave portion 12, respectively. You may do so. In addition, the installation position, the shape, and the number of the resin injection section 9 can be appropriately changed as needed. 2 and 3
FIG. 3 is a view of each of the board modules as viewed from the mounting side of the semiconductor package.
【００２４】次に、本発明の他の実施形態について説明
するが、以下では図１と相対応する部分に同一符号を付
して、第１の実施形態との相違点を中心として説明す
る。 （第２の実施形態）図４は、本発明の第２の実施形態に
係る基板モジュールの実装構造を示す図である。本実施
形態は基板の内層に信号層を形成するようにしたもので
ある。Next, another embodiment of the present invention will be described. In the following, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and the description will focus on differences from the first embodiment. (Second Embodiment) FIG. 4 is a view showing a mounting structure of a board module according to a second embodiment of the present invention. In this embodiment, a signal layer is formed on an inner layer of a substrate.
【００２５】具体的には、絶縁性材料で形成された適当
な厚さを有する基板本体３１の表面にパッド７および配
線パターン８による信号層を形成し、この基板本体３１
上に適当な絶縁性材料で絶縁層３２を設けることにより
内層に信号層を有する基板を形成する。More specifically, a signal layer including pads 7 and wiring patterns 8 is formed on the surface of a substrate body 31 having an appropriate thickness and formed of an insulating material.
By providing the insulating layer 32 with an appropriate insulating material thereon, a substrate having a signal layer as an inner layer is formed.
【００２６】絶縁層３２には、第１の実施形態と同様の
凹部１２およびパッド４が設けられており、この凹部１
２の底面部におけるパッド４と基板の内層におけるパッ
ド７とがスルーホール５を介して電気的に接続される。The insulating layer 32 is provided with the same concave portions 12 and pads 4 as in the first embodiment.
The pad 4 on the bottom surface of the substrate 2 and the pad 7 on the inner layer of the substrate are electrically connected through the through hole 5.
【００２７】このように半導体パッケージ２を凹部１２
に実装した後は、第１の実施形態と同様に樹脂注入部９
を介して樹脂６を凹部１２内に充填することで接続部の
封止を行う。As described above, the semiconductor package 2 is
After that, the resin injection portion 9 is mounted similarly to the first embodiment.
The connection portion is sealed by filling the concave portion 12 with the resin 6 via.
【００２８】このようにして、信号層が基板の内層に設
けられた基板モジュールが得られる。この場合、信号層
が設けられた基板本体３１上に絶縁層３２をさらに設け
ることにより凹部１２を形成しているので、第１の実施
形態のように基板に直接凹部１２を形成する場合に比べ
て製造が容易である。Thus, a substrate module having the signal layer provided in the inner layer of the substrate is obtained. In this case, since the concave portion 12 is formed by further providing the insulating layer 32 on the substrate main body 31 provided with the signal layer, compared with the case where the concave portion 12 is formed directly on the substrate as in the first embodiment. And easy to manufacture.
【００２９】（第３の実施形態）図５は、本発明の第３
の実施形態に係る基板モジュールの構成を示す図で、
（ａ）はこの基板モジュールの実装構造を示す断面図、
（ｂ）はこの基板モジュールを半導体パッケージの実装
側から見た図である。(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of a substrate module according to the embodiment.
(A) is a sectional view showing a mounting structure of the board module,
FIG. 2B is a view of the substrate module as viewed from a mounting side of the semiconductor package.
【００３０】本実施形態は、信号層が凹部の底面に露出
するようにしたものである。具体的には、まず図１で示
した基板１よりも薄い、例えば０．６ｍｍ程度の厚さの
基板本体２１の表面に配線パターン２３および複数のパ
ッド２４を設けて信号層を形成する。In this embodiment, the signal layer is exposed at the bottom of the concave portion. Specifically, first, a signal layer is formed by providing a wiring pattern 23 and a plurality of pads 24 on the surface of a substrate body 21 which is thinner than the substrate 1 shown in FIG. 1, for example, about 0.6 mm thick.
【００３１】次に、この基板本体２１の上に適当な絶縁
性材料によって絶縁層２２を設け、これら基板本体２１
および絶縁層２２によって第１の実施形態と同様の形状
を有する凹部２５および樹脂注入部２６が形成されるよ
うにする。Next, an insulating layer 22 made of an appropriate insulating material is provided on the substrate main body 21.
In addition, the concave portion 25 and the resin injection portion 26 having the same shape as in the first embodiment are formed by the insulating layer 22.
【００３２】なお、本実施形態の基板モジュールの厚さ
は、基板本体２１と絶縁層２２とを合わせた厚さである
ことから、絶縁層２２は基板本体２１と合わせて十分な
強度が確保される程度の厚さ、例えば０．６ｍｍ程度に
する。Since the thickness of the substrate module of the present embodiment is the thickness of the substrate main body 21 and the insulating layer 22, the insulating layer 22 has sufficient strength in combination with the substrate main body 21. Thickness, for example, about 0.6 mm.
【００３３】以下は、第１の実施形態と同様に半導体パ
ッケージ２の各電極と基板本体２１上の各パッド２４と
を複数のはんだボール３で接続することにより半導体パ
ッケージ２を実装し、樹脂注入部２６を介して樹脂６を
注入して接続部の封止を行う。Hereinafter, the semiconductor package 2 is mounted by connecting each electrode of the semiconductor package 2 and each pad 24 on the substrate body 21 with a plurality of solder balls 3 in the same manner as in the first embodiment. The connection portion is sealed by injecting the resin 6 through the portion 26.
【００３４】このようにして、凹部２５の底面に信号層
が露出した基板モジュールが得られる。この場合、第１
および第２の実施形態のように基板にスルーホールを設
ける必要がないので構造が簡単になり、製造コストを低
下させることができる。In this way, a substrate module in which the signal layer is exposed at the bottom of the recess 25 is obtained. In this case, the first
Since there is no need to provide a through hole in the substrate as in the second embodiment, the structure is simplified, and the manufacturing cost can be reduced.
【００３５】[0035]
【発明の効果】以上説明したように本発明によれば、凹
部に樹脂を充填することで封止が行われるので、従来の
ようにダムフレームを用いる場合に比べて樹脂封止に必
要とされる基板面積が少なくなる。As described above, according to the present invention, the sealing is performed by filling the concave portion with the resin, so that the resin sealing is required as compared with the conventional case using the dam frame. Substrate area is reduced.
【００３６】また、凹部に半導体パッケージが埋め込ま
れるように実装されるため、高密度実装が可能になると
共に、基板からの半導体パッケージの抜け落ち等が少な
くなって製造時の歩留りが向上する。さらに、樹脂注入
部を介して樹脂を充填しているので、樹脂が凹部に効果
的に拡散して封止を確実に行うことができる。Further, since the semiconductor package is mounted so as to be embedded in the concave portion, high-density mounting is possible, and at the same time, the semiconductor package is less likely to fall off from the substrate, thereby improving the production yield. Further, since the resin is filled through the resin injection portion, the resin can be effectively diffused into the concave portions and the sealing can be reliably performed.
【図１】本発明の第１の実施形態に係る基板モジュール
の構成を示す図FIG. 1 is a diagram showing a configuration of a board module according to a first embodiment of the present invention.
【図２】図１中の樹脂注入部の別の例を示す図FIG. 2 is a diagram showing another example of the resin injection unit in FIG.
【図３】図１中の樹脂注入部のさらに別の例を示す図FIG. 3 is a diagram showing still another example of the resin injection unit in FIG.
【図４】本発明の第２の実施形態に係る基板モジュール
の実装構造を示す断面図FIG. 4 is a cross-sectional view illustrating a mounting structure of a board module according to a second embodiment of the present invention.
【図５】本発明の第３の実施形態に係る基板モジュール
の構成を示す図FIG. 5 is a diagram showing a configuration of a board module according to a third embodiment of the present invention.
【図６】従来の基板モジュールの構成を示す図FIG. 6 is a diagram showing a configuration of a conventional board module.
１…基板 ２…半導体パッケージ ３…はんだボール ４…パッド ５…スルーホール ６…樹脂 ７…パッド ８…配線パターン ９…樹脂注入部 １０ａ〜１０ｄ…樹脂注入部 １１ａ〜１１ｄ…樹脂注入部 １２…凹部 ２１…基板本体 ２２…絶縁層 ２３…配線パターン ２４…パッド ２５…凹部 ２６…樹脂注入部 ３１…基板本体 ３２…絶縁層 １０１…基板 １０２…半導体パッケージ １０３…はんだボール １０４…パッド １０５…配線パターン １０６…ダムフレーム １０７…樹脂 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Semiconductor package 3 ... Solder ball 4 ... Pad 5 ... Through hole 6 ... Resin 7 ... Pad 8 ... Wiring pattern 9 ... Resin injection part 10a-10d ... Resin injection part 11a-11d ... Resin injection part 12 ... Concave part DESCRIPTION OF SYMBOLS 21 ... Board main body 22 ... Insulating layer 23 ... Wiring pattern 24 ... Pad 25 ... Concave part 26 ... Resin injection part 31 ... Board main body 32 ... Insulating layer 101 ... Substrate 102 ... Semiconductor package 103 ... Solder ball 104 ... Pad 105 ... Wiring pattern 106 ... dam frame 107 ... resin
Claims (5)
と、 前記凹部の周辺から連続して形成される樹脂注入部と、 前記樹脂注入部を介して前記凹部内に充填される樹脂と
を具備することを特徴とする基板モジュール。1. A semiconductor package, a substrate having a concave portion on which the semiconductor package is mounted, a resin injection portion formed continuously from the periphery of the concave portion, and filling the concave portion through the resin injection portion. And a resin to be used.
特徴とする請求項１記載の基板モジュール。2. The substrate module according to claim 1, wherein a plurality of the resin injection portions are provided.
極が設けられ、前記凹部の底面部には前記半導体パッケ
ージの電極にそれぞれ電気的に接続されるパッドが設け
られ、この複数のパッドは前記基板の信号層に電気的に
接続されることを特徴とする請求項２記載の基板モジュ
ール。3. A plurality of electrodes are provided on a bottom surface of the semiconductor package, and pads electrically connected to electrodes of the semiconductor package are provided on a bottom surface of the recess, respectively. 3. The board module according to claim 2, wherein the board module is electrically connected to a signal layer of the board.
前記パッドはスルーホールを介して前記信号層に電気的
に接続されることを特徴とする請求項３記載の基板モジ
ュール。4. The signal layer is provided on an inner layer of the substrate,
The board module according to claim 3, wherein the pad is electrically connected to the signal layer via a through hole.
極が設けられ、前記凹部の底面には前記電極にそれぞれ
電気的に接続する信号層が露出していることを特徴とす
る請求項２記載の基板モジュール。5. The semiconductor package according to claim 2, wherein a plurality of electrodes are provided on a bottom surface of the semiconductor package, and signal layers electrically connected to the electrodes are exposed on a bottom surface of the concave portion. Board module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8247797A JPH1092970A (en) | 1996-09-19 | 1996-09-19 | Substrate module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8247797A JPH1092970A (en) | 1996-09-19 | 1996-09-19 | Substrate module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1092970A true JPH1092970A (en) | 1998-04-10 |
Family
ID=17168804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8247797A Pending JPH1092970A (en) | 1996-09-19 | 1996-09-19 | Substrate module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1092970A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002078078A3 (en) * | 2001-03-26 | 2003-12-18 | Intel Corp | Dispensing process for fabrication of microelectronic packages |
| JP2006100459A (en) * | 2004-09-29 | 2006-04-13 | Mitsumi Electric Co Ltd | Electronic circuit modular component and its manufacturing method |
| US7078788B2 (en) | 2000-08-16 | 2006-07-18 | Intel Corporation | Microelectronic substrates with integrated devices |
| EP2003748A1 (en) * | 2007-06-12 | 2008-12-17 | Funai Electric Co., Ltd. | Laser diode attachment holder |
| WO2014045139A1 (en) * | 2012-09-18 | 2014-03-27 | Assa Abloy Ab | Method of protecting an electrical component in a laminate |
-
1996
- 1996-09-19 JP JP8247797A patent/JPH1092970A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7078788B2 (en) | 2000-08-16 | 2006-07-18 | Intel Corporation | Microelectronic substrates with integrated devices |
| WO2002078078A3 (en) * | 2001-03-26 | 2003-12-18 | Intel Corp | Dispensing process for fabrication of microelectronic packages |
| US6706553B2 (en) | 2001-03-26 | 2004-03-16 | Intel Corporation | Dispensing process for fabrication of microelectronic packages |
| JP2006100459A (en) * | 2004-09-29 | 2006-04-13 | Mitsumi Electric Co Ltd | Electronic circuit modular component and its manufacturing method |
| JP4543316B2 (en) * | 2004-09-29 | 2010-09-15 | ミツミ電機株式会社 | Electronic circuit module component and manufacturing method thereof |
| EP2003748A1 (en) * | 2007-06-12 | 2008-12-17 | Funai Electric Co., Ltd. | Laser diode attachment holder |
| WO2014045139A1 (en) * | 2012-09-18 | 2014-03-27 | Assa Abloy Ab | Method of protecting an electrical component in a laminate |
| US9358722B2 (en) | 2012-09-18 | 2016-06-07 | Assa Abloy Ab | Method of protecting an electrical component in a laminate |
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