JPH1050747A - Substrate wiring structure - Google Patents

Substrate wiring structure

Info

Publication number
JPH1050747A
JPH1050747A JP8198621A JP19862196A JPH1050747A JP H1050747 A JPH1050747 A JP H1050747A JP 8198621 A JP8198621 A JP 8198621A JP 19862196 A JP19862196 A JP 19862196A JP H1050747 A JPH1050747 A JP H1050747A
Authority
JP
Japan
Prior art keywords
wiring layer
pad
substrate
connection tape
tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8198621A
Other languages
Japanese (ja)
Inventor
Yasuo Otsuki
康雄 大槻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP8198621A priority Critical patent/JPH1050747A/en
Publication of JPH1050747A publication Critical patent/JPH1050747A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a substrate wiring structure allowing the substrate size to be reduced by improving the mounting efficiency. SOLUTION: A first connecting tape 24 is provided on the periphery of a bare chip 21 to cover signal wire bonding pads 22 and both ends are connected to a substrate surface with a mid part floated up from this surface. A second conductive connecting tape 27 is provided near the first tape 24 with both ends connected to the substrate surface but the middle floated up therefrom. Vias connected to a first wiring layer are connected to both ends of the first tape 24 and vias connected to a second wiring layer are connected to both ends of the second tape. First and second pads of a bare chip 21 are wire-bonded to the first and second tapes 24 and 27. The first wiring layer is either a ground or power wiring layer and the second wiring layer is the other.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ベアチップを実装
してなる基板の配線構造に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a wiring structure of a substrate on which a bare chip is mounted.

【０００２】[0002]

【従来の技術】従来、この種の基板配線構造として、例
えば図２（ａ）、（ｂ）に示すものが知られている。図
２（ａ）において符号１は基板であり、この基板１上に
は、狭パッドピッチのベアチップ２が一つ、フェースア
ップ実装されている。なお、図２（ａ）では、一点鎖線
の左右で異なる位置の断面を示しており、したがって図
２（ａ）上では左右が非対称になっているものの、実際
には左右が略対称な構造となっている。2. Description of the Related Art Conventionally, as this type of substrate wiring structure, for example, the structure shown in FIGS. 2A and 2B is known. In FIG. 2A, reference numeral 1 denotes a substrate, on which one bare chip 2 having a narrow pad pitch is face-up mounted. FIG. 2A shows cross sections at different positions on the left and right of the dashed-dotted line. Therefore, although the left and right are asymmetric in FIG. Has become.

【０００３】ベアチップ２には、その上面にベアチップ
信号パッドＳ、ベアチップグランドパッド（以下、ベア
チップＧＮＤパッドと略称する）Ｇ、ベアチップ電源パ
ッドＶが、図２（ｂ）に示すようにＳ、Ｇ、Ｓ、Ｖ…の
順に配列されている。ベアチップ２の周辺部には、信号
用ワイヤボンディングパッド（以下、信号用Ｗ／Ｂパッ
ドと略称する）３ｓ、グランド用ワイヤボンディングパ
ッド（以下、ＧＮＤ用Ｗ／Ｂパッドと略称する）３ｇ、
電源用ワイヤボンディングパッド（以下、電源用Ｗ／Ｂ
パッドと略称する）３ｖがそれぞれ基板１上に形成され
ており、これらには、それぞれ対応する前記パッドＳ、
Ｇ、Ｖとの間でワイヤボンディングがなされている。The bare chip 2 has a bare chip signal pad S, a bare chip ground pad (hereinafter simply referred to as a bare chip GND pad) G, and a bare chip power supply pad V on its upper surface, as shown in FIG. Are arranged in the order of S, V... At the periphery of the bare chip 2, signal wire bonding pads (hereinafter abbreviated as signal W / B pads) 3s, ground wire bonding pads (hereinafter abbreviated as W / B pads for GND) 3g,
Power supply wire bonding pad (W / B for power supply)
3v are respectively formed on the substrate 1, and these are respectively provided with the corresponding pads S,
Wire bonding is performed between G and V.

【０００４】これら信号用Ｗ／Ｂパッド３ｓ、ＧＮＤ用
Ｗ／Ｂパッド３ｇ、電源用Ｗ／Ｂパッド３ｖは、図２
（ｂ）に示したように、信号用Ｗ／Ｂパッド３ｓ…がベ
アチップ２近傍に配置され、ＧＮＤ用Ｗ／Ｂパッド３ｇ
…、電源用Ｗ／Ｂパッド３ｖ…が信号用Ｗ／Ｂパッド３
ｓに対してベアチップ２と反対の側に配置されたものと
なっている。また、これらは千鳥状に配置されており、
これによって各パッド間のピッチが小さく抑えられてい
る。The signal W / B pad 3s, GND W / B pad 3g, and power supply W / B pad 3v are shown in FIG.
As shown in (b), the signal W / B pads 3s are arranged near the bare chip 2 and the GND W / B pads 3g.
, W / B pad 3v for power supply is W / B pad 3 for signal
s is arranged on the side opposite to the bare chip 2. These are arranged in a staggered pattern,
This keeps the pitch between the pads small.

【０００５】これら信号用Ｗ／Ｂパッド３ｓ、ＧＮＤ用
Ｗ／Ｂパッド３ｇ、電源用Ｗ／Ｂパッド３ｖは、図２
（ａ）に示したようにそれぞれ各配線４ｓ（４ｇ、４
ｖ）を介して各ビア（ＶＩＡ）５ｓ（５ｇ、５ｖ）に接
続されている。各ビア５ｓ（５ｇ、５ｖ）は、それぞれ
対応する配線層、すなわち信号配線層６ｓ、グランド配
線層（以下、ＧＮＤ配線層と略称する）６ｇ、電源配線
層６ｖのいずれかに接続されている。そして、このよう
な構成によりベアチップ信号用パッドＳはワイヤ（図示
略）、信号用Ｗ／Ｂパッド３ｓ、配線４ｓ、ビア５ｓを
介して信号配線層６ｓに接続され、ベアチップＧＮＤ用
パッドＧはワイヤ（図示略）、ＧＮＤ用Ｗ／Ｂパッド３
ｇ、配線４ｇ、ビア５ｇを介してＧＮＤ配線層６ｇに接
続され、ベアチップ電源用パッドＶはワイヤ（図示
略）、電源用Ｗ／Ｂパッド３ｖは配線４ｖ、ビア５ｖを
介して電源配線層６ｖに接続されている。The signal W / B pad 3s, the GND W / B pad 3g, and the power supply W / B pad 3v are shown in FIG.
As shown in (a), each wiring 4s (4g, 4g
v) are connected to each via (VIA) 5s (5g, 5v). Each via 5s (5g, 5v) is connected to a corresponding wiring layer, that is, one of a signal wiring layer 6s, a ground wiring layer (hereinafter abbreviated as a GND wiring layer) 6g, and a power supply wiring layer 6v. With such a configuration, the bare chip signal pad S is connected to the signal wiring layer 6s through a wire (not shown), the signal W / B pad 3s, the wiring 4s, and the via 5s, and the bare chip GND pad G is connected to the wire. (Not shown), GND W / B pad 3
g, wiring 4g, and via 5g to GND wiring layer 6g, bare chip power supply pad V is a wire (not shown), power supply W / B pad 3v is wiring 4v, and power supply wiring layer 6v is via via 5v. It is connected to the.

【０００６】また、これら信号配線層６ｓ、ＧＮＤ配線
層６ｇ、電源配線層６ｖには、別のビア７ｓ（７ｇ、７
ｖ）を介してＩ／Ｏパッド８が接続され、Ｉ／Ｏパッド
８にはＩ／Ｏリード９が接続されている。また、ＧＮＤ
用Ｗ／Ｂパッド３ｇ、電源用Ｗ／Ｂパッド３ｖの側方に
は、基板１表層部に形成されたコンデンサパッド１０を
介してコンデンサ１１が配設されている。The signal wiring layer 6s, the GND wiring layer 6g, and the power supply wiring layer 6v have separate vias 7s (7g, 7g).
An I / O pad 8 is connected via v), and an I / O lead 9 is connected to the I / O pad 8. Also, GND
A capacitor 11 is disposed on the side of the power W / B pad 3g and the power supply W / B pad 3v via a capacitor pad 10 formed on the surface layer of the substrate 1.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、前記配
線構造では、図２（ｂ）に示したようにＧＮＤ用のビア
５ｇおよび電源用のビア５ｖを、ベアチップ２の周辺、
すなわち信号用の配線４ｓに接続するビア５ｓの近傍に
配置していることから、各ビア５ｓ、５ｇ、５ｖ間のピ
ッチ、およびこれに接続する各配線４ｓ、４ｇ、４ｖ間
のピッチを確保するため、各配線層６ｓ、６ｇ、６ｖに
接続するまでの各配線４ｓ、４ｇ、４ｖの長さがそれぞ
れ長くなってしまう。したがって、このように各配線４
ｓ、４ｇ、４ｖの長さが長くなってしまうことから、フ
ットプリントが増加し、これにより基板サイズが大きく
なってしまう。However, in the wiring structure, as shown in FIG. 2B, the via 5g for the GND and the via 5v for the power supply are connected to the periphery of the bare chip 2,
That is, the pitch between the vias 5s, 5g, and 5v, and the pitch between the wirings 4s, 4g, and 4v connected to the vias 5s, 5g, and 5v are ensured because they are arranged near the via 5s connected to the signal wiring 4s. Therefore, the length of each of the wirings 4s, 4g, and 4v before connecting to each of the wiring layers 6s, 6g, and 6v increases. Therefore, each wiring 4
Since the lengths of s, 4g, and 4v become longer, the footprint increases, thereby increasing the substrate size.

【０００８】本発明は前記事情に鑑みてなされたもの
で、その目的とするところは、実装効率を向上し、これ
により基板サイズの小型化を可能にした基板配線構造を
提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a substrate wiring structure which can improve mounting efficiency and thereby reduce the size of a substrate.

【０００９】[0009]

【課題を解決するための手段】本発明の基板配線構造で
は、ベアチップの周辺部における基板表層部に信号用ワ
イヤボンディングパッドを配設し、該信号用ワイヤボン
ディングパッドの少なくとも一部を覆って導電性の第１
の接続用テープを配置し、かつ該第１の接続用テープ
を、その両端部が基板面に接続するとともにその中間部
が基板面の上方に浮いた状態となるようにして設け、該
第１の接続用テープの前記ベアチップと反対の側に、該
第１の接続用テープに近接して導電性の第２の接続用テ
ープを配設し、かつ該第２の接続用テープを、その両端
部が基板面に接続するとともにその中間部が基板面の上
方に浮いた状態となるようにして設け、前記第１の接続
用テープの基板面に接続した両端部に、第１の配線層に
接続したビアを接続するとともに、前記第２の接続用テ
ープの基板面に接続した両端部に、第２の配線層に接続
したビアを接続し、前記ベアチップに形成された第１の
パッドと前記第１の接続用テープとをワイヤボンディン
グするとともに、第２のパッドと前記第２の接続用テー
プとをワイヤボンディングしてなり、前記第１の配線層
を、グランド配線層と電源配線層とのうちの一方とし、
かつ前記第２の配線層を、グランド配線層と電源配線層
とのうちの他方とするとともに、前記第１のパッドを第
１の配線層に対応するパッドとし、かつ前記第２のパッ
ドを第２の配線層に対応するパッドとしたことを前記課
題の解決手段とした。According to the substrate wiring structure of the present invention, a signal wire bonding pad is provided on a surface layer of a substrate around a bare chip, and at least a part of the signal wire bonding pad is covered with a conductive material. Sex First
And the first connecting tape is provided such that both ends thereof are connected to the substrate surface and the intermediate portion thereof is floated above the substrate surface. A conductive second connection tape is disposed adjacent to the first connection tape on the side of the connection tape opposite to the bare chip, and the second connection tape is connected to both ends thereof. The first connection tape is connected to the substrate surface and the intermediate portion is provided above the substrate surface so as to be floated. The connected vias are connected, and vias connected to a second wiring layer are connected to both ends connected to the substrate surface of the second connection tape, and the first pad formed on the bare chip is connected to the first pad. While wire bonding with the first connection tape, The the pad and the second connecting tape becomes to wire bonding, the first wiring layer, and one of a ground wiring layer and the power supply wiring layer,
And the second wiring layer is the other of a ground wiring layer and a power supply wiring layer, the first pad is a pad corresponding to the first wiring layer, and the second pad is a second wiring layer. A pad corresponding to the second wiring layer is a means for solving the above problem.

【００１０】この基板配線構造によれば、ビアを介して
第１の配線層に接続した第１の接続用テープと、ベアチ
ップに形成された第１のパッドとをワイヤボンディング
したので、第１の配線層と第１のパッドとが導通したも
のとなり、同様に、ビアを介して第２の配線層に接続し
た第２の接続用テープと、ベアチップに形成された第２
のパッドとをワイヤボンディングしたので、第２の配線
層と第２のパッドとが導通したものとなる。そして、第
１の配線層と第２の配線層とを、その一方をグランド配
線層とし、他方を電源配線層としたので、前記第１の接
続用テープ、第２の接続用テープが従来のＧＮＤ用Ｗ／
Ｂパッド、電源用Ｗ／Ｂパッドとして機能するととも
に、ＧＮＤ用配線、電源用配線としても機能するものと
なる。According to this substrate wiring structure, the first connection tape connected to the first wiring layer via the via and the first pad formed on the bare chip are wire-bonded. The wiring layer and the first pad are electrically connected, and similarly, the second connection tape connected to the second wiring layer via the via, and the second connection tape formed on the bare chip.
Since the second pad is wire-bonded, the second wiring layer and the second pad are electrically connected. Since the first wiring layer and the second wiring layer have one of them as a ground wiring layer and the other as a power supply wiring layer, the first connection tape and the second connection tape are conventional. W / for GND
It functions as a B pad and a power supply W / B pad, and also functions as a GND wiring and a power supply wiring.

【００１１】したがって、第１の接続用テープ、第２の
接続用テープが、その中間部が基板より浮かした状態で
設けられているので、基板上に形成されるフットプリン
トが実質的に縮小されるとともに、第１の接続用テー
プ、第２の接続用テープの両端部位置にビアを配したの
で、これらグランド用のビア、電源用のビアと信号用の
ビアとが互いに干渉することがなくなり、信号用の配線
やビアについても第１接続用テープや第２の接続用テー
プの下方に配置することが可能になる。Therefore, the first connection tape and the second connection tape are provided in a state where the intermediate portions thereof are floating above the substrate, so that the footprint formed on the substrate is substantially reduced. In addition, vias are provided at both ends of the first connection tape and the second connection tape, so that the ground via, the power supply via, and the signal via do not interfere with each other. Also, it is possible to arrange the signal wirings and vias below the first connection tape and the second connection tape.

【００１２】[0012]

【発明の実施の形態】以下、本発明の基板配線構造をそ
の実施形態例に基づいて詳しく説明する。図１（ａ）、
（ｂ）、（ｃ）は、本発明の基板配線構造の一実施形態
例を示す図であり、これらの図において符号２０は基板
である。この基板２０上には、図２に示した従来例と同
様に、狭パッドピッチのベアチップ２１が一つ、フェー
スアップ実装されている。ベアチップ２１には、その上
面にベアチップ信号パッドＳ、ベアチップＧＮＤパッド
Ｇ、ベアチップ電源パッドＶが、図１（ｂ）に示すよう
にＳ、Ｇ、Ｓ、Ｖ…の順に配列されている。ベアチップ
２１の周辺部には、信号用Ｗ／Ｂパッド２２…がベアチ
ップ２１の側面に沿った状態で基板２０の表層部に配設
されており、これら信号用Ｗ／Ｂパッド２２…と前記ベ
アチップ信号パッドＳ…との間にはそれぞれにワイヤ２
３ｓがボンディングされている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a substrate wiring structure of the present invention will be described in detail based on an embodiment. FIG. 1 (a),
(B), (c) is a figure which shows one Embodiment of the board | substrate wiring structure of this invention, In these figures, the code | symbol 20 is a board | substrate. One bare chip 21 with a narrow pad pitch is face-up mounted on the substrate 20, as in the conventional example shown in FIG. On the upper surface of the bare chip 21, a bare chip signal pad S, a bare chip GND pad G, and a bare chip power supply pad V are arranged in the order of S, G, S, V... As shown in FIG. At the periphery of the bare chip 21, signal W / B pads 22 are arranged on the surface layer of the substrate 20 along the side surface of the bare chip 21. These signal W / B pads 22 and the bare chip Wires 2 are provided between the signal pads S and so on.
3s are bonded.

【００１３】また、ベアチップ２１の周辺部には、信号
用Ｗ／Ｂパッド２２…のそれぞれの一部を覆うようにし
てこれらの上に、ＧＮＤ接続用テープ（第１の接続用テ
ープ）２４が配設されている。このＧＮＤ接続用テープ
２４は、アルミニウム等の金属からなる導電性のもの
で、図１（ｃ）に示すようにその両端部が基板２０の表
面に接続するとともに、その中間部が基板２０面はもち
ろん前記信号用Ｗ／Ｂパッド２２…よりも上方に浮いた
状態となるように、はんだ等によって基板２０面上に取
り付けられたものである。すなわち、このＧＮＤ接続用
テープ２４は、両端部から少し中央側にて折曲されてそ
れぞれが下方に下り、そこからさらにそれぞれが外側に
折曲されて中央部と平行な端部が形成されることによ
り、中央部にコ字状の立ち上がり部を有したものとなっ
ている。On the periphery of the bare chip 21, a GND connection tape (first connection tape) 24 is provided on each of the signal W / B pads 22 so as to cover a part thereof. It is arranged. The GND connection tape 24 is made of a conductive material made of metal such as aluminum, and has both ends connected to the surface of the substrate 20 as shown in FIG. Of course, they are mounted on the surface of the substrate 20 by soldering or the like so as to float above the signal W / B pads 22. In other words, the GND connection tape 24 is bent slightly from the both ends toward the center side, and each of them is lowered, from which each is bent outward to form an end parallel to the center. Thus, a U-shaped rising portion is provided at the center.

【００１４】また、このＧＮＤ接続用テープ２４の、基
板２０に接続する両端部２４ａ、２４ａには、基板２０
中に形成されたＧＮＤ配線層２５ｇ（図１（ａ）参照）
に接続するビア２６ｇが接続されている。さらに、ＧＮ
Ｄ接続用テープ２４と前記ベアチップＧＮＤパッドＧと
の間にはワイヤ２３ｇがボンディングされており、これ
によってベアチップＧＮＤパッドＧは、ワイヤ２３ｇ、
ＧＮＤ接続用テープ２４、ビア２６ｇを介してＧＮＤ配
線層２５ｇに電気的に接続されたものとなっている。Further, both ends 24a of the GND connection tape 24 connected to the substrate 20 are provided with the substrate 20.
25 g of GND wiring layer formed therein (see FIG. 1A)
Is connected to the via 26g. Furthermore, GN
A wire 23g is bonded between the D connecting tape 24 and the bare chip GND pad G, whereby the bare chip GND pad G is connected to the wire 23g,
It is electrically connected to the GND wiring layer 25g via the GND connection tape 24 and the via 26g.

【００１５】ＧＮＤ接続用テープ２４の、前記ベアチッ
プ２１と反対の側には、該ＧＮＤ接続用テープ２４に近
接して電源接続用テープ（第２の接続用テープ）２７が
配設されている。この電源接続用テープ２７は、前記Ｇ
ＮＤ接続用テープ２４と同様にアルミニウム等の金属か
らなる導電性のもので、その両端部が基板２０の表面に
接続するとともに、その中間部が基板２０面より上方に
浮いた状態となるように、はんだ等によって基板２０面
上に取り付けられたものである。On the side of the GND connection tape 24 opposite to the bare chip 21, a power supply connection tape (second connection tape) 27 is disposed close to the GND connection tape 24. This tape 27 for power supply connection is
Like the ND connection tape 24, the conductive tape is made of a metal such as aluminum. Both ends of the tape are connected to the surface of the substrate 20, and the intermediate portion is floated above the surface of the substrate 20. It is mounted on the surface of the substrate 20 by solder, or the like.

【００１６】また、この電源接続用テープ２７の、基板
２０に接続する両端部２７ａ、２７ａには、基板２０中
に形成された電源配線層２５ｖ（図１（ａ）参照）に接
続するビア２６ｖが接続されている。さらに、電源接続
用テープ２７と前記ベアチップ電源パッドＶとの間には
ワイヤ２３ｖがボンディングされており、これによって
ベアチップ電源パッドＶは、ワイヤ２３ｖ、電源接続用
テープ２７、ビア２６ｖを介して電源配線層２５ｖに電
気的に接続されたものとなっている。Further, both ends 27a of the power supply connection tape 27 connected to the substrate 20 are provided with vias 26v connected to a power supply wiring layer 25v formed in the substrate 20 (see FIG. 1A). Is connected. Further, a wire 23v is bonded between the power supply connection tape 27 and the bare chip power supply pad V, so that the bare chip power supply pad V is connected to the power supply wiring via the wire 23v, the power supply connection tape 27, and the via 26v. It is electrically connected to the layer 25v.

【００１７】電源接続用テープ２７の中間部の下方に
は、基板２０中に形成された信号配線層２５ｓ（図１
（ａ）参照）に接続するビア２６ｓ…が、基板２０上に
臨んで配設されている。これらビア２６ｓ…と前記信号
用Ｗ／Ｂパッド２１…とは、対応するもの同士が基板２
０表面に形成された配線２８によって接続されており、
これによってベアチップ信号パッドＳは、ワイヤ２３
ｓ、信号用Ｗ／Ｂパッド２２、ワイヤ２３ｓ、ビア２６
ｓを介して信号配線層２５ｓに電気的に接続されたもの
となっている。Below the intermediate portion of the power supply connecting tape 27, a signal wiring layer 25s formed in the substrate 20 (FIG. 1).
(See (a)) are arranged facing the substrate 20. The vias 26 s and the signal W / B pads 21 correspond to each other on the substrate 2.
0 are connected by a wiring 28 formed on the surface,
As a result, the bare chip signal pad S is connected to the wire 23
s, signal W / B pad 22, wire 23s, via 26
and is electrically connected to the signal wiring layer 25s via the s.

【００１８】また、ＧＮＤ接続用テープ２４と電源接続
用テープ２７との間には、バイパスコンデンサ２９が架
け渡された状態ではんだ等により固定されている。ま
た、信号配線層２５ｓ、ＧＮＤ配線層２５ｇ、電源配線
層２５ｖには、別のビア７ｓ（７ｇ、７ｖ）を介してＩ
／Ｏパッド８が接続され、Ｉ／Ｏパッド８にはＩ／Ｏリ
ード９が接続されている。なお、図１（ｂ）、（ｃ）で
は、ベアチップ２１の一方の側しか図示していないが、
本実施形態例においては、ＧＮＤ接続用テープ２４およ
び電源接続用テープ２７はベアチップ２１の両側に配設
されている。A bypass capacitor 29 is fixed between the GND connection tape 24 and the power supply connection tape 27 with solder or the like in a state of being bridged. Further, the signal wiring layer 25s, the GND wiring layer 25g, and the power supply wiring layer 25v are connected to each other via another via 7s (7g, 7v).
The / O pad 8 is connected, and the I / O pad 9 is connected to the I / O lead 9. Although FIGS. 1B and 1C show only one side of the bare chip 21,
In the embodiment, the GND connection tape 24 and the power supply connection tape 27 are provided on both sides of the bare chip 21.

【００１９】このような構成の基板配線構造にあって
は、ＧＮＤ接続用テープ２４を従来のＧＮＤ用Ｗ／Ｂパ
ッドおよびＧＮＤ用配線として機能させ、また、電源接
続用テープ２７を従来の電源用Ｗ／Ｂパッドおよび電源
用配線として機能させており、しかも、ＧＮＤ接続用テ
ープ２４、電源接続用テープ２７の中間部をそれぞれ基
板２０面より浮かしているので、基板２０上に形成する
フットプリントを実質的に縮小することができる。ま
た、ＧＮＤ接続用テープ２４、電源接続用テープ２７の
両端部位置にビア２６ｇ、２６ｖを配したので、これら
が、ＧＮＤ接続用テープ２４、電源接続用テープ２７の
下に配置した信号用の配線２８やビア２６ｓに干渉する
ことがなくなり、したがって基板２０面の有効利用が可
能になり、実装効率の向上を図ることができる。また、
バイパスコンデンサ２９を基板２０に直接実装せず、Ｇ
ＮＤ接続用テープ２４と電源接続用テープ２７との間に
架け渡したので、実装効率をより一層向上することがで
きる。In the substrate wiring structure having such a structure, the GND connection tape 24 functions as a conventional GND W / B pad and GND wiring, and the power supply connection tape 27 serves as a conventional power supply tape. Since they function as W / B pads and power supply wiring, and the intermediate portions of the GND connection tape 24 and the power supply connection tape 27 are respectively lifted from the surface of the substrate 20, the footprint formed on the substrate 20 can be reduced. It can be substantially reduced. Further, since the vias 26g and 26v are arranged at both end positions of the GND connection tape 24 and the power supply tape 27, these are used for signal wiring arranged below the GND connection tape 24 and the power supply tape 27. Interference with the vias 28 and the vias 26s is eliminated, so that the surface of the substrate 20 can be effectively used, and the mounting efficiency can be improved. Also,
Without mounting the bypass capacitor 29 directly on the substrate 20,
Since it is bridged between the ND connection tape 24 and the power supply connection tape 27, the mounting efficiency can be further improved.

【００２０】なお、前記実施形態例では、ベアチップ２
１を一つ実装した場合について説明したが、本発明はこ
れに限定されることなく、ベアチップを複数実装した場
合にも適用できるのはもちろんである。また、前記実施
形態例では、ベアチップ側に配置する第１の接続用テー
プをＧＮＤ接続用テープ２４とし、これに近接する第２
の接続用テープを電源接続用テープ２７としたが、本発
明では、これらを逆にして第１の接続用テープを電源接
続用テープ２７とし、第２の接続用テープをＧＮＤ接続
用テープ２４としてもよい。In the above embodiment, the bare chip 2
Although the case where one is mounted has been described, the present invention is not limited to this, and it is needless to say that the present invention can be applied to a case where a plurality of bare chips are mounted. In the embodiment, the first connection tape disposed on the bare chip side is the GND connection tape 24, and the second connection tape adjacent thereto is the second connection tape.
In the present invention, the first connecting tape is used as the power connecting tape 27, and the second connecting tape is used as the GND connecting tape 24 in the present invention. Is also good.

【００２１】[0021]

【発明の効果】以上説明したように本発明の基板配線構
造は、第１の接続用テープ、第２の接続用テープを従来
のＧＮＤ用Ｗ／Ｂパッド、電源用Ｗ／Ｂパッドとして機
能させるとともに、ＧＮＤ用配線、電源用配線としても
機能させ、しかも、これら第１の接続用テープ、第２の
接続用テープの中間部をそれぞれ基板面より浮かしたも
のであるから、基板上に形成するフットプリントを実質
的に縮小することができ、これにより実装効率の向上を
図ることができる。また、第１の接続用テープ、第２の
接続用テープの両端部位置にグランド用ビア、電源用ビ
アを配したので、これらが信号用のビアと干渉すること
がなくなり、したがって信号用の配線やビアについても
第１接続用テープや第２の接続用テープの下方に配置す
ることが可能になり、これにより実装効率をより一層高
めることができる。よって、このように実装効率の向上
を可能にすることができることから、基板サイズの小型
化を可能にすることができる。また、コンデンサを基板
に直接実装せず、第１の接続用テープと第２の接続用テ
ープとの間に架け渡すようにすれば、実装効率をより一
層向上することができる。As described above, in the substrate wiring structure of the present invention, the first connection tape and the second connection tape function as conventional W / B pads for GND and W / B pads for power supply. At the same time, they function as GND wiring and power supply wiring. Further, since the intermediate portions of the first connection tape and the second connection tape are respectively raised above the substrate surface, they are formed on the substrate. The footprint can be substantially reduced, thereby improving mounting efficiency. In addition, since the ground via and the power supply via are arranged at both ends of the first connection tape and the second connection tape, they do not interfere with the signal via, and therefore, the signal wiring is provided. Also, the vias can be arranged below the first connection tape and the second connection tape, so that the mounting efficiency can be further improved. Therefore, since the mounting efficiency can be improved as described above, the size of the substrate can be reduced. Further, if the capacitor is not directly mounted on the substrate but is bridged between the first connection tape and the second connection tape, the mounting efficiency can be further improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の基板配線構造の一実施形態例の概略構
成を示す図であり、（ａ）は要部側断面図、（ｂ）は要
部平面図、（ｃ）は要部斜視図である。FIGS. 1A and 1B are diagrams showing a schematic configuration of an embodiment of a substrate wiring structure of the present invention, in which FIG. 1A is a sectional side view of a main part, FIG. FIG.

【図２】従来の基板配線構造の一例の概略構成を示す図
であり、（ａ）は要部側断面図、（ｂ）は要部平面図で
ある。FIGS. 2A and 2B are diagrams showing a schematic configuration of an example of a conventional substrate wiring structure, in which FIG. 2A is a sectional side view of a main part, and FIG.

【符号の説明】[Explanation of symbols]

２０ 基板 ２１ ベアチップ ２２ 信号用ワイヤボンディングパッド（信号用Ｗ／Ｂ
パッド） ２４ ＧＮＤ接続用テープ（第１の接続用テープ） ２５ｇ ＧＮＤ用配線層 ２５ｓ 信号用配線層 ２５ｖ 電源用配線層 ２６ｇ、２６ｓ、２６ｖ ビア ２７ 電源接続用テープ（第２の接続用テープ） ２８ 配線 ２９ バイパスコンデンサReference Signs List 20 substrate 21 bare chip 22 signal wire bonding pad (signal W / B
Pad) 24 GND connection tape (first connection tape) 25 g GND wiring layer 25 s signal wiring layer 25 v power supply wiring layer 26 g, 26 s, 26 v via 27 power supply connection tape (second connection tape) 28 Wiring 29 Bypass capacitor

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 ベアチップを実装してなる基板の配線構
造であって、 前記ベアチップの周辺部における基板表層部に信号用ワ
イヤボンディングパッドを配設し、 該信号用ワイヤボンディングパッドの少なくとも一部を
覆って導電性の第１の接続用テープを配置し、かつ該第
１の接続用テープを、その両端部が基板面に接続すると
ともにその中間部が基板面の上方に浮いた状態となるよ
うにして設け、 該第１の接続用テープの前記ベアチップと反対の側に、
該第１の接続用テープに近接して導電性の第２の接続用
テープを配設し、かつ該第２の接続用テープを、その両
端部が基板面に接続するとともにその中間部が基板面の
上方に浮いた状態となるようにして設け、 前記第１の接続用テープの基板面に接続した両端部に、
第１の配線層に接続したビアを接続するとともに、前記
第２の接続用テープの基板面に接続した両端部に、第２
の配線層に接続したビアを接続し、 前記ベアチップに形成された第１のパッドと前記第１の
接続用テープとをワイヤボンディングするとともに、第
２のパッドと前記第２の接続用テープとをワイヤボンデ
ィングしてなり、 前記第１の配線層を、グランド配線層と電源配線層との
うちの一方とし、かつ前記第２の配線層を、グランド配
線層と電源配線層とのうちの他方とするとともに、前記
第１のパッドを第１の配線層に対応するパッドとし、か
つ前記第２のパッドを第２の配線層に対応するパッドと
したことを特徴とする基板配線構造。1. A wiring structure of a substrate on which a bare chip is mounted, wherein a signal wire bonding pad is disposed on a surface layer of the substrate around the bare chip, and at least a part of the signal wire bonding pad is provided. An electrically conductive first connection tape is arranged to cover the first connection tape, and both ends of the first connection tape are connected to the substrate surface, and an intermediate portion thereof is floated above the substrate surface. Provided on the opposite side of the first connection tape from the bare chip,
A conductive second connection tape is disposed adjacent to the first connection tape, and both ends of the second connection tape are connected to a substrate surface, and an intermediate portion thereof is connected to the substrate. Provided so as to float above the surface, at both ends of the first connection tape connected to the substrate surface,
Vias connected to the first wiring layer are connected, and both ends of the second connection tape connected to the substrate surface are provided with the second connection tape.
The first pad formed on the bare chip is wire-bonded to the first connection tape, and the second pad and the second connection tape are connected to each other. The first wiring layer is formed as one of a ground wiring layer and a power wiring layer, and the second wiring layer is formed as the other of the ground wiring layer and the power wiring layer. Wherein the first pad is a pad corresponding to a first wiring layer, and the second pad is a pad corresponding to a second wiring layer. 【請求項２】 前記第１の接続用テープと第２の接続用
テープとの間にコンデンサを架け渡したことを特徴とす
る請求項１記載の基板配線構造。2. The substrate wiring structure according to claim 1, wherein a capacitor is bridged between said first connecting tape and said second connecting tape.
JP8198621A 1996-07-29 1996-07-29 Substrate wiring structure Pending JPH1050747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8198621A JPH1050747A (en) 1996-07-29 1996-07-29 Substrate wiring structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8198621A JPH1050747A (en) 1996-07-29 1996-07-29 Substrate wiring structure

Publications (1)

Publication Number Publication Date
JPH1050747A true JPH1050747A (en) 1998-02-20

Family

ID=16394250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8198621A Pending JPH1050747A (en) 1996-07-29 1996-07-29 Substrate wiring structure

Country Status (1)

Country Link
JP (1) JPH1050747A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001298039A (en) * 2000-04-12 2001-10-26 Matsushita Electric Ind Co Ltd Semiconductor device
US9823527B2 (en) 2014-02-27 2017-11-21 Mitsubishi Electric Corporation Liquid crystal display

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001298039A (en) * 2000-04-12 2001-10-26 Matsushita Electric Ind Co Ltd Semiconductor device
US9823527B2 (en) 2014-02-27 2017-11-21 Mitsubishi Electric Corporation Liquid crystal display

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