JPH10335823A - Multilayered ceramic circuit board and manufacture thereof - Google Patents
Multilayered ceramic circuit board and manufacture thereofInfo
- Publication number
- JPH10335823A JPH10335823A JP9138940A JP13894097A JPH10335823A JP H10335823 A JPH10335823 A JP H10335823A JP 9138940 A JP9138940 A JP 9138940A JP 13894097 A JP13894097 A JP 13894097A JP H10335823 A JPH10335823 A JP H10335823A
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- frame
- circuit board
- laminate
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、表裏両主面に半導
体チップや各種電子部品を収容するキャビティーを形成
した積層セラミック回路基板及びその製造方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic circuit board having a cavity for accommodating a semiconductor chip and various electronic components on both front and back main surfaces, and a method for manufacturing the same.
【0002】[0002]
【従来の技術】従来、両主面にキャビティーを有する積
層セラミック回路基板は、特開平6−302709号、
特開平8−330509号が知られている。2. Description of the Related Art Conventionally, a multilayer ceramic circuit board having cavities on both main surfaces is disclosed in Japanese Patent Application Laid-Open No. 6-302709.
JP-A-8-330509 is known.
【0003】何れの従来技術においては見掛け上、表裏
両主面に半導体チップや各種電子部品を収容するキャビ
ティーが形成されているものの、実際には一方主面、例
えば裏面側にキャビティーが形成されている積層セラミ
ック回路基板の表面側に、金属製、またはセラミック製
の枠体などを接着接合して、両主面にキャビティーを有
する積層セラミック回路基板としており、真の両主面に
キャビティーを有する積層セラミック回路基板ではなか
った。[0003] In any of the prior arts, cavities for accommodating semiconductor chips and various electronic components are formed on both front and back main surfaces, but actually, cavities are formed on one main surface, for example, the back side. A metal or ceramic frame or the like is bonded and bonded to the front side of the laminated ceramic circuit board to form a laminated ceramic circuit board with cavities on both main surfaces. It was not a laminated ceramic circuit board having a tee.
【0004】上述の構造では、高密度配線化された積層
セラミック回路基板を達成することが困難であった。即
ち、疑似的にキャビティーを形成するために積層セラミ
ック層回路基板に接合した枠体には、内部配線導体を形
成することができず、同時に枠体の表面に所定外部配線
導体を形成できないためである。[0004] With the above-described structure, it has been difficult to achieve a multilayer ceramic circuit board with high-density wiring. That is, since the internal wiring conductor cannot be formed on the frame joined to the multilayer ceramic circuit board in order to form the cavity in a pseudo manner, at the same time, the predetermined external wiring conductor cannot be formed on the surface of the frame. It is.
【0005】これは、積層セラミック回路基板の表面と
枠体との間を絶縁性接着剤で接合しようとすると、枠体
内に内部配線導体を形成しても根本的に積層セラミック
回路基板の表面に形成した外部配線導体との電気的な接
続は達成できず、また、導電性接着剤を用いて枠体を積
層セラミック回路基板に接合しようとすると、積層セラ
ミック回路基板の表面に形成した外部配線導体どうしが
短絡してしまう。[0005] This is because, when an attempt is made to join the surface of the multilayer ceramic circuit board and the frame with an insulating adhesive, even if an internal wiring conductor is formed in the frame, the surface of the multilayer ceramic circuit board is basically covered by the insulating adhesive. Electrical connection with the formed external wiring conductor cannot be achieved, and when the frame is joined to the multilayer ceramic circuit board using a conductive adhesive, the external wiring conductor formed on the surface of the multilayer ceramic circuit board is not obtained. Short circuit between them.
【0006】また、積層セラミック回路基板に枠体を接
合するため、その製造工程に全く異質な工程が付加され
ることになり、製造工程が煩雑になり、また、枠体に囲
まれたキャビティーの気密性信頼性が低下してしまうと
いう問題があった。Further, since the frame is joined to the multilayer ceramic circuit board, a completely different process is added to the manufacturing process, which complicates the manufacturing process, and further reduces the cavity surrounded by the frame. However, there has been a problem that the airtightness and reliability of the device have been reduced.
【0007】[0007]
【発明が解決しようとする課題】また、両主面にキャビ
ティーを有する積層セラミック回路基板を、内部配線導
体、外部配線導体となる導体パターンが形成された複数
枚のセラミックグリーンシートの載置、積層圧着及び焼
成という製造方法で製造する場合には、一方主面側の複
数の枠状のセラミックグリーンシート、複数の矩形状の
セラミックグリーンシート、裏面側の複数の枠状セラミ
ックグリーンシートを積層して圧着を行う必要がある
が、圧着時に、両キャビティーの底面となる矩形状セラ
ミックグリーンシート部分には、均一な圧力がかから
ず、その結果、焼成後、矩形状セラミックグリーンシー
トの層間で剥離現象が発生してしまう。Further, a multilayer ceramic circuit board having cavities on both main surfaces is mounted on a plurality of ceramic green sheets on which conductor patterns serving as internal wiring conductors and external wiring conductors are formed. In the case of manufacturing by a manufacturing method called lamination pressing and firing, a plurality of frame-shaped ceramic green sheets on one main surface side, a plurality of rectangular ceramic green sheets, and a plurality of frame-shaped ceramic green sheets on the back side are laminated. Although it is necessary to perform pressure bonding during pressing, uniform pressure is not applied to the rectangular ceramic green sheet portion that is the bottom surface of both cavities, and as a result, after firing, between the layers of the rectangular ceramic green sheet. The peeling phenomenon occurs.
【0008】また、セラミックグリーンシートの圧着時
に、上金型及び下金型にキャビティーの形状に合致した
突部を形成しておくことも考えられるが、キャビティー
形状の変更にともっなってこのような治具を変える必要
があり、実用的ではなかった。Further, it is conceivable to form projections corresponding to the shape of the cavity in the upper mold and the lower mold at the time of pressing the ceramic green sheet. Such a jig had to be changed, which was not practical.
【0009】本発明は、上述の問題点に鑑みて案出され
たものであり、その目的は、両主面にも配線導体を形成
でき、しかも、キャビティーの形状が変わっても簡単に
製造することができる両面にキャビティーを有する積層
セラミック回路基板及びその製造方法を提供するもので
ある。The present invention has been devised in view of the above-mentioned problems, and has as its object to form a wiring conductor on both main surfaces, and to easily manufacture even if the shape of the cavity changes. And a method for manufacturing the same.
【0010】[0010]
【課題を解決するための手段】本発明の第1の発明によ
れば、層間に内部配線導体を介在させて複数のセラミッ
ク層を積層するとともに、表裏両主面に電子部品を収納
する凹部状キャビティー及び前記内部配線導体と接続す
る外部配線導体を形成して成り、前記一方主面のキャビ
ティーは、他方主面のキャビティー内に背合わせに配置
されていることを特徴とする積層セラミック回路基板で
ある。According to the first aspect of the present invention, a plurality of ceramic layers are laminated with an internal wiring conductor interposed between layers, and a concave shape for accommodating electronic components on both front and back main surfaces. A multilayer ceramic, comprising: a cavity and an external wiring conductor connected to the internal wiring conductor, wherein the cavity on one main surface is disposed back to back in the cavity on the other main surface. It is a circuit board.
【0011】本発明の第2の発明は、第1の発明の製造
方法であり、(1)内部配線導体及び又は外部配線導体
となる導体パターンを有する複数のセラミックグリーン
シートを積層圧着し、開口を有する第1、第2の枠状積
層体を形成する工程、(2)内部配線導体となる導体パ
ターンを有する複数のセラミックグリーンシートを積層
圧着し、中間積層体を形成する工程、(3)前記中間積
層体の一方主面側に、第1枠状積層体を圧着接合する工
程と、(4)前記中間積層体の他方主面側に、第2枠状
積層体を、その開口が第1の枠状積層体の開口内に背合
わせに配置するように圧着接合すると工程と、(5)前
記第1、第2枠状積層体及び中間積層体を一体的に焼成
する工程とを含むことを特徴とする積層セラミック回路
基板の製造方法である。[0011] The second invention of the present invention is the manufacturing method of the first invention, wherein (1) a plurality of ceramic green sheets having a conductor pattern serving as an internal wiring conductor and / or an external wiring conductor are laminated and pressure-bonded, and an opening is formed. (2) forming a plurality of ceramic green sheets having conductor patterns to be internal wiring conductors by laminating and pressing to form an intermediate laminate; and (3) forming an intermediate laminate. A step of crimp-bonding a first frame-shaped laminate to one main surface of the intermediate laminate; and (4) a second frame-shaped laminate to the other main surface of the intermediate laminate, the opening having And (5) a step of integrally firing the first and second frame-shaped laminates and the intermediate laminate. A method for manufacturing a multilayer ceramic circuit board, characterized in that That.
【0012】[0012]
【作用】第1の発明によれば、両にキャビティーが形成
されていることにより、積層セラミック回路基板の両主
面にそれぞれ半導体チップ、電子部品を配置することが
できるため、基板の大型化が防止でき、高密度の積層セ
ラミック回路基板が達成される。According to the first aspect of the present invention, since the cavities are formed on both sides, the semiconductor chip and the electronic component can be arranged on both main surfaces of the multilayer ceramic circuit board, respectively. Can be prevented, and a high-density multilayer ceramic circuit board can be achieved.
【0013】しかも、両主面側のキャビティーの周囲の
表面にも、内部配線導体に接続した外部配線導体を形成
することができ、非常に高密度配線の積層セラミック回
路基板が達成される。Moreover, external wiring conductors connected to the internal wiring conductors can be formed also on the surfaces around the cavities on both main surfaces, and a multilayer ceramic circuit board with very high-density wiring can be achieved.
【0014】また、第2の発明によれば、例えば、底面
側キャビティーは、そのキャビティーの開口周囲の積層
体が、投影平面上、例えば表面側キャビティーの開口周
囲の積層体部の領域内に配されている。従って、まず、
表面側及び裏面側キャビティーの開口周囲の積層体とな
る表面側及び裏面側枠状積層体をセラミックグリーンシ
ートの圧着により形成しておき、同時に、両枠状積層体
に挟まれる中間積層体を圧着により形成しておき、次
に、表面側枠状積層体を中間積層体の表面に圧着接合
し、しかる後、前記裏面側枠状積層体を中間積層体の裏
面に圧着接合することができる。即ち、2つの枠状積層
体、1つの中間積層体を構成する各セラミック層間に
も、また、2つの枠状積層体、1つの中間積層体が接合
しあう接合面部分でも、夫々所定以上の圧力で圧着され
ているため、全てのセラミック層間で剥離が一切発生す
ることがない。According to the second aspect of the present invention, for example, the bottom cavity is formed such that the laminate around the opening of the cavity is formed on the projection plane, for example, in the region of the laminate portion around the opening of the front cavity. It is arranged within. Therefore, first,
The front-side and back-side frame-shaped laminates to be the laminates around the openings of the front-side and back-side cavities are formed by pressing the ceramic green sheets, and at the same time, the intermediate laminate sandwiched between both frame-shaped laminates is formed. After being formed by pressing, the front-side frame-shaped laminate can be pressure-bonded to the surface of the intermediate laminate, and then the back-side frame-shaped laminate can be pressure-bonded to the back surface of the intermediate laminate. . That is, the two frame-shaped laminates, the respective ceramic layers constituting the intermediate laminate, and the joint surface portions where the two frame-shaped laminates and the intermediate laminate are joined to each other, respectively, have a predetermined size or more. Since pressure bonding is performed, no separation occurs between all ceramic layers.
【0015】従って上述の製造方法では、積層セラミッ
ク回路基板の一方主面にキャビティーを構成する枠体を
接着する必要がなく、また、通常の積層セラミック回路
基板のように積層圧着のみで両面にキャビティーを有す
る積層セラミック回路基板を形成することができ、焼成
時のセラミック層間の剥離がなく、簡単な製造方法で信
頼性の高い積層セラミック回路基板が達成される。Therefore, in the above-described manufacturing method, it is not necessary to adhere a frame forming a cavity to one main surface of the multilayer ceramic circuit board, and it is necessary to bond the frame to both sides only by laminating and crimping as in a normal multilayer ceramic circuit board. A multilayer ceramic circuit board having a cavity can be formed, and there is no separation between ceramic layers during firing, and a highly reliable multilayer ceramic circuit board can be achieved by a simple manufacturing method.
【0016】[0016]
【発明の実施の形態】以下、本発明の積層セラミック回
路基板及びその製造方法を図面に基づいて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer ceramic circuit board according to the present invention and a method for manufacturing the same will be described with reference to the drawings.
【0017】図1(a)は、第1の発明に係る積層セラ
ミック回路基板の断面図であり、図1(b)は、表裏キ
ャビティーの位置関係を示す平面図である。FIG. 1A is a cross-sectional view of a multilayer ceramic circuit board according to the first invention, and FIG. 1B is a plan view showing the positional relationship between front and back cavities.
【0018】図において、10は積層セラミック回路基
板であり、積層セラミック回路基板10は、例えばセラ
ミック層1a〜1fからなる積層基板1と、積層基板1
の表面に形成されたキャビティー2aと、積層基板1の
裏面に形成されたキャビティー2fと、積層基板1の内
部に形成された内部配線導体3と、積層基板1の両表面
に形成された外部配線導体4a、4fと、キャビティー
2aに納配置された電子部品5aと、キャビティー2f
に収納配置された電子部品5fと、外部配線導体4aに
接続した各種電子部品6とから構成されている。In FIG. 1, reference numeral 10 denotes a multilayer ceramic circuit board. The multilayer ceramic circuit board 10 includes, for example, a multilayer substrate 1 including ceramic layers 1a to 1f and a multilayer substrate 1
, A cavity 2f formed on the back surface of the laminated substrate 1, an internal wiring conductor 3 formed inside the laminated substrate 1, and a cavity 2a formed on both surfaces of the laminated substrate 1. External wiring conductors 4a, 4f, electronic component 5a housed in cavity 2a, and cavity 2f
And electronic components 6 connected to the external wiring conductor 4a.
【0019】尚、図1(b)は、表面のキャビティー2
aと裏面のキャビティー2fの位置関係を明示するた
め、外部配線導体4a、4fや電子部品5a、5f、6
を省略している。FIG. 1B shows a cavity 2 on the surface.
In order to clarify the positional relationship between the external wiring conductors 4a, 4f and the electronic components 5a, 5f, 6
Is omitted.
【0020】積層基板1は、表面側から枠状セラミック
層1a、1b、矩形状セラミック層1c、1d、枠状セ
ラミック層1e、1fが積層されている。この枠状セラ
ミック層1a、1bによって、表面側キャビティー2a
の周囲が構成され、矩形状セラミック層1cによって表
面側キャビティー2aの底面が構成される。同様に、枠
状セラミック層1e、1fによって、両面側キャビティ
ー2fの周囲が構成され、矩形状セラミック層1dによ
って表面側キャビティー2fの底面が構成される。In the laminated substrate 1, frame-shaped ceramic layers 1a and 1b, rectangular ceramic layers 1c and 1d, and frame-shaped ceramic layers 1e and 1f are stacked from the front side. The front side cavity 2a is formed by the frame-shaped ceramic layers 1a and 1b.
Is formed, and the bottom surface of the front-side cavity 2a is formed by the rectangular ceramic layer 1c. Similarly, the frame-shaped ceramic layers 1e and 1f form the periphery of the double-sided cavity 2f, and the rectangular ceramic layer 1d forms the bottom surface of the front-side cavity 2f.
【0021】しかも、各セラミック層1a〜1fの層間
に内部配線導体3及び各セラミック層を貫くようにスル
ーホール導体7が形成されている。また、積層基板1の
表面を構成するセラミック層1aの表面には、外部配線
導体4aが、積層基板1の裏面を構成するセラミック層
1fの表面(接合されない面)には、外部配線導体4f
が形成されている。尚、セラミック層1cが露出する表
面側キャビティー2aの底面部分に、所定配線導体3a
が、セラミック層1dが露出する裏面側キャビティー2
fの底面部分に、所定配線導体3fが夫々形成されてい
る。In addition, a through-hole conductor 7 is formed between the ceramic layers 1a to 1f so as to penetrate the internal wiring conductor 3 and each ceramic layer. An external wiring conductor 4a is provided on the surface of the ceramic layer 1a constituting the surface of the laminated substrate 1, and an external wiring conductor 4f is provided on the surface (non-joined surface) of the ceramic layer 1f constituting the back surface of the laminated substrate 1.
Are formed. A predetermined wiring conductor 3a is provided on the bottom surface of the front side cavity 2a where the ceramic layer 1c is exposed.
Is the backside cavity 2 from which the ceramic layer 1d is exposed.
Predetermined wiring conductors 3f are respectively formed on the bottom surface of f.
【0022】ビアホール導体7は、各セラミック層1a
〜1fの層間に配置されて内部配線導体3どうしを接続
したり、また、内部配線導体3と外部配線導体4a、4
fとを接続するために導体であり、所定配線導体3a、
3fは、各種電子部品5a、5fを接合または接続する
ための導体である。The via-hole conductor 7 is formed of each ceramic layer 1a.
To 1f to connect the internal wiring conductors 3 to each other, or to connect the internal wiring conductors 3 to the external wiring conductors 4a, 4a, 4f.
f and a predetermined wiring conductor 3a,
3f is a conductor for joining or connecting various electronic components 5a and 5f.
【0023】各セラミック層1a〜1fは、アルミナ、
ムライト、酸化チタン、チタン酸バリウムなどの絶縁性
セラミックやアルミナと低融点ガラス成分とからなるガ
ラス−セラミックなどから構成されている。Each of the ceramic layers 1a to 1f is made of alumina,
It is composed of an insulating ceramic such as mullite, titanium oxide, barium titanate, or a glass-ceramic comprising alumina and a low-melting glass component.
【0024】内部配線導体3、所定配線導体3a、3
f、ビアホール導体7は、タングステン系(タングステ
ン単体及びその合金)、モリブデン系、銀系、銅系など
導体からなり、その厚みは8〜15μm程度であり、ビ
アホール導体7の直径は任意な値とすることができる
が、例えば直径は50〜150μmである。The internal wiring conductor 3, predetermined wiring conductors 3a, 3
f, the via-hole conductor 7 is made of a conductor such as a tungsten-based (tungsten and its alloy), a molybdenum-based, a silver-based, and a copper-based conductor. For example, the diameter is 50 to 150 μm.
【0025】また、外部配線導体4a、4fは、積層基
板1のキャビティー2a、2fの周囲表面に形成され、
端子電極として作用し、また、電子部品6を接続するた
めの接続パッドとしても作用するものであり、タングス
テン系(タングステン単体及びその合金)、モリブデン
系、銀系、銅系など導体からなり、さらに必要に応じて
表面にメッキ処理が施されている。The external wiring conductors 4a, 4f are formed on the peripheral surfaces of the cavities 2a, 2f of the laminated substrate 1,
It functions as a terminal electrode and also as a connection pad for connecting the electronic component 6, and is made of a conductor such as tungsten (tungsten and its alloy), molybdenum, silver, copper, and the like. The surface is plated as necessary.
【0026】尚、キャビティー2a、2fの底面で、電
子部品5a、5fと接合する所定配線導体3a、3f
は、内部配線導体3・・と同一工程で形成され、必要に
応じて、外部配線導体4a、4fと同一工程でメッキ被
覆される。The predetermined wiring conductors 3a, 3f to be joined to the electronic components 5a, 5f on the bottom surfaces of the cavities 2a, 2f.
Are formed in the same step as the internal wiring conductors 3... And, if necessary, are plated and coated in the same step as the external wiring conductors 4 a and 4 f.
【0027】また、積層基板1の表面には、概略矩形状
で開口した所定深さを有するキャビティー2aが形成さ
れ、このキャビティー2a内には、所定配線導体3aに
接合又は接続した電子部品5aが収納配置され、ワイヤ
ボンディング細線などにより、外部配線導体4aに電気
的に接続されている。また、積層基板1の裏面には、概
略矩形状で開口した所定深さを有するキャビティー2f
が形成され、このキャビティー2f内には、所定配線導
体3fに接続した電子部品5f、5fが収納配置してい
る。On the surface of the laminated substrate 1, a cavity 2a having a substantially rectangular opening and a predetermined depth is formed, and an electronic component joined or connected to a predetermined wiring conductor 3a is formed in the cavity 2a. 5a are housed and arranged, and are electrically connected to the external wiring conductor 4a by a thin wire bonding wire or the like. In addition, a cavity 2f having a predetermined depth and a substantially rectangular opening is provided on the back surface of the laminated substrate 1.
The electronic components 5f and 5f connected to the predetermined wiring conductor 3f are housed and arranged in the cavity 2f.
【0028】ここで、積層基板1を厚み方向に3つに分
解すると、セラミック層1a、1bから構成された表面
側の第1枠状積層体10a、セラミック層1c、1dか
ら構成された矩形状の中間積層体10b及び裏面側の第
2枠状積層体10cとに分けられる。Here, when the laminated substrate 1 is disassembled into three parts in the thickness direction, the first frame-shaped laminated body 10a on the front side composed of the ceramic layers 1a and 1b and the rectangular shape composed of the ceramic layers 1c and 1d are formed. And a second frame-shaped laminate 10c on the back side.
【0029】即ち、第1枠状積層体10aは、表面側キ
ャビティー2aの開口周囲となる部位であり、第2枠状
積層体10bは、裏面側キャビティー2fの開口周囲と
なる部位であり、中間積層体10bは両キャビティー2
a、2fの底面を構成するものである。しかも、各積層
体10a〜10cの何れにも内部配線導体3が形成され
ている。That is, the first frame-shaped laminate 10a is a portion around the opening of the front-side cavity 2a, and the second frame-shaped laminate 10b is a portion around the opening of the back-side cavity 2f. , The intermediate laminate 10b is formed in both cavities 2
a and 2f constitute the bottom surface. In addition, the internal wiring conductor 3 is formed in each of the laminates 10a to 10c.
【0030】即ち、両キャビティー2a、2fの開口周
囲の表面に、外部配線導体4a、4fを形成しても、キ
ャビティー2a、2fの開口周囲を構成する枠状積層体
10a、10bに内層された内部配線導体2とビアホー
ル導体7を介して電気的に接続される。従って、全体と
して高密度配線化した積層セラミック回路基板となる。That is, even if the external wiring conductors 4a, 4f are formed on the surfaces around the openings of the cavities 2a, 2f, the inner layer is formed on the frame-shaped laminates 10a, 10b constituting the periphery of the openings of the cavities 2a, 2f. The internal wiring conductor 2 is electrically connected via the via-hole conductor 7. Therefore, a multilayer ceramic circuit board having high-density wiring as a whole is obtained.
【0031】ここで、積層基板1の両主面に形成された
キャビティー2a、2fの位置関係を説明すると、表面
側キャビティー2aは、投影平面上、裏面側キャビティ
ー2fの開口内に配置されている。これによって、従来
のように積層セラミック回路基板を、セラミックグリー
ンシートの積層圧着方式で簡単に両面にキャビティー2
a、2fを有する積層セラミック回路基板10が達成で
きる。Here, the positional relationship between the cavities 2a and 2f formed on both main surfaces of the laminated substrate 1 will be described. The front-side cavity 2a is arranged in the opening of the rear-side cavity 2f on the projection plane. Have been. As a result, a multilayer ceramic circuit board can be easily formed on both sides by a ceramic green sheet laminating and pressing method as in the related art.
a, 2f can be achieved.
【0032】その製造方法を図2の工程流れ図に沿って
説明する。The manufacturing method will be described with reference to the process flow chart of FIG.
【0033】まず、表面側の枠状積層体10aとなる未
焼成の第1枠状積層体を形成する。First, an unfired first frame-shaped laminate to be the frame-shaped laminate 10a on the front side is formed.
【0034】具体的には、セラミック層1a、1bとな
るセラミックグリーンシートを用意し、シートの表面に
内部配線導体3、外部配線導体4aとなる導体パターン
を形成し、グリーンシートの厚み方向にスルーホール導
体7となる導体を形成する。そして、このグリーンシー
トを積層し、所定圧力を与えて圧着する。その後、グリ
ーンシート積層体に、キャビティー2aの形状に応じ
て、プレス打ち抜きを行う。これにより、未焼成の第1
枠状積層体が完成する。尚、予め開口が形成された枠状
のセラミックグリーンシートを積層し、圧着を行っても
構わない。Specifically, a ceramic green sheet to be the ceramic layers 1a and 1b is prepared, and a conductor pattern to be the internal wiring conductor 3 and the external wiring conductor 4a is formed on the surface of the sheet. A conductor to be the hole conductor 7 is formed. Then, the green sheets are laminated and pressed under a predetermined pressure. Thereafter, press punching is performed on the green sheet laminate according to the shape of the cavity 2a. As a result, the unfired first
The frame laminate is completed. Note that a frame-shaped ceramic green sheet having an opening formed in advance may be laminated and pressure-bonded.
【0035】次に、中間積層体10bとなる未焼成の矩
形状積層体を形成する。具体的には、セラミック層1
c、1dとなるセラミックグリーンシートを用意し、グ
リーンシートの主面に、内部配線導体3、導体3a、3
fとなる導体パターンを形成し、各グリーンシートの厚
み方向にスルーホール導体7となる導体を形成する。そ
の後、矩形状のセラミックグリーンシートを積層し、圧
着を行う。Next, an unfired rectangular laminate to be the intermediate laminate 10b is formed. Specifically, the ceramic layer 1
c, 1d ceramic green sheets are prepared, and the inner wiring conductors 3, conductors 3a, 3
A conductor pattern serving as f is formed, and a conductor serving as a through-hole conductor 7 is formed in the thickness direction of each green sheet. Thereafter, rectangular ceramic green sheets are laminated and pressure-bonded.
【0036】次に、裏面側の枠状積層体10cとなる未
焼成の第2枠状積層体を形成する。Next, an unfired second frame-shaped laminate to be the frame-shaped laminate 10c on the back side is formed.
【0037】具体的には、セラミック層1e、1fとな
るセラミックグリーンシートを用意し、シートの表面に
内部配線導体3、外部配線導体4fとなる導体パターン
を形成し、グリーンシートの厚み方向にスルーホール導
体7となる導体を形成する。そして、このグリーンシー
トを積層し、所定圧力を与えて圧着する。その後、グリ
ーンシート積層体に、キャビティー2fの形状に応じ
て、プレス打ち抜きを行う。これにより、未焼成の第2
枠状積層体が完成する。尚、予め開口が形成された枠状
のセラミックグリーンシートを積層し、接合を行っても
構わない。Specifically, a ceramic green sheet to be the ceramic layers 1e and 1f is prepared, and a conductor pattern to be the internal wiring conductor 3 and the external wiring conductor 4f is formed on the surface of the sheet. A conductor to be the hole conductor 7 is formed. Then, the green sheets are laminated and pressed under a predetermined pressure. Then, press punching is performed on the green sheet laminate according to the shape of the cavity 2f. As a result, the unfired second
The frame laminate is completed. Note that a frame-shaped ceramic green sheet having an opening formed in advance may be laminated and joined.
【0038】次に、第1回目の接合圧着を行う。具体的
には、未焼成中間積層体の表面側主面に、未焼成の第1
枠状積層体を位置合わせして載置し、所定圧力を与え
て、接合を行う。この時、両者の接合面の投影上の底面
は、中間積層体の底面であり、全面が平面となっている
ため、接合圧着時の圧力が両者の接合領域に均一に与え
られ、安定した圧着接合が達成される。Next, the first bonding and pressure bonding is performed. Specifically, the unfired first laminate is provided on the main surface side of the unfired intermediate laminate.
The frame-shaped laminate is positioned and placed, and a predetermined pressure is applied to perform joining. At this time, the projected bottom surface of the joining surface of both is the bottom surface of the intermediate laminate, and the entire surface is flat, so that the pressure at the time of joining and crimping is uniformly applied to the joining region of both, and stable crimping is performed. Joining is achieved.
【0039】次に、第2回目の接合圧着を行う。具体的
には、上述の第1回目の圧着によって接合した第1の枠
状積層体と中間積層体との接合体の裏面側主面に、未焼
成の第2の枠状積層体を位置合わせして載置し、両者に
所定圧力を与えて、接合を行う。この時、第2の枠状積
層体の表面が、第1の枠状積層体の開口周囲の表面部分
内に位置しているため、この第2回目の圧着時の圧力
が、第2の枠状積層体と、未焼成の矩形状積層との接合
面に均一な圧力がかかり、安定した圧着が達成される。Next, the second bonding and pressure bonding is performed. Specifically, the unfired second frame-shaped laminate is aligned with the back surface side main surface of the joined body of the first frame-shaped laminate and the intermediate laminate joined by the first press bonding described above. Then, a predetermined pressure is applied to both of them to perform joining. At this time, since the surface of the second frame-shaped laminated body is located in the surface portion around the opening of the first frame-shaped laminated body, the pressure at the time of the second pressure bonding is reduced to the second frame. A uniform pressure is applied to the joint surface between the shape-like laminate and the unfired rectangular shape laminate, and stable pressure bonding is achieved.
【0040】これによって、両主面にキャビティー2
a、2fとなる凹部が形成された未焼成状態の積層基板
が達成される。Thus, the cavities 2 are formed on both main surfaces.
An unfired laminated substrate in which the recesses a and 2f are formed is achieved.
【0041】次に、この未焼成の積層回路基板の焼成処
理を行う。この焼成条件は、セラミック層となる材料、
各導体パターン、導体によって決定され、例えば、セラ
ミック層にガラス−セラミック、配線導体等に銀系導体
を使用した場合には、大気雰囲気中に例えばピーク温度
850℃で約2時間程度の焼成が行われる。この焼成工
程によって、積層体1の両主面にキャビティー2a、2
fが形成され、その内部に内部配線導体3、ビアホール
導体7が形成され、キャビティー2a、2fの周囲の表
面に外部配線導体4a、4fが形成され、キャビティー
2a、2fの底面に所定配線導体3a、3fが形成され
ることになる。そして、必要に応じて、外部配線導体4
a、4fや所定配線導体3a、3fにメッキ被覆を行
う。Next, the unfired laminated circuit board is fired. The firing conditions are as follows:
It is determined by each conductor pattern and conductor. For example, when a glass-ceramic is used for the ceramic layer and a silver-based conductor is used for the wiring conductor, baking is performed in an air atmosphere at a peak temperature of 850 ° C. for about 2 hours, for example. Will be By this firing step, the cavities 2a, 2a
f, an internal wiring conductor 3 and a via hole conductor 7 are formed therein, external wiring conductors 4a and 4f are formed on surfaces around the cavities 2a and 2f, and a predetermined wiring is formed on the bottom surface of the cavities 2a and 2f. Conductors 3a and 3f are formed. Then, if necessary, the external wiring conductor 4
a, 4f and the predetermined wiring conductors 3a, 3f are plated.
【0042】次に、電子部品5a、5f、6を実装す
る。まず、キャビティー2a、2f内に電子部品5a、
5fを収納配置する。即ち、裏面側キャビティー2fの
所定配線導体3fに電子部品5f、5fを接合または接
続する。次に、表面側キャビティー2a内に電子部品5
aを収納配置する。即ち、表面側キャビティー2aの所
定配線導体3aに電子部品5a接合し、外部配線導体4
aとの間にワイヤボンディング細線などを用いて電気的
に接続する。Next, the electronic components 5a, 5f and 6 are mounted. First, the electronic components 5a are placed in the cavities 2a and 2f.
5f is stored and arranged. That is, the electronic components 5f and 5f are joined or connected to the predetermined wiring conductor 3f of the back side cavity 2f. Next, the electronic component 5 is placed in the front side cavity 2a.
a is stored. That is, the electronic component 5a is joined to the predetermined wiring conductor 3a of the front side cavity 2a,
a is electrically connected to each other by using a wire bonding thin wire or the like.
【0043】また、同時に表面の外部配線導体4a上に
電子部品6を実装を行う。At the same time, the electronic component 6 is mounted on the external wiring conductor 4a on the surface.
【0044】上述の製造方法において、外部配線導体4
a、4fとなる導体パターンをセラミックグリーンシー
トの状態で形成したが、外部配線導体4aとなる導体パ
ターンを第1の枠状積層体を形成する工程の最後に、ま
た、外部配線導体4fとなる導体パターンを第2の枠状
積層体を形成する工程の最後に形成しても構わない。In the above manufacturing method, the external wiring conductor 4
The conductor patterns a and 4f are formed in the form of ceramic green sheets. However, the conductor pattern serving as the external wiring conductor 4a becomes the external wiring conductor 4f at the end of the step of forming the first frame-shaped laminate. The conductor pattern may be formed at the end of the step of forming the second frame-shaped laminate.
【0045】また、外部配線導体4aを第1の接合圧着
した後に、また、外部配線導体4fを第2の接合圧着し
た後に夫々形成してもよく、また、焼成前の積層体に形
成してもよく、焼成後の積層基板の両面に別焼成によっ
て焼きつけても構わない。The external wiring conductor 4a may be formed after the first bonding and pressure bonding, and the external wiring conductor 4f may be formed after the second bonding and pressure bonding, or may be formed on a laminate before firing. Alternatively, the layers may be baked on both sides of the fired laminated substrate by separate firing.
【0046】さらに、電子部品5a、5f、5f、6の
実装も、先に、裏面側キャビティー2f内に電子部品5
f、5fを収納・配置を行い、次いで、表面導体パター
ンに電子部品6を実装して、最後に表面側にキャビティ
ー2a内に電子部品5aを収納して、ワイヤボンディン
グ細線を最後に行うなど、電子部品5a、5f、5f、
6の実装方法によって種々変化させてもかまなわい。ま
た、電子部品6として、厚膜抵抗体膜のように焼きつけ
を伴う場合に、焼成後の積層基板1に直ちに形成した
り、焼成条件が合えば積層体基板の焼成ど同時に行って
もよい。また、メッキ被覆を避けるためにガラス保護層
や樹脂保護層などを適宜工程付加しても構わない。Further, when mounting the electronic components 5a, 5f, 5f, and 6, the electronic components 5a, 5f, 5f, and 6 are first placed in the back side cavity 2f.
f, 5f are stored and arranged, then the electronic component 6 is mounted on the surface conductor pattern, and finally, the electronic component 5a is stored in the cavity 2a on the front surface side, and the wire bonding fine wire is performed last. , Electronic components 5a, 5f, 5f,
Various changes may be made depending on the mounting method of No. 6. In the case where the electronic component 6 involves baking like a thick film resistor film, the electronic component 6 may be formed immediately on the laminated substrate 1 after baking, or may be performed simultaneously with baking of the laminated substrate if the baking conditions are met. Further, in order to avoid plating coating, a glass protective layer, a resin protective layer, and the like may be added as appropriate.
【0047】上述の製造方法によれば、前記表面側キャ
ビティー2aは、投影平面上、裏面キャビティー2a内
に配されているため、セラミック層1a〜1fの積層に
おいて、表面側のキャビティー2aを構成するための第
1の枠状積層体10aと第2の枠状積層体10c、中間
積層体10bを夫々別々に圧着積層して形成しておき、
先ず、第1の枠状積層体10aを中間積層体10bの表
面側に圧着接合させ、続いて、第2の枠状積層体10c
を中間積層体10bの裏面側に圧着接合させることによ
り、少なくとも接合圧着領域に所定圧力が印加されるこ
とになる。According to the above-described manufacturing method, since the front-side cavity 2a is disposed in the rear-side cavity 2a on the projection plane, the front-side cavity 2a is formed in the lamination of the ceramic layers 1a to 1f. The first frame-shaped laminated body 10a, the second frame-shaped laminated body 10c, and the intermediate laminated body 10b are separately formed by pressure bonding and lamination, respectively.
First, the first frame-shaped laminate 10a is pressure-bonded to the surface of the intermediate laminate 10b, and then the second frame-shaped laminate 10c
Is pressure-bonded to the back side of the intermediate laminate 10b, whereby a predetermined pressure is applied to at least the bonded pressure-bonded region.
【0048】従って、焼成工程において、各積層体10
a〜10c内のセラミック層1aと1b、1cと1d、
1eと1fとの間で剥離が発生することがなくしかも、
3つの積層体10a〜10c間の接合面で1bと1c、
1dと1eとの間においても、接合剥がれが発生するこ
とが一切ないものとなる。Therefore, in the firing step, each laminated body 10
a to 10c, ceramic layers 1a and 1b, 1c and 1d,
No peeling occurs between 1e and 1f, and
1b and 1c at the joint surface between the three laminates 10a to 10c,
Even between 1d and 1e, there is no occurrence of bonding peeling.
【0049】しかも、製造工程においては、通常の積層
セラミック回路基板のように、複数のグリーンシートの
積層圧着でのみ製造できる。In addition, in the manufacturing process, as in the case of a normal multilayer ceramic circuit board, it can be manufactured only by stacking and pressing a plurality of green sheets.
【0050】図3〜図6には、第2の発明の製造方法に
よって製造可能な本発明の積層セラミック回路基板であ
り、各図(a)は断面図、(b)は表面側の断面図であ
る。FIGS. 3 to 6 show the multilayer ceramic circuit board of the present invention which can be manufactured by the manufacturing method of the second invention. FIG. 3A is a sectional view, and FIG. It is.
【0051】尚、各図ともに電子部品5a、5f、5
f、6は省略している。The electronic components 5a, 5f, 5
f and 6 are omitted.
【0052】図3は、表面側に1つのキャビティー2a
が形成されており、裏面側には2つのキャビティー21
f、22fが形成されている。平面図(図3(b))に
おいて、点線で示す2つの裏面側のキャビティー21
f、22fのうち、キャビティー21fの開口は、実線
で示す表面側のキャビティー2aの開口形状の全体を含
む形状となっており、キャビティー21fは、実線で示
す表面側のキャビティー2aの開口周囲の部分、即ち、
第1の枠状積層体10aと中間積層体10bの接合領域
に形成さられている。FIG. 3 shows one cavity 2a on the surface side.
Are formed, and two cavities 21 are formed on the back side.
f, 22f are formed. In the plan view (FIG. 3B), two cavities 21 on the back surface side indicated by dotted lines
f, 22f, the opening of the cavity 21f has a shape including the entire opening shape of the cavity 2a on the front side shown by the solid line, and the cavity 21f is the opening of the cavity 2a on the front side shown by the solid line. The part around the opening, that is,
It is formed in a joint region between the first frame-shaped laminate 10a and the intermediate laminate 10b.
【0053】図4は、表面側に2つのキャビティー21
a、22aが形成されており、裏面側には2つのキャビ
ティー21f、22fが形成されている。平面図(図4
(b))において、点線で示す2つの裏面側のキャビテ
ィー21f、22aのうち、キャビティー21fの開口
は、実線で示す表面側のキャビティー21aの開口形状
の全体を含む形状となっており、キャビティー22fの
開口は、実線で示す表面側のキャビティー22aの開口
形状の全体を含む形状となっている。FIG. 4 shows two cavities 21 on the front side.
a and 22a are formed, and two cavities 21f and 22f are formed on the back surface side. Plan view (Fig. 4
In (b)), of the two backside cavities 21f and 22a indicated by the dotted lines, the opening of the cavity 21f has a shape including the entire opening shape of the front side cavity 21a indicated by the solid line. The opening of the cavity 22f has a shape including the entire opening shape of the cavity 22a on the front surface side indicated by a solid line.
【0054】図5は、表面側に2つのキャビティー21
a、22aが形成されており、裏面側には1つのキャビ
ティー2fが形成されている。平面図(図5(b))に
おいて、点線で示す裏面側のキャビティー2fの開口
は、実線で示す表面側のキャビティー21a、22aの
開口形状の全体を含む形状となっている。FIG. 5 shows two cavities 21 on the surface side.
a and 22a are formed, and one cavity 2f is formed on the back surface side. In the plan view (FIG. 5 (b)), the opening of the cavity 2f on the back surface indicated by the dotted line has a shape including the entire opening shape of the cavities 21a and 22a on the front surface indicated by the solid line.
【0055】図6は、図5の積層セラミック回路基板の
キャビティー21aの内壁に導体31aを有する段差部
22が形成されている。FIG. 6 shows a stepped portion 22 having a conductor 31a formed on the inner wall of a cavity 21a of the multilayer ceramic circuit board of FIG.
【0056】何れの図3〜図6は、従って、未焼成の中
間積層体10bの表面に未焼成の第1の枠状積層体10
aを圧着するにあたり支障なく第1の接合圧着すること
ができ、次いで、未焼成の中間積層体10bの裏面に未
焼成の第2の枠状積層体10cを圧着するにあたり、第
2の枠状積層体10cと中間積層体1bとの接合面は、
投影的に全て、第1の枠状積層体10aの表面形状に含
まれているため、安定した第2の接合圧着することがで
きる。FIGS. 3 to 6 show that the unfired first frame-like laminate 10 is formed on the surface of the unfired intermediate laminate 10b.
a can be subjected to the first bonding pressure bonding without any trouble in pressing the second frame-shaped laminated body 10c to the back surface of the unfired intermediate laminated body 10b. The bonding surface between the laminate 10c and the intermediate laminate 1b is
Since all of the projections are included in the surface shape of the first frame-shaped laminate 10a, stable second bonding and pressure bonding can be performed.
【0057】尚、上述の実施例では、裏面側キャビティ
ー2fは、そのキャビティー2fの開口周囲の表面が、
投影平面上、表面側キャビティー2aの開口周囲の表面
領域内に配されているが、その逆で表面側キャビティー
2aは、そのキャビティー2aの開口周囲の表面が、投
影平面上、裏面側キャビティー2fの開口周囲の表面領
域内に配されてもよく、また、セラミック層の積層数は
所定回路網によって種々変更可能である。In the above-described embodiment, the back surface side cavity 2f has a surface around the opening of the cavity 2f.
On the projection plane, it is arranged in the surface area around the opening of the front-side cavity 2a, but conversely, the front-side cavity 2a has the surface around the opening of the cavity 2a on the projection plane and the rear side. It may be arranged in the surface area around the opening of the cavity 2f, and the number of laminated ceramic layers can be variously changed by a predetermined circuit network.
【0058】[0058]
【発明の効果】以上のように、両主面にキャビティーを
有する積層セラミック回路基板によれば、両主面のキャ
ビティーの開口周囲の積層部分に内部配線導体を内層す
ることができ、その表面に外部配線導体を形成すること
ができ、しかも、両主面のキャビティーに各種電子部品
を収容することができるため、高密度配線及び高密度実
装可能な積層セラミック回路基板となる。As described above, according to the multilayer ceramic circuit board having the cavities on both main surfaces, the internal wiring conductor can be inner-layered in the laminated portion around the opening of the cavity on both main surfaces. Since external wiring conductors can be formed on the surface and various electronic components can be accommodated in the cavities on both main surfaces, a multilayer ceramic circuit board capable of high-density wiring and high-density mounting can be obtained.
【0059】また、上述の構造の両主面にキャビティー
を有する積層セラミック回路基板をグリーンシートの圧
着、焼成で形成しても、圧着のムラ、圧着不足によるセ
ラミック層間の剥離が発生することがない。しかも、従
来のようにグリーンシートの積層圧着のみで製造できる
ため、非常に実用に適した積層セラミック回路基板の製
造方法となる。Even when a multilayer ceramic circuit board having cavities on both main surfaces of the above structure is formed by pressing and firing green sheets, unevenness in pressing and peeling between ceramic layers due to insufficient pressing may occur. Absent. Moreover, since it can be manufactured only by laminating and pressing of green sheets as in the related art, it is a method of manufacturing a multilayer ceramic circuit board which is very suitable for practical use.
【図1】(a)は、本発明に係る積層セラミック回路基
板の断面図であり、(b)は表面側のキャビティー及び
裏面側のキャビティーの位置関係を説明する平面図であ
る。FIG. 1A is a cross-sectional view of a multilayer ceramic circuit board according to the present invention, and FIG. 1B is a plan view illustrating a positional relationship between a cavity on a front surface side and a cavity on a back surface side.
【図2】本発明の積層セラミック回路基板の製造を説明
するための工程流れ図である。FIG. 2 is a process flow chart for explaining the manufacture of the multilayer ceramic circuit board of the present invention.
【図3】(a)は他の積層セラミック回路基板の断面図
であり、(b)は表面側のキャビティー及び裏面側のキ
ャビティーの位置関係を説明する平面図である。3A is a cross-sectional view of another multilayer ceramic circuit board, and FIG. 3B is a plan view illustrating a positional relationship between a cavity on a front surface side and a cavity on a back surface side.
【図4】(a)は他の積層セラミック回路基板の断面図
であり、(b)は表面側のキャビティー及び裏面側のキ
ャビティーの位置関係を説明する平面図である。FIG. 4A is a cross-sectional view of another multilayer ceramic circuit board, and FIG. 4B is a plan view illustrating a positional relationship between a front cavity and a rear cavity.
【図5】(a)は他の積層セラミック回路基板の断面図
であり、(b)は表面側のキャビティー及び裏面側のキ
ャビティーの位置関係を説明する平面図である。FIG. 5A is a cross-sectional view of another multilayer ceramic circuit board, and FIG. 5B is a plan view illustrating a positional relationship between a cavity on a front surface and a cavity on a back surface.
【図6】(a)は他の積層セラミック回路基板の断面図
であり、(b)は表面側のキャビティー及び裏面側のキ
ャビティーの位置関係を説明する平面図である。FIG. 6A is a cross-sectional view of another multilayer ceramic circuit board, and FIG. 6B is a plan view illustrating a positional relationship between a cavity on the front side and a cavity on the back side.
10・・・・・・積層セラミック回路基板 1・・・・・・積層基板 1a〜1f・・・セラミック層 10a・・・第1枠状積層体 10b・・・中間積層体 10c・・・第2枠状積層体 2a、2f・・・キャビティー 3・・・・・・・内部配線導体 4a、4f・・・外部配線導体 5a、5f、6・・電子部品 10 multilayer ceramic circuit board 1 multilayer board 1a to 1f ceramic layer 10a first frame-shaped multilayer body 10b intermediate multilayer body 10c multilayer 2 frame-shaped laminated body 2a, 2f ... cavity 3 ... internal wiring conductors 4a, 4f ... external wiring conductors 5a, 5f, 6 ... electronic components
Claims (2)
セラミック層を積層するとともに、表裏両主面に電子部
品を収納する凹部状キャビティー及び前記内部配線導体
と接続する外部配線導体を形成して成り、 前記一方主面のキャビティーは、他方主面のキャビティ
ー内に背合わせに配置されていることを特徴とする積層
セラミック回路基板。1. A plurality of ceramic layers are laminated with an internal wiring conductor interposed between layers, and a concave cavity for accommodating an electronic component is formed on both front and back main surfaces, and an external wiring conductor connected to the internal wiring conductor is formed. The multilayer ceramic circuit board, wherein the cavity on the one main surface is disposed back to back in the cavity on the other main surface.
となる導体パターンを有する複数のセラミックグリーン
シートを積層圧着し、開口を有する第1、第2の枠状積
層体を形成する工程、(2)内部配線導体となる導体パ
ターンを有する複数のセラミックグリーンシートを積層
圧着し、中間積層体を形成する工程、(3)前記中間積
層体の一方主面側に、第1枠状積層体を圧着接合する工
程と、(4)前記中間積層体の他方主面側に、第2枠状
積層体を、その開口が第1の枠状積層体の開口内と背合
わせに配置するように圧着接合すると工程と、(5)前
記第1、第2枠状積層体及び中間積層体を一体的に焼成
する工程とを含むことを特徴とする積層セラミック回路
基板の製造方法。2. A step of laminating and pressing a plurality of ceramic green sheets having conductor patterns to be internal wiring conductors and / or external wiring conductors to form first and second frame-shaped laminates having openings. (2) a step of laminating and pressing a plurality of ceramic green sheets having a conductor pattern serving as an internal wiring conductor to form an intermediate laminate; and (3) a first frame-like laminate on one main surface side of the intermediate laminate. And (4) placing the second frame-shaped laminate on the other main surface side of the intermediate laminate so that the opening thereof is opposed to the inside of the opening of the first frame-shaped laminate. A method for manufacturing a multilayer ceramic circuit board, comprising: a step of performing pressure bonding; and (5) a step of integrally firing the first and second frame-shaped laminates and the intermediate laminate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13894097A JP3793547B2 (en) | 1997-05-28 | 1997-05-28 | Manufacturing method of multilayer ceramic circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13894097A JP3793547B2 (en) | 1997-05-28 | 1997-05-28 | Manufacturing method of multilayer ceramic circuit board |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005206386A Division JP2005354093A (en) | 2005-07-15 | 2005-07-15 | Electronic component packaging substrate and its manufacturing method |
JP2006059605A Division JP2006148177A (en) | 2006-03-06 | 2006-03-06 | Laminated ceramic circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10335823A true JPH10335823A (en) | 1998-12-18 |
JP3793547B2 JP3793547B2 (en) | 2006-07-05 |
Family
ID=15233713
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13894097A Expired - Fee Related JP3793547B2 (en) | 1997-05-28 | 1997-05-28 | Manufacturing method of multilayer ceramic circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3793547B2 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100447554B1 (en) * | 2000-05-16 | 2004-09-08 | 히다찌 에이아이시 가부시키가이샤 | Printed wiring board having cavity |
JP2006128363A (en) * | 2004-10-28 | 2006-05-18 | Kyocera Corp | Multiple patterning wiring board and electronic device |
US7209362B2 (en) | 2002-07-26 | 2007-04-24 | Murata Manufacturing Co., Ltd. | Multilayer ceramic substrate with a cavity |
JPWO2005076351A1 (en) * | 2004-02-09 | 2007-08-02 | 株式会社村田製作所 | Component built-in module and manufacturing method thereof |
JP2008159725A (en) * | 2006-12-22 | 2008-07-10 | Kyocera Corp | Ceramic multi-layered substrate, and its manufacturing method |
JP2008235911A (en) * | 2008-03-26 | 2008-10-02 | Murata Mfg Co Ltd | Low-temperature fired ceramic circuit board and method of manufacturing the same |
JP2010067729A (en) * | 2008-09-10 | 2010-03-25 | Ngk Spark Plug Co Ltd | Manufacturing method of ceramic package |
KR101005491B1 (en) | 2008-07-31 | 2011-01-04 | 주식회사 코리아써키트 | Electronic components embedded pcb and method of manufacturing the same |
WO2014046133A1 (en) * | 2012-09-18 | 2014-03-27 | 京セラ株式会社 | Package for accommodating electronic part, and electronic device |
CN114980580A (en) * | 2022-06-24 | 2022-08-30 | 湖北金禄科技有限公司 | 5G communication circuit board and back-to-back stacked circuit board production and processing method |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0563140A (en) * | 1991-09-03 | 1993-03-12 | Soshin Denki Kk | Structure of hybrid integrated circuit |
JPH0559879U (en) * | 1992-01-14 | 1993-08-06 | 株式会社村田製作所 | Circuit board |
JPH06275739A (en) * | 1993-03-23 | 1994-09-30 | Sony Corp | Adaptor made of ceramics, and ceramic package |
JPH1075058A (en) * | 1996-08-30 | 1998-03-17 | Nec Eng Ltd | Ceramic board and its manufacture |
-
1997
- 1997-05-28 JP JP13894097A patent/JP3793547B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0563140A (en) * | 1991-09-03 | 1993-03-12 | Soshin Denki Kk | Structure of hybrid integrated circuit |
JPH0559879U (en) * | 1992-01-14 | 1993-08-06 | 株式会社村田製作所 | Circuit board |
JPH06275739A (en) * | 1993-03-23 | 1994-09-30 | Sony Corp | Adaptor made of ceramics, and ceramic package |
JPH1075058A (en) * | 1996-08-30 | 1998-03-17 | Nec Eng Ltd | Ceramic board and its manufacture |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100447554B1 (en) * | 2000-05-16 | 2004-09-08 | 히다찌 에이아이시 가부시키가이샤 | Printed wiring board having cavity |
US7209362B2 (en) | 2002-07-26 | 2007-04-24 | Murata Manufacturing Co., Ltd. | Multilayer ceramic substrate with a cavity |
US7569925B2 (en) | 2004-02-09 | 2009-08-04 | Murata Manufacturing Co. Ltd. | Module with built-in component |
JPWO2005076351A1 (en) * | 2004-02-09 | 2007-08-02 | 株式会社村田製作所 | Component built-in module and manufacturing method thereof |
JP2006128363A (en) * | 2004-10-28 | 2006-05-18 | Kyocera Corp | Multiple patterning wiring board and electronic device |
JP4511311B2 (en) * | 2004-10-28 | 2010-07-28 | 京セラ株式会社 | Multi-circuit board and electronic device |
JP2008159725A (en) * | 2006-12-22 | 2008-07-10 | Kyocera Corp | Ceramic multi-layered substrate, and its manufacturing method |
JP2008235911A (en) * | 2008-03-26 | 2008-10-02 | Murata Mfg Co Ltd | Low-temperature fired ceramic circuit board and method of manufacturing the same |
KR101005491B1 (en) | 2008-07-31 | 2011-01-04 | 주식회사 코리아써키트 | Electronic components embedded pcb and method of manufacturing the same |
JP2010067729A (en) * | 2008-09-10 | 2010-03-25 | Ngk Spark Plug Co Ltd | Manufacturing method of ceramic package |
WO2014046133A1 (en) * | 2012-09-18 | 2014-03-27 | 京セラ株式会社 | Package for accommodating electronic part, and electronic device |
JPWO2014046133A1 (en) * | 2012-09-18 | 2016-08-18 | 京セラ株式会社 | Electronic component storage package and electronic device |
CN114980580A (en) * | 2022-06-24 | 2022-08-30 | 湖北金禄科技有限公司 | 5G communication circuit board and back-to-back stacked circuit board production and processing method |
CN114980580B (en) * | 2022-06-24 | 2023-12-19 | 湖北金禄科技有限公司 | Production and processing method of 5G communication circuit board and back-to-back stacked circuit board |
Also Published As
Publication number | Publication date |
---|---|
JP3793547B2 (en) | 2006-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6518502B2 (en) | Ceramic multilayer circuit boards mounted on a patterned metal support substrate | |
JP3531573B2 (en) | Multilayer ceramic electronic component, method of manufacturing the same, and electronic device | |
KR20040031680A (en) | Electronic device and production process thereof | |
KR100489820B1 (en) | Ceramic Multilayer Substrate and its Manufacturing Process | |
JP3793547B2 (en) | Manufacturing method of multilayer ceramic circuit board | |
JP4503871B2 (en) | Manufacturing method of ceramic substrate | |
JP2007251192A (en) | Electronic part mounting circuit board | |
JP2715934B2 (en) | Multilayer printed wiring board device and method of manufacturing the same | |
JP2010067729A (en) | Manufacturing method of ceramic package | |
JP2008072151A (en) | Circuit board | |
JP2000277916A (en) | Substrate and split substrate | |
JPH05327222A (en) | Ceramic multilayer wiring board | |
JP4388410B2 (en) | Multiple wiring board | |
JP3330104B2 (en) | Manufacturing method of multi-cavity ceramic wiring board | |
JPH10200008A (en) | Multilayer circuit board and manufacture thereof | |
JP2006148177A (en) | Laminated ceramic circuit board | |
JP2000068149A (en) | Laminated electronic component and manufacture therefor | |
JPH06252558A (en) | Multilayered glass ceramic cavity substrate | |
JP2001267744A (en) | Laminated ceramic electronic part and its manufacturing method, green laminate for obtaining laminated ceramic electronic part, and electronic device | |
JP2005354093A (en) | Electronic component packaging substrate and its manufacturing method | |
JP2019186441A (en) | Wiring board and manufacturing method of the same | |
JP2942424B2 (en) | Package for storing semiconductor elements | |
JPH0738217A (en) | Ceramic board | |
JP2001160681A (en) | Multilayer ceramic board and its manufacturing method | |
JP2018181995A (en) | Wiring board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040922 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20041026 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20041222 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20050517 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050715 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060110 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060306 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060404 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060408 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090414 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100414 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110414 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110414 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120414 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120414 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130414 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140414 Year of fee payment: 8 |
|
LAPS | Cancellation because of no payment of annual fees |