JPH10282524A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
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- JPH10282524A JPH10282524A JP9367397A JP9367397A JPH10282524A JP H10282524 A JPH10282524 A JP H10282524A JP 9367397 A JP9367397 A JP 9367397A JP 9367397 A JP9367397 A JP 9367397A JP H10282524 A JPH10282524 A JP H10282524A
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- capacitor
- electric charge
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は液晶表示装置に関す
る。[0001] The present invention relates to a liquid crystal display device.
【０００２】[0002]
【従来の技術】一般に、パーソナルコンピュータや携帯
情報端末機（ＰＤＡ）用の液晶表示装置（ＬＣＤ）で
は、バッテリー駆動での使用時間を長くするために、低
消費電力化が要求されているが、スイッチング素子とし
てＴＦＴ（薄膜トランジスタ）を用いた液晶表示装置
（ＴＦＴ−ＬＣＤ）は、画質が優れているが、消費電力
が大きいという問題を有していた。2. Description of the Related Art In general, in a liquid crystal display (LCD) for a personal computer or a personal digital assistant (PDA), low power consumption is required in order to prolong a use time by a battery drive. A liquid crystal display device (TFT-LCD) using a TFT (thin film transistor) as a switching element has excellent image quality, but has a problem of large power consumption.
【０００３】近年、ＴＦＴ−ＬＣＤの開口率の向上技術
やバックライトの発光効率の向上技術が開発され、バッ
クライトにおいては消費電力の低減が達成されつつあ
る。In recent years, techniques for improving the aperture ratio of TFT-LCDs and techniques for improving the luminous efficiency of the backlight have been developed, and the power consumption of the backlight is being reduced.
【０００４】一方、ＴＦＴパネルを駆動する回路につい
ては、ロジック電源とアナログ電源とを一本化して電源
電圧を低下させることで、駆動回路の消費電力を低減す
る方法が採られている。On the other hand, for a circuit for driving a TFT panel, a method has been adopted in which a logic power supply and an analog power supply are unified to lower the power supply voltage, thereby reducing the power consumption of the drive circuit.
【０００５】[0005]
【発明が解決しようとする課題】しかし、従来からのＴ
ＦＴを用いた液晶表示装置では、画質維持の観点から、
信号線を印加する電圧とともに対向電極に印加する電圧
を、１水平（走査）期間（ 1Ｈ）の周期で極性反転する
駆動方法が採られているため、駆動回路の消費電力が増
大し、低消費電力化には限界があった。However, the conventional T
In a liquid crystal display device using FT, from the viewpoint of maintaining image quality,
Since a driving method is employed in which the polarity of the voltage applied to the common electrode together with the voltage applied to the signal line is inverted in a cycle of one horizontal (scanning) period (1H), the power consumption of the drive circuit increases, and the power consumption is reduced There was a limit to electrification.
【０００６】本発明は、このような問題を解決するため
になされたもので、良好な表示画質が得られ、かつ駆動
回路の消費電力が低減された液晶表示装置を提供するこ
とを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a liquid crystal display device capable of obtaining a good display image quality and reducing the power consumption of a driving circuit. .
【０００７】[0007]
【課題を解決するための手段】本発明の液晶表示装置
は、複数の走査線と信号線と、前記走査線を駆動するた
めの走査ドライバと、前記信号線を駆動するための信号
ドライバと、前記走査線と信号線の交点に設けられたス
イッチング素子と、該スイッチング素子を介して前記信
号線に接続された画素電極と、該画素電極との間に液晶
層に印加するための電圧を形成する対向電極と、前記画
素電極の電圧を保持するための補助容量とを備えた液晶
表示装置において、前記補助容量の前記画素電極と反対
側の端部が、走査線ごとに一括されスイッチング素子を
介してコンデンサに接続されており、かつＮ行目の走査
線により画素に信号線の電圧を書き込む１水平期間に、
（Ｎ＋１）行目の走査線に対応する画素および補助容量
に保持された電荷を、前記コンデンサに回収し、この電
荷を次の１水平期間に、前記Ｎ行目の書き込み後の画素
電極に供給し、該画素電極の電位を上昇させる制御を行
なう補助容量駆動部を有することを特徴とする。A liquid crystal display device according to the present invention comprises: a plurality of scanning lines and signal lines; a scanning driver for driving the scanning lines; a signal driver for driving the signal lines; A switching element provided at the intersection of the scanning line and the signal line; a pixel electrode connected to the signal line via the switching element; and a voltage for applying a liquid crystal layer between the pixel electrode and the pixel electrode. In a liquid crystal display device having a common electrode and a storage capacitor for holding a voltage of the pixel electrode, an end of the storage capacitor on the side opposite to the pixel electrode is collectively provided for each scanning line to serve as a switching element. In one horizontal period in which the voltage of the signal line is written to the pixel by the Nth scanning line,
The electric charge held in the pixel corresponding to the (N + 1) th row scanning line and the auxiliary capacitance is collected in the capacitor, and this electric charge is supplied to the pixel electrode after the writing in the Nth row in the next one horizontal period. And a storage capacitor driving unit that performs control to increase the potential of the pixel electrode.
【０００８】本発明の液晶表示装置においては、画素電
極に接続された補助容量の他端部が、走査線ごとに一括
して束ねられ、ＴＦＴのようなスイッチング素子を介し
てコンデンサに接続されている。そして、補助容量駆動
部により、Ｎ行（ライン）目の走査線により画素（容
量）に信号線の電圧を書き込む１水平期間（ 1Ｈ）に、
（Ｎ＋１）ライン目の一括接続された補助容量の他端が
コンデンサに接続され、これらの補助容量および対応す
る画素（容量）に蓄積保持された電荷がこのコンデンサ
に回収されるとともに、次の１水平期間に、Ｎライン目
の一括接続された補助容量の端部がそのコンデンサに接
続され、その結果コンデンサに回収された電荷が、書き
込み後の画素電極に供給・充電されるように制御されて
いる。In the liquid crystal display device of the present invention, the other end of the storage capacitor connected to the pixel electrode is collectively bundled for each scanning line and connected to a capacitor via a switching element such as a TFT. I have. Then, in the one horizontal period (1H) during which the voltage of the signal line is written to the pixel (capacitance) by the Nth row (line) scanning line by the auxiliary capacitance driving unit,
The other end of the collectively connected auxiliary capacitances of the (N + 1) th line is connected to a capacitor, and the electric charge accumulated and held in these auxiliary capacitances and the corresponding pixels (capacitances) is recovered by this capacitor, and the next 1 In the horizontal period, the ends of the N-th collectively connected auxiliary capacitors are connected to the capacitor, and as a result, the charge collected in the capacitor is controlled so as to be supplied and charged to the pixel electrode after writing. I have.
【０００９】このように（Ｎ＋１）ライン目で回収され
た電荷が、次の１水平期間にＮライン目の画素電極の電
位上昇のために再利用され、この再利用により駆動電圧
の低下分が補われるので、画質の劣化を引き起こすこと
なく、駆動回路の消費電力を低減することができる。The electric charge collected in the (N + 1) -th line is reused in the next one horizontal period due to an increase in the potential of the pixel electrode on the N-th line. As a result, the power consumption of the driving circuit can be reduced without deteriorating the image quality.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施例を、図面に
基づいて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１１】図１は、本発明の液晶表示装置の一実施例
を示す基本回路構成図であり、図２は、実施例の液晶表
示装置において、走査線と信号線に印加される駆動電圧
波形と画素の電圧波形および制御信号の入力タイミング
をそれぞれ示す図である。FIG. 1 is a basic circuit configuration diagram showing one embodiment of a liquid crystal display device of the present invention. FIG. 2 is a diagram showing a driving voltage waveform applied to a scanning line and a signal line in the liquid crystal display device of the embodiment. FIG. 3 is a diagram illustrating a voltage waveform of a pixel and an input timing of a control signal.
【００１２】この液晶表示装置は、図１に示すように、
640× 480ドットの表示画素を有するＴＦＴ液晶表示部
１と、走査線（g1〜gn）２を駆動する駆動回路（走査ド
ライバ）３と、信号線（s1〜sm）４を駆動する駆動回路
（信号ドライバ）５と、対向電極駆動回路６、および補
助容量駆動部７から成っている。そして、ＴＦＴ液晶表
示部１においては、マトリクス状に形成された走査線２
と信号線４との交点に、それぞれスイッチング素子であ
るＴＦＴ（Ｔ11〜Ｔnm）８が設けられており、これらの
ＴＦＴ８を介して、 0Ｖで白表示、 5Ｖ印加で黒表示が
それぞれ得られるＴＮ型液晶から成る画素（容量）９が
接続されている。また、これらの画素には、それぞれ画
素電極の電圧を保持するための補助容量（Ｃs11 〜Ｃsn
m ）１０が接続されている。そして、これらの補助容量
１０の画素電極と反対側の端部は、走査線２ごとに一括
して束ねられ、一括接続線（ｌ1 〜ｌn ）１１は補助容
量駆動部（Ｃs 駆動部）７に接続されている。[0012] As shown in FIG.
A TFT liquid crystal display unit 1 having 640 × 480 dot display pixels, a driving circuit (scan driver) 3 for driving scanning lines (g1 to gn) 2, and a driving circuit for driving signal lines (s1 to sm) 4 ( A signal driver) 5, a counter electrode driving circuit 6, and an auxiliary capacitance driving section 7. Then, in the TFT liquid crystal display section 1, the scanning lines 2 formed in a matrix are formed.
TFTs (T11 to Tnm) 8 as switching elements are provided at the intersections of the signal lines 4 and the TN type, respectively, through which a white display at 0 V and a black display at 5 V are obtained. A pixel (capacitor) 9 made of liquid crystal is connected. Each of these pixels has an auxiliary capacitance (Cs11 to Csn) for holding the voltage of the pixel electrode.
m) 10 is connected. The ends of the auxiliary capacitors 10 on the side opposite to the pixel electrodes are bundled together for each scanning line 2, and the collective connection lines (11 to ln) 11 are connected to the auxiliary capacitor driving unit (Cs driving unit) 7. It is connected.
【００１３】信号ドライバ５は、 5Ｖ単一電源で動作す
るＤＡＣ（デジタル−アナログコンバータ）型であり、
入力されたデータに基づくアナログ電圧を信号線４に出
力するようになっている。また、走査ドライバ３は、高
い電圧の走査パルス電圧（Ｖgh＝20Ｖ）をそれぞれの走
査線２に線順次方式で出力し、信号ドライバ５から出力
される電圧をこの走査線２で選択される画素９に書き込
むように構成されている。The signal driver 5 is of a DAC (digital-to-analog converter) type that operates on a single 5 V power supply.
An analog voltage based on the input data is output to the signal line 4. The scanning driver 3 outputs a high-voltage scanning pulse voltage (Vgh = 20 V) to each scanning line 2 in a line-sequential manner, and outputs a voltage output from the signal driver 5 to a pixel selected by the scanning line 2. 9 is written.
【００１４】Ｃs 駆動部７は、走査ドライバ出力の高電
圧（Ｖgh）に接続されたｄライン１２と、対向電極駆動
回路６に接続されたｅライン１３と、電荷回収用コンデ
ンサＣr １４に接続されたｆライン１５と、各ライン１
２、１３、１５と一括接続線（ｌ1 〜ｌn ）１１との間
をスイッチする制御ＴＦＴ１６とから成り、制御ＴＦＴ
（Ｔa1〜Ｔa3、Ｔb1〜Ｔb3、Ｔc1〜Ｔc3）１６は、制御
信号ライン（a1〜a3、b1〜b3、c1〜c3）１７にそれぞれ
印加される制御信号によりオン−オフ動作が制御される
ように成っている。The Cs driving unit 7 is connected to the d line 12 connected to the high voltage (Vgh) of the scanning driver output, the e line 13 connected to the counter electrode driving circuit 6, and the charge recovery capacitor Cr 14. F line 15 and each line 1
2, 13 and 15 and a control TFT 16 for switching between the collective connection lines (11 to ln) 11.
(Ta1 to Ta3, Tb1 to Tb3, Tc1 to Tc3) 16 are controlled so that on-off operations are controlled by control signals applied to control signal lines (a1 to a3, b1 to b3, c1 to c3) 17, respectively. It consists of
【００１５】図２に、本発明の液晶表示装置におけるＣ
s 駆動部７の動作タイミングを示す。但し、Ｖa1〜Ｖa
3、Ｖb1〜Ｖb3、Ｖc1〜Ｖc3は、それぞれ制御信号ライ
ン（a1〜a3、b1〜b3、c1〜c3）１７に印加される制御信
号、Ｖg1〜Ｖg3はそれぞれ走査線（g1〜g3）２の駆動電
圧波形、Ｖs1〜Ｖs3はそれぞれ信号線（s1〜s3）４の駆
動電圧波形、Ｖcom は対向電極電圧波形、Ｖl1〜Ｖl3は
それぞれ束ねられた一括接続線（l1〜l3）１１の電圧波
形をそれぞれ示す。またＶpnm は、 n行目の走査線（g
n）２と m列目の信号線（sm）４により形成される画素
（pnm ）９の電圧波形を示す。なお、１垂直期間（ 1
Ｖ）は16.7ms、１水平期間（ 1Ｈ）は32μｓである。さ
らに、対向電極の電圧Ｖcom としては、直流の電圧が供
給されており、その値は、画素９の電圧Ｖp の振幅の 1
/2に、走査ドライバ３から出力される走査パルス電圧が
ＴＦＴ８を介して画素電極に突き抜ける電圧を加えた値
となっている。FIG. 2 shows C in the liquid crystal display device of the present invention.
s The operation timing of the drive unit 7 is shown. However, Va1 to Va
3, Vb1 to Vb3, Vc1 to Vc3 are control signals applied to the control signal lines (a1 to a3, b1 to b3, c1 to c3) 17, respectively, and Vg1 to Vg3 are the scan lines (g1 to g3) 2, respectively. The driving voltage waveforms, Vs1 to Vs3 are the driving voltage waveforms of the signal lines (s1 to s3) 4, Vcom is the counter electrode voltage waveform, and Vl1 to Vl3 are the voltage waveforms of the bundled connection lines (l1 to l3) 11, respectively. Shown respectively. Vpnm is the scanning line (g
3 shows a voltage waveform of a pixel (pnm) 9 formed by n) 2 and m-th signal lines (sm) 4. Note that one vertical period (1
V) is 16.7 ms, and one horizontal period (1H) is 32 μs. Further, a DC voltage is supplied as the voltage Vcom of the common electrode, and the value of the voltage Vcom is one of the amplitude of the voltage Vp of the pixel 9.
The value obtained by adding a voltage that allows the scan pulse voltage output from the scan driver 3 to pass through the pixel electrode to the pixel electrode via the TFT 8 is added to / 2.
【００１６】ここで、画素９の電圧Ｖp が対向電極の電
圧Ｖcom より高いときを、正極性の書き込み時とする。Here, the time when the voltage Vp of the pixel 9 is higher than the voltage Vcom of the counter electrode is defined as the time of writing with positive polarity.
【００１７】Ｎライン目の走査線２例えばg1が選択さ
れ、これが正極性の書き込み期間（Ｖg1＝20Ｖ）である
とき、制御信号ラインb1１７に印加される制御信号Ｖb1
がオン電圧となっているので、制御ＴＦＴ１６のＴb1が
オン動作となり、画素p11 ９に信号電圧（Ｖs1＝ 5Ｖ）
が書き込まれる（画素電圧Ｖp11 ）。このとき、同じ列
で（Ｎ＋１）ライン目は、画素p21 ９に正極性の電圧が
保持される最後の水平期間（ 1Ｈ）となっている。When an N-th scanning line 2, for example, g1, is selected and this is a positive writing period (Vg1 = 20V), the control signal Vb1 applied to the control signal line b117 is selected.
Is turned on, so that Tb1 of the control TFT 16 is turned on, and a signal voltage (Vs1 = 5V) is applied to the pixel p119.
Is written (pixel voltage Vp11). At this time, the (N + 1) th line in the same column is the last horizontal period (1H) in which the positive voltage is held in the pixel p219.
【００１８】本発明では、（Ｎ＋１）ライン目が極性反
転する直前の電荷が、Ｃｓ駆動部７に設けられた電荷回
収用コンデンサＣr １４により１時的に回収される。す
なわちＮライン目の画素p11 ９に信号電圧を書き込んで
いるとき、同じ列の（Ｎ＋１）ライン目では、制御信号
ラインc2１７に印加される制御信号Ｖc2がオン電圧とな
っているので、制御ＴＦＴ１６のＴc2がオンとなり、一
括接続線ｌ2 は電荷回収用コンデンサＣｒ１４に接続さ
れ、画素p21 ９と補助容量Ｃs21 １０に保持された電荷
がコンデンサＣｒ１４に回収される。回収された電荷
は、Ｎライン目の画素p11 ９の信号電圧書き込み後に画
素電極に供給され、画素電極の電位の上昇のために再び
用いられる。In the present invention, the electric charge immediately before the polarity inversion of the (N + 1) -th line is temporarily collected by the charge collecting capacitor Cr 14 provided in the Cs driving section 7. In other words, when a signal voltage is being written to the pixel p119 of the Nth line, the control signal Vc2 applied to the control signal line c217 is an ON voltage in the (N + 1) th line of the same column. Tc2 is turned on, the collective connection line l2 is connected to the charge recovery capacitor Cr14, and the charge held in the pixel p2 9 and the auxiliary capacitance Cs2 10 is recovered by the capacitor Cr14. The collected charge is supplied to the pixel electrode after the signal voltage of the pixel p119 on the Nth line is written, and is used again to increase the potential of the pixel electrode.
【００１９】再利用のタイミングは次の通りである。す
なわち、Ｎライン目の画素p11 ９に正極性の信号線電圧
を書き込んだ後の１水平期間に、制御信号Ｖc1をオン電
圧にしてＴc1をオンにすることにより、一括接続線ｌ1
は電荷回収用コンデンサＣｒ１４に接続される。その結
果、（Ｎ＋１）ライン目でコンデンサＣr １４に回収さ
れた電荷がＮライン目に供給され、補助容量Ｃs11 １０
とのコンデンサ結合により画素電極の電位が上昇する。
また、このような回収電荷の再利用で不十分な電圧上昇
分は、つづくタイミングで補われる。すなわち、次に制
御信号Ｖa1をオン電圧にしてＴa1をオンにすることによ
り、高いゲート電圧Ｖghが補助容量Ｃs11 を介して画素
p11 ９に印加され、画素電圧Ｖp11 はコンデンサ結合に
より上昇する。The timing of reuse is as follows. That is, the control signal Vc1 is turned on and Tc1 is turned on during one horizontal period after writing the signal line voltage of the positive polarity to the pixel p119 of the Nth line, so that the collective connection line l1
Is connected to the charge recovery capacitor Cr14. As a result, the electric charge collected in the capacitor Cr 14 at the (N + 1) th line is supplied to the Nth line, and the auxiliary capacitance Cs11 10
, The potential of the pixel electrode rises.
Insufficient voltage rise due to such reuse of collected charges is compensated at the subsequent timing. That is, when the control signal Va1 is turned on to turn on Ta1, the high gate voltage Vgh is applied to the pixel via the storage capacitor Cs11.
Applied to p119, the pixel voltage Vp11 rises due to capacitor coupling.
【００２０】一方、負極性が書き込まれるラインでは、
信号電圧の書き込み後、制御信号Ｖb1〜Ｖb3がオン電圧
となり制御ＴＦＴ（Ｔb1〜Ｔb3）１６がオンとなること
で、一括接続線（ｌ1 〜ｌn ）１１は対向電極駆動回路
６に接続され、一般の保持動作となる。On the other hand, in the line where the negative polarity is written,
After the writing of the signal voltage, the control signals Vb1 to Vb3 are turned on and the control TFTs (Tb1 to Tb3) 16 are turned on, so that the collective connection lines (l1 to ln) 11 are connected to the counter electrode driving circuit 6, and Holding operation.
【００２１】このように、Ｃs 駆動部７では、スイッチ
制御信号Ｖa 、Ｖb 、Ｖc によって、各走査線２の画素
電位上昇用電荷の回収と再利用が行なわれる。ところ
で、スイッチ制御信号Ｖa 、Ｖb 、Ｖc は、前記したよ
うにライン毎のタイミングを要する。そこで、本実施例
では、ＴＦＴアレイ基板上のＣs 駆動部７に、これらを
制御するためのスイッチ制御回路を設けている。As described above, in the Cs driving unit 7, the charge for increasing the pixel potential of each scanning line 2 is collected and reused by the switch control signals Va, Vb, and Vc. Incidentally, the switch control signals Va, Vb, and Vc require timing for each line as described above. Therefore, in the present embodiment, a switch control circuit for controlling these is provided in the Cs driver 7 on the TFT array substrate.
【００２２】図３に、スイッチ制御回路の構成を示す。FIG. 3 shows the configuration of the switch control circuit.
【００２３】制御信号Ｖa 、Ｖb 、Ｖc の３系統のシフ
トレジスタ回路を、奇数ライン用、偶数ライン用にそれ
ぞれ設け、外部のゲートアレイから発生させた a odd,b
odd、 c odd、a even、b even、c evenデータをそれぞ
れ入力して、クロックには水平同期信号ＣＰＶを 1/2に
分周した信号を用い、走査線毎に順次シフトさせた。Three shift register circuits of control signals Va, Vb, and Vc are provided for odd-numbered lines and for even-numbered lines, respectively, and a odd, b generated from an external gate array.
Odd, c odd, a even, b even, and c even data were input, respectively, and a signal obtained by dividing the horizontal synchronizing signal CPV by 1/2 was used as a clock and sequentially shifted for each scanning line.
【００２４】このように動作される実施例の液晶表示装
置では、従来の装置ではそのまま捨てていた補助容量Ｃ
s に蓄積された電荷や画素に書き込まれた電荷が回収さ
れ、（Ｎ＋１）ライン目で回収された電荷がＮラィン目
に供給されて、画素電極電位の上昇がなされているの
で、駆動回路の消費電力が効率的に低減される。また、
信号線に印加する電圧を１水平期間（ 1Ｈ）ごとに極性
反転する駆動（Ｈ反転駆動）を、対向電極に直流電圧を
印加する駆動方式により実現することができるので、画
質を良好に維持しながら低消費電力化を図ることができ
る。In the liquid crystal display device of the embodiment operated as described above, in the conventional device, the auxiliary capacitance C is discarded as it is in the conventional device.
Since the electric charge accumulated in s and the electric charge written in the pixel are collected, the electric charge collected in the (N + 1) th line is supplied to the Nth line, and the pixel electrode potential is increased. Power consumption is efficiently reduced. Also,
The driving method of inverting the polarity of the voltage applied to the signal line every one horizontal period (1H) (H inversion driving) can be realized by the driving method of applying a DC voltage to the counter electrode, thereby maintaining good image quality. However, power consumption can be reduced.
【００２５】[0025]
【発明の効果】以上の説明から明らかなように、本発明
の液晶表示装置においては、画素や補助容量に蓄積保持
された電荷が、捨てられることなく回収され、隣接する
ラインの画素電極の電位上昇のために再利用されている
ので、駆動回路の消費電力を低減することができる。ま
た、対向電極に直流電圧を印加し、かつ信号線に印加す
る電圧を１水平期間ごとに極性反転して駆動することが
できるので、画質劣化を引き起こすことなく、良好な画
質の表示を得ることができる。As is apparent from the above description, in the liquid crystal display device of the present invention, the electric charge accumulated and held in the pixel and the auxiliary capacitance is recovered without being discarded, and the potential of the pixel electrode on the adjacent line is recovered. Since it is reused for the rise, the power consumption of the drive circuit can be reduced. In addition, since a DC voltage can be applied to the counter electrode and the voltage applied to the signal line can be inverted with respect to the polarity every one horizontal period, the display can be performed with good image quality without deteriorating the image quality. Can be.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の液晶表示装置の一実施例を示す基本回
路構成図。FIG. 1 is a basic circuit configuration diagram showing one embodiment of a liquid crystal display device of the present invention.
【図２】実施例の液晶表示装置における走査線と信号線
の駆動電圧波形図と画素電圧波形図、および制御信号の
入力タイミングをそれぞれ示す図。FIG. 2 is a diagram showing a driving voltage waveform diagram and a pixel voltage waveform diagram of a scanning line and a signal line in the liquid crystal display device of the embodiment, and a diagram showing an input timing of a control signal, respectively.
【図３】実施例の液晶表示装置において、Ｃs 駆動部内
に設けられたスイッチ制御回路の構成を示し、（ａ）は
奇数ライン用回路、（ｂ）は偶数ライン用回路。FIGS. 3A and 3B show a configuration of a switch control circuit provided in a Cs driving unit in the liquid crystal display device of the embodiment, where FIG. 3A shows a circuit for odd lines and FIG. 3B shows a circuit for even lines.
１………ＴＦＴ液晶表示部 ２………走査線 ３………走査ドライバ ４………信号線 ５………信号ドライバ ６………対向電極駆動回路 ７………補助容量駆動部 ８………ＴＦＴ ９………画素 １０………補助容量 １１………一括接続線 １４………電荷回収用コンデンサ １６………制御ＴＦＴ １７………制御信号ライン DESCRIPTION OF SYMBOLS 1 ... TFT liquid crystal display part 2 ... Scan line 3 ... Scan driver 4 ... Signal line 5 ... Signal driver 6 ... Counter electrode drive circuit 7 ... Auxiliary capacitance drive part 8 ... ...... TFT 9 ...... Pixel 10 ...... Auxiliary capacitance 11 ...... Batch connection line 14 ...... Charge recovery capacitor 16 ...... Control TFT 17 ...... Control signal line
───────────────────────────────────────────────────── フロントページの続き (72)発明者 平井 保功 神奈川県横浜市磯子区新杉田町８番地 株 式会社東芝横浜事業所内 (72)発明者 佐藤 清一 神奈川県川崎市川崎区日進町７番地１ 東 芝電子エンジニアリング株式会社内 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yasutoshi Hirai 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Seiichi Sato 7-Nisshincho, Kawasaki-ku, Kawasaki-shi, Kanagawa 1. Toshiba Electronic Engineering Corporation
Claims (1)
駆動するための走査ドライバと、前記信号線を駆動する
ための信号ドライバと、前記走査線と信号線の交点に設
けられたスイッチング素子と、該スイッチング素子を介
して前記信号線に接続された画素電極と、該画素電極と
の間に液晶層に印加するための電圧を形成する対向電極
と、前記画素電極の電圧を保持するための補助容量とを
備えた液晶表示装置において、 前記補助容量の前記画素電極と反対側の端部が、走査線
ごとに一括されスイッチング素子を介してコンデンサに
接続されており、かつＮ行目の走査線により画素に信号
線の電圧を書き込む１水平期間に、（Ｎ＋１）行目の走
査線に対応する画素および補助容量に保持された電荷
を、前記コンデンサに回収し、この電荷を次の１水平期
間に、前記Ｎ行目の書き込み後の画素電極に供給し、該
画素電極の電位を上昇させる制御を行なう補助容量駆動
部を有することを特徴とする液晶表示装置。A plurality of scanning lines and signal lines; a scanning driver for driving the scanning lines; a signal driver for driving the signal lines; and an intersection of the scanning lines and the signal lines. A switching element, a pixel electrode connected to the signal line via the switching element, a counter electrode for forming a voltage between the pixel electrode and the pixel electrode for applying a voltage to the liquid crystal layer, and holding a voltage of the pixel electrode An end of the auxiliary capacitance opposite to the pixel electrode is collectively connected for each scanning line, connected to a capacitor via a switching element, and connected to the N-th row. In one horizontal period in which the voltage of the signal line is written to the pixel by the scanning line of the first line, the electric charge held in the pixel and the auxiliary capacitance corresponding to the scanning line of the (N + 1) th row is collected by the capacitor, and this electric charge is then transferred to In one horizontal period, a liquid crystal display device characterized by having the supplied to the pixel electrode after writing the N-th row, the auxiliary capacitor driving unit for performing a control for increasing the potential of the pixel electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9367397A JPH10282524A (en) | 1997-04-11 | 1997-04-11 | Liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9367397A JPH10282524A (en) | 1997-04-11 | 1997-04-11 | Liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10282524A true JPH10282524A (en) | 1998-10-23 |
Family
ID=14088931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9367397A Withdrawn JPH10282524A (en) | 1997-04-11 | 1997-04-11 | Liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10282524A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001054108A1 (en) * | 2000-01-21 | 2001-07-26 | Ultrachip, Inc. | System for driving a liquid crystal display with power saving and other improved features |
| KR100369336B1 (en) * | 2000-12-20 | 2003-01-24 | 주식회사 하이닉스반도체 | LCD with energy recovery and method for driving the same |
| EP1345203A1 (en) * | 2002-03-13 | 2003-09-17 | Matsushita Electric Industrial Co., Ltd. | Active matrix liquid crystal panel driving device using multi-phase charge sharing |
| KR100427992B1 (en) * | 2000-03-15 | 2004-04-27 | 샤프 가부시키가이샤 | Active matrix type display apparatus and method for driving the same |
| JP2005031595A (en) * | 2003-07-11 | 2005-02-03 | Toshiba Matsushita Display Technology Co Ltd | Liquid crystal display device, liquid crystal display method, program for the same, and recording medium |
| KR100496844B1 (en) * | 2001-03-15 | 2005-06-22 | 히다치디바이스 엔지니어링가부시키가이샤 | Liquid crystal display device having a low-voltage driving circuit |
| JP2005222072A (en) * | 1997-05-13 | 2005-08-18 | Oki Electric Ind Co Ltd | Driving circuit and method for liquid crystal display device |
| WO2008015813A1 (en) * | 2006-08-02 | 2008-02-07 | Sharp Kabushiki Kaisha | Active matrix substrate and display device with same |
-
1997
- 1997-04-11 JP JP9367397A patent/JPH10282524A/en not_active Withdrawn
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005222072A (en) * | 1997-05-13 | 2005-08-18 | Oki Electric Ind Co Ltd | Driving circuit and method for liquid crystal display device |
| WO2001054108A1 (en) * | 2000-01-21 | 2001-07-26 | Ultrachip, Inc. | System for driving a liquid crystal display with power saving and other improved features |
| KR100427992B1 (en) * | 2000-03-15 | 2004-04-27 | 샤프 가부시키가이샤 | Active matrix type display apparatus and method for driving the same |
| KR100369336B1 (en) * | 2000-12-20 | 2003-01-24 | 주식회사 하이닉스반도체 | LCD with energy recovery and method for driving the same |
| US6961041B2 (en) | 2001-03-15 | 2005-11-01 | Hitachi, Ltd. | Liquid crystal display device having a low-voltage driving circuit |
| US7567230B2 (en) | 2001-03-15 | 2009-07-28 | Hitachi, Ltd. | Liquid crystal display device having a low-voltage driving circuit |
| KR100496844B1 (en) * | 2001-03-15 | 2005-06-22 | 히다치디바이스 엔지니어링가부시키가이샤 | Liquid crystal display device having a low-voltage driving circuit |
| US7764260B2 (en) | 2002-03-13 | 2010-07-27 | Panasonic Corporation | Liquid crystal panel driving device |
| US7084852B2 (en) | 2002-03-13 | 2006-08-01 | Matsushita Electric Industrial Co., Ltd. | Liquid crystal panel driving device |
| CN1311420C (en) * | 2002-03-13 | 2007-04-18 | 松下电器产业株式会社 | Liquid crystal panel driver |
| EP1345203A1 (en) * | 2002-03-13 | 2003-09-17 | Matsushita Electric Industrial Co., Ltd. | Active matrix liquid crystal panel driving device using multi-phase charge sharing |
| US8035602B2 (en) | 2002-03-13 | 2011-10-11 | Panasonic Corporation | Liquid crystal panel driving device |
| JP2005031595A (en) * | 2003-07-11 | 2005-02-03 | Toshiba Matsushita Display Technology Co Ltd | Liquid crystal display device, liquid crystal display method, program for the same, and recording medium |
| WO2008015813A1 (en) * | 2006-08-02 | 2008-02-07 | Sharp Kabushiki Kaisha | Active matrix substrate and display device with same |
| JP4823312B2 (en) * | 2006-08-02 | 2011-11-24 | シャープ株式会社 | Active matrix substrate and display device including the same |
| US8228273B2 (en) | 2006-08-02 | 2012-07-24 | Sharp Kabushiki Kaisha | Active matrix substrate and display device having the same |
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