JPH10242458A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH10242458A JPH10242458A JP9040261A JP4026197A JPH10242458A JP H10242458 A JPH10242458 A JP H10242458A JP 9040261 A JP9040261 A JP 9040261A JP 4026197 A JP4026197 A JP 4026197A JP H10242458 A JPH10242458 A JP H10242458A
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor device
- type
- conductivity type
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 70
- 239000012535 impurity Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 14
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 238000007599 discharging Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は半導体装置、特に
良好な帰還容量特性と低オン電圧化を図る構造部分に特
徴のあるＭＯＳ型の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MOS type semiconductor device characterized by a structure for achieving good feedback capacitance characteristics and low on-voltage.
【０００２】[0002]
【従来の技術】パワーＭＯＳＦＥＴやＩＧＢＴ等のＭＯ
Ｓ構造の半導体装置は、電力用半導体素子やモータドラ
イブ用のインバータ等，パワーデバイスとして種々の用
途に使用されている。2. Description of the Related Art MOs such as power MOSFETs and IGBTs
Semiconductor devices having the S structure are used in various applications as power devices, such as power semiconductor elements and inverters for motor drives.
【０００３】図７は従来の一のＭＯＳ型半導体装置の構
造を示す断面図である。図８は従来の他のＭＯＳ型半導
体装置の構造を示す断面図である。ここで、図７に示す
構造をＡ構造の半導体装置、図８に示す構造をＢ構造の
半導体装置とする。FIG. 7 is a sectional view showing the structure of a conventional MOS type semiconductor device. FIG. 8 is a sectional view showing the structure of another conventional MOS type semiconductor device. Here, the structure illustrated in FIG. 7 is referred to as a semiconductor device having an A structure, and the structure illustrated in FIG. 8 is referred to as a semiconductor device having a B structure.
【０００４】図７に示すＡ構造の半導体装置は、半導体
基板２１上に、Ｎ−型ドリフト領域２２が積層され、同
ドリフト領域２２にＰ型ベース領域２３及びＮ＋型ソー
ス領域２６が設けられ、ドリフト領域２２、ベース領域
２３及びソース領域２６間にポリシリコンで形成される
ゲート電極２５が設けられて構成されている。In the semiconductor device having the structure A shown in FIG. 7, an N− type drift region 22 is stacked on a semiconductor substrate 21, and a P type base region 23 and an N + type source region 26 are provided in the drift region 22. A gate electrode 25 made of polysilicon is provided between the drift region 22, the base region 23, and the source region 26.
【０００５】一方、図８に示すＢ構造の半導体装置に
は、Ａ構造の半導体装置と同様な構成を有する他、ポリ
シリコンゲート電極２５に対向しかつベース領域２３を
除くドリフト領域上の部分に、ドリフト領域２２と同じ
導電型の高濃度のＮ＋型不純物領域２４が設けられてい
る。On the other hand, the semiconductor device having the structure B shown in FIG. 8 has the same structure as that of the semiconductor device having the structure A, and has a portion facing the polysilicon gate electrode 25 and on the drift region excluding the base region 23. , A high-concentration N + -type impurity region 24 of the same conductivity type as the drift region 22 is provided.
【０００６】なお、Ｐ型ベース領域２３、Ｎ＋型ソース
領域２６は、ポリシリコンゲート電極をマスク材として
形成されるものである。ここで、Ｂ構造のようにＰ型ベ
ース領域を形成する前にＮ−型ドリフト領域中に高濃度
のＮ＋型領域を形成しておくと、Ｐ型ベース領域の作成
の際、横方向拡散が抑制され短チャネル化し、またジャ
ンクションＦＥＴ抵抗も小さくできること（ＪＦＥＴ効
果）から、Ａ構造の半導体装置に対してオン電圧が改善
される。The P-type base region 23 and the N + -type source region 26 are formed using a polysilicon gate electrode as a mask material. Here, if a high-concentration N + type region is formed in the N− type drift region before the P type base region is formed as in the case of the B structure, when the P type base region is formed, the lateral diffusion is reduced. Since the channel is suppressed and the channel length is reduced, and the junction FET resistance can be reduced (JFET effect), the ON voltage is improved with respect to the semiconductor device having the A structure.
【０００７】一方、ＭＯＳ型半導体装置の容量特性はド
レイン電圧の依存性を持ち、特にゲート−ドレイン間容
量（帰還容量）は電圧依存性が大きい。帰還容量はゲー
ト酸化膜の絶縁容量と半導体表面に形成される空乏層の
シリーズ容量であるので、Ｂ構造のようにＰ型ベース領
域２３間に高濃度のＮ＋型不純物領域２４が形成される
と、ゲート電極２５下の空乏層ののびが抑制される。し
たがって、Ｂ構造ではゲート電極２５に蓄積される電荷
は高いドレイン電圧になるまで減少しない（以下、この
電荷の放電を帰還容量の低下、ともいう）。On the other hand, the capacitance characteristics of a MOS type semiconductor device depend on the drain voltage, and in particular, the gate-drain capacitance (feedback capacitance) has a large voltage dependence. Since the feedback capacitance is the series capacitance of the insulating capacitance of the gate oxide film and the depletion layer formed on the semiconductor surface, if a high-concentration N + type impurity region 24 is formed between the P type base regions 23 as in the B structure. In addition, the extension of the depletion layer below the gate electrode 25 is suppressed. Therefore, in the B structure, the charge stored in the gate electrode 25 does not decrease until a high drain voltage is reached (hereinafter, discharge of this charge is also referred to as a decrease in feedback capacity).
【０００８】このようにＢ構造の半導体装置では、帰還
容量が高いドレイン電圧になるまで低下しないため、印
加されるドレイン電圧が入力容量と帰還容量とに分圧さ
れ、その結果Ａ構造の場合よりもゲート電位が上昇す
る。これにより、誤動作動作が生じやすくなり、またス
イッチング・ロスの増大等を招くこととなる。As described above, in the semiconductor device having the B structure, since the feedback capacitance does not decrease until the drain voltage becomes high, the applied drain voltage is divided into the input capacitance and the feedback capacitance. Also, the gate potential increases. As a result, malfunctions are likely to occur, and switching loss will increase.
【０００９】[0009]
【発明が解決しようとする課題】上述した従来のＡ，Ｂ
各構造の半導体装置では、容量特性とオン電圧の改善は
相反する関係にあり、どちらか一方の特性を犠牲にしな
ければならないという問題があった。SUMMARY OF THE INVENTION The above-mentioned conventional A, B
In the semiconductor device of each structure, there is a problem that the improvement of the capacitance characteristic and the improvement of the on-voltage are in conflict with each other, and one of the characteristics has to be sacrificed.
【００１０】本発明は、このような実情を考慮してなさ
れたもので、良好な帰還容量特性と低オン電圧とを同時
に実現し、ひいては安定した動作を確保することができ
る構造の半導体装置を提供することを目的とする。The present invention has been made in view of such circumstances, and provides a semiconductor device having a structure capable of simultaneously realizing a good feedback capacitance characteristic and a low on-state voltage and ensuring a stable operation. The purpose is to provide.
【００１１】[0011]
【課題を解決するための手段】本発明の骨子は、ＭＯＳ
型半導体装置の構造に関し、Ｐ型ベース領域の側面にＮ
−型ドリフト領域より濃度の高いＮ＋型領域を形成し、
隣り合うＰ型ベース領域間（ＭＯＳ部）のゲート直下の
中央部分には高濃度Ｎ＋型領域が形成されないようにす
ることで、良好な帰還容量特性と低オン電圧とを同時に
実現することにある。The gist of the present invention is a MOS transistor.
With respect to the structure of the p-type semiconductor device, N
Forming an N + type region having a higher concentration than the − type drift region,
By preventing the formation of the high-concentration N + type region in the central portion immediately below the gate between adjacent P-type base regions (MOS portion), good feedback capacitance characteristics and low on-voltage are simultaneously realized. .
【００１２】また、上記課題の解決は、より具体的に
は、以下のような解決手段により実現される。まず、請
求項１に対応する発明は、半導体基板上に形成された第
１導電型のドリフト領域と、ドリフト領域の一方の主面
に選択的に形成された第２導電型のベース領域と、ベー
ス領域中に選択的に形成された第１導電型のソース領域
と、第１導電型ドリフト領域，第２導電型ベース領域及
び第１伝導型ソース領域上に形成された絶縁膜を介して
形成されたゲート電極を有するＭＯＳ型半導体装置を具
備し、ベース領域の側面にドリフト領域より高濃度に不
純物添加された第１導電型の不純物領域を有し、かつゲ
ート電極下側のドリフト領域には不純物領域よりも不純
物濃度の低い第１導電型領域が形成されている半導体装
置である。[0012] The above-mentioned object can be more specifically achieved by the following means. First, an invention corresponding to claim 1 includes a first conductivity type drift region formed on a semiconductor substrate, a second conductivity type base region selectively formed on one main surface of the drift region, Formed via a first conductivity type source region selectively formed in the base region, and a first conductivity type drift region, a second conductivity type base region, and an insulating film formed on the first conductivity type source region. A MOS type semiconductor device having a doped gate electrode, a first conductivity type impurity region doped at a higher concentration than the drift region on the side surface of the base region, and a drift region below the gate electrode. A semiconductor device in which a first conductivity type region having an impurity concentration lower than an impurity region is formed.
【００１３】本発明は、このような構成を設けたので、
例えばＭＯＳＦＥＴやＩＧＢＴにおいて、ベース領域の
側面に高濃度な不純物領域が存在することで、短チャネ
ル効果及びＪＦＥＴ効果が働きオン電圧が低減される。
さらに、ゲート電極下側の領域には不純物濃度の低い第
１導電型領域が形成されているため、この部分における
帰還容量を小さくでき、低いドレイン電圧でその容量を
減少させることができる。According to the present invention, such a configuration is provided.
For example, in a MOSFET or an IGBT, the presence of a high-concentration impurity region on the side surface of the base region causes a short-channel effect and a JFET effect to reduce the on-voltage.
Further, since the first conductivity type region having a low impurity concentration is formed in the region below the gate electrode, the feedback capacitance at this portion can be reduced, and the capacitance can be reduced at a low drain voltage.
【００１４】したがって、良好な帰還容量特性と低オン
電圧とを同時に実現することができる。次に、請求項２
に対応する発明は、請求項１に対応する発明において、
不純物領域は、ゲート電極下側における不純物濃度の低
い第１導電型領域側の端部を、ゲート電極端部から５μ
ｍ以下の位置に有する半導体装置である。Therefore, good feedback capacitance characteristics and low on-state voltage can be simultaneously realized. Next, claim 2
The invention corresponding to claim 1 is the invention according to claim 1,
The impurity region is formed such that an end on the side of the first conductivity type region having a low impurity concentration below the gate electrode is 5 μm from the end of the gate electrode.
m is a semiconductor device at a position of m or less.
【００１５】本発明は、このような構成を設けたので、
請求項１に対応する発明の半導体装置と同様な作用効果
を奏する他、ゲート電極直下において高濃度不純物領域
の占める面積を確実に小さくすることができるので、よ
り確実に上記効果を奏することができる。The present invention is provided with such a configuration.
In addition to having the same function and effect as the semiconductor device of the invention corresponding to claim 1, the area occupied by the high-concentration impurity region immediately below the gate electrode can be reliably reduced, so that the above-described effect can be more reliably achieved. .
【００１６】また、請求項３に対応する発明は、請求項
１又は２に対応する発明において、不純物濃度の低い第
１導電型領域は、ドリフト領域である半導体装置であ
る。本発明は、このような構成を設けたので、請求項１
又は２に対応する発明の半導体装置と同様な作用効果を
奏する。The invention according to claim 3 is the semiconductor device according to claim 1 or 2, wherein the first conductivity type region having a low impurity concentration is a drift region. The present invention has such a configuration.
Alternatively, the same operation and effect as those of the semiconductor device according to the second aspect of the invention can be obtained.
【００１７】さらに、請求項４に対応する発明は、第１
導電型のドリフト領域と、第２導電型のベース領域と、
第１導電型のソース領域と、絶縁膜を介して形成された
ゲート電極とによって構成されるＭＯＳ型半導体装置を
具備し、ベース領域の側面のドリフト領域側に、ドリフ
ト領域より高濃度に不純物添加された第１導電型の不純
物領域を有し、かつこの不純物領域のゲート電極下側に
占めるゲート電極に対向する面積が、ドリフト領域のゲ
ート電極に対向する面積よりも小さい半導体装置であ
る。Further, the invention according to claim 4 is the first invention.
A conductivity type drift region, a second conductivity type base region,
A MOS type semiconductor device including a first conductivity type source region and a gate electrode formed with an insulating film interposed therebetween, wherein an impurity is doped at a higher concentration than the drift region on a drift region side of a base region; A semiconductor device having a first conductivity type impurity region, wherein an area of the impurity region below the gate electrode and facing the gate electrode is smaller than an area of the drift region facing the gate electrode.
【００１８】本発明は、このような構成を設けたので、
例えば電極を全てチップ表面に有する横形ＭＯＳ型半導
体装置においても、請求項１に対応する発明の半導体装
置と同様な作用効果を奏する。Since the present invention has such a configuration,
For example, the lateral MOS type semiconductor device having all the electrodes on the chip surface has the same operation and effect as the semiconductor device according to the first aspect of the present invention.
【００１９】[0019]
【発明の実施の形態】以下、本発明の実施の形態につい
て説明する。 （発明の第１の実施の形態）図１は本発明の第１の実施
の形態に係る半導体装置の構成例を示す断面図である。Embodiments of the present invention will be described below. (First Embodiment of the Invention) FIG. 1 is a sectional view showing a configuration example of a semiconductor device according to a first embodiment of the present invention.
【００２０】この半導体装置はパワーＭＯＳＦＥＴであ
って、図１に示すように、Ｎ型半導体基板１の主面上に
耐圧系に応じた不純物濃度と厚さで形成されたＮ型ドリ
フト領域２が形成されている。このドリフト領域２上に
は、ゲート酸化膜５ａ及びポリシリコンゲート電極５ｂ
からなるゲート電極５が所定間隔で設けられている。This semiconductor device is a power MOSFET. As shown in FIG. 1, an N-type drift region 2 formed on a main surface of an N-type semiconductor substrate 1 with an impurity concentration and a thickness corresponding to a breakdown voltage system. Is formed. On the drift region 2, a gate oxide film 5a and a polysilicon gate electrode 5b are formed.
Are formed at predetermined intervals.
【００２１】また、ドリフト領域２のゲート電極５側の
主面には不純物注入により拡散形成されたＮ＋型不純物
領域４が選択的に形成されており、さらに不純物領域４
のゲート電極５側の主面にはＰ型ベース領域３、Ｎ＋型
ソース領域６が形成されている。なお、特に図示しない
が、ソース電極、ドレイン電極等のパワーＭＯＳＦＥＴ
としての他の構成要素も設けられている。On the main surface of the drift region 2 on the side of the gate electrode 5, an N + type impurity region 4 diffused and formed by impurity implantation is selectively formed.
A P-type base region 3 and an N + -type source region 6 are formed on the main surface on the side of the gate electrode 5. Although not particularly shown, power MOSFETs such as a source electrode and a drain electrode
Other components are also provided.
【００２２】ここで、Ｎ＋型不純物領域４の構成につい
てさらに詳しく説明する。この半導体装置の製造工程に
おいては、まず不純物領域４がゲート電極５間の位置に
深さ２〜３μｍで形成され、その内側に、主面から不純
物領域４を貫通するようにベース領域３が形成されるた
め、図１に示すように、不純物領域４は、ゲート電極５
下でベース領域３及びドリフト領域２に挟まれる薄い層
として構成されている。ここで、ポリシリコンゲート電
極５ｂの端部から不純物領域４のドリフト領域２側端部
までの距離ｘは５μｍ以下である。したがって、ゲート
酸化膜５ａにおける半導体基板１側の大部分はドリフト
領域２と直接接触している。Here, the structure of the N + type impurity region 4 will be described in more detail. In the manufacturing process of this semiconductor device, first, impurity region 4 is formed at a position between gate electrodes 5 to a depth of 2 to 3 μm, and base region 3 is formed inside main region so as to penetrate impurity region 4 from the main surface. Therefore, as shown in FIG. 1, the impurity region 4
It is configured as a thin layer sandwiched between the base region 3 and the drift region 2 below. Here, distance x from the end of polysilicon gate electrode 5b to the end of impurity region 4 on the drift region 2 side is 5 μm or less. Therefore, most of the gate oxide film 5a on the semiconductor substrate 1 side is in direct contact with the drift region 2.
【００２３】なお、不純物領域４は、ドープ量１０12ｃ
ｍ-3程度のリンＰや砒素Ａｓの添加にされており、ドリ
フト領域２と同導電型の低抵抗不純物領域である。した
がって、この半導体装置では、Ｎ−型ドリフト領域に選
択的高濃度Ｎ＋型領域が形成され、かつゲート電極５中
央部の直下にはＮ＋型領域が形成されない構成となって
いる。The impurity region 4 has a doping amount of 10 12 c
About m −3 of phosphorus P or arsenic As is added, and is a low-resistance impurity region of the same conductivity type as the drift region 2. Therefore, in this semiconductor device, a selectively high-concentration N + type region is formed in the N− type drift region, and no N + type region is formed immediately below the center of the gate electrode 5.
【００２４】図２は本実施の形態の半導体装置を上方か
ら見た図である。同図（ａ）に示すように、この半導体
装置はゲート５としてメッシュゲートが用いられている
（図面一部省略）。なお、同図（ｂ）に示すように、本
実施の形態の半導体装置はゲート５としてストライプゲ
ートを用いる場合（図面一部省略）に適用させてもよ
い。FIG. 2 is a view of the semiconductor device according to the present embodiment as viewed from above. As shown in FIG. 1A, this semiconductor device uses a mesh gate as the gate 5 (part of the drawing is omitted). As shown in FIG. 2B, the semiconductor device of the present embodiment may be applied to a case where a stripe gate is used as the gate 5 (part of the drawing is omitted).
【００２５】次に、以上のように構成された本発明の実
施の形態に係る半導体装置の作用について図３を用いて
説明する。図３は本実施形態の半導体装置におけるＮ＋
型不純物領域及びドリフト領域の作用を説明する図であ
る。Next, the operation of the semiconductor device thus configured according to the embodiment of the present invention will be described with reference to FIG. FIG. 3 shows N + in the semiconductor device of the present embodiment.
FIG. 4 is a diagram for explaining the function of a type impurity region and a drift region.
【００２６】Ｐ型ベース領域３の形成は、ゲート電極５
をマスクとして不純物添加されることで行われる。この
不純物添加の際、高濃度のＮ＋型不純物領域４が前もっ
て形成されていることから、Ｐ型ベース領域４の横方向
の拡散が抑えられる。よって、同図（ａ）に示すように
ベース領域４における短チャネル効果が働き、チャネル
抵抗が小さくなってオン電圧が低減する。The formation of the P-type base region 3 is performed by using the gate electrode 5
This is performed by adding impurities using the mask as a mask. At the time of this impurity addition, since the high-concentration N + type impurity region 4 is formed in advance, the lateral diffusion of the P type base region 4 is suppressed. Therefore, as shown in FIG. 3A, the short channel effect in the base region 4 works, the channel resistance is reduced, and the on-voltage is reduced.
【００２７】次に、オン抵抗はソースからドレインに至
るまでのキャリア経路の抵抗の総和であるが、この中に
ＪＦＥＴ抵抗と呼ばれるものがある。ＪＦＥＴ抵抗は、
ベース領域の両端が４分円になると近似した時のゲート
電極直下から８分円までのベース領域に囲まれた部分に
存在する抵抗である。図３（ｂ）に示す空乏層が広がる
効果（ＪＦＥＴ効果）として把握することもできる。Next, the on-resistance is the sum of the resistances of the carrier paths from the source to the drain. Among them, there is a so-called JFET resistance. The JFET resistance is
This resistance is present in a portion surrounded by the base region from immediately below the gate electrode to the eighth circle when both ends of the base region are approximated to be a quadrant. It can also be understood as the effect (JFET effect) of expanding the depletion layer shown in FIG.
【００２８】さて、ここでベース領域３の外側に高濃度
の不純物領域４が設けられていると、図３（ｂ）に示す
空乏層は広がりにくいものとなる。言い換えると、低抵
抗の不純物領域４の存在によりＪＦＥＴ抵抗の低減がな
されることとなり、オン電圧が低減する。If the high-concentration impurity region 4 is provided outside the base region 3 here, the depletion layer shown in FIG. In other words, the JFET resistance is reduced due to the presence of the low-resistance impurity region 4, and the ON voltage is reduced.
【００２９】以上より、Ｎ＋型不純物領域４の存在は短
チャネル効果及びＪＦＥＴ効果による低オン電圧化に寄
与することになる。したがって、ソース−ドレイン間に
電流が流れている時には、オン抵抗の低減化による利点
を得ることができる。As described above, the presence of the N + type impurity region 4 contributes to the reduction of the on-state voltage due to the short channel effect and the JFET effect. Therefore, when a current flows between the source and the drain, an advantage due to a reduction in on-resistance can be obtained.
【００３０】次に、スイッチングを行う際には、帰還容
量が小さい方が有利である。すなわち、スイッチング速
度は寄生容量を充放電できる速さで決まるからであり、
またスイッチング時に低いドレイン電圧で電荷を放電で
きるからである。Next, when switching is performed, it is advantageous that the feedback capacitance is small. That is, the switching speed is determined by the speed at which the parasitic capacitance can be charged and discharged.
Also, the charge can be discharged with a low drain voltage during switching.
【００３１】さて、本実施形態の構成では、ゲート電極
５直下の大部分にはドリフト領域２が接しており、高濃
度のＮ＋型不純物領域４の接する部分はわずかである。
したがって、図３（ｃ）に示すように、この部分は空乏
層が広がりやすく、帰還容量が小さいと捉えることがで
きる。したがって、低ドレイン電圧から帰還容量の低下
（電荷の放電）が起こることとなる。このため、スイッ
チング時におけるゲート電位の上昇は起こりにくくなっ
ている。In the structure of the present embodiment, the drift region 2 is in contact with most of the portion immediately below the gate electrode 5, and the portion where the high-concentration N + type impurity region 4 is in contact is small.
Therefore, as shown in FIG. 3C, it can be considered that the depletion layer easily spreads in this portion and the feedback capacitance is small. Therefore, a decrease in the feedback capacitance (discharge of electric charge) occurs from a low drain voltage. For this reason, the rise of the gate potential during switching is unlikely to occur.
【００３２】上述したように、本発明の実施の形態に係
る半導体装置によれば、ＭＯＳ型半導体装置の構造に関
し、Ｐ型ベース領域３の側面にＮ−型ドリフト領域より
濃度の高いＮ＋型不純物領域４を形成し、隣り合うＰ型
ベース領域３間（ＭＯＳ部）のゲート直下の中央部分に
は高濃度Ｎ＋型領域が形成されていない構成としたの
で、短チャネル化及びＪＦＥＴ効果による低オン電圧化
を図ることができ、かつ帰還容量を低ドレイン電圧から
減少させることができる。As described above, according to the semiconductor device according to the embodiment of the present invention, with respect to the structure of the MOS type semiconductor device, an N + type impurity having a higher concentration than the N− type drift region is provided on the side surface of the P type base region 3. Since the region 4 is formed and the high-concentration N + type region is not formed in the central portion immediately below the gate between the adjacent P-type base regions 3 (MOS portion), low ON-state due to short channel and JFET effect is achieved. The voltage can be increased, and the feedback capacitance can be reduced from a low drain voltage.
【００３３】このようにオン電圧を低減し、かつ帰還容
量特性の改善によるゲート電位の上昇をおこりにくくし
たので、スイッチングの発振・誤動作を抑えることがで
き、スイッチングロスも低減できる。As described above, since the ON voltage is reduced and the gate potential is hardly increased due to the improvement of the feedback capacitance characteristic, the switching oscillation and malfunction can be suppressed, and the switching loss can be reduced.
【００３４】また、ＪＦＥＴ抵抗を低減し、ベース領域
３外側における空乏層の広がりを抑えることができるた
め素子間隔を小さくすることができるとともに、本実施
形態の装置は従来と同様な工程で製造できるので、オン
電圧の改善によるチップ縮小が可能となり、製造コスト
の低減を図ることができる。In addition, since the JFET resistance can be reduced and the expansion of the depletion layer outside the base region 3 can be suppressed, the element spacing can be reduced, and the device of the present embodiment can be manufactured by the same process as the conventional one. Therefore, the chip can be reduced by improving the on-state voltage, and the manufacturing cost can be reduced.
【００３５】なお、本実施形態の半導体装置ではベース
領域３は不純物領域４を突き抜けて形成されるとした
が、本発明はこれに限られるものでなく、ゲート電極５
直下の構成が同様であればベース領域３が不純物領域４
を突き抜けないように形成されてもよい。また、ゲート
電極の材料は、ポリシリコンに限られるものでなく、他
の材料を使用してもよい。Although the base region 3 is formed to penetrate the impurity region 4 in the semiconductor device of the present embodiment, the present invention is not limited to this.
If the structure immediately below is the same, the base region 3 becomes the impurity region 4
May be formed so as not to pass through. Further, the material of the gate electrode is not limited to polysilicon, and another material may be used.
【００３６】さらに、本実施形態の半導体装置ではＮチ
ャネル型ＭＯＳＦＥＴを構成させた場合について説明し
たが、本発明はこれに限られるものでない。例えば半導
体ウェーハの選択によりＩＧＢＴにも適用できる。ま
た、導電型を逆にすることでＰチャネル型についても適
用できる。Further, in the semiconductor device of the present embodiment, the case where an N-channel MOSFET is formed has been described, but the present invention is not limited to this. For example, the present invention can be applied to an IGBT by selecting a semiconductor wafer. Further, the present invention can be applied to a P-channel type by reversing the conductivity type.
【００３７】以下に、本実施形態をＩＧＢＴに適用した
場合における静特性及び容量特性を図４及び図５に示
す。図４は、本発明の構造と従来の構造のＩＧＢＴにお
ける静特性（Ｉｃ−Ｖｃｅ）の比較例を示す図である。FIGS. 4 and 5 show static characteristics and capacitance characteristics when the present embodiment is applied to an IGBT. FIG. 4 is a diagram showing a comparative example of the static characteristics (Ic-Vce) of the IGBT having the structure of the present invention and the conventional structure.
【００３８】図５は、本発明の構造と従来の構造のＩＧ
ＢＴにおける容量特性（Ｃｒｅｓ−Ｖｃｅ）の比較例を
示す図である。図４，図５においてＡ構造、Ｂ構造とい
うのは、従来技術で図７，図８により説明した各構造を
ＩＧＢＴに適用したものである。FIG. 5 shows an IG of the structure of the present invention and an IG of the conventional structure.
It is a figure showing the comparative example of the capacity characteristic (Cres-Vce) in BT. 4 and 5, the structures A and B are obtained by applying the structures described with reference to FIGS. 7 and 8 in the related art to the IGBT.
【００３９】図４に示すように、本発明のＩＧＢＴで
は、オン抵抗が低減されているので、従来のＡ構造のも
のに比べ静特性が良好なものとなっている。具体的に
は、低オン電圧化により、パラメータｇm ＝ΔＩc ／Δ
Ｖge（ここでΔＩc はコレクタ電流、ΔＶgeはゲート電
圧）が高くなり、静特性の傾きが大きくなっているもの
である。As shown in FIG. 4, in the IGBT of the present invention, the on-resistance is reduced, so that the static characteristics are better than those of the conventional A structure. Specifically, the parameter g m = ΔI c / Δ
V ge (where [Delta] I c is the collector current, [Delta] V ge gate voltage) becomes higher, in which the gradient of the static characteristics increases.
【００４０】一方、図５には、本発明のＩＧＢＴでは、
Ｂ構造のものに比べ、帰還容量が低ドレイン電圧から減
少することが示されている。つまり、本発明のＩＧＢＴ
では、Ａ構造及びＢ構造の双方の利点が得られるように
なっている。 （発明の第２の実施の形態）本実施形態では、図１に示
す第１の実施形態で説明した半導体装置の製造方法につ
いて説明する。On the other hand, FIG. 5 shows that in the IGBT of the present invention,
It is shown that the feedback capacitance is reduced from a low drain voltage as compared with that of the B structure. That is, the IGBT of the present invention
Thus, the advantages of both the A structure and the B structure can be obtained. (Second Embodiment of the Invention) In this embodiment, a method of manufacturing the semiconductor device described in the first embodiment shown in FIG. 1 will be described.
【００４１】図６は本発明の第２の実施の形態の半導体
装置製造方法における主要な製造工程の一例を示す図で
あり、図１と同一部分には同一符号を付して説明を省略
する。FIG. 6 is a view showing an example of main manufacturing steps in a semiconductor device manufacturing method according to the second embodiment of the present invention. The same parts as those in FIG. .
【００４２】まず、ドリフト領域２の製造までは、一般
的な半導体装置の場合と同様であり、その説明を省略す
る。次に、図６（ａ）に示すように、Ｎ型ドリフト領域
２の主面上にドープ量１０12ｃｍ-3程度のリンＰや砒素
Ａｓを添加して選択的な領域にＮ＋型不純物領域４を形
成する。この不純物領域４の形成は、ドープ剤となる不
純物をイオン注入し２〜３（μｍ）の深さに拡散して行
う。またその他の一般的な手法を用いてもよい。なお、
この不純物領域４は、ポリシリコンゲート電極が形成さ
れる部分（正確にはその１〜２（μｍ）内側）を除いて
形成される。First, the process up to the manufacture of the drift region 2 is the same as that of a general semiconductor device, and a description thereof will be omitted. Next, as shown in FIG. 6A , phosphorus P or arsenic As having a doping amount of about 10 12 cm −3 is added to the main surface of the N-type drift region 2 to selectively add an N + type impurity region to a selective region. 4 is formed. The formation of the impurity region 4 is performed by ion-implanting an impurity serving as a dopant to a depth of 2 to 3 (μm). Further, other general methods may be used. In addition,
This impurity region 4 is formed except for a portion where the polysilicon gate electrode is formed (more precisely, the inside of 1-2 (μm) thereof).
【００４３】次に、ゲート酸化膜を形成し、ポリシリコ
ンをゲート電極５として形成する。（図６（ｂ））。次
に、ポリシリコンをマスク材としてイオン注入によりＰ
型ベース領域３を形成する（図６（ｃ））。Next, a gate oxide film is formed, and polysilicon is formed as the gate electrode 5. (FIG. 6 (b)). Next, P is formed by ion implantation using polysilicon as a mask material.
The mold base region 3 is formed (FIG. 6C).
【００４４】以下、Ｎ＋型ソース領域を形成し、さらに
ソース電極その他の構成要素も設け、半導体装置として
完成させる。上述したように、本発明の実施の形態の半
導体装置製造方法によれば、Ｎ＋型不純物領域４を形成
する工程を設けただけなので、従来の半導体装置の製造
とほとんど同様にして、第１の実施形態の半導体装置を
製造することができる。Hereinafter, an N + type source region is formed, and further, a source electrode and other components are provided to complete the semiconductor device. As described above, according to the method of manufacturing a semiconductor device of the embodiment of the present invention, only the step of forming the N + type impurity region 4 is provided. The semiconductor device of the embodiment can be manufactured.
【００４５】なお、本実施形態ではＮチャネル型ＭＯＳ
ＦＥＴの半導体装置を製造する場合について説明した
が、本発明はこれに限られるものでなく、ＩＧＢＴにも
適用できる。また、導電型を逆にすることでＰチャネル
型についても適用できる。また、本発明は、上記各実施
の形態に限定されるものでなく、その要旨を逸脱しない
範囲で種々に変形することが可能である。In this embodiment, the N-channel MOS
Although the case of manufacturing a semiconductor device of an FET has been described, the present invention is not limited to this, and can be applied to an IGBT. Further, the present invention can be applied to a P-channel type by reversing the conductivity type. In addition, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof.
【００４６】[0046]
【発明の効果】以上詳記したように本発明によれば、Ｎ
−型ドリフト領域にベースと接する高濃度Ｎ＋型領域を
形成し、かつゲート直下にはそのＮ＋型領域がほどんど
形成されない構成としたので、良好な帰還容量特性と低
オン電圧とを同時に実現し、ひいては安定した動作を確
保することができる構造の半導体装置を提供することが
できる。As described in detail above, according to the present invention, N
Since a high-concentration N + type region in contact with the base is formed in the − type drift region and the N + type region is hardly formed immediately below the gate, good feedback capacitance characteristics and low on-voltage are simultaneously realized. Thus, a semiconductor device having a structure capable of ensuring stable operation can be provided.
【図１】本発明の第１の実施の形態に係る半導体装置の
構成例を示す断面図。FIG. 1 is a sectional view showing a configuration example of a semiconductor device according to a first embodiment of the present invention.
【図２】同実施の形態の半導体装置を上方から見た図。FIG. 2 is a view of the semiconductor device of the embodiment as viewed from above;
【図３】同実施形態の半導体装置におけるＮ＋型不純物
領域及びドリフト領域の作用を説明する図。FIG. 3 is an exemplary view for explaining the function of an N + type impurity region and a drift region in the semiconductor device according to the embodiment;
【図４】本発明の構造と従来の構造のＩＧＢＴにおける
静特性（Ｉｃ−Ｖｃｅ）の比較例を示す図。FIG. 4 is a diagram showing a comparative example of static characteristics (Ic-Vce) of IGBTs of the structure of the present invention and a conventional structure.
【図５】本発明の構造と従来の構造のＩＧＢＴにおける
容量特性（Ｃｒｅｓ−Ｖｃｅ）の比較例を示す図。FIG. 5 is a diagram showing a comparative example of capacitance characteristics (Cres-Vce) of the IGBT having the structure of the present invention and the conventional structure.
【図６】本発明の第２の実施の形態の半導体装置製造方
法における主要な製造工程の一例を示す図。FIG. 6 is a diagram showing an example of main manufacturing steps in a semiconductor device manufacturing method according to a second embodiment of the present invention.
【図７】従来の一のＭＯＳ型半導体装置の構造を示す断
面図。FIG. 7 is a sectional view showing the structure of a conventional MOS type semiconductor device.
【図８】従来の他のＭＯＳ型半導体装置の構造を示す断
面図。FIG. 8 is a sectional view showing the structure of another conventional MOS type semiconductor device.
１…半導体基板 ２…ドリフト領域 ３…ベース領域 ４…不純物領域 ５…ゲート電極 ６…ソース領域 REFERENCE SIGNS LIST 1 semiconductor substrate 2 drift region 3 base region 4 impurity region 5 gate electrode 6 source region
Claims (4)
ドリフト領域と、前記ドリフト領域の一方の主面に選択
的に形成された第２導電型のベース領域と、前記ベース
領域中に選択的に形成された第１導電型のソース領域
と、前記第１導電型ドリフト領域，前記第２導電型ベー
ス領域及び前記第１伝導型ソース領域上に形成された絶
縁膜を介して形成されたゲート電極を有するＭＯＳ型半
導体装置を具備し、 前記ベース領域の側面に前記ドリフト領域より高濃度に
不純物添加された第１導電型の不純物領域を有し、かつ
ゲート電極下側の前記ドリフト領域には前記不純物領域
よりも不純物濃度の低い第１導電型領域が形成されてい
ることを特徴とする半導体装置。A first conductivity type drift region formed on a semiconductor substrate; a second conductivity type base region selectively formed on one main surface of the drift region; A source region of the first conductivity type selectively formed, and an insulating film formed on the first conductivity type drift region, the second conductivity type base region, and the first conductivity type source region. A MOS type semiconductor device having a gate electrode, a first conductivity type impurity region doped at a higher concentration than the drift region on a side surface of the base region, and the drift region below the gate electrode. A first conductivity type region having an impurity concentration lower than that of the impurity region.
における前記不純物濃度の低い第１導電型領域側の端部
を、前記ゲート電極端部から５μｍ以下の位置に有する
ことを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the impurity region has an end on the side of the first conductivity type region having a low impurity concentration below the gate electrode at a position of 5 μm or less from the end of the gate electrode. Item 2. The semiconductor device according to item 1.
は、前記ドリフト領域であることを特徴とする請求項１
又は２記載の半導体装置。3. The drift region according to claim 1, wherein the first conductivity type region having a low impurity concentration is the drift region.
Or the semiconductor device according to 2.
型のベース領域と、第１導電型のソース領域と、絶縁膜
を介して形成されたゲート電極とによって構成されるＭ
ＯＳ型半導体装置を具備し、 前記ベース領域の側面の前記ドリフト領域側に、前記ド
リフト領域より高濃度に不純物添加された第１導電型の
不純物領域を有し、かつこの不純物領域の前記ゲート電
極下側に占めるゲート電極に対向する面積が、前記ドリ
フト領域のゲート電極に対向する面積よりも小さいこと
を特徴とする半導体装置。4. A semiconductor device comprising a first conductivity type drift region, a second conductivity type base region, a first conductivity type source region, and a gate electrode formed via an insulating film.
An OS type semiconductor device, a first conductivity type impurity region doped at a higher concentration than the drift region on a side of the base region on the drift region side, and the gate electrode of the impurity region; A semiconductor device, wherein an area occupying a lower side of the drift region facing the gate electrode is smaller than an area of the drift region facing the gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9040261A JPH10242458A (en) | 1997-02-25 | 1997-02-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9040261A JPH10242458A (en) | 1997-02-25 | 1997-02-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10242458A true JPH10242458A (en) | 1998-09-11 |
Family
ID=12575732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9040261A Pending JPH10242458A (en) | 1997-02-25 | 1997-02-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10242458A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1058317A2 (en) * | 1999-06-03 | 2000-12-06 | Intersil Corporation | Low voltage dual-well MOS device |
| JP2005005578A (en) * | 2003-06-13 | 2005-01-06 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| DE102008015690A1 (en) | 2007-09-14 | 2009-04-02 | Mitsubishi Electric Corp. | Semiconductor device |
| JP2011204711A (en) * | 2010-03-24 | 2011-10-13 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| JP2012064741A (en) * | 2010-09-16 | 2012-03-29 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| JP2012235001A (en) * | 2011-05-06 | 2012-11-29 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method therefor |
| WO2014046073A1 (en) * | 2012-09-24 | 2014-03-27 | 住友電気工業株式会社 | Silicon carbide semiconductor device and fabrication method for same |
| CN104409507A (en) * | 2014-12-08 | 2015-03-11 | 武汉大学 | Low-on-resistance VDMOS device and preparing method thereof |
| JP2020031133A (en) * | 2018-08-22 | 2020-02-27 | トヨタ自動車株式会社 | Switching element |
-
1997
- 1997-02-25 JP JP9040261A patent/JPH10242458A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1058317A2 (en) * | 1999-06-03 | 2000-12-06 | Intersil Corporation | Low voltage dual-well MOS device |
| EP1058317A3 (en) * | 1999-06-03 | 2002-11-13 | Intersil Corporation | Low voltage dual-well MOS device |
| JP2005005578A (en) * | 2003-06-13 | 2005-01-06 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| DE102008015690A1 (en) | 2007-09-14 | 2009-04-02 | Mitsubishi Electric Corp. | Semiconductor device |
| US7741655B2 (en) | 2007-09-14 | 2010-06-22 | Mitsubishi Electric Corporation | Semiconductor device |
| JP2011204711A (en) * | 2010-03-24 | 2011-10-13 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| JP2012064741A (en) * | 2010-09-16 | 2012-03-29 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| JP2012235001A (en) * | 2011-05-06 | 2012-11-29 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method therefor |
| WO2014046073A1 (en) * | 2012-09-24 | 2014-03-27 | 住友電気工業株式会社 | Silicon carbide semiconductor device and fabrication method for same |
| CN104409507A (en) * | 2014-12-08 | 2015-03-11 | 武汉大学 | Low-on-resistance VDMOS device and preparing method thereof |
| JP2020031133A (en) * | 2018-08-22 | 2020-02-27 | トヨタ自動車株式会社 | Switching element |
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