JPH10242335A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH10242335A
JPH10242335A JP9044027A JP4402797A JPH10242335A JP H10242335 A JPH10242335 A JP H10242335A JP 9044027 A JP9044027 A JP 9044027A JP 4402797 A JP4402797 A JP 4402797A JP H10242335 A JPH10242335 A JP H10242335A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
wiring layer
layers
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9044027A
Other languages
Japanese (ja)
Inventor
Yoshifumi Moriyama
好文 森山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9044027A priority Critical patent/JPH10242335A/en
Publication of JPH10242335A publication Critical patent/JPH10242335A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To provide a multi-functional module to be a semiconductor device which allots the functions of a substrate and wiring layers to realize a small and light-wt. device and improve the connection reliability, substrate productivity and assembling efficiency. SOLUTION: The device comprises a ceramic structure 1 having standardized via conductors 2 and lands 3 but no wiring layer inside, org. wiring layers 4A, 4B having resin insulation layers 5A, 5B or conductive layers 6 laminated on both surfaces of the substrate 1, semiconductor elements 8 connected to the conductive layers 6 through connecting electrodes 7, and outer electrodes 10. The elements 8 are connected to externals through the conductor layers 6 of the layers 4A, 4B and via conductors 2 of the substrate 1. The substrate 1 has only connections between the front and back surfaces, thus enhancing the dimensional stability of the layers 4A, 4B designed to have a laminate structure easy to peel off the pattern and absorbs the stress at connecting components.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置に関し、
特に回路配線基板上に半導体素子などの電子部品を実装
してなる半導体装置に関する。The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having electronic components such as semiconductor elements mounted on a circuit wiring board.

【０００２】[0002]

【従来の技術】従来、この種の半導体装置は、大型コン
ピュータのプロセッシングユニット等の比較的大規模な
集積回路に用いられている。2. Description of the Related Art Conventionally, this kind of semiconductor device is used for a relatively large-scale integrated circuit such as a processing unit of a large-sized computer.

【０００３】かかる半導体装置は、構造上の特徴とし
て、セラミック多層基板の片側にポリイミド系樹脂等の
絶縁層および銅（Ｃｕ）などの導体層からなる有機配線
層を形成しており、しかもこの有機配線層を多層構造と
している場合が多い。特に、このセラミック多層基板は
比較的高価であるため、機能の高い部分を小型モジュー
ル化することにより、基板としての特徴が生かされてい
る。Such a semiconductor device has a structural feature that an organic wiring layer composed of an insulating layer such as a polyimide resin and a conductor layer such as copper (Cu) is formed on one side of a ceramic multilayer substrate. In many cases, the wiring layer has a multilayer structure. In particular, since the ceramic multilayer substrate is relatively expensive, the features of the substrate are exploited by miniaturizing a high-function portion into a small module.

【０００４】例えば、特開平１−１４０７９６号公報の
図１などに記されているように、セラミック多層基板上
にＣｕとポリイミドからなる有機配線層を形成し、半導
体素子をフリップチップ実装したもの、あるいは特開昭
６０−１０６９８号公報の図２などに記されているよう
に、セラミック基板にリード状の端子を設けたものなど
が一般的である。For example, as shown in FIG. 1 of JP-A-1-140796, an organic wiring layer made of Cu and polyimide is formed on a ceramic multilayer substrate, and a semiconductor element is flip-chip mounted. Alternatively, as shown in FIG. 2 of JP-A-60-10698, a ceramic substrate provided with lead-shaped terminals is generally used.

【０００５】図４はかかる従来の一例を説明するための
半導体装置の断面図である。図４に示すように、従来の
半導体装置は、内部に複数の第１の配線層６ａ，６ｂを
形成し且つこれらの第１の配線層６ａ，６ｂを電気的に
接続する導体部２ａを備えたセラミック基板１ａと、こ
のセラミック基板１ａ上に形成されるとともに、ポリイ
ミド絶縁膜１５ａ，１５ｂおよび複数の第２の配線層１
６ａ，１６ｂからなる有機配線層４と、セラミック基板
１ａの導体部２ａにはんだ付けされる外部接続のための
外部端子１７とを有し、回路モジュールを形成してい
る。この回路モジュールは高機能化されているため、基
板のサイズとして、５０ｍｍ角以上の大きさになる場合
が多い。FIG. 4 is a cross-sectional view of a semiconductor device for explaining one example of the related art. As shown in FIG. 4, the conventional semiconductor device includes a plurality of first wiring layers 6a and 6b formed therein, and a conductor 2a for electrically connecting the first wiring layers 6a and 6b. Ceramic substrate 1a, polyimide insulating films 15a and 15b and a plurality of second wiring layers 1 formed on the ceramic substrate 1a.
It has an organic wiring layer 4 composed of 6a and 16b, and an external terminal 17 for external connection soldered to the conductor 2a of the ceramic substrate 1a to form a circuit module. Since this circuit module is sophisticated, the size of the substrate is often 50 mm square or more.

【０００６】このように、従来の半導体装置は、ベース
となる基板（コア基板）にセラミック基板を用い、回路
モジュールを形成しているため、外部端子１７はかかる
回路モジュールを実装するボードとの整合をとり易いリ
ード状の端子にする必要があり、しかもリード状の外部
端子１７はロウ付けなどの手法により、セラミック基板
１ａの周囲または基板裏面に設けられている。As described above, in the conventional semiconductor device, since the circuit module is formed by using the ceramic substrate as the base substrate (core substrate), the external terminals 17 are aligned with the board on which the circuit module is mounted. It is necessary to use a lead-like terminal which is easy to remove, and the lead-like external terminal 17 is provided around the ceramic substrate 1a or on the back surface of the substrate by a method such as brazing.

【０００７】また、半導体装置としての回路モジュール
は、セラミック基板１ａと有機配線層４をそれぞれ多層
構造としているため、小規模なものでも８層以上の積層
が可能であり、実用上十分な配線構造が得られている。Further, the circuit module as a semiconductor device has a multilayer structure of the ceramic substrate 1a and the organic wiring layer 4, so that even a small-scale circuit module can have eight or more laminated layers, and a wiring structure sufficient for practical use. Has been obtained.

【０００８】[0008]

【発明が解決しようとする課題】上述した従来の半導体
装置は、コア基板としてセラミック基板を用いた場合、
基板自体が高価となるため、民生的用途には価格の面で
用いられにくいという問題がある。The above-described conventional semiconductor device uses a ceramic substrate as a core substrate.
Since the substrate itself is expensive, there is a problem in that it is difficult to use it for consumer use in terms of price.

【０００９】その理由は、セラミック多層基板をベース
基板としているため、その部分のコストそのものが高い
ことが挙げられる。また、個片基板の状態で外部端子取
り付けや有機配線層の形成を行うため、総じて基板コス
トが高くなってしまうからである。The reason is that the cost itself of the portion is high because the ceramic multilayer substrate is used as the base substrate. In addition, since external terminals are attached and the organic wiring layer is formed in the state of the individual substrate, the substrate cost is generally increased.

【００１０】また、従来の半導体装置は、完成されたパ
ッケージの専用性が高いことが挙げられる。つまり、基
本的に高い設計自由度を有するものの、一度できあがっ
た製品の設計変更は行いにくいという問題がある。In addition, the conventional semiconductor device is characterized in that the completed package has a high degree of exclusiveness. That is, although there is basically a high degree of freedom in design, there is a problem that it is difficult to change the design of a product once completed.

【００１１】その理由は、設計変更が必要となった場
合、セラミック多層基板と有機配線層の両方を開発する
ことになり、開発コストが大きくなるからである。The reason is that if a design change is required, both the ceramic multilayer substrate and the organic wiring layer will be developed, and the development cost will increase.

【００１２】本発明の主たる目的は、このようなコア基
板としてのセラミック基板と有機配線層の持つ機能を振
り分け、回路モジュールとして小型・軽量化するととも
に、高集積化を図った半導体装置を提供することにあ
る。A main object of the present invention is to provide a semiconductor device which has a ceramic substrate as a core substrate and a function of an organic wiring layer, which is reduced in size and weight as a circuit module, and which is highly integrated. It is in.

【００１３】また、本発明の他の目的は、有機配線層を
介して、電子部品あるいはパッケージの実装を行うこと
により、接続の信頼性を高めた半導体装置を提供するこ
とにある。Another object of the present invention is to provide a semiconductor device in which an electronic component or a package is mounted via an organic wiring layer, so that connection reliability is improved.

【００１４】さらに、本発明の他の目的は、セラミック
基板を標準化した構造とすることにより、基板の生産性
を高めると同時に、回路モジュールとしての組立て効率
を向上させ、大幅なコストダウンを実現できる半導体装
置を提供することにある。Further, another object of the present invention is to improve the productivity of the substrate, improve the efficiency of assembling the circuit module, and realize a significant cost reduction by using a standardized structure of the ceramic substrate. It is to provide a semiconductor device.

【００１５】[0015]

【課題を解決するための手段】本発明の半導体装置は、
表裏面を結合するための規則的に配列されたビア導体を
備えるとともに、内部には配線層が形成されない絶縁性
基板と、前記絶縁性基板の両面にそれぞれ樹脂絶縁層お
よび導体層を積層して形成された第１および第２の有機
配線層と、前記第１の有機配線層の前記導体層に接続さ
れる半導体素子などの電子部品とを有し、前記電子部品
は前記第１および第２の有機配線層の前記導体層および
前記絶縁性基板の前記ビア導体を介して外部に電気的に
接続されるように構成される。According to the present invention, there is provided a semiconductor device comprising:
Along with regularly arranged via conductors for bonding the front and back surfaces, an insulating substrate in which no wiring layer is formed, and a resin insulating layer and a conductor layer laminated on both surfaces of the insulating substrate, respectively. It has first and second organic wiring layers formed, and electronic components such as semiconductor elements connected to the conductor layers of the first organic wiring layers, wherein the electronic components are the first and second organic wiring layers. And electrically connected to the outside via the conductor layer of the organic wiring layer and the via conductor of the insulating substrate.

【００１６】また、本発明の半導体装置における絶縁性
基板は、セラミックを基材とするセラミック基板を用い
ることができる。Further, as the insulating substrate in the semiconductor device of the present invention, a ceramic substrate having a ceramic base material can be used.

【００１７】また、本発明の半導体装置におけるビア導
体の少なくとも一部は、格子状もしくは市松状に配置さ
れる。Further, at least a part of the via conductor in the semiconductor device of the present invention is arranged in a lattice shape or a checkered shape.

【００１８】また、本発明の半導体装置におけるビア導
体は、絶縁性基板の表面および裏面への露出部近傍にコ
ンタクトランドを形成している。Further, the via conductor in the semiconductor device of the present invention forms a contact land near the exposed portion on the front surface and the back surface of the insulating substrate.

【００１９】また、本発明の半導体装置における絶縁性
基板は、その表裏面の端部に有機配線層を形成しない基
板露出部を形成することができる。Further, the insulating substrate in the semiconductor device of the present invention can have an exposed portion of the substrate on which no organic wiring layer is formed at the front and back ends.

【００２０】また、本発明の半導体装置における第１の
有機配線層は、その上面に電子部品と接続するための部
品接続電極を形成し、第２の有機配線層は、その上面に
外部に接続するための外部電極を形成している。Further, in the semiconductor device of the present invention, the first organic wiring layer has a component connection electrode for connecting to an electronic component on the upper surface, and the second organic wiring layer has an external connection on the upper surface. External electrodes are formed.

【００２１】また、本発明の半導体装置における電子部
品は、バンプ電極を備え、第１の有機配線層の部品接続
電極にバンプ接続することができる。Further, the electronic component in the semiconductor device of the present invention has a bump electrode, and can be bump-connected to the component connection electrode of the first organic wiring layer.

【００２２】さらに、本発明の半導体装置における第２
の有機配線層の外部電極は、はんだバンプを形成するこ
とができる。Further, in the semiconductor device of the present invention, the second
The external electrodes of the organic wiring layer can form solder bumps.

【００２３】[0023]

【発明の実施の形態】次に、本発明の実施の形態ついて
図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.

【００２４】図１は本発明の第１の実施の形態を説明す
るための半導体装置の断面図である。図１に示すよう
に、この実施の形態における半導体装置は、複数のビア
導体２および表裏両面に形成するとともに、ビア導体２
の両端に接続されるコンタクトランド３を備えた絶縁性
基板としてのセラミック基板１と、このセラミック基板
１の上面（表面）側に形成し且つ樹脂絶縁層５Ａ，配線
導体６および樹脂絶縁層５Ｂからなる第１の有機配線層
４Ａと、セラミック基板１の下面（裏面）側に形成し且
つ樹脂絶縁層５Ａ，配線導体６および樹脂絶縁層５Ｂか
らなる第２の有機配線層４Ｂと、第１の有機配線層４Ａ
の上に形成した部品接続電極７と、部品接続電極７にボ
ンディングワイヤ９を介して（あるいははんだ実装方
式）接続される半導体素子８と、第２の有機配線層４Ｂ
の上に形成した外部との接続のための外部電極１０と、
第１，第２の有機配線層４Ａ，４Ｂ上に形成された各電
極７，１０が接続される個所などの所定個所を覆った樹
脂絶縁層５Ｃとを有している。ここで、ビア導体２と接
続されるコンタクトランド３は、セラミック基板１の表
裏面上に規則正しく並べられ、通常格子状または市松状
に配置される。この結果、半導体素子８は第１および第
２の有機配線層４Ａ，４Ｂの配線導体６およびセラミッ
ク基板１のビア導体２を介して外部に電気的に接続され
ることになる。FIG. 1 is a sectional view of a semiconductor device for explaining a first embodiment of the present invention. As shown in FIG. 1, the semiconductor device according to the present embodiment is formed on a plurality of via conductors 2 and on both front and back surfaces.
A ceramic substrate 1 as an insulating substrate provided with contact lands 3 connected to both ends of the ceramic substrate 1 and a resin insulating layer 5A, a wiring conductor 6, and a resin insulating layer 5B formed on the upper surface (front surface) of the ceramic substrate 1. A first organic wiring layer 4A, a second organic wiring layer 4B formed on the lower surface (back surface) side of the ceramic substrate 1 and including a resin insulating layer 5A, a wiring conductor 6, and a resin insulating layer 5B; Organic wiring layer 4A
Component connection electrode 7 formed thereon, semiconductor element 8 connected to component connection electrode 7 via bonding wire 9 (or solder mounting method), and second organic wiring layer 4B
An external electrode 10 for connection to the outside formed on the
And a resin insulating layer 5C formed on the first and second organic wiring layers 4A and 4B and covering a predetermined location such as a location where the electrodes 7 and 10 are connected. Here, the contact lands 3 connected to the via conductors 2 are regularly arranged on the front and back surfaces of the ceramic substrate 1 and are usually arranged in a lattice or checkered pattern. As a result, the semiconductor element 8 is electrically connected to the outside via the wiring conductors 6 of the first and second organic wiring layers 4A and 4B and the via conductor 2 of the ceramic substrate 1.

【００２５】まず、ビア導体２とコンタクトランド３を
有するセラミック基板１の表裏面に、配線導体６と樹脂
絶縁層５Ａ，５Ｂからなる第１，第２の有機配線層４
Ａ，４Ｂが形成される。このセラミック基板１は、厚さ
０．２〜２．０ｍｍのアルミナ基板を用いる。このアル
ミナ基板は、コア材として十分な強度を有し、金型加工
あるいはレーザーによる穴あけ加工により、高精度なビ
アホール（バイアホール）形成が可能であり、比較的廉
価な材料である。このような特性を有する材料であれ
ば、窒化アルミ，炭化ケイ素など他のセラミック材を使
用することも可能である。First, on the front and back surfaces of a ceramic substrate 1 having a via conductor 2 and a contact land 3, a first and a second organic wiring layer 4 composed of a wiring conductor 6 and resin insulating layers 5A and 5B are provided.
A and 4B are formed. As the ceramic substrate 1, an alumina substrate having a thickness of 0.2 to 2.0 mm is used. This alumina substrate has a sufficient strength as a core material, is capable of forming a highly accurate via hole (via hole) by die processing or laser drilling, and is a relatively inexpensive material. Other ceramic materials such as aluminum nitride and silicon carbide can be used as long as they have such characteristics.

【００２６】また、本実施の形態では、セラミック基板
１の一方の面、例えば表面側の第１の有機配線層４Ａを
形成した後に、他方の面、すなわち裏面側の第２の有機
配線層４Ｂにより回路形成を行うため、反りの少ない材
質としてセラミック基板を用いる例を示したが、配線層
形成が可能な範囲で基材の強度が確保できれば、セラミ
ック以外の材料、例えば樹脂材を用いることもできる。Further, in the present embodiment, after one surface of the ceramic substrate 1, for example, the first organic wiring layer 4 A on the front surface side is formed, the other surface, ie, the second organic wiring layer 4 B on the back surface side, is formed. An example in which a ceramic substrate is used as a material having a small amount of warpage for forming a circuit according to the present invention has been described. it can.

【００２７】一方、有機配線層４Ａ，４Ｂを形成する樹
脂絶縁層５Ａ〜５Ｃとしては、ビルドアップ基板材料と
して用いられているエポキシ系樹脂またはポリイミド系
樹脂を用いる。樹脂絶縁層５Ａ〜５Ｃの厚みは、下地と
なるセラミック基板１の平坦性にによっても差が生じ、
概ね１０〜５０μｍ程度である。これら樹脂絶縁層５Ａ
〜５Ｃのビアホール形成は、フォトビア加工，レーザー
加工等の方式があるが、一般に言われているビルドアッ
プ基板の加工と同様の工程で行われる。また、有機配線
層４Ａ，４Ｂを形成する配線導体６は、銅箔をアディテ
ィブ法で形成し、その厚さは５〜２０μｍ程度とする。On the other hand, as the resin insulating layers 5A to 5C forming the organic wiring layers 4A and 4B, an epoxy resin or a polyimide resin used as a build-up substrate material is used. The thickness of the resin insulating layers 5A to 5C also differs depending on the flatness of the ceramic substrate 1 as a base,
It is about 10 to 50 μm. These resin insulating layers 5A
The formation of via holes of 5C to 5C includes methods such as photo via processing and laser processing, and is performed in the same process as that of generally-known processing of a build-up substrate. The wiring conductors 6 forming the organic wiring layers 4A and 4B are formed of a copper foil by an additive method and have a thickness of about 5 to 20 μm.

【００２８】さらに、セラミック基板１のビア導体２
は、その上部にコンタクトランド３を設ける構造として
いるが、この構造は、ビルドアップ（積層）する導体層
６の位置ずれを吸収し、確実に接続を行えるようにする
ためである。特に、絶縁性基板としてセラミック基板１
を用いた場合のビア導体２には、モリブデンまたはタン
グステン等の高融点金属を用いる。Further, the via conductor 2 of the ceramic substrate 1
Has a structure in which the contact land 3 is provided on the upper part thereof, but this structure is to absorb the positional displacement of the conductor layer 6 to be built up (laminated) and to make sure the connection. In particular, the ceramic substrate 1 is used as an insulating substrate.
Is used as the via conductor 2 using a high melting point metal such as molybdenum or tungsten.

【００２９】図２は図１におけるセラミック基板の平面
図である。図２に示すように、このセラミック基板１
は、セラミックを基材とし、ビア導体２およびこのビア
導体２に表裏面の近傍で接続されるコンタクトランド３
は、格子状もしくは市松状に配置される。なお、この規
則的配置は一部でもよい。FIG. 2 is a plan view of the ceramic substrate shown in FIG. As shown in FIG.
Are made of a ceramic base material, and a contact land 3 connected to the via conductor 2 near the front and back surfaces of the via conductor 2
Are arranged in a lattice or checkered pattern. This regular arrangement may be a part.

【００３０】要するに、このセラミック基板１は、表裏
面に形成する２つの配線層を接続させる機能のみで済む
ため、構造が簡単になると同時に、標準化できるという
利点がある。In short, the ceramic substrate 1 has only the function of connecting the two wiring layers formed on the front and back surfaces, so that there is an advantage that the structure can be simplified and standardized.

【００３１】このように、ビア導体２，コンタクトラン
ド３が規則的に形成されたセラミック基板１の必要とす
るコンタクトランド３を選択的に使用して基板表配線部
と基板裏配線部を接続することにより、セラミック基板
１は複数の回路モジュールに対して共通の部材として扱
うことができるようになる。また、セラミック基板１の
有機配線層４Ａの上には、半導体素子８等の電子部品を
実装する部品接続電極７を形成しており、有機配線層４
Ｂの上には、外部（他のボード基板等）に接続する外部
電極１０を形成している。すなわち、基板裏面のコンタ
クトランド３より引き出された配線導体６を用い、任意
の場所にランド電極を形成することにより、外部電極１
０とすることができる。この外部電極１０は、はんだ接
続により他のボード基板への実装が可能である。As described above, the contact land 3 required by the ceramic substrate 1 on which the via conductors 2 and the contact lands 3 are regularly formed is selectively used to connect the front wiring portion and the rear wiring portion of the substrate. Thus, the ceramic substrate 1 can be handled as a common member for a plurality of circuit modules. On the organic wiring layer 4A of the ceramic substrate 1, a component connection electrode 7 for mounting an electronic component such as a semiconductor element 8 is formed.
On B, an external electrode 10 connected to the outside (another board substrate or the like) is formed. That is, by using the wiring conductor 6 drawn out from the contact land 3 on the back surface of the substrate and forming a land electrode at an arbitrary position, the external electrode 1 is formed.
It can be set to 0. This external electrode 10 can be mounted on another board substrate by solder connection.

【００３２】しかるに、従来はセラミック基板１ａ上に
形成したランドと他のボード基板とを接続する場合、ボ
ード基板とモジュール基板との熱膨張係数差によるスト
レスの発生が問題となっていたが、本実施の形態の構造
によれば、樹脂絶縁層５Ａ，５Ｂを積層してなる有機配
線層４Ａ，４Ｂが発生した応力を吸収し、ボードとの接
続に対しても高い接続信頼性を確保することができる。
また、本実施の形態においては、基板内には配線層を形
成せず、しかも垂直に形成される外部ピンもないため、
半導体装置としても小型化および軽量化することができ
る。Conventionally, when connecting a land formed on the ceramic substrate 1a to another board substrate, stress has been a problem due to a difference in thermal expansion coefficient between the board substrate and the module substrate. According to the structure of the embodiment, the organic wiring layers 4A and 4B formed by laminating the resin insulating layers 5A and 5B absorb the generated stress and ensure high connection reliability even when connecting to the board. Can be.
Further, in the present embodiment, since no wiring layer is formed in the substrate and there are no external pins formed vertically,
The size and weight of the semiconductor device can also be reduced.

【００３３】要するに、本実施の形態による半導体装置
は、コアとなる絶縁性基板としてのセラミック基板と、
この基板を挟んで上，下に形成する有機配線層と、上側
の有機配線層に搭載する半導体素子とを有し、セラミッ
ク基板には、表裏面を結合し且つ少なくとも一部が規則
的に配列されたビア導体を備えることにより、基板の導
体部としてはビア導体およびコンタクトランドだけであ
るので、セラミック基板そのものを標準化された構造と
することができ、異なる製品に対して共通の部材とする
ことができる。また、回路パターンの引き廻しは、有機
配線層に委ねることにより、廉価で自由度の高い基板開
発を実現することができる。In short, the semiconductor device according to the present embodiment includes a ceramic substrate as an insulating substrate serving as a core;
It has an organic wiring layer formed above and below the substrate, and a semiconductor element mounted on the upper organic wiring layer. The ceramic substrate has its front and back surfaces joined and at least a part thereof is regularly arranged. By providing a via conductor, the conductor part of the substrate is only the via conductor and the contact land, so that the ceramic substrate itself can have a standardized structure, and a common member for different products Can be. In addition, if circuit wiring is entrusted to an organic wiring layer, it is possible to realize an inexpensive and highly flexible substrate development.

【００３４】図３は本発明の第２の実施の形態を説明す
るための半導体装置の断面図である。図３に示すよう
に、この実施の形態は、小型モジュールに適用した例で
あり、より小型化可能なバンプ構造を採用するととも
に、絶縁性基板としてのセラミック基板１は、分割しや
すくするために、その端部に有機配線層４Ａ，４Ｂを形
成しないセラミック露出部１１を形成したことにある。FIG. 3 is a sectional view of a semiconductor device for explaining a second embodiment of the present invention. As shown in FIG. 3, this embodiment is an example in which the present invention is applied to a small module. In addition to adopting a bump structure that can be further miniaturized, the ceramic substrate 1 as an insulating substrate is made to be easily divided. That is, the ceramic exposed portion 11 in which the organic wiring layers 4A and 4B are not formed is formed at the end.

【００３５】まず、厚さ０．４ｍｍのアルミナセラミッ
ク基板１は、１ｍｍピッチの格子状に配列したビア導体
２と、表裏面でビア導体２を覆うコンタクトランド３と
を備えている。このベースとなる基板１にエポキシ系樹
脂からなる樹脂絶縁層５と配線導体６を積層し有機配線
層４Ａ，４Ｂを形成する。なお、絶縁層５については、
説明を簡略化するため、一まとめにしている。First, an alumina ceramic substrate 1 having a thickness of 0.4 mm is provided with via conductors 2 arranged in a lattice pattern at a pitch of 1 mm, and contact lands 3 covering the via conductors 2 on the front and back surfaces. A resin insulating layer 5 made of an epoxy resin and a wiring conductor 6 are laminated on the substrate 1 serving as a base to form organic wiring layers 4A and 4B. In addition, about the insulating layer 5,
For simplicity of description, they are grouped together.

【００３６】ここで、有機配線層４Ａ，４Ｂ内部に形成
される配線回路層、すなわち配線導体６が表裏各１〜３
層程度の低層数である場合は、ベースとなる基板１の材
質はガラスエポキシ材とすることも可能である。Here, the wiring circuit layer formed inside the organic wiring layers 4A and 4B, that is, the wiring conductor 6 is formed on each of the front and back surfaces 1-3.
When the number of layers is as low as the number of layers, the material of the substrate 1 serving as a base may be a glass epoxy material.

【００３７】また、有機配線層４Ａは、表面に半導体素
子８をバンプ電極１２によってバンプ接続するための電
極ランドになる部品接続電極７を形成している。この電
極ランドは、約１００μｍピッチレベルのファインパタ
ーン化が必要となるが、ビルドアップ形成される導体層
としての配線導体６はこれらの加工が可能である。On the surface of the organic wiring layer 4A, component connection electrodes 7 serving as electrode lands for bump connection of the semiconductor element 8 with the bump electrodes 12 are formed. The electrode lands need to be finely patterned at a pitch level of about 100 μm, and the wiring conductor 6 as a conductor layer to be built up can be processed.

【００３８】さらに、有機配線層４Ｂは、ランド電極と
なる外部電極１０を形成するが、実装性を高めるために
あらかじめはんだを供給し、はんだバンプ１３を形成し
ておいてもよい。本例のように、小型のモジュールの組
み立て行う場合、複数の基板を編集し、集合基板として
おいた方が効率が良い。Further, the organic wiring layer 4B forms the external electrodes 10 serving as land electrodes. However, solder may be supplied in advance to improve the mountability, and the solder bumps 13 may be formed. When assembling a small module as in this example, it is more efficient to edit a plurality of boards and to set them as an aggregate board.

【００３９】本実施の形態においては、半導体モジュー
ルの周囲、すなわち端部の樹脂絶縁層５を取り除き、セ
ラミック露出部１１を設けておくことにより、基板１の
分割が可能になるので、モジュールそのものが小型にな
った場合でも、編集基板のまま組立て工程を通すことが
できる。実際の基板１の分割は、レーザー光を照射して
っ分割溝を形成するレーザースクライブ法の適用が可能
である。なお、レーザースクライブ法は、基板製造工
程、組立て工程を終了した後の工程で行うことができる
ため、前工程における基板割れを発生させずに済み、し
かもスクライブラインを任意に設定できるため、少量多
品種のモジュールの生産にも対応が可能である。In the present embodiment, the substrate 1 can be divided by removing the resin insulating layer 5 around the semiconductor module, that is, by removing the resin insulating layer 5 at the end and providing the ceramic exposed section 11. Even in the case where the size is reduced, the assembling process can be performed without changing the editing board. For actual division of the substrate 1, a laser scribing method of forming a division groove by irradiating a laser beam can be applied. Note that the laser scribe method can be performed in a step after the substrate manufacturing step and the assembling step are completed, so that the substrate can be prevented from cracking in the previous step, and the scribe line can be set arbitrarily. It is also possible to produce modules of various types.

【００４０】また、本実施の形態においても、コア材と
なるセラミック基板１のビア導体２を選択的に使用して
有機配線層４Ａ，４Ｂの配線導体６と接続し、使用され
ないビア導体２は配線層４Ａ，４Ｂとの接続を行わない
まま基板１中に放置される。このような構造とすること
により、コア材となるセラミック基板１を標準部材と
し、回路配線はビルドアップ層として基板１の表裏に形
成する有機配線層４Ａ，４Ｂにパターン形成することが
できる。Also in the present embodiment, the via conductor 2 of the ceramic substrate 1 serving as a core material is selectively used to be connected to the wiring conductor 6 of the organic wiring layers 4A and 4B, and the unused via conductor 2 is formed. The substrate is left in the substrate 1 without being connected to the wiring layers 4A and 4B. By adopting such a structure, the ceramic substrate 1 serving as a core material can be used as a standard member, and circuit wiring can be formed as a build-up layer on the organic wiring layers 4A and 4B formed on the front and back surfaces of the substrate 1.

【００４１】要するに、本実施の形態による半導体装置
は、コアとなる絶縁性基板としてのセラミック基板と、
この基板を挟んで上，下に形成する有機配線層と、上側
の有機配線層に搭載する半導体素子とを有し、セラミッ
ク基板には、表裏面を結合し且つ少なくとも一部が規則
的に配列されたビア導体を備えるとともに、半導体素子
にバンプ電極を、外部電極にはんだバンプを設けること
により、半導体素子を基板上にバンプ接続する際にも、
接続部に対するストレスを緩和することができ、高い接
続信頼性を得ることができる。In short, the semiconductor device according to the present embodiment includes a ceramic substrate as a core insulating substrate,
It has an organic wiring layer formed above and below the substrate, and a semiconductor element mounted on the upper organic wiring layer. The ceramic substrate has its front and back surfaces joined and at least a part thereof is regularly arranged. By providing a via conductor, a bump electrode is provided on the semiconductor element, and a solder bump is provided on the external electrode.
Stress on the connection part can be reduced, and high connection reliability can be obtained.

【００４２】さらに、上述した２つの実施の形態の他に
も、各種の変形例が可能である。すなわち、セラミック
基板１のビア導体２は、格子状あるいは市松状に規則的
に配置することを述べたが、用途によっては半導体装置
としてのパッケージのサイズを限定し、そのパッケージ
の中で周辺部にのみ配列するように配置する等の規則性
を保った状態で、ビア導体２を配置することもできる。
かかるビア導体配置に規則性を持たせることは、基板の
汎用性を高めると同時に、有機配線層における配線導体
設計を容易にすることになる。Further, in addition to the above-described two embodiments, various modifications are possible. That is, it has been described that the via conductors 2 of the ceramic substrate 1 are regularly arranged in a lattice shape or a checkered shape. However, depending on the application, the size of the package as a semiconductor device is limited, and in the peripheral portion in the package. The via conductors 2 can be arranged in a state where regularity is maintained such that the via conductors 2 are arranged.
Providing regularity in the via conductor arrangement increases the versatility of the substrate and facilitates the design of the wiring conductor in the organic wiring layer.

【００４３】また、ビア導体２の各表裏両端部に形成さ
れるコンタクトランド３は、例えば１ｍｍピッチの格子
状では、ランド径０．４〜０．６ｍｍφの円形としてそ
の効果がある。しかし、このランド３の形状は、四角
形，楕円形等ビア導体の配置などにより任意に設定可能
である。実際、このランド３は、位置合わせマークを兼
ね、周期的にランド形状またはサイズを変えてもよい。
特に、セラミック基板をを使用したときには、有機配線
層における導体パターンの形成は、印刷で行われるの
で、任意の場所に導体パターンを形成することができ
る。このため、コンタクトランド３の間に導体による位
置合わせマーク等のパターンを入れることができ、好都
合である。The contact lands 3 formed on both the front and back ends of the via conductor 2 have a circular shape with a land diameter of 0.4 to 0.6 mm, for example, in a 1 mm pitch lattice. However, the shape of the land 3 can be arbitrarily set according to the arrangement of via conductors such as a square and an ellipse. In fact, the land 3 may also serve as an alignment mark, and may have a periodically changed land shape or size.
In particular, when a ceramic substrate is used, since the formation of the conductor pattern in the organic wiring layer is performed by printing, the conductor pattern can be formed at an arbitrary position. Therefore, a pattern such as an alignment mark made of a conductor can be provided between the contact lands 3, which is convenient.

【００４４】[0044]

【発明の効果】以上説明したように、本発明の半導体装
置は、コア材となる絶縁性基板、特にセラミック基板を
標準化し且つその基板の表裏に形成する有機配線層を多
層化容易なビルドアップ（積層）構造とすることによ
り、それぞれの機能を活かすことができるので、小型・
軽量化するとともに、接続の信頼性を高めた高精度で多
ピン化（高集積化）対応可能な回路モジュールを実現で
き、しかも基板開発費を不要にするとともに、全体のコ
ストを下げることができるという効果がある。As described above, according to the semiconductor device of the present invention, an insulating substrate as a core material, in particular, a ceramic substrate is standardized, and an organic wiring layer formed on the front and back of the substrate is easily multi-layered. By adopting a (laminated) structure, each function can be utilized.
It is possible to realize a high-precision, high-pin-count (high-integration) circuit module with reduced connection weight and improved connection reliability, and to eliminate the need for board development costs and reduce the overall cost. This has the effect.

【００４５】また、本発明の半導体装置は、絶縁性基板
に標準化配列されたビア導体だけを備え、そのビア導体
の必要な個所を選択的に使用して基板表裏の接続を行う
とともに、有機配線層をビルドアップ（積層）構造とす
ることにより、回路パターンの引き廻しが容易になり、
回路モジュール内部のパーン設計の自由度を大きくでき
るという効果がある。Further, the semiconductor device of the present invention is provided with only via conductors arranged in a standardized manner on an insulating substrate. By making the layer a build-up (laminated) structure, it is easy to route circuit patterns,
There is an effect that the degree of freedom in designing the pan inside the circuit module can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態を説明するための半
導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device for describing a first embodiment of the present invention.

【図２】図１におけるセラミック基板の平面図である。FIG. 2 is a plan view of the ceramic substrate in FIG.

【図３】本発明の第２の実施の形態を説明するための半
導体装置の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device for explaining a second embodiment of the present invention.

【図４】従来の一例を説明するための半導体装置の断面
図である。FIG. 4 is a cross-sectional view of a semiconductor device for explaining an example of the related art.

【符号の説明】[Explanation of symbols]

１ セラミック基板 ２ ビア導体 ３ コンタクトランド ４Ａ，４Ｂ 有機配線層 ５，５Ａ〜５Ｃ 樹脂絶縁層 ６ 配線導体 ７ 部品接続電極 ８ 半導体素子 ９ ボンディングワイヤ １０ 外部電極 １１ セラミック露出部 １２ バンプ電極 １３ はんだバンプ DESCRIPTION OF SYMBOLS 1 Ceramic board 2 Via conductor 3 Contact land 4A, 4B Organic wiring layer 5, 5A-5C Resin insulating layer 6 Wiring conductor 7 Component connection electrode 8 Semiconductor element 9 Bonding wire 10 External electrode 11 Ceramic exposure part 12 Bump electrode 13 Solder bump

Claims (8)

【特許請求の範囲】[Claims] 【請求項１】 表裏面を結合するための規則的に配列さ
れたビア導体を備えるとともに、内部には配線層が形成
されない絶縁性基板と、前記絶縁性基板の両面にそれぞ
れ樹脂絶縁層および導体層を積層して形成された第１お
よび第２の有機配線層と、前記第１の有機配線層の前記
導体層に接続される半導体素子などの電子部品とを有
し、前記電子部品は前記第１および第２の有機配線層の
前記導体層および前記絶縁性基板の前記ビア導体を介し
て外部に電気的に接続されることを特徴とする半導体装
置。An insulating substrate provided with regularly arranged via conductors for coupling the front and back surfaces and having no wiring layer formed therein, and a resin insulating layer and a conductor on both surfaces of the insulating substrate, respectively. A first organic wiring layer formed by stacking layers, and an electronic component such as a semiconductor element connected to the conductor layer of the first organic wiring layer. A semiconductor device, wherein the semiconductor device is electrically connected to the outside via the conductor layer of the first and second organic wiring layers and the via conductor of the insulating substrate. 【請求項２】 前記絶縁性基板は、セラミックを基材と
するセラミック基板を用いた請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the insulating substrate is a ceramic substrate having a ceramic base material. 【請求項３】 前記ビア導体の少なくとも一部は、格子
状もしくは市松状に配置される請求項１記載の半導体装
置。3. The semiconductor device according to claim 1, wherein at least a part of said via conductor is arranged in a lattice or checkered pattern. 【請求項４】 前記ビア導体は、前記絶縁性基板の表面
および裏面への露出部近傍にコンタクトランドを形成し
た請求項１記載の半導体装置。4. The semiconductor device according to claim 1, wherein said via conductor has a contact land formed in the vicinity of an exposed portion on a front surface and a back surface of said insulating substrate. 【請求項５】 前記絶縁性基板は、その表裏面の端部に
前記有機配線層を形成しない基板露出部を形成した請求
項１記載の半導体装置。5. The semiconductor device according to claim 1, wherein the insulative substrate has a substrate exposed portion where the organic wiring layer is not formed at an end of the front and back surfaces. 【請求項６】 前記第１の有機配線層は、その上面に前
記電子部品と接続するための部品接続電極を形成し、前
記第２の有機配線層は、その上面に外部に接続するため
の外部電極を形成した請求項１記載の半導体装置。6. The first organic wiring layer has a component connection electrode for connecting to the electronic component on an upper surface thereof, and the second organic wiring layer has an upper surface for connecting to an external device. 2. The semiconductor device according to claim 1, wherein an external electrode is formed. 【請求項７】 前記電子部品は、バンプ電極を備え、前
記第１の有機配線層の前記部品接続電極にバンプ接続さ
れる請求項６記載の半導体装置。7. The semiconductor device according to claim 6, wherein the electronic component has a bump electrode, and is connected to the component connection electrode of the first organic wiring layer by a bump. 【請求項８】 前記第２の有機配線層の前記外部電極
は、はんだバンプを形成した請求項６記載の半導体装
置。8. The semiconductor device according to claim 6, wherein said external electrodes of said second organic wiring layer form solder bumps.
JP9044027A 1997-02-27 1997-02-27 Semiconductor device Pending JPH10242335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9044027A JPH10242335A (en) 1997-02-27 1997-02-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9044027A JPH10242335A (en) 1997-02-27 1997-02-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH10242335A true JPH10242335A (en) 1998-09-11

Family

ID=12680172

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9044027A Pending JPH10242335A (en) 1997-02-27 1997-02-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH10242335A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100390969C (en) * 2001-05-30 2008-05-28 株式会社日立制作所 Semiconductor device
CN100452349C (en) * 2004-06-07 2009-01-14 株式会社东芝 Computer implemented method for designing a semiconductor device, an automated design system and a semiconductor device
JP2009164462A (en) * 2008-01-09 2009-07-23 Fujitsu Microelectronics Ltd Circuit substrate, manufacturing method therefor and semiconductor device
US7649252B2 (en) 2003-12-26 2010-01-19 Murata Manufacturing Co., Ltd. Ceramic multilayer substrate
JP2012099861A (en) * 1999-09-02 2012-05-24 Ibiden Co Ltd Printed wiring board
US8717772B2 (en) 1999-09-02 2014-05-06 Ibiden Co., Ltd. Printed circuit board
US8780573B2 (en) 1999-09-02 2014-07-15 Ibiden Co., Ltd. Printed circuit board

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012099861A (en) * 1999-09-02 2012-05-24 Ibiden Co Ltd Printed wiring board
JP2012114457A (en) * 1999-09-02 2012-06-14 Ibiden Co Ltd Printed wiring board
US8717772B2 (en) 1999-09-02 2014-05-06 Ibiden Co., Ltd. Printed circuit board
US8763241B2 (en) 1999-09-02 2014-07-01 Ibiden Co., Ltd. Method of manufacturing printed wiring board
US8780573B2 (en) 1999-09-02 2014-07-15 Ibiden Co., Ltd. Printed circuit board
US8830691B2 (en) 1999-09-02 2014-09-09 Ibiden Co., Ltd. Printed circuit board and method of manufacturing printed circuit board
US8842440B2 (en) 1999-09-02 2014-09-23 Ibiden Co., Ltd. Printed circuit board and method of manufacturing printed circuit board
US9060446B2 (en) 1999-09-02 2015-06-16 Ibiden Co., Ltd. Printed circuit board
CN100390969C (en) * 2001-05-30 2008-05-28 株式会社日立制作所 Semiconductor device
US7649252B2 (en) 2003-12-26 2010-01-19 Murata Manufacturing Co., Ltd. Ceramic multilayer substrate
CN100452349C (en) * 2004-06-07 2009-01-14 株式会社东芝 Computer implemented method for designing a semiconductor device, an automated design system and a semiconductor device
JP2009164462A (en) * 2008-01-09 2009-07-23 Fujitsu Microelectronics Ltd Circuit substrate, manufacturing method therefor and semiconductor device

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