JPH10229109A - Method for measuring life time of minority carriers and manufacture of semiconductor device - Google Patents
Method for measuring life time of minority carriers and manufacture of semiconductor deviceInfo
- Publication number
- JPH10229109A JPH10229109A JP3015697A JP3015697A JPH10229109A JP H10229109 A JPH10229109 A JP H10229109A JP 3015697 A JP3015697 A JP 3015697A JP 3015697 A JP3015697 A JP 3015697A JP H10229109 A JPH10229109 A JP H10229109A
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- layer
- charge
- pad electrode
- soi
- measuring
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置における
少数キャリアのライフタイムの測定技術に係り、特に絶
縁膜上に単結晶シリコン層を積層させてなるＳＯＩ構造
の半導体装置における少数キャリアのライフタイムの測
定法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for measuring the lifetime of minority carriers in a semiconductor device, and more particularly to the technology for measuring the lifetime of minority carriers in a semiconductor device having an SOI structure in which a single crystal silicon layer is laminated on an insulating film. It concerns the measurement method.
【０００２】Silicon on Insulator構造（以下、ＳＯＩ
構造と略称する）のＭＯＳＦＥＴは寄生容量が少ないこ
とが特徴であるから消費電力が少なく、また、ＤＲＡＭ
に適用すると、ピット線容量が少なくなり、高速で動作
させることが可能である。[0002] A silicon on insulator structure (hereinafter referred to as SOI
MOSFETs) are characterized by low parasitic capacitance, and therefore consume less power.
In this case, the pit line capacity is reduced, and the device can be operated at high speed.
【０００３】しかし、ＳＯＩ構造には、埋め込み酸化膜
とシリコン界面の少数キャリアのライフタイムが短いと
いう問題がある。ライフタイムが短いと、ｐｎ接合の逆
方向リーク電流が大きくなり、消費電力の増加や、ＤＲ
ＡＭの電荷保持特性の劣化などの問題が生じる。However, the SOI structure has a problem that the minority carrier at the interface between the buried oxide film and the silicon has a short lifetime. If the lifetime is short, the reverse leakage current of the pn junction becomes large, and the power consumption increases,
Problems such as deterioration of the charge retention characteristics of the AM occur.
【０００４】このため、ＳＯＩ構造では、少数キャリア
のライフタイムを定量的にモニターすることが必要であ
る。以上のような状況から、ＳＯＩ層の少数キャリアの
ライフタイムを正確に測定することが可能な少数キャリ
アのライフタイムの測定法が要望されている。Therefore, in the SOI structure, it is necessary to quantitatively monitor the minority carrier lifetime. Under the circumstances described above, there is a demand for a method for measuring the minority carrier lifetime that can accurately measure the minority carrier lifetime in the SOI layer.
【０００５】[0005]
【従来の技術】従来のＳＯＩ層内に発生させた少数キャ
リアが再結合して消滅するまでの時間、即ち少数キャリ
アのライフタイムの測定は、一般に、ＳＯＩ層に波長が
800nm〜1,000nm の電磁波を照射して少数キャリアを励
起し、この少数キャリアの濃度の経時変化を、ＳＯＩ層
に照射したマイクロ波の反射強度を計測することにより
行われている。2. Description of the Related Art In the conventional measurement of the time required for minority carriers generated in an SOI layer to recombine and disappear, that is, the lifetime of the minority carrier, generally, the wavelength is measured in the SOI layer.
Irradiation of electromagnetic waves of 800 nm to 1,000 nm excites minority carriers, and the change over time of the concentration of the minority carriers is performed by measuring the reflection intensity of the microwave applied to the SOI layer.
【０００６】このようなマイクロ波を用いる少数キャリ
ア濃度の測定については、例えば、"Microwave Techniq
ues in Measurement of Lifetime in Germanium",Journ
alof Applied Physics,Vol.30,N0.7,pp.1054-1060(195
9) に記載されている。[0006] The measurement of the minority carrier concentration using such a microwave is described in, for example, "Microwave Techniq."
ues in Measurement of Lifetime in Germanium ", Journ
alof Applied Physics, Vol. 30, N0.7, pp. 1054-1060 (195
9).
【０００７】[0007]
【発明が解決しようとする課題】以上説明した従来の少
数キャリアのライフタイムの測定法においては、可視光
をＳＯＩ層に照射すると、数十μm 程度の深さまで可視
光が到達することが知られている。In the conventional method for measuring the lifetime of minority carriers described above, it is known that when visible light is applied to an SOI layer, the visible light reaches a depth of about several tens of μm. ing.
【０００８】ＳＯＩ層に可視光を照射した場合には、可
視光がＳＯＩ層の支持基板に達し、この支持基板部分に
おいても少数キャリアが励起されるため、ＳＯＩ層にの
み励起された少数キャリアのライフタイムを正確に測定
することができないという課題があった。When the SOI layer is irradiated with visible light, the visible light reaches the support substrate of the SOI layer, and the minority carriers are also excited in the support substrate portion. There was a problem that the lifetime could not be measured accurately.
【０００９】本発明は以上のような状況から、簡単且つ
容易にＳＯＩ層のみに励起された少数キャリアのライフ
タイムの測定を行うことが可能となる少数キャリアのラ
イフタイムの測定法の提供を目的としたものである。In view of the above, an object of the present invention is to provide a method for measuring the lifetime of minority carriers which makes it possible to easily and easily measure the lifetime of minority carriers excited only in the SOI layer. It is what it was.
【００１０】[0010]
【課題を解決するための手段】本発明の少数キャリアの
ライフタイムの測定法は、ｐ型のＳＯＩ層にｐ+層とｎ+
層を形成し、このｐ+層とｎ+層とをそれぞれｐ+層パッ
ド電極とｎ+パッド層電極と接続するメタル配線層を備
えた半導体装置における少数キャリアのライフタイムの
測定法において、このｎ+層パッド電極とアースの間に
電荷計測器を設け、このｐ+層パッド電極をアースに接
続し、このｐ+層とｎ+層との間のＳＯＩ層にイオンを注
入した際にこの電荷計測器によりこのｎ+層パッド電極
に収集された電荷量を計測し、このイオンの注入位置と
収集電荷量の関係に基づき、このＳＯＩ層の少数キャリ
アのライフタイムを算出するように構成する。According to the method of measuring the minority carrier lifetime of the present invention, a p + layer and an n +
In the method of measuring the minority carrier lifetime in a semiconductor device having a metal wiring layer for forming a layer and connecting the p + layer and the n + layer to the p + layer pad electrode and the n + pad layer electrode, respectively, A charge measuring device is provided between the n + layer pad electrode and the ground, and the p + layer pad electrode is connected to the ground. When ions are implanted into the SOI layer between the p + layer and the n + layer, The charge measuring device measures the amount of charge collected in the n + layer pad electrode, and calculates the lifetime of minority carriers in the SOI layer based on the relationship between the ion implantation position and the collected charge amount. .
【００１１】即ち本発明においては図１に示すように、
支持基板１の表面に絶縁膜２を形成し、この絶縁膜２の
表面にｐ層からなるＳＯＩ層３を形成し、このＳＯＩ層
３の表面にｐ+層４とｎ+層５を形成し、ｎ+層５とアー
スの間に電荷計測器８を設けて、このｐ+層４とｎ+層５
との間のＳＯＩ層３にイオン７を注入すると、ＳＯＩ層
３内及び支持基板１内に少数キャリアが励起されるが、
ＳＯＩ層３と支持基板１との間に絶縁膜２が形成されて
いるので、支持基板１に励起された少数キャリアは、こ
の電荷計測器８の測定には影響を与えず、ＳＯＩ層３の
みに励起された少数キャリアのライフタイムの測定を行
うことが可能となる。That is, in the present invention, as shown in FIG.
An insulating film 2 is formed on the surface of the support substrate 1, an SOI layer 3 made of a p-layer is formed on the surface of the insulating film 2, and ap + layer 4 and an n + layer 5 are formed on the surface of the SOI layer 3. by providing an n + layer 5 and a charge measurement device 8 during ground, the p + layer 4 and n + layer 5
When the ions 7 are implanted into the SOI layer 3 between them, minority carriers are excited in the SOI layer 3 and the support substrate 1.
Since the insulating film 2 is formed between the SOI layer 3 and the support substrate 1, the minority carriers excited by the support substrate 1 do not affect the measurement of the charge measuring device 8, and only the SOI layer 3 It becomes possible to measure the lifetime of the minority carriers excited by the above.
【００１２】この場合、イオンの照射位置と拡散層、即
ちｎ+層との距離と、この電荷計測器により収集した収
集電荷量との関係は図２に示すようになり、この距離が
大きくなればこの収集電荷量が減少するので、入射位置
に対応する収集電荷量を測定し、図２において入射位置
の線と収集電荷量の線との交点でライフタイムを見つけ
ることにより、ＳＯＩ層３の少数キャリアのライフタイ
ムの測定を行うことが可能となる。In this case, the relationship between the distance between the ion irradiation position and the diffusion layer, that is, the n + layer, and the amount of charge collected by the charge measuring device is as shown in FIG. 2, and this distance is increased. For example, since the collected charge amount decreases, the collected charge amount corresponding to the incident position is measured, and the lifetime is found at the intersection of the line of the incident position and the line of the collected charge amount in FIG. It becomes possible to measure the lifetime of minority carriers.
【００１３】[0013]
【発明の実施の形態】以下図３〜図９により本発明の第
１〜第４の実施例について詳細に説明する。図３は本発
明による第１の実施例の断面図、図４は本発明による第
１の実施例の平面図、図５は本発明による第２の実施例
の断面図、図６は本発明による第２の実施例の平面図、
図７は本発明による第３の実施例の断面図、図８は本発
明による第３の実施例の平面図、図９は本発明による第
４の実施例の断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, first to fourth embodiments of the present invention will be described in detail with reference to FIGS. FIG. 3 is a sectional view of a first embodiment according to the present invention, FIG. 4 is a plan view of the first embodiment according to the present invention, FIG. 5 is a sectional view of a second embodiment according to the present invention, and FIG. Plan view of a second embodiment according to
7 is a sectional view of a third embodiment according to the present invention, FIG. 8 is a plan view of the third embodiment according to the present invention, and FIG. 9 is a sectional view of a fourth embodiment according to the present invention.
【００１４】本発明による第１の実施例においては、図
３に示すようにｐ型シリコン層13に50μm の間隔でｐ+
層４とｎ+層５を形成し、図４に示すようにｐ+層４とｐ
+層パッド電極4aとをアルミニウムなどからなるメタル
配線6aで接続し、ｎ+層５とｎ+層パッド電極5aとをアル
ミニウムなどからなるメタル配線6bで接続する。In the first embodiment according to the present invention, as shown in FIG. 3, the p + type silicon layer 13 has p +
A layer 4 and n + layer 5, p and p + layer 4 as shown in FIG. 4
+ Layer pad electrode 4a is connected by metal wiring 6a made of aluminum or the like, and n + layer 5 and n + layer pad electrode 5a are connected by metal wiring 6b made of aluminum or the like.
【００１５】そして、0.1 ｆＣの精度で電荷を計測する
ことが可能な電荷計測器８をｎ+層パッド電極を介して
図１に示すようにこのｎ+層５に接続する。その後、図
３に示すようにこのｎ+層５とｐ+層４の間に数ＭｅＶ程
度に加速したイオン７を照射し、この電荷計測器８によ
り収集電荷量を計測する。A charge measuring device 8 capable of measuring charges with an accuracy of 0.1 fC is connected to the n + layer 5 through an n + layer pad electrode as shown in FIG. Thereafter, as shown in FIG. 3, ions 7 accelerated to about several MeV are irradiated between the n + layer 5 and the p + layer 4, and the charge measuring device 8 measures the amount of collected charges.
【００１６】イオンの照射位置の制御は、平行平板型の
コンデンサにより数μm の精度で行うことが必要であ
る。そして、図２を用いて、イオンの入射位置の線と収
集電荷量の線との交点でライフタイムを見つけることに
より、ＳＯＩ層３の少数キャリアのライフタイムの測定
を行うことが可能となる。It is necessary to control the irradiation position of ions with a parallel plate type condenser with an accuracy of several μm. Then, the lifetime of the minority carrier in the SOI layer 3 can be measured by finding the lifetime at the intersection of the line of the incident position of the ion and the line of the amount of collected charges with reference to FIG.
【００１７】本発明による第２の実施例においては、図
５に示すようにｐ型シリコン層13に50μm の間隔でｐ+
層４とｎ+層５を形成し、図６に示すようにｐ+層４とｐ
+層パッド電極4aとをアルミニウムなどからなるメタル
配線6aで接続し、ｎ+層５とｎ+層パッド電極5aとをアル
ミニウムなどからなるメタル配線6bで接続する。In the second embodiment according to the present invention, as shown in FIG. 5, p +
A layer 4 and n + layer 5, p and p + layer 4 as shown in FIG. 6
+ Layer pad electrode 4a is connected by metal wiring 6a made of aluminum or the like, and n + layer 5 and n + layer pad electrode 5a are connected by metal wiring 6b made of aluminum or the like.
【００１８】そして、0.1 ｆＣの精度で電荷を計測する
ことが可能な電荷計測器８をｎ+層パッド電極を介して
図１に示すようにこのｎ+層５に接続する。この第２の
実施例においては、メタル配線6a,6b を形成した後、図
５に示すようにα線を遮蔽することができる膜厚30μm
のポリイミド膜９を堆積し、このポリイミド膜９に図６
に示すように２μm □のポリイミドホール9aを形成す
る。Then, a charge measuring device 8 capable of measuring charges with an accuracy of 0.1 fC is connected to the n + layer 5 through an n + layer pad electrode as shown in FIG. In the second embodiment, after the metal wirings 6a and 6b are formed, as shown in FIG.
6 is deposited on the polyimide film 9 shown in FIG.
A 2 μm square polyimide hole 9a is formed as shown in FIG.
【００１９】そして、α線7bを放射するα線源7aをシリ
コン基板上に置くと、α線源7aから放射されるα線7bの
エネルギーは約５ＭｅＶであるから、膜厚30μm のポリ
イミド膜９中でエネルギーが減衰し、ｐ型シリコン層13
までは到達しない。このためポリイミドホール9aの部分
のみにα線7bが入射する。When the α-ray source 7a for emitting the α-ray 7b is placed on a silicon substrate, the energy of the α-ray 7b emitted from the α-ray source 7a is about 5 MeV. The energy is attenuated in the p-type silicon layer 13
Do not reach. Therefore, the α-ray 7b is incident only on the polyimide hole 9a.
【００２０】このポリイミドホール9aの位置と収集電荷
量の関係から、第１の実施例の場合と同様に、少数キャ
リアのライフタイムの測定を行うことが可能となる。こ
の第２の実施例においては、α線7bの入射位置を決める
ポリイミドホール9aをリソグラフィー技術を用いて形成
するので、α線7bの入射位置の制御を安価に且つ簡単に
行うことが可能である。From the relationship between the position of the polyimide hole 9a and the amount of collected charges, it becomes possible to measure the minority carrier lifetime as in the first embodiment. In the second embodiment, since the polyimide hole 9a for determining the incident position of the α-ray 7b is formed by using the lithography technique, it is possible to control the incident position of the α-ray 7b at low cost and easily. .
【００２１】本発明による第３の実施例においては、図
７に示すようにｐ型シリコン層13に50μm の間隔でｐ+
層４とｎ+層５を形成する前に、ｐ型シリコン層13の表
面にゲート酸化膜10b を介してゲート電極10を形成し、
図８に示すようにｐ+層４とｐ+層パッド電極4aとをアル
ミニウムなどからなるメタル配線6aで接続し、ｎ+層５
とｎ+層パッド電極5aとをアルミニウムなどからなるメ
タル配線6bで接続する。[0021] In the third embodiment according to the present invention, at intervals of 50μm to p-type silicon layer 13 as shown in FIG. 7 p +
Before forming the layer 4 and the n + layer 5, the gate electrode 10 is formed on the surface of the p-type silicon layer 13 via the gate oxide film 10b,
As shown in FIG. 8, the p + layer 4 and the p + layer pad electrode 4a are connected by a metal wiring 6a made of aluminum or the like, and the n + layer 5
And n + layer pad electrode 5a are connected by metal wiring 6b made of aluminum or the like.
【００２２】そして、0.1 ｆＣの精度で電荷を計測する
ことが可能な電荷計測器８をｎ+層パッド電極を介して
図１に示すようにこのｎ+層５に接続する。この第３の
実施例においては、電荷計測器８により電荷量を収集す
る際には、ゲート電極10に正の電圧を印加するから、ｐ
型シリコン層13に発生した電子は、ゲート電極10の直下
の界面を流れるようになるので、第１の実施例や第２の
実施例においてはｐ型シリコン層13の上側の界面と下側
の界面のライフタイムを別々に測定出来なかったが、こ
の第３の実施例ではｐ型シリコン層13の上側の界面のラ
イフタイムの測定を行うことが可能となる。Then, a charge measuring device 8 capable of measuring electric charges with an accuracy of 0.1 fC is connected to this n + layer 5 through an n + layer pad electrode as shown in FIG. In the third embodiment, a positive voltage is applied to the gate electrode 10 when the charge amount is collected by the charge measuring device 8;
Since the electrons generated in the p-type silicon layer 13 flow through the interface immediately below the gate electrode 10, in the first and second embodiments, the upper interface and the lower Although the lifetimes of the interfaces could not be measured separately, in the third embodiment, the lifetime of the interface above the p-type silicon layer 13 can be measured.
【００２３】本発明による第４の実施例においては、図
９に示すように酸化膜12の形成工程中にゲート電極10を
形成した後、ゲート酸化膜10b を介してｐ型シリコン層
13を形成し、50μm の間隔でｐ+層４とｎ+層５を形成
し、0.1 ｆＣの精度で電荷を計測することが可能な電荷
計測器８をｎ+層パッド電極を介して図１に示すように
このｎ+層５に接続する。In the fourth embodiment according to the present invention, as shown in FIG. 9, after the gate electrode 10 is formed during the step of forming the oxide film 12, the p-type silicon layer is formed via the gate oxide film 10b.
13, a p + layer 4 and an n + layer 5 are formed at an interval of 50 μm, and a charge measuring device 8 capable of measuring a charge with an accuracy of 0.1 fC is connected to an n + layer pad electrode as shown in FIG. Is connected to this n + layer 5 as shown in FIG.
【００２４】その後、図９に示すようにこのｎ+層５と
ｐ+層４の間に数ＭｅＶ程度に加速したイオン７を照射
し、この電荷計測器８により収集電荷量を計測する。Thereafter, as shown in FIG. 9, ions 7 accelerated to about several MeV are irradiated between the n + layer 5 and the p + layer 4, and the amount of collected charges is measured by the charge measuring device 8.
【００２５】イオンの照射位置の制御は、平行平板型の
コンデンサにより数μm の精度で行うことが必要であ
る。この第４の実施例においても第３の実施例と同様
に、電荷計測器８により電荷量を収集する際には、ゲー
ト電極10に正の電圧を印加するから、ｐ型シリコン層13
に発生した電子は、この場合はゲート電極10の直上の界
面を流れるようになるので、第１の実施例や第２の実施
例においてはｐ型シリコン層13の上側の界面と下側の界
面のライフタイムを別々に測定出来なかったが、この第
４の実施例ではｐ型シリコン層13の下側の界面のライフ
タイムの測定を行うことが可能となる。It is necessary to control the irradiation position of ions with a parallel plate type capacitor with an accuracy of several μm. In the fourth embodiment, similarly to the third embodiment, a positive voltage is applied to the gate electrode 10 when collecting the charge by the charge measuring device 8, so that the p-type silicon layer 13
In this case, the electrons generated at this time flow through the interface immediately above the gate electrode 10. Therefore, in the first and second embodiments, the upper interface and the lower interface of the p-type silicon layer 13 are used. However, in the fourth embodiment, the lifetime of the lower interface of the p-type silicon layer 13 can be measured.
【００２６】本実施例では、ｎ+層パッド電極とアース
の間に電荷計測器を設け、ｐ+層パッド電極をアースに
接続し、このｐ+層とｎ+層との間のＳＯＩ層にイオンを
注入した際にこの電荷計測器によりこのｎ+層パッド電
極に収集された電荷量を計測し、このイオンの注入位置
と収集電荷量の関係に基づき、このＳＯＩ層の少数キャ
リアのライフタイムを算出しているが、本実施例とは逆
に電荷計測器をｐ+層パッド電極とアースの間に設け、
ｎ+層パッド電極をアースに接続し、このｎ+層とｐ+層
との間のＳＯＩ層にイオンを注入した際にこの電荷計測
器によりこのｐ+層パッド電極に収集された電荷量を計
測し、このイオンの注入位置と収集電荷量の関係に基づ
き、このＳＯＩ層の正孔の少数キャリアのライフタイム
を算出することが可能となる。In this embodiment, a charge measuring device is provided between the n + layer pad electrode and the ground, the p + layer pad electrode is connected to the ground, and the SOI layer between the p + layer and the n + layer is connected. The amount of charge collected on the n + layer pad electrode by the charge measuring device when the ions are implanted is measured, and the minority carrier lifetime of the SOI layer is determined based on the relationship between the ion implantation position and the collected charge amount. In contrast to this embodiment, a charge measuring device is provided between the p + layer pad electrode and the ground,
The n + layer pad electrode is connected to the ground, and the amount of charge collected by the charge measuring device at the p + layer pad electrode when ions are implanted into the SOI layer between the n + layer and the p + layer. It is possible to calculate the lifetime of the minority carriers of holes in the SOI layer based on the measured relationship between the ion implantation position and the collected charge amount.
【００２７】[0027]
【発明の効果】以上の説明から明らかなように、本発明
によれば極めて簡単な方法により支持基板の表面のＳＯ
Ｉ層に形成した少数キャリアのライフタイムの測定を、
半導体装置の製造工程の途中において行うことが可能
で、少数キャリアのライフタイムの短い半導体基板を工
程の途中で除去することができる利点があり、著しい経
済的及び、信頼性向上の効果が期待できる少数キャリア
のライフタイムの測定法及び半導体装置の製造方法の提
供が可能である。As is apparent from the above description, according to the present invention, the SO on the surface of the supporting substrate can be obtained by a very simple method.
Measurement of the lifetime of minority carriers formed in the I layer,
The method can be performed in the course of a semiconductor device manufacturing process, and has the advantage that a semiconductor substrate with a short lifetime of minority carriers can be removed in the middle of the process, and significant economical and reliability improvement effects can be expected. A method for measuring the lifetime of minority carriers and a method for manufacturing a semiconductor device can be provided.
【図１】 本発明の原理図FIG. 1 is a principle diagram of the present invention.
【図２】 ｎ+層とイオン入射位置との距離と電荷計測
器により収集した収集電荷量との関係を示す図FIG. 2 is a diagram showing a relationship between a distance between an n + layer and an ion incident position and a collected charge amount collected by a charge measuring device.
【図３】 本発明による第１の実施例の断面図FIG. 3 is a cross-sectional view of the first embodiment according to the present invention.
【図４】 本発明による第１の実施例の平面図FIG. 4 is a plan view of the first embodiment according to the present invention.
【図５】 本発明による第２の実施例の断面図FIG. 5 is a sectional view of a second embodiment according to the present invention.
【図６】 本発明による第２の実施例の平面図FIG. 6 is a plan view of a second embodiment according to the present invention.
【図７】 本発明による第３の実施例の断面図FIG. 7 is a sectional view of a third embodiment according to the present invention.
【図８】 本発明による第３の実施例の平面図FIG. 8 is a plan view of a third embodiment according to the present invention.
【図９】 本発明による第４の実施例の断面図FIG. 9 is a sectional view of a fourth embodiment according to the present invention.
１ 支持基板 ２ 絶縁膜 ３ ＳＯＩ層 ４ ｐ+層 4a ｐ+層パッド電極 ５ ｎ+層 5a ｎ+層パッド電極 6a メタル配線 6b メタル配線 ７ イオン 7a α線源 7b α線 ８ 電荷計測器 ９ ポリイミド膜 9a ポリイミドホール 10 ゲート電極 10a ゲート電極のパッド電極 10b ゲート酸化膜 11 シリコン基板 12 酸化膜 13 ｐ型シリコン層REFERENCE SIGNS LIST 1 support substrate 2 insulating film 3 SOI layer 4 p + layer 4 a p + layer pad electrode 5 n + layer 5 an + layer pad electrode 6 a metal wiring 6 b metal wiring 7 ion 7 a α-ray source 7 b α-ray 8 charge measuring instrument 9 polyimide Film 9a polyimide hole 10 gate electrode 10a gate electrode pad electrode 10b gate oxide film 11 silicon substrate 12 oxide film 13 p-type silicon layer
Claims (5)
し、該ｐ+層とｎ+層とをそれぞれｐ+層パッド電極とｎ+
層パッド電極と接続するメタル配線層を備えた半導体装
置における少数キャリアのライフタイムの測定法におい
て、 前記ｎ+層パッド電極とアースの間に電荷計測器を設
け、前記ｐ+層パッド電極をアースに接続し、前記ｐ+層
とｎ+層との間のＳＯＩ層にイオンを注入した際に前記
電荷計測器により前記ｎ+層パッド電極に収集された電
荷量を計測し、前記イオンの注入位置と収集電荷量の関
係に基づき、前記ＳＯＩ層の少数キャリアのライフタイ
ムを算出することを特徴とする少数キャリアのライフタ
イムの測定法。1. A p.sup. + Layer and an n.sup. + Layer are formed on a p-type SOI layer, and the p.sup. + Layer and the n.sup. + Layer are respectively connected to a p.sup. + Layer pad electrode and an n.sup. + Layer.
In a method for measuring the lifetime of minority carriers in a semiconductor device having a metal wiring layer connected to a layer pad electrode, a charge measuring device is provided between the n + layer pad electrode and ground, and the p + layer pad electrode is grounded. And measuring the amount of charge collected in the n + layer pad electrode by the charge measuring device when ions are implanted into the SOI layer between the p + layer and the n + layer, and implanting the ions. A method for measuring a minority carrier lifetime, comprising calculating a minority carrier lifetime of the SOI layer based on a relationship between a position and a collected charge amount.
る被膜を形成して該被膜に開口を設け、前記α線の放射
線源を前記半導体装置の上に設け、前記開口の位置と収
集電荷量の関係に基づき、前記ＳＯＩ層の少数キャリア
のライフタイムを算出することを特徴とする請求項１記
載の少数キャリアのライフタイムの測定法。2. A coating for blocking α-rays is formed on the surface of the metal wiring layer, an opening is provided in the coating, a radiation source for the α-rays is provided on the semiconductor device, and the position of the opening and collection of 2. The method for measuring the minority carrier lifetime according to claim 1, wherein the minority carrier lifetime of the SOI layer is calculated based on a charge amount relationship.
後、前記ＳＯＩ層にｐ+層とｎ+層を形成し、該ゲート電
極に正の電圧を印加した状態において前記ｐ +層とｎ+層
との間のＳＯＩ層にイオンを注入した際に前記電荷計測
器により前記ｎ+層パッド電極に収集された電荷量を計
測し、前記イオンの注入位置と収集電荷量の関係に基づ
き、前記ＳＯＩ層の上側界面の少数キャリアのライフタ
イムを算出することを特徴とする請求項１記載の少数キ
ャリアのライフタイムの測定法。3. A gate electrode is formed on the SOI layer.
Then, p is added to the SOI layer.+Layers and n+Forming a layer, and
When a positive voltage is applied to the pole, +Layers and n+layer
Charge measurement when ions are implanted into the SOI layer between
N+The amount of charge collected on the layer pad electrode
Measured based on the relationship between the ion implantation position and the amount of collected charges.
A minority carrier rifter at the upper interface of the SOI layer.
2. The minority key according to claim 1, wherein
Carrier lifetime measurement method.
工程中にゲート電極を形成した後、前記ＳＯＩ層にｐ+
層とｎ+層を形成し、該ゲート電極に正の電圧を印加し
た状態において前記ｐ+層とｎ+層との間のＳＯＩ層にイ
オンを注入した際に前記電荷計測器により前記ｎ+層パ
ッド電極に収集された電荷量を計測し、前記イオンの注
入位置と収集電荷量の関係に基づき、前記ＳＯＩ層の下
側界面の少数キャリアのライフタイムを算出することを
特徴とする請求項１記載の少数キャリアのライフタイム
の測定法。4. After forming a gate electrode during an oxide film forming step between the SOI layer and the support substrate, p + is added to the SOI layer.
Wherein a layer and n + layer, by the charge meter upon implanting ions into the SOI layer between the p + layer and the n + layer in a state of applying a positive voltage to the gate electrode n + The charge amount collected by the layer pad electrode is measured, and the lifetime of minority carriers at the lower interface of the SOI layer is calculated based on the relationship between the ion implantation position and the collected charge amount. 2. The method for measuring the minority carrier lifetime according to 1.
１、２、３または４記載の方法により少数キャリアのラ
イフタイムを測定する工程と、ライフタイムが設定値よ
り短い半導体基板を除去する工程とを含むことを特徴と
する半導体装置の製造方法。5. A method for manufacturing a semiconductor device, comprising: a step of measuring a minority carrier lifetime by the method according to claim 1, and a step of removing a semiconductor substrate having a lifetime shorter than a set value. And a method of manufacturing a semiconductor device.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03015697A JP3661334B2 (en) | 1997-02-14 | 1997-02-14 | Minority carrier lifetime measurement method and semiconductor device manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03015697A JP3661334B2 (en) | 1997-02-14 | 1997-02-14 | Minority carrier lifetime measurement method and semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10229109A true JPH10229109A (en) | 1998-08-25 |
| JP3661334B2 JP3661334B2 (en) | 2005-06-15 |
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ID=12295902
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|---|---|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364322A (en) * | 2011-06-30 | 2012-02-29 | 常州天合光能有限公司 | Surface treatment method for testing minority carrier lifetime of silicon wafer |
| CN106853443A (en) * | 2016-12-07 | 2017-06-16 | 安徽爱森能源有限公司 | The detection method of silico briquette after a kind of evolution |
-
1997
- 1997-02-14 JP JP03015697A patent/JP3661334B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364322A (en) * | 2011-06-30 | 2012-02-29 | 常州天合光能有限公司 | Surface treatment method for testing minority carrier lifetime of silicon wafer |
| CN106853443A (en) * | 2016-12-07 | 2017-06-16 | 安徽爱森能源有限公司 | The detection method of silico briquette after a kind of evolution |
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| Publication number | Publication date |
|---|---|
| JP3661334B2 (en) | 2005-06-15 |
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