JPH10209618A - Circuit board device and its manufacture - Google Patents
Circuit board device and its manufactureInfo
- Publication number
- JPH10209618A JPH10209618A JP9017906A JP1790697A JPH10209618A JP H10209618 A JPH10209618 A JP H10209618A JP 9017906 A JP9017906 A JP 9017906A JP 1790697 A JP1790697 A JP 1790697A JP H10209618 A JPH10209618 A JP H10209618A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- weight
- conductive bonding
- bonding material
- wiring conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は回路基板上に回路部品の
電極端子がろう付けされた構成の回路基板装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board device in which electrode terminals of circuit components are brazed on a circuit board.
【０００２】[0002]
【従来の技術】図１及び図２に示すようにセラミック等
の絶縁性回路基板１の上に、チップコンデンサ等のチッ
プ型回路部品２を配置して混成集積回路装置を構成する
ことは公知である。この回路装置を更に詳しく説明する
と、回路部品２は平面形状がほぼ四角形の本体部３と一
対の電極端子４とを有し、一対の電極端子４は本体部３
の側面にキャップ状に形成されている。なお、一対の電
極端子４を本体部３の底面のみに形成することも可能で
ある。回路基板１上には回路部品２を接続するための配
線導体５が設けられ、ここに電極端子４が導電性接合材
としての半田６で接合されている。配線導体５は電極端
子４に対向した長手の端子接続領域（電極パッド）５ａ
とこれを別の回路部品又は端子に接続するための相互接
続領域５ｂとを有する。回路基板１の上には配線導体５
の相互接続領域５ｂ及び厚膜抵抗素子（図示せず）等を
保護するための周知のオーバーコートガラス膜７が設け
られている。このガラス膜７は回路部品２を配置するた
めの開口８を有する。この開口８は電極端子４に対応す
る領域に平面的に見てほぼ四角形に形成され、この縁は
本体部３の４つの側面３ａ又は３ｂ、３ｃ、３ｄに対し
てほぼ均一な間隔を有して対向している。なお、図１及
び図２において図示を簡略化するために一対の電極端子
４の相互間距離は回路素子２と開口８との縁との間隔に
比べて実際よりも短く示されている。2. Description of the Related Art As shown in FIGS. 1 and 2, it is known that a chip type circuit component 2 such as a chip capacitor is arranged on an insulating circuit board 1 such as a ceramic to constitute a hybrid integrated circuit device. is there. The circuit device 2 will be described in more detail. The circuit component 2 has a main body 3 having a substantially square planar shape and a pair of electrode terminals 4.
Is formed in the shape of a cap on the side surface. Note that the pair of electrode terminals 4 can be formed only on the bottom surface of the main body 3. A wiring conductor 5 for connecting the circuit component 2 is provided on the circuit board 1, and the electrode terminal 4 is bonded to the wiring terminal 5 with solder 6 as a conductive bonding material. The wiring conductor 5 has a long terminal connection region (electrode pad) 5 a facing the electrode terminal 4.
And an interconnect region 5b for connecting the same to another circuit component or terminal. On the circuit board 1, a wiring conductor 5 is provided.
A well-known overcoat glass film 7 for protecting the interconnection region 5b and the thick film resistance element (not shown) is provided. This glass film 7 has an opening 8 for disposing the circuit component 2. The opening 8 is formed in a region corresponding to the electrode terminal 4 to have a substantially rectangular shape in plan view, and its edge has a substantially uniform interval with respect to the four side surfaces 3a or 3b, 3c, 3d of the main body 3. Facing each other. 1 and 2, the distance between the pair of electrode terminals 4 is shorter than the distance between the circuit element 2 and the edge of the opening 8 for simplicity.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上記の混成
集積回路装置において、半田６に鉛（Ｐｂ）と錫（Ｓ
ｎ）の合金半田を使用し、配線導体５を銀（Ａｇ）・パ
ラジウム（Ｐｄ）の厚膜導体ペースト（金属粉末に少量
のガラス粉末等の無機バインダと有機バインダとを添加
したもの）で形成した場合には、銀と錫の相互拡散によ
って配線導体５の端子接続領域５ａと相互接続領域５ｂ
の境界部が脆くなることがある。このような場合、半田
６と配線導体５とは熱膨張係数が異なるため、回路部品
２の半田付け後の工程又は使用時の加熱によって両者の
熱膨張係数差に起因する熱応力が配線導体５の端子接続
領域５ａと相互接続領域５ｂ境界部に加わり、この脆く
なった端子接続領域５ａと相互接続領域５ｂの境界部に
亀裂又は分断が生じることがある。By the way, in the above-mentioned hybrid integrated circuit device, lead (Pb) and tin (S
Using the alloy solder of n), the wiring conductor 5 is formed of a thick-film conductor paste of silver (Ag) / palladium (Pd) (a metal powder to which a small amount of an inorganic binder such as a glass powder and an organic binder are added). In this case, the terminal connection region 5a of the wiring conductor 5 and the interconnection region 5b
May become brittle. In such a case, since the solder 6 and the wiring conductor 5 have different thermal expansion coefficients, the thermal stress caused by the difference in the thermal expansion coefficient between the solder and the process after soldering of the circuit component 2 or the heating during use causes the wiring conductor 5 to fail. At the boundary between the terminal connection region 5a and the interconnection region 5b, and the boundary between the weakened terminal connection region 5a and the interconnection region 5b may be cracked or divided.
【０００４】そこで、本発明の目的は、上記のような銀
と錫の相互拡散を抑制し、配線導体の分断（断線）を防
止できる回路基板装置を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit board device capable of suppressing the above-described mutual diffusion of silver and tin and preventing the wiring conductor from being separated (disconnected).
【０００５】[0005]
【課題を解決するための手段】上記課題を解決し、上記
目的を達成するための装置の発明は、回路基板と、前記
回路基板に端子接続領域及び相互接続領域を有するよう
に銀を含む厚膜導体材料で形成された配線導体と、導電
性接合材によって前記端子接続領域に接続された端子を
有する回路部品とを備えた回路基板装置において、前記
導電性接合材が８１．５〜８７．５重量％のＰｂと９．
５〜１０．５重量％のＳｎと３．０〜８．０重量％のＳ
ｂとら成ることを特徴とする回路基板装置に係わるもの
である。また、方法の発明は、銀を含む厚膜導体材料に
よって端子接続領域及び相互接続領域を有するように形
成された配線導体を備えている回路基板を用意し、前記
端子接続領域に８１．５〜８７．５重量％のＰｂと９．
５〜１０．５重量％のＳｎと３．０〜８．０重量％のＳ
ｂとから成る導電性接合材ペーストを塗布し、前記導電
性接合材ペーストの上に回路部品の端子を配置して加熱
することによって前記端子を前記端子接続領域に接続す
ることを特徴とする回路基板装置の製造方法に係わるも
のである。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems and to achieve the above-mentioned object, an invention of an apparatus includes a circuit board, and a board containing silver so that the circuit board has a terminal connection region and an interconnection region. In a circuit board device including a wiring conductor formed of a film conductor material and a circuit component having a terminal connected to the terminal connection region by a conductive bonding material, the conductive bonding material may be 81.5 to 87. 8. 5% by weight of Pb and
5 to 10.5% by weight of Sn and 3.0 to 8.0% by weight of S
b. The present invention relates to a circuit board device characterized by the above character b. In addition, the invention of the method provides a circuit board including a wiring conductor formed to have a terminal connection region and an interconnection region by a thick film conductor material containing silver, and the terminal connection region has a thickness of 81.5 to 87.5% by weight of Pb and 9.
5 to 10.5% by weight of Sn and 3.0 to 8.0% by weight of S
b) applying a conductive bonding material paste consisting of b), arranging a terminal of a circuit component on the conductive bonding material paste, and heating the circuit component to connect the terminal to the terminal connection region. The present invention relates to a method for manufacturing a substrate device.
【０００６】[0006]
【発明の作用及び効果】各請求項の発明においては、Ｐ
ｂ（鉛）とＳｎ（錫）とＳｂ（アンチモン）とから成る
導電性接合材（半田）を使用するので、Ｓｂ（アンチモ
ン）が配線導体中のＡｇ（銀）の導電性接合材への拡散
を抑制する。このため、Ａｇ（銀）とＳｎ（錫）との合
金の生成速度を十分に遅延させて配線導体が脆くなるこ
とを防止できる。この結果、配線導体の亀裂又は分断が
防止される。In the invention of each claim, P
Since a conductive bonding material (solder) composed of b (lead), Sn (tin), and Sb (antimony) is used, Sb (antimony) diffuses Ag (silver) in the wiring conductor into the conductive bonding material. Suppress. Therefore, the generation speed of the alloy of Ag (silver) and Sn (tin) can be sufficiently delayed to prevent the wiring conductor from becoming brittle. As a result, cracking or division of the wiring conductor is prevented.
【０００７】[0007]
【実施例】次に、図３を参照して本発明の実施例に係わ
る回路基板装置（混成集積回路装置）を説明する。但
し、図３において図１及び図２と実質的に同一の部分に
は同一の符号を付してその詳しい説明を省略する。Next, a circuit board device (hybrid integrated circuit device) according to an embodiment of the present invention will be described with reference to FIG. However, in FIG. 3, substantially the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.
【０００８】図３に示す本発明に従う回路基板装置は、
導電性接合材６ａを除いて図２に示す回路装置と実質的
に同一に形成され、また、図１と同一の平面形状を有し
ている。即ち、セラミックから成る回路基板１の上に銀
・パラジウム（Ａｇ−Ｐｄ）の厚膜導体ペーストを印刷
し、焼付けることによって配線導体５が形成されてい
る。配線導体５は、図１及び図２と同様に端子接続領域
（電極パッド）５ａと相互接続領域５ｂとを有する。オ
ーバーコートガラス膜７は端子接続領域５ａを露出させ
るための開口８を有するように形成され、相互接続領域
５ｂの大部分を被覆している。一対の電極端子４を有す
るチップコンデンサから成る回路部品２は、導電性接合
材６ａによって端子接続領域５ａに接続されている。The circuit board device according to the present invention shown in FIG.
Except for the conductive bonding material 6a, it is formed substantially the same as the circuit device shown in FIG. 2, and has the same planar shape as that of FIG. That is, the wiring conductor 5 is formed by printing and baking a thick-film conductor paste of silver / palladium (Ag-Pd) on the circuit board 1 made of ceramic. The wiring conductor 5 has a terminal connection region (electrode pad) 5a and an interconnection region 5b as in FIGS. The overcoat glass film 7 is formed to have an opening 8 for exposing the terminal connection region 5a, and covers most of the interconnection region 5b. The circuit component 2 composed of a chip capacitor having a pair of electrode terminals 4 is connected to a terminal connection region 5a by a conductive bonding material 6a.
【０００９】しかし、本実施例の導電性接合材６ａの組
成が図２の従来の半田６と相違している。本実施例の導
電性接合材６ａはＰｂ（鉛）、Ｓｎ（錫）、Ｓｂ（アン
チモン）の三元合金半田から成り、Ｐｂ：Ｓｎ：Ｓｂ＝
８２：１０：８の組成比（重量比）を有する。なお、Ｐ
ｂ、Ｓｎ、Ｓｂの組成比は、次の範囲にすることが望ま
しい。 Ｐｂ ８１．５〜８７．５重量％ Ｓｎ ９．５〜１０．５重量％ Ｓｂ ３．０〜 ８．０重量％ Ｓｎが９．５重量％を下回ると半田の溶融温度が上って
しまい、製造上望ましくない。また、Ｓｎが１０．５重
量％を上回ると、従来のＰｂＳｎの共晶半田と同じ特性
になり、ＡｇＳｎ合金層の形成を抑制する効果が実質的
に得られなくなる。また、Ｓｂが８重量％を上回ると、
半田の濡れ性（広がり性）が著しく低下してしまう。ま
た、Ｓｂが３重量％を下回ると、ＡｇＳｎ合金層の生成
速度を低減させる効果が損われてしまう。However, the composition of the conductive bonding material 6a of this embodiment is different from that of the conventional solder 6 of FIG. The conductive bonding material 6a of this embodiment is made of a ternary alloy solder of Pb (lead), Sn (tin), and Sb (antimony), and Pb: Sn: Sb =
It has a composition ratio (weight ratio) of 82: 10: 8. Note that P
It is desirable that the composition ratio of b, Sn, and Sb be in the following range. Pb 81.5 to 87.5% by weight Sn 9.5 to 10.5% by weight Sb 3.0 to 8.0% by weight If Sn is less than 9.5% by weight, the melting temperature of the solder increases. Not desirable for manufacturing. On the other hand, when Sn exceeds 10.5% by weight, the characteristics become the same as those of the conventional PbSn eutectic solder, and the effect of suppressing the formation of the AgSn alloy layer cannot be substantially obtained. When Sb exceeds 8% by weight,
Solder wettability (spreadability) is significantly reduced. If Sb is less than 3% by weight, the effect of reducing the generation rate of the AgSn alloy layer will be impaired.
【００１０】この回路基板装置を製造する時には、回路
基板１上に銀・パラジウムの導体ペーストを周知のスク
リーン印刷法によって所定パターンに塗布して焼成する
ことによって厚膜導体から成る配線導体５を形成し、そ
の後、ガラスペーストを周知のスクリーン印刷法で所定
パターンに塗布して焼成することによってガラス膜７を
形成する。次に、導電性接合材としての上述した組成比
のＰｂ−Ｓｎ−Ｓｂから成る半田ペーストを配線導体５
の端子接続領域５ａの上にスクリーン印刷法で塗布し、
この上に回路部品２の電極端子４を配置して加熱する。
これにより、半田ペーストが溶融し、その後固化し、導
電性接合材（半田）６ａによる接続が達成される。When the circuit board device is manufactured, a conductor paste of silver / palladium is applied on the circuit board 1 in a predetermined pattern by a well-known screen printing method and baked to form the wiring conductor 5 made of a thick film conductor. Then, the glass film 7 is formed by applying a glass paste in a predetermined pattern by a well-known screen printing method and firing it. Next, a solder paste made of Pb-Sn-Sb having the above-described composition ratio as a conductive bonding material was applied to the wiring conductor 5.
Is applied by a screen printing method on the terminal connection area 5a of
The electrode terminals 4 of the circuit component 2 are arranged thereon and heated.
As a result, the solder paste is melted and then solidified, and connection by the conductive bonding material (solder) 6a is achieved.
【００１１】本実施例の回路基板装置によれば、導電性
接合材６ａがＳｂを含有しており、このＳｂが配線導体
５中のＡｇの導電性接合材６ａへの拡散を抑制する。こ
のため、ＡｇＳｎ合金層の成長速度を十分に遅延するこ
とができ、合金層の形成によって配線導体５が脆くなる
ことを阻止し、配線導体５の特に相互接続領域５ｂの開
口８から露出している部分の亀裂又は分断を防止するこ
とができる。According to the circuit board device of this embodiment, the conductive bonding material 6a contains Sb, and this Sb suppresses the diffusion of Ag in the wiring conductor 5 into the conductive bonding material 6a. For this reason, the growth rate of the AgSn alloy layer can be sufficiently delayed, the formation of the alloy layer prevents the wiring conductor 5 from becoming brittle, and the wiring conductor 5 is exposed particularly from the opening 8 in the interconnect region 5b. This can prevent cracks or splits in the existing parts.
【００１２】[0012]
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 （１） 回路部品２は半導体素子、抵抗素子、インダク
タンス素子、又はＩＣ（集積回路）でもよい。また、回
路部品２の電極端子４の形状を種々変えることができ
る。 （２） 開口８に連続させて流動した導電性接合材（半
田）の逃げ部分（流れ込み部分）として突出部分（オー
バーコートガラス膜除去部分）を相互接続領域５ｂに沿
って設けることができる。 （３） 配線導体５はＡｇ−Ｐｄ導体に限ることなく、
銀（Ａｇ）のみ又は銀を含む別の導体とすることができ
る。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The circuit component 2 may be a semiconductor element, a resistance element, an inductance element, or an IC (integrated circuit). Further, the shape of the electrode terminal 4 of the circuit component 2 can be variously changed. (2) A protruding portion (overcoat glass film removal portion) can be provided along the interconnect region 5b as a relief portion (flow-in portion) for the conductive bonding material (solder) flowing continuously to the opening 8. (3) The wiring conductor 5 is not limited to the Ag-Pd conductor,
It may be silver (Ag) alone or another conductor containing silver.
【図１】従来及び本発明の実施例の回路基板装置を導電
性接合材（半田）を省いて示す平面図である。FIG. 1 is a plan view showing a conventional circuit board device and an embodiment of the present invention without a conductive bonding material (solder).
【図２】図１のＡ−Ａ線断面図である。FIG. 2 is a sectional view taken along line AA of FIG.
【図３】本発明の実施例に従う回路基板装置を図２と同
様に示す断面図である。FIG. 3 is a sectional view showing a circuit board device according to the embodiment of the present invention, similarly to FIG. 2;
１ 回路基板 ２ 回路部品 ４ 電極端子 ５ 配線導体 ６ａ 導電性接合材 DESCRIPTION OF SYMBOLS 1 Circuit board 2 Circuit component 4 Electrode terminal 5 Wiring conductor 6a Conductive bonding material
Claims (2)
域及び相互接続領域を有するように銀を含む厚膜導体材
料で形成された配線導体と、導電性接合材によって前記
端子接続領域に接続された端子を有する回路部品とを備
えた回路基板装置において、 前記導電性接合材が８１．５〜８７．５重量％のＰｂと
９．５〜１０．５重量％のＳｎと３．０〜８．０重量％
のＳｂとから成ることを特徴とする回路基板装置。1. A circuit board, a wiring conductor formed of a thick film conductor material containing silver so as to have a terminal connection area and an interconnection area on the circuit board, and connected to the terminal connection area by a conductive bonding material. A circuit component having a circuit component having a terminal, wherein the conductive bonding material is composed of 81.5 to 87.5% by weight of Pb, 9.5 to 10.5% by weight of Sn, and 3.0 to 3.0% by weight. 8.0% by weight
A circuit board device comprising: Sb.
領域及び相互接続領域を有するように形成された配線導
体を備えている回路基板を用意し、 前記端子接続領域に８１．５〜８７．５重量％のＰｂと
９．５〜１０．５重量％のＳｎと３．０〜８．０重量％
のＳｂとから成る導電性接合材ペーストを塗布し、 前記導電性接合材ペーストの上に回路部品の端子を配置
して加熱することによって前記端子を前記端子接続領域
に接続することを特徴とする回路基板装置の製造方法。2. A circuit board having a wiring conductor formed to have a terminal connection region and an interconnection region with a thick film conductor material containing silver is provided. 5% by weight of Pb, 9.5 to 10.5% by weight of Sn and 3.0 to 8.0% by weight
And applying a conductive bonding material paste made of Sb, and arranging and heating the terminals of the circuit component on the conductive bonding material paste, thereby connecting the terminals to the terminal connection regions. A method for manufacturing a circuit board device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9017906A JPH10209618A (en) | 1997-01-16 | 1997-01-16 | Circuit board device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9017906A JPH10209618A (en) | 1997-01-16 | 1997-01-16 | Circuit board device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10209618A true JPH10209618A (en) | 1998-08-07 |
Family
ID=11956796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9017906A Pending JPH10209618A (en) | 1997-01-16 | 1997-01-16 | Circuit board device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10209618A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100318317B1 (en) * | 1999-04-02 | 2001-12-22 | 김영환 | Bare Chip Mounting Printed Circuit Board |
| JP2003518743A (en) * | 1999-12-21 | 2003-06-10 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Organic packages with solder for reliable flip-chip connection |
-
1997
- 1997-01-16 JP JP9017906A patent/JPH10209618A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100318317B1 (en) * | 1999-04-02 | 2001-12-22 | 김영환 | Bare Chip Mounting Printed Circuit Board |
| JP2003518743A (en) * | 1999-12-21 | 2003-06-10 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Organic packages with solder for reliable flip-chip connection |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3436818A (en) | Method of fabricating a bonded joint | |
| JP3348528B2 (en) | Method for manufacturing semiconductor device, method for manufacturing semiconductor device and electronic circuit device, and electronic circuit device | |
| JP2763034B2 (en) | Semiconductor chip package | |
| JPS60119737A (en) | Method of forming back height solder connector | |
| US20160372293A1 (en) | Fuse in chip design | |
| JPH0810716B2 (en) | Electronic package | |
| EP0997941B1 (en) | Conductive paste and ceramic printed circuit substrate using the same | |
| JP3929675B2 (en) | Piezoelectric vibrator | |
| USRE27934E (en) | Circuit structure | |
| JPH081770B2 (en) | Electrical contact structure | |
| JP3369665B2 (en) | Ceramic lid substrate and ceramic lid for semiconductor package | |
| JP2007227718A (en) | Electronic component having resistive element and manufacturing method thereof | |
| JPH10209618A (en) | Circuit board device and its manufacture | |
| KR100715410B1 (en) | Hybrid integrated circuit | |
| US5962151A (en) | Method for controlling solderability of a conductor and conductor formed thereby | |
| JPH0677631A (en) | Mounting method of chip component onto aluminum board | |
| JP2515202B2 (en) | Ceramic wiring board and manufacturing method thereof | |
| JP7136672B2 (en) | Wiring board and electronic device | |
| JPH10223402A (en) | Chip part | |
| JP3024506B2 (en) | Connection method between Si chip and package | |
| JPH10173080A (en) | Circuit board device | |
| JP4346183B2 (en) | Fuse manufacturing method and chip-type fuse manufacturing method | |
| JP2002359104A (en) | Chip type thermistor | |
| JPH02244530A (en) | Base board type thermo-fuse and manufacture thereof | |
| JP3808358B2 (en) | Wiring board |