JPH10172920A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH10172920A JPH10172920A JP8342720A JP34272096A JPH10172920A JP H10172920 A JPH10172920 A JP H10172920A JP 8342720 A JP8342720 A JP 8342720A JP 34272096 A JP34272096 A JP 34272096A JP H10172920 A JPH10172920 A JP H10172920A
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- Prior art keywords
- film
- substrate
- semiconductor substrate
- semiconductor device
- ion implantation
- Prior art date
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- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本願の発明は、半導体基板と
金属膜とを反応させて半導体基板の拡散層上に化合物膜
を形成する半導体装置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a compound film is formed on a diffusion layer of a semiconductor substrate by reacting a semiconductor substrate with a metal film.
【０００２】[0002]
【従来の技術】半導体装置の微細化に伴う短チャネル効
果等を抑制するために、電界効果トランジスタのソース
／ドレイン等になっている拡散層を浅くする必要がある
が、拡散層を浅くすると、この拡散層のシート抵抗が増
大して、高速、低消費電力の半導体装置を製造すること
が困難になる。そこで、半導体と金属との低抵抗の化合
物膜であるＴｉＳｉ2 膜やＣｏＳｉ2 膜等を拡散層上に
形成する構造が考えられている。2. Description of the Related Art In order to suppress a short channel effect and the like accompanying miniaturization of a semiconductor device, it is necessary to make a diffusion layer serving as a source / drain of a field effect transistor shallow. The sheet resistance of the diffusion layer increases, and it becomes difficult to manufacture a high-speed, low-power-consumption semiconductor device. Therefore, a structure in which a TiSi 2 film, a CoSi 2 film, or the like, which is a low-resistance compound film of a semiconductor and a metal, is formed on the diffusion layer has been considered.
【０００３】図３は、この様な構造を有するＣＭＯＳト
ランジスタの製造方法の一従来例を示している。この一
従来例では、図３（ａ）に示す様に、Ｓｉ基板１１の表
面に素子分離酸化膜としてのＳｉＯ2 膜１２とゲート酸
化膜としてのＳｉＯ2 膜１３とを形成し、多結晶Ｓｉ膜
１４でゲート電極を形成する。FIG. 3 shows a conventional example of a method for manufacturing a CMOS transistor having such a structure. In this conventional example, as shown in FIG. 3A, an SiO 2 film 12 as an element isolation oxide film and an SiO 2 film 13 as a gate oxide film are formed on the surface of a Si substrate 11 to form a polycrystalline Si. A gate electrode is formed with the film 14.
【０００４】その後、多結晶Ｓｉ膜１４及びＳｉＯ2 膜
１２をマスクにして、ＮＭＯＳトランジスタの形成領域
にはＡｓを低濃度でイオン注入し、ＰＭＯＳトランジス
タの形成領域にはＢＦ2 を低濃度でイオン注入し、Ｓｉ
Ｏ2 膜１５でゲート電極の側壁スペーサを形成する。Thereafter, using the polycrystalline Si film 14 and the SiO 2 film 12 as masks, As is ion-implanted into the NMOS transistor formation region at a low concentration, and BF 2 is ion-implanted at a low concentration into the PMOS transistor formation region. Implanted, Si
The O 2 film 15 forms a side wall spacer of the gate electrode.
【０００５】そして、多結晶Ｓｉ膜１４及びＳｉＯ2 膜
１２、１５をマスクにして、ＮＭＯＳトランジスタの形
成領域にはＡｓを高濃度でイオン注入し、ＰＭＯＳトラ
ンジスタの形成領域にはＢＦ2 を高濃度でイオン注入し
て、ＬＤＤ構造のＮ型の拡散層１６及びＰ型の拡散層１
７を夫々形成する。Then, using the polycrystalline Si film 14 and the SiO 2 films 12 and 15 as masks, As is ion-implanted at a high concentration in the NMOS transistor formation region, and BF 2 is doped at a high concentration in the PMOS transistor formation region. The N type diffusion layer 16 and the P type diffusion layer 1 having the LDD structure are ion-implanted.
7 are formed respectively.
【０００６】次に、図３（ｂ）に示す様に、拡散層１
６、１７及び多結晶Ｓｉ膜１４上の自然酸化膜（図示せ
ず）を弗酸で完全に除去してから、Ｔｉ膜１８を全面に
形成する。そして、図３（ｃ）に示す様に、熱処理でＳ
ｉ基板１１及び多結晶Ｓｉ膜１４とＴｉ膜１８とを反応
させてＴｉＳｉ2 膜１９を選択的に形成し、アンモニア
過水等に浸して、ＳｉＯ2 膜１２、１５上に未反応のま
ま残っているＴｉ膜１８を除去する。[0006] Next, as shown in FIG.
After completely removing the native oxide films (not shown) on the polycrystalline Si film 14 and 6, 17 and the hydrofluoric acid, a Ti film 18 is formed on the entire surface. Then, as shown in FIG.
A TiSi 2 film 19 is selectively formed by reacting the i-substrate 11 and the polycrystalline Si film 14 with the Ti film 18, immersed in ammonia peroxide, etc., and left unreacted on the SiO 2 films 12 and 15. The remaining Ti film 18 is removed.
【０００７】次に、図３（ｄ）に示す様に、層間絶縁膜
２１を形成し、層間絶縁膜２１に接続孔２２を形成し、
ＴｉＮ／Ｔｉ膜２３及びＷ膜２４で接続孔２２を埋め
る。そして、Ｔｉ膜２５及びＡｌ−Ｓｉ膜２６で配線を
形成し、更に従来公知の工程を実行して、ＮＭＯＳトラ
ンジスタ２７及びＰＭＯＳトランジスタ２８を有するＣ
ＭＯＳトランジスタ２９を完成させる。Next, as shown in FIG. 3D, an interlayer insulating film 21 is formed, and a connection hole 22 is formed in the interlayer insulating film 21.
The connection holes 22 are filled with the TiN / Ti film 23 and the W film 24. Then, a wiring is formed with the Ti film 25 and the Al-Si film 26, and a conventionally known process is performed to form a wiring having an NMOS transistor 27 and a PMOS transistor 28.
The MOS transistor 29 is completed.
【０００８】[0008]
【発明が解決しようとする課題】ところが、ＣＭＯＳト
ランジスタ２９の微細化に伴って拡散層１６、１７の線
幅も狭くなってきており、Ａｓで形成して且つ線幅の狭
い拡散層１６上では、図３（ｃ）（ｄ）に示した様にＴ
ｉＳｉ2 膜１９が凝集する。この結果、ＴｉＳｉ2 膜１
９を形成しても拡散層１６のシート抵抗が低減しないと
いう細線効果が生じ易く、図３に示した一従来例では、
高速、低消費電力及び微細なＣＭＯＳトランジスタ２９
を製造することが困難であった。However, with the miniaturization of the CMOS transistor 29, the line width of the diffusion layers 16 and 17 has also been reduced, and the diffusion layers 16 and 17 are formed of As and have a small line width. , T as shown in FIGS.
The iSi 2 film 19 aggregates. As a result, the TiSi 2 film 1
Even if 9 is formed, the thin line effect that the sheet resistance of the diffusion layer 16 does not decrease is likely to occur, and in the conventional example shown in FIG.
High speed, low power consumption and fine CMOS transistor 29
Was difficult to manufacture.
【０００９】しかも、既述の様にＣＭＯＳトランジスタ
２９を微細化するためには拡散層１６を浅くする必要が
あるので、ＴｉＳｉ2 膜１９とＳｉ基板１１との短絡を
防止するためにＴｉＳｉ2 膜１９も薄くする必要があ
る。このため、ＴｉＳｉ2 膜１９が更に凝集し易くて、
高速、低消費電力及び微細なＣＭＯＳトランジスタ２９
を製造することが更に困難であった。Further, as described above, the diffusion layer 16 must be made shallow in order to miniaturize the CMOS transistor 29. Therefore, in order to prevent a short circuit between the TiSi 2 film 19 and the Si substrate 11, a TiSi 2 film is formed. 19 also needs to be thin. For this reason, the TiSi 2 film 19 is more easily aggregated,
High speed, low power consumption and fine CMOS transistor 29
Was more difficult to produce.
【００１０】これに対して、ＴｉＳｉ2 膜１９の代わり
にＣｏＳｉ2 膜を拡散層１６上に形成すると、細線効果
が生じにくい。しかし、ＣｏＳｉ2 膜の耐熱性はＴｉＳ
ｉ2膜１９と同等程度の７５０〜８００℃程度であまり
高くなく、その後の熱処理の余裕が小さくて、高速、低
消費電力及び微細な半導体装置を高い歩留りで製造する
ことが困難であった。On the other hand, if a CoSi 2 film is formed on the diffusion layer 16 instead of the TiSi 2 film 19, the thin line effect is less likely to occur. However, the heat resistance of the CoSi 2 film is TiS
The temperature is not so high at about 750 to 800 ° C., which is about the same as that of the i 2 film 19, and the margin of the subsequent heat treatment is small, so that it is difficult to manufacture a high-speed, low power consumption and fine semiconductor device with high yield.
【００１１】また、細線効果を抑制する別の方法とし
て、Ａｓのイオン注入でＳｉ基板１１の表面部を非晶質
化しておいた状態でＴｉ膜１８を形成し、その後の高速
熱処理でＴｉＳｉ2 膜１９を形成する方法があった。し
かし、この方法でも、耐熱性の高いＴｉＳｉ2 膜１９を
形成することはできなかった。As another method for suppressing the fine wire effect, a Ti film 18 is formed in a state where the surface of the Si substrate 11 is made amorphous by ion implantation of As, and then TiSi 2 is formed by high-speed heat treatment. There was a method of forming the film 19. However, even with this method, the TiSi 2 film 19 having high heat resistance could not be formed.
【００１２】一方、耐熱性の高いＴｉＳｉ2 膜１９を形
成する方法として、Ｓｉ基板１１上にＴｉ膜１８を形成
した状態でＳｉをイオン注入してＳｉ基板１１とＴｉ膜
１８との界面においてこれらを混合させ、その後の高速
熱処理でＴｉＳｉ2 膜１９を形成する方法があった。こ
の方法では、８５０℃程度までＴｉＳｉ2 膜１９の耐熱
性が向上していた。On the other hand, as a method for forming the TiSi 2 film 19 having high heat resistance, Si is ion-implanted in a state where the Ti film 18 is formed on the Si substrate 11, and these are formed at the interface between the Si substrate 11 and the Ti film 18. And then forming a TiSi 2 film 19 by high-speed heat treatment. In this method, the heat resistance of the TiSi 2 film 19 has been improved up to about 850 ° C.
【００１３】しかし、この方法で耐熱性の高いＴｉＳｉ
2 膜１９を形成するためには、１０15ｃｍ-2台以上のド
ーズ量でＳｉをイオン注入する必要があり、その結果、
Ｓｉ基板１１とＴｉ膜１８との界面に多数の結晶欠陥が
形成されて、この結晶欠陥をその後の熱処理で消滅させ
ることができなかった。このため、拡散層１６における
接合リーク電流が多くて、特性の優れたＣＭＯＳトラン
ジスタ２９を製造することが困難であった。However, in this method, TiSi having high heat resistance is used.
In order to form the second film 19, it is necessary to ion-implant Si with a dose of 10 15 cm −2 or more.
Many crystal defects were formed at the interface between the Si substrate 11 and the Ti film 18, and these crystal defects could not be eliminated by a subsequent heat treatment. For this reason, the junction leakage current in the diffusion layer 16 is large, and it is difficult to manufacture the CMOS transistor 29 having excellent characteristics.
【００１４】つまり、従来の上述の何れの方法でも、高
速、低消費電力及び微細で且つ特性の優れた半導体装置
を高い歩留りで製造することが困難であった。従って、
本願の発明は、高速、低消費電力及び微細で且つ特性の
優れた半導体装置を高い歩留りで製造することができる
半導体装置の製造方法を提供することを目的としてい
る。That is, it is difficult to manufacture a semiconductor device with high speed, low power consumption, fineness and excellent characteristics at a high yield by any of the above-mentioned conventional methods. Therefore,
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of manufacturing a semiconductor device with high speed, low power consumption, fineness, and excellent characteristics at a high yield.
【００１５】[0015]
【課題を解決するための手段】本願の発明による半導体
装置の製造方法は、半導体基板上に金属膜を形成し、前
記半導体基板と前記金属膜とを反応させて前記半導体基
板の拡散層上に化合物膜を形成する半導体装置の製造方
法において、前記金属膜の形成前に、前記半導体基板を
構成している原子の径以上の径を有する原子を前記半導
体基板にイオン注入して、この半導体基板の表面部を非
晶質化する工程と、前記金属膜の形成後に、前記半導体
基板を構成している原子の径以上の径を有する原子を前
記半導体基板にイオン注入して、この半導体基板と前記
金属膜との界面においてこれらを混合させる工程とを具
備することを特徴としている。According to a method of manufacturing a semiconductor device according to the present invention, a metal film is formed on a semiconductor substrate, and the semiconductor substrate reacts with the metal film to form a metal film on a diffusion layer of the semiconductor substrate. In the method of manufacturing a semiconductor device for forming a compound film, before forming the metal film, atoms having a diameter equal to or greater than the diameter of atoms constituting the semiconductor substrate are ion-implanted into the semiconductor substrate. Amorphizing the surface portion of the semiconductor substrate, and after forming the metal film, ion-implanting atoms having a diameter equal to or larger than the diameter of atoms constituting the semiconductor substrate into the semiconductor substrate, Mixing them at the interface with the metal film.
【００１６】本願の発明による半導体装置の製造方法
は、前記非晶質化のための前記イオン注入における投影
飛程が前記化合物膜の厚さの半分であることが好まし
い。In the method of manufacturing a semiconductor device according to the present invention, it is preferable that a projection range in the ion implantation for amorphization is half a thickness of the compound film.
【００１７】本願の発明による半導体装置の製造方法
は、前記混合のための前記イオン注入における投影飛程
が前記金属膜の厚さであることが好ましい。In the method of manufacturing a semiconductor device according to the present invention, it is preferable that a projection range in the ion implantation for the mixing is a thickness of the metal film.
【００１８】本願の発明による半導体装置の製造方法
は、前記非晶質化のための前記イオン注入及び前記混合
のための前記イオン注入におけるドーズ量が１×１０15
ｃｍ-2以下であることが好ましい。In the method of manufacturing a semiconductor device according to the present invention, the dose in the ion implantation for the amorphization and the ion implantation for the mixing is 1 × 10 15.
cm −2 or less.
【００１９】本願の発明による半導体装置の製造方法
は、前記半導体基板としてＳｉ基板を用い、前記径を有
する原子として、Ｓｉ、Ａｒ、Ｋｒ、Ｘｅ、Ａｓ、Ｇ
ｅ、Ｓｂの何れかを用いることができる。In the method of manufacturing a semiconductor device according to the present invention, a Si substrate is used as the semiconductor substrate, and Si, Ar, Kr, Xe, As, G
E or Sb can be used.
【００２０】本願の発明による半導体装置の製造方法
は、前記金属膜として、Ｔｉ膜、Ｃｏ膜、Ｎｉ膜、Ｐｔ
膜、Ａｕ膜、Ｃｕ膜、Ｚｒ膜、Ｈｆ膜、Ｐｄ膜、Ｗ膜、
Ｍｏ膜、Ｔａ膜、ＴｉＮ／Ｔｉ膜、ＴｉＮ／Ｃｏ膜、Ｔ
ｉ／Ｃｏ膜、Ｃｏ／Ｔｉ膜の何れかを用いることができ
る。In the method of manufacturing a semiconductor device according to the present invention, the metal film may be a Ti film, a Co film, a Ni film, or a Pt film.
Film, Au film, Cu film, Zr film, Hf film, Pd film, W film,
Mo film, Ta film, TiN / Ti film, TiN / Co film, T
Either an i / Co film or a Co / Ti film can be used.
【００２１】本願の発明による半導体装置の製造方法で
は、金属膜の形成前のイオン注入で半導体基板の表面部
を非晶質化しているので、半導体基板と金属膜との反応
が均一に進行して、線幅の細い拡散層上に化合物膜を形
成しても化合物膜が凝集しにくい。In the method of manufacturing a semiconductor device according to the present invention, since the surface of the semiconductor substrate is made amorphous by ion implantation before the formation of the metal film, the reaction between the semiconductor substrate and the metal film proceeds uniformly. Therefore, even when a compound film is formed on a diffusion layer having a small line width, the compound film is not easily aggregated.
【００２２】しかも、金属膜の形成後のイオン注入で半
導体基板と金属膜との界面においてこれらを混合させて
いるので、半導体基板と金属膜との反応が進行し易くて
化合物膜の結晶粒が大きくなると考えられること等によ
って、耐熱性の高い化合物膜を形成することができる。Moreover, since these are mixed at the interface between the semiconductor substrate and the metal film by ion implantation after the formation of the metal film, the reaction between the semiconductor substrate and the metal film is apt to proceed, and the crystal grains of the compound film are reduced. A compound film having high heat resistance can be formed by being considered to be large.
【００２３】更に、非晶質化及び混合の何れのイオン注
入でも、半導体基板を構成している原子の径以上の径を
有する原子を用いているので、非晶質化及び混合のため
に必要なドーズ量が少なくてよい。このため、化合物膜
の形成に伴って形成される結晶欠陥が少なく、この結晶
欠陥をその後の熱処理で消滅させることができる。In addition, in any of the ion implantation of the amorphization and the mixing, atoms having a diameter larger than the diameter of the atoms constituting the semiconductor substrate are used. The dose may be small. Therefore, few crystal defects are formed with the formation of the compound film, and the crystal defects can be eliminated by a subsequent heat treatment.
【００２４】また、非晶質化のためのイオン注入におけ
る投影飛程を化合物膜の厚さの半分にすれば、半導体基
板のうちで後に化合物膜が形成される部分を効果的に非
晶質化することができる。このため、半導体基板と金属
膜との反応が更に均一に進行して、線幅の細い拡散層上
に化合物膜を形成しても化合物膜が更に凝集しにくい。Further, if the projection range in ion implantation for amorphization is set to half the thickness of the compound film, the portion of the semiconductor substrate where the compound film is to be formed later can be effectively made amorphous. Can be For this reason, the reaction between the semiconductor substrate and the metal film proceeds more uniformly, and even when the compound film is formed on the diffusion layer having a small line width, the compound film is less likely to aggregate.
【００２５】また、混合のためのイオン注入における投
影飛程を金属膜の厚さにすれば、半導体基板と金属膜と
を効果的に混合させることができる。このため、半導体
基板と金属膜との反応が更に進行し易くて化合物膜の結
晶粒が更に大きくなると考えられること等によって、耐
熱性の更に高い化合物膜を形成することができる。If the projection range in the ion implantation for mixing is set to the thickness of the metal film, the semiconductor substrate and the metal film can be effectively mixed. For this reason, it is considered that the reaction between the semiconductor substrate and the metal film is more likely to proceed and the crystal grains of the compound film are further increased, so that a compound film having higher heat resistance can be formed.
【００２６】また、非晶質化及び混合の何れのイオン注
入でもドーズ量を１×１０15ｃｍ-2以下にすれば、化合
物膜の形成に伴って形成される結晶欠陥を効果的に減少
させることができ、この結晶欠陥をその後の熱処理で容
易に消滅させることができる。In addition, when the dose is set to 1 × 10 15 cm −2 or less in any of the ion implantation of the amorphization and the mixing, the crystal defects formed along with the formation of the compound film can be effectively reduced. This crystal defect can be easily eliminated by a subsequent heat treatment.
【００２７】[0027]
【発明の実施の形態】以下、ＣＭＯＳトランジスタの製
造に適用した本願の発明の第１〜第４実施形態を、図
１、２を参照しながら説明する。図１が、化合物膜とし
てＴｉＳｉ2 膜を形成する第１実施形態を示している。
この第１実施形態でも、図１（ａ）に示す様に、ＳｉＯ
2 膜１５でゲート電極の側壁スペーサを形成するまで
は、図３に示した一従来例と実質的に同様の工程を実行
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, first to fourth embodiments of the present invention applied to the manufacture of a CMOS transistor will be described with reference to FIGS. FIG. 1 shows a first embodiment in which a TiSi 2 film is formed as a compound film.
Also in the first embodiment, as shown in FIG.
Until the sidewall spacer of the gate electrode is formed by the two films 15, substantially the same steps as those of the conventional example shown in FIG. 3 are executed.
【００２８】しかし、この第１実施形態では、その後、
Ｏ2 ガスを４ｓｌｍの割合で供給し８００℃、１０分の
熱酸化を施して、厚さ１０ｎｍのＳｉＯ2 膜３１をＳｉ
基板１１の露出部の全面に形成する。However, in the first embodiment,
O 2 gas is supplied at a rate of 4 slm, and thermal oxidation is performed at 800 ° C. for 10 minutes to form a SiO 2 film 31 having a thickness of 10 nm on Si.
It is formed on the entire exposed portion of the substrate 11.
【００２９】そして、ＮＭＯＳトランジスタの形成領域
を覆うレジスト（図示せず）と多結晶Ｓｉ膜１４及びＳ
ｉＯ2 膜１２、１５とをマスクにして、４０ｋｅＶの加
速エネルギー及び３×１０15ｃｍ-2のドーズ量でＢＦ2
をイオン注入して、ＰＭＯＳトランジスタの形成領域に
Ｐ型の拡散層１７を形成する。Then, a resist (not shown) covering the formation region of the NMOS transistor, the polycrystalline Si film 14 and the S
Using the iO 2 films 12 and 15 as a mask, BF 2 is applied at an acceleration energy of 40 keV and a dose of 3 × 10 15 cm −2.
Is ion-implanted to form a P-type diffusion layer 17 in the formation region of the PMOS transistor.
【００３０】次に、図１（ｂ）に示す様に、ＳｉＯ2 膜
３１を弗酸で除去した後、ＰＭＯＳトランジスタの形成
領域を覆うレジスト（図示せず）と多結晶Ｓｉ膜１４及
びＳｉＯ2 膜１２、１５とをマスクにして、５０ｋｅＶ
の加速エネルギー及び３×１０15ｃｍ-2のドーズ量でＡ
ｓをイオン注入して、ＮＭＯＳトランジスタの形成領域
にＮ型の拡散層１６を形成する。そして、Ｎ2 雰囲気中
で１０００℃、１０秒の熱処理を施して、拡散層１６、
１７中の不純物を活性化させる。Next, as shown in FIG. 1B, after removing the SiO 2 film 31 with hydrofluoric acid, a resist (not shown) covering the formation region of the PMOS transistor, the polycrystalline Si film 14 and the SiO 2 film 50 keV using the films 12 and 15 as a mask
A at an acceleration energy of 3 × 10 15 cm -2
s is ion-implanted to form an N-type diffusion layer 16 in the formation region of the NMOS transistor. Then, a heat treatment at 1000 ° C. for 10 seconds is performed in an N 2 atmosphere to form a diffusion layer 16.
The impurities in 17 are activated.
【００３１】次に、緩衝弗酸で自然酸化膜（図示せず）
を除去してから、４０ｋｅＶの加速エネルギー及び３×
１０14ｃｍ-2のドーズ量でＳｉ基板１１の全面にＡｓを
イオン注入して、Ｓｉ基板１１の表面部を非晶質化す
る。このときのＡｓの投影飛程は、後に形成するＴｉＳ
ｉ2 膜１９の厚さの半分である。また、このときのドー
ズ量は１×１０15ｃｍ-2以下であればよい。Next, a natural oxide film (not shown) using buffered hydrofluoric acid
Is removed, the acceleration energy of 40 keV and 3 ×
As is ion-implanted into the entire surface of the Si substrate 11 at a dose of 10 14 cm -2 , the surface of the Si substrate 11 is made amorphous. At this time, the projection range of As is TiS to be formed later.
This is half the thickness of the i 2 film 19. The dose at this time may be 1 × 10 15 cm −2 or less.
【００３２】そして、再び緩衝弗酸で自然酸化膜（図示
せず）を除去してから、図１（ｃ）に示す様に、電力
０．５ｋＷ、温度１５０℃、Ａｒ１００ｓｃｃｍ、圧力
０．４７Ｐａのスパッタ法で、厚さ３０ｎｍのＴｉ膜１
８をＳｉ基板１１上の全面に形成する。Then, after removing the natural oxide film (not shown) again with buffered hydrofluoric acid, as shown in FIG. 1 (c), power of 0.5 kW, temperature of 150 ° C., Ar of 100 sccm, and pressure of 0.47 Pa were applied. 30 nm thick Ti film 1 by sputtering
8 is formed on the entire surface of the Si substrate 11.
【００３３】次に、図１（ｄ）に示す様に、３０ｋｅＶ
の加速エネルギー及び３×１０14ｃｍ-2のドーズ量でＳ
ｉをイオン注入して、Ｓｉ基板１１とＴｉ膜１８との界
面にこれらの混合領域３２を形成する。このときのＳｉ
の投影飛程は、Ｔｉ膜１８の厚さである。また、このと
きのドーズ量は１×１０15ｃｍ-2以下であればよい。Next, as shown in FIG.
At an acceleration energy of 3 and a dose of 3 × 10 14 cm -2
i is ion-implanted to form a mixed region 32 at the interface between the Si substrate 11 and the Ti film 18. Si at this time
Is the thickness of the Ti film 18. The dose at this time may be 1 × 10 15 cm −2 or less.
【００３４】次に、図１（ｅ）に示す様に、Ｎ2 ガスを
５ｓｌｍの割合で供給し６５０℃、３０秒の熱処理を施
して、Ｓｉ基板１１及び多結晶Ｓｉ膜１４とＴｉ膜１８
とを反応させてＴｉＳｉ2 膜１９を選択的に形成する。
そして、アンモニア過水に浸して、ＳｉＯ2 膜１２、１
５上に未反応のまま残っているＴｉ膜１８を除去した
後、再び、Ｎ2 ガスを５ｓｌｍの割合で供給し８００
℃、３０秒の熱処理を施して、ＴｉＳｉ2 膜１９を安定
化させる。Next, as shown in FIG. 1E, a N 2 gas is supplied at a rate of 5 slm, and a heat treatment is performed at 650 ° C. for 30 seconds, so that the Si substrate 11, the polycrystalline Si film 14, and the Ti film 18 are formed.
To form a TiSi 2 film 19 selectively.
Then, it is immersed in ammonia peroxide to form the SiO 2 films 12 and 1.
After removing the unreacted Ti film 18 on the substrate 5, N 2 gas is again supplied at a rate of 5 slm to 800
The heat treatment is performed at 30 ° C. for 30 seconds to stabilize the TiSi 2 film 19.
【００３５】次に、ＳｉＨ4 ／Ｏ2 ガス＝０．０３／
０．５４ｓｌｍ、温度４００℃、圧力１０．２Ｐａの減
圧ＣＶＤ法で厚さ１００ｎｍのＳｉＯ2 膜を形成する
か、または、ＳｉＨ2 Ｃｌ2 ／ＮＨ3 ／Ｎ2 ガス＝０．
０５／０．２／０．２ｓｌｍ、温度７６０℃、圧力７０
Ｐａの減圧ＣＶＤ法で厚さ５０ｎｍのＳｉＮ膜を形成す
る。Next, SiH 4 / O 2 gas = 0.03 /
Either a 100 nm thick SiO 2 film is formed by low pressure CVD at 0.54 slm, temperature of 400 ° C. and pressure of 10.2 Pa, or SiH 2 Cl 2 / NH 3 / N 2 gas = 0.
05 / 0.2 / 0.2 slm, temperature 760 ° C, pressure 70
An SiN film having a thickness of 50 nm is formed by the reduced pressure CVD method of Pa.
【００３６】そして、Ｏ3 ＋ＴＥＯＳガス＝５０ｓｃｃ
ｍ、温度７２０℃、圧力４０Ｐａの減圧ＣＶＤ法で厚さ
５００ｎｍのＢＰＳＧ膜を形成する。以上のＳｉＯ2 膜
またはＳｉＮ膜とＢＰＳＧ膜とで、図１（ｆ）に示す様
に、層間絶縁膜２１を形成する。Then, O 3 + TEOS gas = 50 scc
A BPSG film having a thickness of 500 nm is formed by low pressure CVD at a temperature of 720 ° C. and a pressure of 40 Pa. From the above SiO 2 film or SiN film and the BPSG film, an interlayer insulating film 21 is formed as shown in FIG.
【００３７】その後、層間絶縁膜２１上でレジスト（図
示せず）をパターニングし、このレジストをマスクにし
て、Ｃ4 Ｆ8 ガス＝５０ｓｃｃｍ、高周波電力１２００
Ｗ、圧力２Ｐａのドライエッチングを施して、層間絶縁
膜２１に接続孔２２を形成する。Thereafter, a resist (not shown) is patterned on the interlayer insulating film 21, and using this resist as a mask, C 4 F 8 gas = 50 sccm, high frequency power 1200
A connection hole 22 is formed in the interlayer insulating film 21 by performing dry etching at W and a pressure of 2 Pa.
【００３８】その後、接続孔２２のマスクずれに対応す
るために、レジスト（図示せず）及び層間絶縁膜２１を
マスクにして、ＮＭＯＳトランジスタの形成領域の接続
孔２２から露出しているＳｉ基板１１に５０ｋｅＶの加
速エネルギー及び３×１０15ｃｍ-2のドーズ量でＡｓを
イオン注入する。Thereafter, in order to cope with the mask displacement of the connection hole 22, the resist (not shown) and the interlayer insulating film 21 are used as a mask to expose the Si substrate 11 exposed from the connection hole 22 in the NMOS transistor formation region. As ions are implanted at an acceleration energy of 50 keV and a dose of 3 × 10 15 cm −2 .
【００３９】また、ＰＭＯＳトランジスタの形成領域の
接続孔２２から露出しているＳｉ基板１１に５０ｋｅＶ
の加速エネルギー及び３×１０15ｃｍ-2のドーズ量でＢ
Ｆ2をイオン注入する。そして、Ｎ2 雰囲気中で８５０
℃、３０秒の熱処理を施して、接続孔２２からＳｉ基板
１１にイオン注入した不純物を活性化させる。Further, 50 keV is applied to the Si substrate 11 exposed from the connection hole 22 in the formation region of the PMOS transistor.
B at an acceleration energy of 3 × 10 15 cm -2
F 2 is ion-implanted. 850 in an N 2 atmosphere
A heat treatment is performed at 30 ° C. for 30 seconds to activate the impurities ion-implanted into the Si substrate 11 from the connection holes 22.
【００４０】その後、電力８ｋＷ、温度１５０℃、Ａｒ
１００ｓｃｃｍ、圧力０．４７Ｐａのスパッタ法で厚さ
１０ｎｍのＴｉ膜を形成し、更に、電力５ｋＷ、Ａｒ／
Ｎ2＝４０／２０ｓｃｃｍ、圧力０．４７Ｐａの反応性
スパッタ法で厚さ７０ｎｍのＴｉＮ膜を形成して、接続
孔２２内を含むＳｉ基板１１上の全面にＴｉＮ／Ｔｉ膜
２３を形成する。Thereafter, power 8 kW, temperature 150 ° C., Ar
A Ti film having a thickness of 10 nm was formed by a sputtering method at 100 sccm and a pressure of 0.47 Pa. Further, a power of 5 kW and Ar /
A TiN film having a thickness of 70 nm is formed by a reactive sputtering method at N 2 = 40/20 sccm and a pressure of 0.47 Pa, and a TiN / Ti film 23 is formed on the entire surface of the Si substrate 11 including the inside of the connection hole 22.
【００４１】その後、Ａｒ／Ｎ2 ／Ｈ2 ／ＷＦ6 ガス＝
２２００／３００／５００／７５ｓｃｃｍ、温度４５０
℃、圧力１０６４０ＰａのＣＶＤ法で、厚さ４００ｎｍ
のＷ膜２４を形成する。そして、ＳＦ6 ガス＝５０ｓｃ
ｃｍ、高周波電力１５０Ｗ、圧力１．３３Ｐａのエッチ
バックを施して、ＴｉＮ／Ｔｉ膜２３及びＷ膜２４で接
続孔２２を埋める。Then, Ar / N 2 / H 2 / WF 6 gas =
2200/300/500/75 sccm, temperature 450
400 nm in thickness by CVD method at 10 ° C. and pressure of 10640 Pa
Is formed. And SF 6 gas = 50 sc
The connection hole 22 is filled with a TiN / Ti film 23 and a W film 24 by performing an etch-back process with a high-frequency power of 150 W and a pressure of 1.33 Pa.
【００４２】その後、電力４ｋＷ、温度１５０℃、Ａｒ
１００ｓｃｃｍ、圧力０．４７Ｐａのスパッタ法で厚さ
３０ｎｍのＴｉ膜２５を形成し、更に、電力２２．５ｋ
Ｗ、温度１５０℃、Ａｒ５０ｓｃｃｍ、圧力０．４７Ｐ
ａのスパッタ法で厚さ０．５μｍのＡｌ−Ｓｉ膜２６を
形成する。Thereafter, power 4 kW, temperature 150 ° C., Ar
A Ti film 25 having a thickness of 30 nm is formed by a sputtering method at 100 sccm and a pressure of 0.47 Pa.
W, temperature 150 ° C, Ar 50 sccm, pressure 0.47P
An Al—Si film 26 having a thickness of 0.5 μm is formed by the sputtering method a.
【００４３】その後、Ａｌ−Ｓｉ膜２６上でレジスト
（図示せず）をパターニングし、このレジストをマスク
にして、ＢＣｌ3 ／Ｃｌ2 ガス＝６０／９０ｓｃｃｍ、
マイクロ波電力１０００Ｗ、高周波電力５０Ｗ、圧力
０．０１６Ｐａのドライエッチングを施して、Ｔｉ膜２
５及びＡｌ−Ｓｉ膜２６で配線を形成する。そして、更
に従来公知の工程を実行して、ＮＭＯＳトランジスタ２
７及びＰＭＯＳトランジスタ２８を有するＣＭＯＳトラ
ンジスタ２９を完成させる。Thereafter, a resist (not shown) is patterned on the Al-Si film 26, and using this resist as a mask, BCl 3 / Cl 2 gas = 60/90 sccm,
Dry etching with a microwave power of 1000 W, a high frequency power of 50 W and a pressure of 0.016 Pa is performed to obtain a Ti film 2.
5 and the Al-Si film 26 are formed. Then, a conventionally well-known process is further performed, and the NMOS transistor 2
7 and a CMOS transistor 29 having a PMOS transistor 28 are completed.
【００４４】図２が、化合物膜としてＣｏＳｉ2 膜を形
成する第２実施形態の途中の工程であって上述の第１実
施形態における図１（ｃ）〜（ｅ）に対応する工程を示
している。この第２実施形態でも、Ａｓのイオン注入で
Ｓｉ基板１１の表面部を非晶質化した後、緩衝弗酸で自
然酸化膜を除去するまでは、図１に示した第１実施形態
と実質的に同様の工程を実行する。FIG. 2 shows a step in the course of the second embodiment for forming a CoSi 2 film as a compound film, and corresponds to FIGS. 1C to 1E in the first embodiment. I have. The second embodiment is substantially the same as the first embodiment shown in FIG. 1 until the surface portion of the Si substrate 11 is made amorphous by ion implantation of As and then the natural oxide film is removed with buffered hydrofluoric acid. A similar process is performed.
【００４５】しかし、この第２実施形態では、その後、
図２（ａ）に示す様に、電力０．５ｋＷ、温度１５０
℃、Ａｒ１００ｓｃｃｍ、圧力０．４７Ｐａのスパッタ
法で、厚さ２０ｎｍのＣｏ膜３３をＳｉ基板１１上の全
面に形成する。そして、図２（ｂ）に示す様に、第１実
施形態と同様の工程を実行して、Ｓｉ基板１１とＣｏ膜
３３との界面にこれらの混合領域３２を形成する。However, in the second embodiment,
As shown in FIG. 2A, the power is 0.5 kW and the temperature is 150
A Co film 33 having a thickness of 20 nm is formed on the entire surface of the Si substrate 11 by a sputtering method at 100 ° C., Ar 100 sccm, and pressure 0.47 Pa. Then, as shown in FIG. 2B, the same steps as in the first embodiment are performed to form a mixed region 32 at the interface between the Si substrate 11 and the Co film 33.
【００４６】次に、図２（ｃ）に示す様に、Ｎ2 ガスを
５ｓｌｍの割合で供給し５５０℃、３０秒の熱処理を施
して、Ｓｉ基板１１及び多結晶Ｓｉ膜１４とＣｏ膜３３
とを反応させてＣｏＳｉ2 膜３４を選択的に形成する。
そして、硫酸過水に浸して、ＳｉＯ2 膜１２、１５上に
未反応のまま残っているＣｏ膜３３を除去した後、再
び、Ｎ2 ガスを５ｓｌｍの割合で供給し７００℃、３０
秒の熱処理を施して、ＣｏＳｉ2 膜３４を安定化させ
る。Next, as shown in FIG. 2C, a N 2 gas is supplied at a rate of 5 slm, and a heat treatment is performed at 550 ° C. for 30 seconds, so that the Si substrate 11, the polycrystalline Si film 14 and the Co film 33 are formed.
To form a CoSi 2 film 34 selectively.
Then, after immersing in sulfuric acid and hydrogen peroxide to remove the unreacted Co film 33 on the SiO 2 films 12 and 15, N 2 gas is again supplied at a rate of 5 slm to 700 ° C. and 30 ° C.
A second heat treatment is performed to stabilize the CoSi 2 film 34.
【００４７】その後、再び、図１に示した第１実施形態
と実質的に同様の工程を実行して、ＮＭＯＳトランジス
タ２７とＰＭＯＳトランジスタ２８とを有するＣＭＯＳ
トランジスタ２９を完成させる。Thereafter, the steps substantially the same as those of the first embodiment shown in FIG. 1 are executed again, and a CMOS having an NMOS transistor 27 and a PMOS transistor 28 is formed.
The transistor 29 is completed.
【００４８】次に、Ｓｉ基板１１の表面部の非晶質化及
び混合領域３２の形成のためにＳｂをイオン注入する第
３実施形態を説明する。この第３実施形態でも、拡散層
１６、１７中の不純物を活性化させた後、緩衝弗酸で自
然酸化膜を除去するまでは、図１に示した第１実施形態
と実質的に同様の工程を実行する。Next, a description will be given of a third embodiment in which Sb is ion-implanted for amorphizing the surface portion of the Si substrate 11 and forming the mixed region 32. Also in the third embodiment, after the impurities in the diffusion layers 16 and 17 are activated, the process is substantially the same as that of the first embodiment shown in FIG. 1 until the natural oxide film is removed with buffered hydrofluoric acid. Execute the process.
【００４９】しかし、この第３実施形態では、その後、
４０ｋｅＶの加速エネルギー及び１×１０14ｃｍ-2のド
ーズ量でＳｉ基板１１の全面にＳｂをイオン注入して、
Ｓｉ基板１１の表面部を非晶質化する。この場合、Ｓｂ
の原子の径がＡｓの原子の径よりも大きいので、非晶質
化のために必要なドーズ量が第１実施形態におけるＡｓ
の３×１０14ｃｍ-2よりも少なくてよい。However, in the third embodiment,
Sb is ion-implanted into the entire surface of the Si substrate 11 at an acceleration energy of 40 keV and a dose of 1 × 10 14 cm −2 ,
The surface of the Si substrate 11 is made amorphous. In this case, Sb
Is larger than the diameter of the As atom, the dose required for amorphization is lower than that of the As in the first embodiment.
Less than 3 × 10 14 cm −2 .
【００５０】そして、第１実施形態と同様の工程を実行
してＴｉ膜１８の形成までを行った後、３０ｋｅＶの加
速エネルギー及び１×１０14ｃｍ-2のドーズ量でＳｂを
イオン注入して、Ｓｉ基板１１とＴｉ膜１８との界面に
これらの混合領域３２を形成する。その後、再び、図１
に示した第１実施形態と実質的に同様の工程を実行し
て、ＮＭＯＳトランジスタ２７とＰＭＯＳトランジスタ
２８とを有するＣＭＯＳトランジスタ２９を完成させ
る。After performing the same steps as in the first embodiment up to the formation of the Ti film 18, Sb is ion-implanted at an acceleration energy of 30 keV and a dose of 1 × 10 14 cm −2. The mixed region 32 is formed at the interface between the Si substrate 11 and the Ti film 18. Then again, FIG.
A CMOS transistor 29 having an NMOS transistor 27 and a PMOS transistor 28 is completed by executing substantially the same steps as those of the first embodiment shown in FIG.
【００５１】次に、Ｃｏ膜上にＴｉＮ膜またはＴｉ膜を
積層させた構造から、化合物膜としてのＣｏＳｉ2 膜を
形成する第４実施形態を説明する。この第４実施形態で
も、Ａｓのイオン注入でＳｉ基板１１の表面部を非晶質
化した後、緩衝弗酸で自然酸化膜を除去するまでは、上
述の第２実施形態と実質的に同様の工程を実行する。Next, a fourth embodiment in which a CoSi 2 film is formed as a compound film from a structure in which a TiN film or a Ti film is laminated on a Co film will be described. Also in this fourth embodiment, after the surface of the Si substrate 11 is made amorphous by ion implantation of As, the process is substantially the same as that of the above-described second embodiment until the natural oxide film is removed with buffered hydrofluoric acid. Is performed.
【００５２】しかし、この第４実施形態では、その後、
電力１ｋＷ、Ａｒ１００ｓｃｃｍ、圧力０．４７Ｐａの
スパッタ法で、厚さ１０ｎｍのＣｏ膜をＳｉ基板１１上
の全面に形成する。そして、引き続き、電力５ｋＷ、Ａ
ｒ／Ｎ2 ＝４０／２０ｓｃｃｍ、圧力０．４７Ｐａの反
応性スパッタ法で、厚さ２０ｎｍのＴｉＮ膜をＣｏ膜上
の全面に形成する。However, in the fourth embodiment,
A Co film having a thickness of 10 nm is formed on the entire surface of the Si substrate 11 by a sputtering method with a power of 1 kW, Ar of 100 sccm, and a pressure of 0.47 Pa. Then, continuously, power 5 kW, A
A TiN film having a thickness of 20 nm is formed on the entire surface of the Co film by a reactive sputtering method at r / N 2 = 40/20 sccm and a pressure of 0.47 Pa.
【００５３】なお、電力０．５ｋＷ、Ａｒ／Ｎ2 ＝４０
／２０ｓｃｃｍ、圧力０．４７Ｐａのスパッタ法で、厚
さ１０ｎｍのＴｉ膜を上述のＴｉＮ膜の代わりに形成し
てもよい。その後、再び、上述の第２実施形態と実質的
に同様の工程を実行して、ＮＭＯＳトランジスタ２７と
ＰＭＯＳトランジスタ２８とを有するＣＭＯＳトランジ
スタ２９を完成させる。The power is 0.5 kW, Ar / N 2 = 40.
A Ti film having a thickness of 10 nm may be formed by a sputtering method of / 20 sccm and a pressure of 0.47 Pa instead of the above-described TiN film. Thereafter, the steps substantially the same as those of the above-described second embodiment are executed again to complete the CMOS transistor 29 having the NMOS transistor 27 and the PMOS transistor 28.
【００５４】この様な第４実施形態では、Ｃｏ膜上のＴ
ｉＮ膜またはＴｉ膜が、Ｃｏ膜の表面の酸化を防止して
このＣｏ膜の実質的な厚さが減少するのを防止すること
ができる。また、Ｓｉ基板１１の表面の自然酸化膜や吸
着された酸素を、ＴｉＮ膜またはＴｉ膜がＣｏ膜を介し
て吸着して、Ｓｉ基板１１とＣｏ膜とを均一に反応させ
ることができて、Ｓｉ基板１１に形成される結晶欠陥を
低減させることができる。In the fourth embodiment, the T on the Co film
The iN film or the Ti film can prevent the surface of the Co film from being oxidized, thereby preventing the substantial thickness of the Co film from decreasing. Also, the natural oxide film or the adsorbed oxygen on the surface of the Si substrate 11 is adsorbed by the TiN film or the Ti film via the Co film, so that the Si substrate 11 and the Co film can react uniformly, Crystal defects formed in the Si substrate 11 can be reduced.
【００５５】なお、以上の第１〜第４実施形態はＣＭＯ
Ｓトランジスタの製造に本願の発明を適用したものであ
るが、ＮＭＯＳトランジスタまたはＰＭＯＳトランジス
タのみやバイポーラトランジスタやＣＣＤ撮像素子や液
晶表示素子等の製造にも本願の発明を適用することがで
きる。また、以上の第１〜第４実施形態ではＴｉ膜１８
やＣｏ膜３３をスパッタ法で形成しているが、これらの
膜をＣＶＤ法で形成してもよい。It should be noted that the above-described first to fourth embodiments use the CMO
Although the invention of the present application is applied to the manufacture of an S transistor, the invention of the present application can also be applied to the manufacture of only an NMOS transistor or a PMOS transistor, a bipolar transistor, a CCD imaging device, a liquid crystal display device, and the like. In the first to fourth embodiments, the Ti film 18 is used.
Although the Co film 33 and the Co film 33 are formed by the sputtering method, these films may be formed by the CVD method.
【００５６】また、以上の第１〜第４実施形態では、Ｓ
ｉ基板１１の表面部の非晶質化や混合領域３２の形成の
ために、Ａｓ、Ｓｉ、Ｓｂを用いているが、Ａｒ、Ｋ
ｒ、Ｘｅ、Ｇｅ等のうちの何れかを用いてもよい。In the first to fourth embodiments, S
As, Si, and Sb are used for amorphization of the surface portion of the i-substrate 11 and formation of the mixed region 32.
Any of r, Xe, Ge and the like may be used.
【００５７】また、以上の第１〜第４実施形態では、化
合物膜を形成するための金属膜として、Ｔｉ膜、Ｃｏ
膜、ＴｉＮ／Ｃｏ膜、Ｔｉ／Ｃｏ膜を用いているが、Ｎ
ｉ膜、Ｐｔ膜、Ａｕ膜、Ｃｕ膜、Ｚｒ膜、Ｈｆ膜、Ｐｄ
膜、Ｗ膜、Ｍｏ膜、Ｔａ膜、ＴｉＮ／Ｔｉ膜、Ｃｏ／Ｔ
ｉ膜等のうちの何れかを用いてもよい。In the first to fourth embodiments described above, a Ti film, a Co film,
Film, TiN / Co film and Ti / Co film are used.
i film, Pt film, Au film, Cu film, Zr film, Hf film, Pd
Film, W film, Mo film, Ta film, TiN / Ti film, Co / T
Any of the i-film and the like may be used.
【００５８】[0058]
【発明の効果】本願の発明による半導体装置の製造方法
では、線幅の細い拡散層上に化合物膜を形成しても化合
物膜が凝集しにくいので、細線効果を抑制することがで
き、しかも、耐熱性の高い化合物膜を形成することがで
きるので、その後の熱処理の余裕が大きくて、高速、低
消費電力及び微細な半導体装置を高い歩留りで製造する
ことができる。In the method of manufacturing a semiconductor device according to the present invention, even when a compound film is formed on a diffusion layer having a small line width, the compound film is not easily aggregated, so that the thin line effect can be suppressed. Since a compound film having high heat resistance can be formed, a margin for a subsequent heat treatment is large, and high-speed, low power consumption, and a fine semiconductor device can be manufactured with high yield.
【００５９】更に、化合物膜の形成に伴って形成される
結晶欠陥をその後の熱処理で消滅させることができるの
で、拡散層における接合リーク電流が少なくて、特性の
優れた半導体装置を製造することができる。Further, since the crystal defects formed during the formation of the compound film can be eliminated by the subsequent heat treatment, it is possible to manufacture a semiconductor device having a small junction leak current in the diffusion layer and excellent characteristics. it can.
【００６０】また、非晶質化のためのイオン注入におけ
る投影飛程を化合物膜の厚さの半分にすれば、線幅の細
い拡散層上に化合物膜を形成しても化合物膜が更に凝集
しにくいので、細線効果を更に抑制することができて、
更に高速、低消費電力及び微細な半導体装置を製造する
ことができる。If the projection range in ion implantation for amorphization is set to half the thickness of the compound film, the compound film is further aggregated even if the compound film is formed on a diffusion layer having a small line width. It is difficult to perform, so the fine line effect can be further suppressed,
Further, a high-speed, low power consumption, and fine semiconductor device can be manufactured.
【００６１】また、混合のためのイオン注入における投
影飛程を金属膜の厚さにすれば、耐熱性の更に高い化合
物膜を形成することができるので、高速、低消費電力及
び微細な半導体装置を更に高い歩留りで製造することが
できる。Further, if the projection range in the ion implantation for mixing is set to the thickness of the metal film, a compound film having higher heat resistance can be formed, so that high speed, low power consumption and fine semiconductor device can be achieved. Can be manufactured with a higher yield.
【００６２】また、非晶質化及び混合の何れのイオン注
入でもドーズ量を１×１０15ｃｍ-2以下にすれば、化合
物膜の形成に伴って形成される結晶欠陥をその後の熱処
理で容易に消滅させることができるので、拡散層におけ
る接合リーク電流が更に少なくて、特性の更に優れた半
導体装置を製造することができる。When the dose is set to 1 × 10 15 cm −2 or less in any of the ion implantation of the amorphization and the mixing, the crystal defects formed along with the formation of the compound film can be easily formed by the subsequent heat treatment. Therefore, the junction leakage current in the diffusion layer is further reduced, and a semiconductor device having more excellent characteristics can be manufactured.
【図１】本願の発明の第１実施形態を順次に示す側断面
図である。FIG. 1 is a side sectional view sequentially showing a first embodiment of the present invention.
【図２】本願の発明の第２実施形態の途中の工程であっ
て図１（ｃ）〜（ｅ）に対応する工程を順次に示す側断
面図である。FIG. 2 is a side sectional view showing steps in the middle of a second embodiment of the present invention and corresponding to FIGS. 1 (c) to (e) in order.
【図３】本願の発明の一従来例を順次に示す側断面図で
ある。FIG. 3 is a side sectional view sequentially showing one conventional example of the invention of the present application.
１１ Ｓｉ基板（半導体基板） １６、１７ 拡
散層 １８ Ｔｉ膜（金属膜） １９ ＴｉＳｉ
2 膜（化合物膜） ３２ 混合領域 ３３ Ｃｏ膜（金属膜） ３４ Ｃｏ
Ｓｉ2 膜（化合物膜）Reference Signs List 11 Si substrate (semiconductor substrate) 16, 17 Diffusion layer 18 Ti film (metal film) 19 TiSi
2 film (compound film) 32 mixed region 33 Co film (metal film) 34 Co
Si 2 film (compound film)
Claims (6)
導体基板と前記金属膜とを反応させて前記半導体基板の
拡散層上に化合物膜を形成する半導体装置の製造方法に
おいて、 前記金属膜の形成前に、前記半導体基板を構成している
原子の径以上の径を有する原子を前記半導体基板にイオ
ン注入して、この半導体基板の表面部を非晶質化する工
程と、 前記金属膜の形成後に、前記半導体基板を構成している
原子の径以上の径を有する原子を前記半導体基板にイオ
ン注入して、この半導体基板と前記金属膜との界面にお
いてこれらを混合させる工程とを具備することを特徴と
する半導体装置の製造方法。1. A method for manufacturing a semiconductor device, comprising: forming a metal film on a semiconductor substrate; and reacting the semiconductor substrate with the metal film to form a compound film on a diffusion layer of the semiconductor substrate. Prior to the formation of, the step of ion-implanting atoms having a diameter equal to or greater than the diameter of the atoms constituting the semiconductor substrate into the semiconductor substrate to amorphize a surface portion of the semiconductor substrate; After the formation of, a step of ion-implanting atoms having a diameter equal to or greater than the diameter of the atoms constituting the semiconductor substrate into the semiconductor substrate, and mixing them at the interface between the semiconductor substrate and the metal film. A method of manufacturing a semiconductor device.
おける投影飛程が前記化合物膜の厚さの半分であること
を特徴とする請求項１記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein a projection range in said ion implantation for said amorphization is half the thickness of said compound film.
る投影飛程が前記金属膜の厚さであることを特徴とする
請求項１記載の半導体装置の製造方法。3. The method according to claim 1, wherein a projection range in the ion implantation for the mixing is a thickness of the metal film.
び前記混合のための前記イオン注入におけるドーズ量が
１×１０15ｃｍ-2以下であることを特徴とする請求項１
記載の半導体装置の製造方法。4. The method according to claim 1, wherein a dose in said ion implantation for said amorphousization and said ion implantation for said mixing is 1 × 10 15 cm −2 or less.
The manufacturing method of the semiconductor device described in the above.
Ａｓ、Ｇｅ、Ｓｂの何れかを用いることを特徴とする請
求項１記載の半導体装置の製造方法。5. An Si substrate is used as the semiconductor substrate, and Si, Ar, Kr, Xe,
2. The method for manufacturing a semiconductor device according to claim 1, wherein any one of As, Ge, and Sb is used.
ｉ膜、Ｐｔ膜、Ａｕ膜、Ｃｕ膜、Ｚｒ膜、Ｈｆ膜、Ｐｄ
膜、Ｗ膜、Ｍｏ膜、Ｔａ膜、ＴｉＮ／Ｔｉ膜、ＴｉＮ／
Ｃｏ膜、Ｔｉ／Ｃｏ膜、Ｃｏ／Ｔｉ膜の何れかを用いる
ことを特徴とする請求項１記載の半導体装置の製造方
法。6. The metal film as a Ti film, a Co film, a N film,
i film, Pt film, Au film, Cu film, Zr film, Hf film, Pd
Film, W film, Mo film, Ta film, TiN / Ti film, TiN /
2. The method according to claim 1, wherein one of a Co film, a Ti / Co film, and a Co / Ti film is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8342720A JPH10172920A (en) | 1996-12-06 | 1996-12-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8342720A JPH10172920A (en) | 1996-12-06 | 1996-12-06 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10172920A true JPH10172920A (en) | 1998-06-26 |
Family
ID=18355975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8342720A Pending JPH10172920A (en) | 1996-12-06 | 1996-12-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10172920A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6399485B1 (en) | 1999-07-28 | 2002-06-04 | Nec Corporation | Semiconductor device with silicide layers and method of forming the same |
-
1996
- 1996-12-06 JP JP8342720A patent/JPH10172920A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6399485B1 (en) | 1999-07-28 | 2002-06-04 | Nec Corporation | Semiconductor device with silicide layers and method of forming the same |
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