JPH10163582A - Printed board for reflow soldering - Google Patents
Printed board for reflow solderingInfo
- Publication number
- JPH10163582A JPH10163582A JP31596596A JP31596596A JPH10163582A JP H10163582 A JPH10163582 A JP H10163582A JP 31596596 A JP31596596 A JP 31596596A JP 31596596 A JP31596596 A JP 31596596A JP H10163582 A JPH10163582 A JP H10163582A
- Authority
- JP
- Japan
- Prior art keywords
- soldering
- pattern
- land
- circuit board
- lands
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、リフロー半田付け
用プリント基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board for reflow soldering.
【０００２】[0002]
【従来の技術】以下、従来のリフロー半田付け用プリン
ト基板について説明する。2. Description of the Related Art A conventional printed circuit board for reflow soldering will be described below.
【０００３】従来のリフロー半田付け用プリント基板
は、図３に示すものである。図３に於いて、１はプリン
ト基板であり、２は小形の半田付けランド、３は大形の
半田付けランドである。また、４は半田付けランド２と
半田付けランド３を接続するパターンである。そして、
パターン４上には、レジスト５が印刷されている。A conventional printed circuit board for reflow soldering is shown in FIG. In FIG. 3, 1 is a printed circuit board, 2 is a small soldering land, and 3 is a large soldering land. Reference numeral 4 denotes a pattern for connecting the soldering lands 2 and 3. And
A resist 5 is printed on the pattern 4.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うな従来の構成では、図４に示す様にリフロー半田付け
を行うと、半田付けランド２と半田付けランド３とが近
接している場合に於いては、半田付けランド２の半田が
半田付けランド３の方へ吸い取られて、半田付けランド
２の半田付け不良が生ずるという障害があった。これ
は、半田付けランド２の熱がパターン４を介して半田付
けランド３に伝わったためである。However, in such a conventional configuration, when reflow soldering is performed as shown in FIG. 4, when the soldering land 2 and the soldering land 3 are close to each other, Further, there is an obstacle that the solder of the soldering land 2 is sucked toward the soldering land 3 and a soldering defect of the soldering land 2 occurs. This is because the heat of the soldering land 2 was transmitted to the soldering land 3 via the pattern 4.
【０００５】本発明は、このような問題点を解決するも
ので、半田付け不良の生じないリフロー半田付け用プリ
ント基板を提供することを目的としたものである。An object of the present invention is to solve such a problem, and an object of the present invention is to provide a printed circuit board for reflow soldering which does not cause defective soldering.
【０００６】[0006]
【課題を解決するための手段】この目的を達成するため
に本発明のリフロー半田付け用プリント基板は、半田付
けランド間に設けられたパターン上に、パターンの不形
成部を設けたものである。これにより、半田付け不良を
無くすことができる。In order to achieve this object, a printed circuit board for reflow soldering according to the present invention has a pattern-free portion provided on a pattern provided between soldering lands. . As a result, it is possible to eliminate soldering defects.
【０００７】[0007]
【発明の実施の形態】本発明の請求項１に記載の発明
は、プリント基板と、このプリント基板上に形成された
複数個の半田付けランドと、この半田付けランド間が近
接するとともに、前記半田付けランド間が接続されるパ
ターンと、このパターン上に印刷されたレジストとを備
え、前記パターン上にパターンの不形成部を設けたリフ
ロー半田付け用プリント基板であり、これにより半田付
けランド間に設けられたパターン上にパターンの不形成
部を設けているので、一方のランドの熱が他方のランド
に伝わりにくく半田付け不良がなくなる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a printed circuit board, a plurality of solder lands formed on the printed board, A printed circuit board for reflow soldering comprising a pattern connected between the soldering lands, and a resist printed on the pattern, and a pattern-free portion provided on the pattern. Since the pattern non-formed portion is provided on the pattern provided in the above, the heat of one land is not easily transmitted to the other land, and the soldering failure is eliminated.
【０００８】請求項２に記載の発明は、パターンの不形
成部の形成による半田付けランド間の導通を補うべくパ
ターンの巾を少なくとも一方の半田付けランドよりも太
くした請求項１に記載のリフロー半田付け用プリント基
板であり、たとえパターンの不形成部を設けていてもパ
ターン巾を太くしているので、交流的な特性を維持する
ことができる。According to a second aspect of the present invention, the width of the pattern is made larger than at least one of the soldering lands so as to compensate for conduction between the soldering lands due to the formation of the non-formed portion. This is a printed circuit board for soldering. Even if a pattern non-formed portion is provided, the pattern width is widened, so that it is possible to maintain AC characteristics.
【０００９】以下、本発明の実施の形態について、図
１、図２を用いて説明する。図１において１１は、プリ
ント基板であり、１２はこのプリント基板１１上に設け
られた小形の半田付けランドであり、１３は大形の半田
付けランドである。そして半田付けランド１２，１３の
間はパターン１４で導通されている。また、パターン１
４上にはレジスト印刷１５が設けられている。１６は半
田付けランド１２と半田付けランド１３の間のパターン
１４上に設けられたパターンの不形成部である。このパ
ターンの不形成部１６の中心は、半田付けランド１２と
半田付けランド１３の中心線上に設けられている。ここ
に於いて、この半田付けランド１２と半田付けランド１
３の半田が塗布されるランド間の距離（ランド部を除い
たパターン間の距離）は、本実施の形態に於いては、略
０．５〜１．０ｍｍとしている。この場合に於いてパタ
ーンの不形成部１６も略０．５〜１．０ｍｍ（短部の中
心線長）の楕円形にしたものである。なお、これは円形
でも良い。いずれにしても重要なことは不形成部１６を
形成することである。この不形成部１６により半田熱の
伝導は少なくなり、一方のランドの半田が他方のランド
に吸い取られて半田付け不良を生ずることはなくなる。
また、半田付けランド１２と半田付けランド１３を接続
するパターン１４の残余の部分１４ａ，１４ｂを設けて
おくことも重要である。なお、半田付けランド１２と半
田付けランド１３は同形でもよい。An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, reference numeral 11 denotes a printed board, 12 denotes a small soldering land provided on the printed board 11, and 13 denotes a large soldering land. The lands 12 and 13 are electrically connected by a pattern 14. Also, pattern 1
A resist print 15 is provided on 4. Reference numeral 16 denotes a non-formed portion of the pattern provided on the pattern 14 between the soldering land 12 and the soldering land 13. The center of the non-formed portion 16 of this pattern is provided on the center line of the soldering lands 12 and 13. Here, the soldering land 12 and the soldering land 1
The distance between the lands to which the solder No. 3 is applied (the distance between the patterns excluding the land portion) is approximately 0.5 to 1.0 mm in the present embodiment. In this case, the non-patterned portion 16 is also formed into an elliptical shape of approximately 0.5 to 1.0 mm (the center line length of the short portion). This may be circular. In any case, what is important is to form the non-formed portion 16. The conduction of the solder heat is reduced by the non-formed portion 16, so that the solder of one land is not sucked by the other land and the soldering failure does not occur.
It is also important to provide the remaining portions 14a and 14b of the pattern 14 connecting the solder lands 12 and the solder lands 13. The soldering lands 12 and the soldering lands 13 may have the same shape.
【００１０】図２は、パターンの不形成部１６によって
半田付けランド１２と半田付けランド１３の電気性能を
補うべく半田付けランド１２と半田付けランド１３の間
に設けられたパターン１７の巾を太くしたものである。
このようにパターン１７を太くするのは電気性能を補う
ものである。そのパターン１７の太さは、パターンの不
形成部１６以上であり残余の部分１７ａが小形の半田付
けランド１２と同等以上が望ましい。FIG. 2 shows that the width of a pattern 17 provided between the soldering land 12 and the soldering land 13 is increased in order to supplement the electrical performance of the soldering land 12 and the soldering land 13 by the pattern non-formed portion 16. It was done.
Increasing the thickness of the pattern 17 in this way supplements the electrical performance. The thickness of the pattern 17 is desirably equal to or larger than the non-formed portion 16 and the remaining portion 17a is equal to or larger than the small soldering land 12.
【００１１】[0011]
【発明の効果】以上のように本発明によれば、半田付け
ランド間に設けられたパターン上にパターンの不形成部
を設けているので、一方のランドの熱が他方のランドに
伝わりにくく半田付け不良がなくなる。As described above, according to the present invention, since the pattern non-formed portion is provided on the pattern provided between the soldering lands, the heat of one land is hardly transmitted to the other land. Eliminates poor mounting.
【図１】本発明の一実施の形態によるリフロー半田付け
用プリント基板の要部平面図FIG. 1 is a plan view of a main part of a printed circuit board for reflow soldering according to an embodiment of the present invention.
【図２】同、他の例によるリフロー半田付け用プリント
基板の要部平面図FIG. 2 is a plan view of a main part of a printed circuit board for reflow soldering according to another example of the same.
【図３】従来のリフロー半田付け用プリント基板の要部
斜視図FIG. 3 is a perspective view of a main part of a conventional printed circuit board for reflow soldering.
【図４】同、リフロー半田付け用プリント基板の要部断
面図FIG. 4 is a sectional view of a main part of the printed circuit board for reflow soldering;
１１ プリント基板 １２ 小形半田付けランド １３ 大形半田付けランド １４ パターン １５ レジスト １６ パターンの不形成部 DESCRIPTION OF SYMBOLS 11 Printed circuit board 12 Small soldering land 13 Large soldering land 14 Pattern 15 Resist 16 Non-formed part of pattern
───────────────────────────────────────────────────── フロントページの続き (72)発明者 真保 俊治 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shunji Maho 1006 Kazuma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.
Claims (2)
形成された複数個の半田付けランドと、この半田付けラ
ンド間が近接するとともに、前記半田付けランド間が接
続されるパターンと、このパターン上に印刷されたレジ
ストとを備え、前記パターン上にパターンの不形成部を
設けたリフロー半田付け用プリント基板。1. A printed circuit board, a plurality of solder lands formed on the printed circuit board, a pattern in which the solder lands are close to each other, and the solder lands are connected to each other; A printed circuit board for reflow soldering, comprising: a resist printed thereon; and a pattern-free portion provided on the pattern.
けランド間の導通を補うべくパターンの巾を少なくとも
一方の半田付けランドよりも太くした請求項１に記載の
リフロー半田付け用プリント基板。2. The printed circuit board according to claim 1, wherein the width of the pattern is larger than that of at least one of the solder lands so as to compensate for conduction between the solder lands due to the formation of the non-formed portions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08315965A JP3127845B2 (en) | 1996-11-27 | 1996-11-27 | Printed circuit board for reflow soldering |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08315965A JP3127845B2 (en) | 1996-11-27 | 1996-11-27 | Printed circuit board for reflow soldering |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10163582A true JPH10163582A (en) | 1998-06-19 |
| JP3127845B2 JP3127845B2 (en) | 2001-01-29 |
Family
ID=18071725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP08315965A Expired - Fee Related JP3127845B2 (en) | 1996-11-27 | 1996-11-27 | Printed circuit board for reflow soldering |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3127845B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100330579B1 (en) * | 1999-08-30 | 2002-03-29 | 윤종용 | Quad flat package ic mounted pcb and soldering method thereof |
| KR100330580B1 (en) * | 1999-08-30 | 2002-03-29 | 윤종용 | Quad flat package ic mounted pcb and soldering method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102883529A (en) * | 2012-10-12 | 2013-01-16 | 广东易事特电源股份有限公司 | Packaging structure two-pin element |
-
1996
- 1996-11-27 JP JP08315965A patent/JP3127845B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100330579B1 (en) * | 1999-08-30 | 2002-03-29 | 윤종용 | Quad flat package ic mounted pcb and soldering method thereof |
| KR100330580B1 (en) * | 1999-08-30 | 2002-03-29 | 윤종용 | Quad flat package ic mounted pcb and soldering method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3127845B2 (en) | 2001-01-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |