JPH10163416A - Power semiconductor module - Google Patents
Power semiconductor moduleInfo
- Publication number
- JPH10163416A JPH10163416A JP8321440A JP32144096A JPH10163416A JP H10163416 A JPH10163416 A JP H10163416A JP 8321440 A JP8321440 A JP 8321440A JP 32144096 A JP32144096 A JP 32144096A JP H10163416 A JPH10163416 A JP H10163416A
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- chip
- solder
- transistor
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、インバータ，サー
ボモータなどを始めとするパワーエレクトロニクス分野
で用いるパワー半導体モジュールの構成に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor module used in the field of power electronics such as an inverter and a servomotor.
【０００２】[0002]
【従来の技術】まず、従来より製品化されているパワー
半導体モジュールの組立構造例を図４(a),(b) に示す。
図示例はパッケージ内に４個のパワートランジスタ（Ｉ
ＧＢＴ）を組み込んで並列接続した４個組のＩＧＢＴモ
ジュールを例示したものであり、図において、１はヒー
トシンクとなる銅製の金属ベース板、２は金属ベース板
１の上に搭載したパワー回路組立体、３は外囲樹脂ケー
ス、４はケース３の蓋体を兼ねた端子ブロックであり、
パワー回路組立体２はアルミナ，窒化アルミニウムなど
のセラミックスを基体とする絶縁基板５（図示例では絶
縁基板５が２枚に分割されている）に形成した導体パタ
ーン（銅箔）上にパワートランジスタ（ＩＧＢＴ）６，
およびフリーホイーリングダイオード（ＦＷＤ）７を組
にして各チップ素子を半田マウントし、さらにチップ素
子と導体パターンとの間にワイヤボンディングを施して
内部配線した構成になる。また、端子ブロック４には主
回路端子（エミッタ端子：Ｅ，コレクタ端子：Ｃ）およ
び補助端子（ゲート端子：Ｇ、補助エミッタ端子：ｅ）
の外部導出端子が一体にモールド成形されている。2. Description of the Related Art First, FIGS. 4A and 4B show an example of an assembly structure of a power semiconductor module which has been commercialized conventionally.
In the illustrated example, four power transistors (I
FIG. 1 illustrates an example of a IGBT module in a set of four, which is connected in parallel by incorporating a GBT). In the figure, reference numeral 1 denotes a copper metal base plate serving as a heat sink, and 2 denotes a power circuit assembly mounted on the metal base plate 1. Reference numeral 3 denotes an outer resin case, and reference numeral 4 denotes a terminal block serving also as a lid of the case 3.
The power circuit assembly 2 includes a power transistor (copper foil) formed on a conductive pattern (copper foil) formed on an insulating substrate 5 (in the illustrated example, the insulating substrate 5 is divided into two pieces) based on a ceramic such as alumina or aluminum nitride. IGBT) 6,
In addition, each chip element is solder-mounted with a set of a free wheeling diode (FWD) 7 and further, wire bonding is performed between the chip element and the conductor pattern to form an internal wiring. The terminal block 4 has a main circuit terminal (emitter terminal: E, collector terminal: C) and an auxiliary terminal (gate terminal: G, auxiliary emitter terminal: e).
Are externally molded.
【０００３】次に、図４におけるパワー回路組立体の従
来構成を図５ないし図７に示す。なお、図５は回路組立
体の構成図、図６はフリーホイーリングダイオードの構
造図、図７は図５の等価回路図である。まず、図５にお
いて、絶縁基板５の上面にはパワートランジスタ（ＩＧ
ＢＴ）６のコレクタ，エミッタ，ゲートの各電極に対応
するコレクタ導体パターン８，エミッタ導体パターン
９，およびゲート導体パターン１０が分離形成されてお
り、これら導体パターンには図示のように各半導体素子
が半田マウントされ、さらに図４で示したエミッタ，コ
レクタ，ゲートの各外部導出端子の脚片が半田接合され
る。ここで、コレクタ導体パターン８の上にはコレクタ
電極を下向きにしてトランジスタ６のチップ，およびダ
イオード７のチップがカソード電極を下向きにしてそれ
ぞれ半田マウントされている。さらに、トランジスタ６
のチップ上面側に形成したエミッタ電極，およびダイオ
ード７のチップ上面側に形成したアノード電極とエミッ
タ導体パターン９との間、およびトランジスタ６のゲー
ト電極とゲート導体パターン１０との間がボンディング
ワイヤ１１で相互接続されており、これにより図７の等
価回路に示したパワー回路組立体が構築される。Next, FIGS. 5 to 7 show a conventional structure of the power circuit assembly shown in FIG. 5 is a structural diagram of a circuit assembly, FIG. 6 is a structural diagram of a freewheeling diode, and FIG. 7 is an equivalent circuit diagram of FIG. First, in FIG. 5, a power transistor (IG
A collector conductor pattern 8, an emitter conductor pattern 9, and a gate conductor pattern 10 corresponding to the collector, emitter, and gate electrodes of the BT) 6 are separately formed. Solder mounting is performed, and the legs of the external lead terminals of the emitter, collector, and gate shown in FIG. 4 are soldered. Here, a chip of the transistor 6 and a chip of the diode 7 are solder-mounted on the collector conductor pattern 8 with the collector electrode facing downward and the cathode electrode facing downward. Further, the transistor 6
The bonding wire 11 connects between the emitter electrode formed on the chip upper surface side of the chip, between the anode electrode formed on the chip upper surface side of the diode 7 and the emitter conductor pattern 9, and between the gate electrode of the transistor 6 and the gate conductor pattern 10. They are interconnected, thereby building the power circuit assembly shown in the equivalent circuit of FIG.
【０００４】なお、図６はダイオード７の構造を模式的
に表した図であり、カソード電極７Ｋはプレーナ構造の
接合形チップ素子の裏面側でSi基板上に形成されてお
り、Ti（コンタクト層),Ni (接合層),Au (保護層) から
なる。また、ワイヤボンド側のアノード電極７Ａは、ｐ
−ｎ接合領域からパッシベーション膜（シリコン酸化
膜：SiＯ2 ）の上面側にはみ出し形成されたAl (接合
層),Ni (バッファ層),Au (保護層) からなる島状のオー
バーレイ電極として形成されている。FIG. 6 is a diagram schematically showing the structure of a diode 7. A cathode electrode 7K is formed on a Si substrate on the back surface side of a junction type chip element having a planar structure. ), Ni (bonding layer) and Au (protective layer). Also, the anode electrode 7A on the wire bond side is p
-Formed as an island-shaped overlay electrode composed of Al (bonding layer), Ni (buffer layer), and Au (protective layer) formed on the upper surface side of the passivation film (silicon oxide film: SiO 2 ) from the n-junction region. ing.
【０００５】ここで、パワー回路組立体２を図５のよう
な構成にするのは次の理由による。すなわち、プレーナ
構造の半導体素子では、チップ素子の底面側全面に表面
電極（ＩＧＢＴはコレクタ電極，ダイオードはカソード
電極）が形成されており、絶縁基板５の導体パターンに
半田マウントするための表面処理が容易である。The reason why the power circuit assembly 2 is configured as shown in FIG. 5 is as follows. That is, in a semiconductor element having a planar structure, a surface electrode (a collector electrode for an IGBT, a cathode electrode for a diode) is formed on the entire bottom surface side of the chip element, and a surface treatment for solder mounting on a conductor pattern of the insulating substrate 5 is performed. Easy.
【０００６】[0006]
【発明が解決しようとする課題】ところで、前記したパ
ワー半導体モジュールの従来構造では次記のような問題
点がある。すなわち、図５で示すように絶縁基板５のコ
レクタ導体パターン８にはパワートランジスタ６，フリ
ーホイーリングダイオード７が２個ずつ、合計４個のパ
ワー素子が一括して集中的にマウントされている。一
方、パワー半導体モジュールでは通電，スイッチング動
作に伴い各パワー半導体素子に大きな発熱を生じる。こ
のために、従来の組立構造のままでは絶縁基板５の温度
分布がコレクタ導体パターン８に集中して金属ベース板
１へ伝熱する放熱性が低下するほか、コレクタ導体パワ
ー８の上に集中している各パワー半導体素子の発熱が互
い干渉し合い、これが原因で半導体素子内部の接合温度
が大きく上昇することから、モジュールの最大許容電流
値が低く抑えられる。However, the conventional structure of the power semiconductor module has the following problems. That is, as shown in FIG. 5, the power conductor 6 and the freewheeling diode 7 are respectively mounted on the collector conductor pattern 8 of the insulating substrate 5 and a total of four power elements are collectively mounted collectively. On the other hand, in the power semiconductor module, a large amount of heat is generated in each power semiconductor element due to energization and switching operation. For this reason, if the conventional assembly structure is used, the temperature distribution of the insulating substrate 5 concentrates on the collector conductor pattern 8 and the heat dissipation to the metal base plate 1 is reduced, and the temperature distribution concentrates on the collector conductor power 8. The heat generated by the power semiconductor elements interferes with each other, and this causes the junction temperature inside the semiconductor element to rise significantly, so that the maximum allowable current value of the module can be kept low.
【０００７】本発明は上記の点にかんがみなされたもの
であり、パワートランジスタとフリーホイーリングダイ
オードを組合せたパワー半導体モジュールを対象に、ト
ランジスタチップとダイオードチップとの間での熱的干
渉を抑制して放熱性の大幅な改善が図れるようにしたパ
ワー半導体モジュールの組立構造を提供することを目的
とする。The present invention has been made in view of the above points, and is intended for a power semiconductor module in which a power transistor and a freewheeling diode are combined to suppress thermal interference between a transistor chip and a diode chip. It is an object of the present invention to provide an assembly structure of a power semiconductor module in which heat dissipation can be significantly improved.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に、本発明によれば、外囲樹脂ケースと金属ベース板を
組合せたパッケージに、パワートランジスタ，および該
トランジスタに並列接続したフリーホイーリングダイオ
ードのチップ素子を組とする１ないし複数組のパワー半
導体素子を絶縁基板にマウントしたパワー回路組立体
と、外部導出端子を組み込んで構成したパワー半導体モ
ジュールにおいて、前記のトランジスタチップとダイオ
ードチップを、絶縁基板上に分離形成した導体パターン
上に別々に振り分けてマウントするものとし、具体的に
は次記のような態様で構成する。According to the present invention, there is provided, in accordance with the present invention, a power transistor and a freewheeling connected in parallel to the transistor in a package in which an outer resin case and a metal base plate are combined. A power circuit assembly in which one or a plurality of sets of power semiconductor elements each including a diode chip element are mounted on an insulating substrate, and a power semiconductor module configured by incorporating an external lead terminal, wherein the transistor chip and the diode chip include: It should be separately mounted on the conductor pattern separately formed on the insulating substrate and mounted. Specifically, it is configured in the following manner.
【０００９】１）絶縁基板上にパワートランジスタのコ
レクタ，エミッタ，ゲートの各電極に対応する導体パタ
ーンを分離形成した上で、トランジスタチップをコレク
タ導体パターン上に半田マウントするとともに、ダイオ
ードチップはアノード電極を絶縁基板に向けてエミッタ
導体パターン上に半田マウントし、かつそのカソード電
極とコレクタ導体パターンとの間を接続配線する。1) After separately forming conductor patterns corresponding to the collector, emitter and gate electrodes of a power transistor on an insulating substrate, a transistor chip is solder-mounted on the collector conductor pattern, and a diode chip is connected to an anode electrode. Is solder-mounted on the emitter conductor pattern toward the insulating substrate, and a connection is made between the cathode electrode and the collector conductor pattern.
【００１０】２）前項１）において、ダイオードチップ
に対しそのアノード電極引出し側の主面に、半田マウン
トが可能な半田との親和性の良い金属膜を形成した上
で、絶縁基板のエミッタ導体パターンに半田マウントす
る。 ３）さらに、前項１）において、ダイオードチップのカ
ソード電極と絶縁基板のコレクタ導体パターンとの相互
間を導体片，もしくはワイヤで接続する。2) In 1) above, a metal film having good affinity for solder that can be solder-mounted is formed on the main surface of the diode chip on the anode electrode lead-out side, and then the emitter conductor pattern of the insulating substrate is formed. Solder mount. 3) Further, in 1), the cathode electrode of the diode chip and the collector conductor pattern of the insulating substrate are connected to each other by a conductor piece or a wire.
【００１１】上記構成によれば、パワートランジスタと
フリーホイーリングダイオードは絶縁基板上に分離形成
された別々な導体パターンに振り分けてマウントされて
いるので、絶縁基板全体での温度分布が平均化される。
また、絶縁基板上に形成された各導体パターンの相互間
は互いに分離されて伝熱的には絶縁された形となるの
で、トランジスタチップとダイオードチップの間の直接
的な熱干渉もなくなり、これにより各半導体素子に対す
る放熱性が改善されて仕様面でのモジュールの最大許容
電流値の増大化が図れる。According to the above configuration, since the power transistor and the freewheeling diode are separately mounted on the conductor patterns separately formed on the insulating substrate, the temperature distribution over the entire insulating substrate is averaged. .
In addition, since the conductor patterns formed on the insulating substrate are separated from each other and insulated thermally, there is no direct thermal interference between the transistor chip and the diode chip. Thereby, the heat radiation to each semiconductor element is improved, and the maximum allowable current value of the module in terms of specifications can be increased.
【００１２】また、フリーホイーリングダイオードのカ
ソード電極と絶縁基板のコレクタ導体パターンとの間の
接続を、ボンディングワイヤに代えて通電能力の大きな
導体片を用いて行うことにより、複数本のワイヤをボン
ディングする接続方式と比べて内部配線の半田付け工程
が簡略化されるほか、接続部の寸法も小さくなってモジ
ュールを小型化できる。In addition, the connection between the cathode electrode of the freewheeling diode and the collector conductor pattern of the insulating substrate is performed by using a conductor piece having a large current-carrying capacity instead of the bonding wire, thereby bonding a plurality of wires. In addition to simplifying the process of soldering the internal wiring as compared with the connection method, the size of the connection portion is reduced, and the module can be downsized.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施例を図面に基
づいて説明する。なお、各実施例の図中で図５，図６に
対応する同一部材には同じ符号が付してある。 〔実施例１〕図１は図５と同じく、２個のパワートラン
ジスタ（ＩＧＢＴ）６と２個のフリーホイーリングダイ
オード（プレーナ構造のダイオード）７を組合せて金属
ベース板１に搭載した絶縁基板５に半田マウントしたパ
ワー半導体モジュールのパワー回路部を示す実施例の組
立構造図である。この実施例においては、パワートラン
ジスタ６のチップは、図５の構成と同様にコレクタ電極
を下向きにして絶縁基板５のコレクタ導体パターン８の
上に半田マウントし、さらにエミッタ電極とエミッタ導
体パターン９との間，およびゲート電極とゲート導体パ
ターン１０との間がそれぞれワイヤ１１でボンディング
されている。これに対して、フリーホイーリングダイオ
ード７のチップは、アノード電極を下向きにして絶縁基
板上に前記のコレクタ導体パターン８と分離形成された
エミッタ導体パターン９の上に半田マウントされ、さら
にダイオード７のカソード電極とコレクタ導体パターン
８との間に銅板，あるいはアルミニウム板の表面にニッ
ケルなどのメッキを施した接続導体片１２を半田付けし
て相互接続している。Embodiments of the present invention will be described below with reference to the drawings. In the drawings of each embodiment, the same members corresponding to FIGS. 5 and 6 are denoted by the same reference numerals. [Embodiment 1] FIG. 1 shows an insulating substrate 5 mounted on a metal base plate 1 by combining two power transistors (IGBTs) 6 and two freewheeling diodes (diodes having a planar structure) 7 as in FIG. FIG. 3 is an assembly structure diagram of an embodiment showing a power circuit portion of a power semiconductor module solder-mounted on the embodiment. In this embodiment, the chip of the power transistor 6 is solder-mounted on the collector conductor pattern 8 of the insulating substrate 5 with the collector electrode facing downward as in the configuration of FIG. , And between the gate electrode and the gate conductor pattern 10 are respectively bonded by wires 11. On the other hand, the chip of the freewheeling diode 7 is solder-mounted on the emitter conductor pattern 9 formed separately from the collector conductor pattern 8 on an insulating substrate with the anode electrode facing downward. Between the cathode electrode and the collector conductor pattern 8, a connection conductor piece 12 in which a surface of a copper plate or an aluminum plate is plated with nickel or the like is soldered and interconnected.
【００１４】ここで、フリーホイーリングダイオード７
はに対しては、前記の半田マウントに備えてあらかじめ
アノード電極７Ａを含めてダイオードチップのパッシベ
ーション膜（シリコン酸化膜：SiＯ2 ）の表面側に半田
マウントを可能にする処理を施すものとし、この処理は
チップ素子単位で行うか，あるいはサイズの小さなチッ
プ素子単位で処理することが困難な場合には、ダイオー
ドチップをダイシングする以前のウエーハの状態で施す
ことができる。そして、前記の処理としては、例えばパ
ッシベーション膜の周縁部を残して（所要の絶縁耐圧を
確保するため）その内側領域のシリコン酸化膜の上にニ
ッケル等の半田との親和性の高い金属膜を形成し、必要
に応じてアノード電極７Ａを包含して表面が平坦面を呈
するように予備半田１３を施す。なお、アノード電極７
Ａがチップ上の複数箇所に分散して島状に電極付けして
あるダイオードでは、各アノード電極７Ａの間を連ねて
チップ表面に予備半田１３を施すものとする。また、予
備半田１３の代わりに、各アノード電極の間にまたがっ
て伝熱性，半田濡れ性の良い平坦な電極板を接合するこ
とも可能である。Here, the freewheeling diode 7
In order to prepare for the solder mount, the surface of the passivation film (silicon oxide film: SiO 2 ) of the diode chip including the anode electrode 7A is subjected to a process for enabling solder mount in advance. The processing can be performed on a chip element basis, or when it is difficult to perform the processing on a chip element having a small size, the processing can be performed on the wafer before dicing the diode chip. As the above-mentioned process, for example, a metal film having a high affinity for solder such as nickel is formed on the silicon oxide film in the inner region except for the peripheral portion of the passivation film (to secure a required withstand voltage). Then, if necessary, the preliminary solder 13 is applied so as to include the anode electrode 7A and have a flat surface. The anode electrode 7
In a diode in which A is dispersed at a plurality of locations on the chip and electrode-attached in an island shape, preliminary solder 13 is applied to the chip surface by connecting between the anode electrodes 7A. In place of the preliminary solder 13, a flat electrode plate having good heat conductivity and good solder wettability can be joined between the anode electrodes.
【００１５】そして、ダイオードチップを絶縁基板５の
エミッタ導体パターン９の上に半田マウントする際に
は、図示のようにアノード電極７Ａを絶縁基板５側に向
けてエミッタ導体パターン９の上にマウントして半田接
合する。この半田接合部を符号１４で表す。その後に、
ダイオード７のカソード電極７Ｋと絶縁基板５のコレク
タ導体パターン８との間にまたがって接続導体片１２を
架け渡し、その両端とカソード電極７Ｋ，導体パターン
８との間を半田付けする。なお、ダイオード７のカソー
ド側はもともとチップ表面の全面域にカソード電極７Ｋ
が形成されているので、ボンディングワイヤを使わずに
接続導体片１２を直接半田付けすることが可能である。
これにより、図７に示した等価回路のように、フリーホ
イーリングダイオード７がパワートランジスタ６のエミ
ッタとコレクタの間に並列接続される。When the diode chip is solder-mounted on the emitter conductor pattern 9 of the insulating substrate 5, the anode electrode 7A is mounted on the emitter conductor pattern 9 with the anode electrode 7A facing the insulating substrate 5 as shown in the figure. Soldering. This solder joint is denoted by reference numeral 14. Then,
A connection conductor piece 12 is bridged between the cathode electrode 7K of the diode 7 and the collector conductor pattern 8 of the insulating substrate 5, and both ends thereof and the cathode electrode 7K and the conductor pattern 8 are soldered. Note that the cathode side of the diode 7 originally covers the entire surface area of the chip surface with the cathode electrode 7K.
Is formed, it is possible to directly solder the connection conductor piece 12 without using a bonding wire.
Thus, as in the equivalent circuit shown in FIG. 7, the freewheeling diode 7 is connected in parallel between the emitter and the collector of the power transistor 6.
【００１６】〔実施例２〕図３は先記実施例１の応用実
施例を示すものであり、図１と異なる点は、絶縁基板５
のエミッタ導体パターン９に半田マウントされたフリー
ホイーリングダイオード７のカソード電極７Ｋとコレク
タ導体パターン８との相互間が複数本のボンディングワ
イヤ１１で接続されている。[Embodiment 2] FIG. 3 shows an applied embodiment of Embodiment 1 described above. The difference from FIG.
The cathode electrode 7K of the freewheeling diode 7 solder-mounted on the emitter conductor pattern 9 and the collector conductor pattern 8 are connected to each other by a plurality of bonding wires 11.
【００１７】なお、図示実施例ではパワートランジスタ
６としてＩＧＢＴを使用しているが、ほかに電界効果ト
ランジスタ（接合形ＦＥＴ，ＭＯＳＦＥＴ）を採用した
パワー半導体モジュールにも同様に実施適用できること
は勿論であり、この場合にはＩＧＢＴのコレクタ，エミ
ッタをＦＥＴのドレイン，ソースに置き換えて絶縁基板
上に半田マウントすればよい。Although the IGBT is used as the power transistor 6 in the illustrated embodiment, it is needless to say that the present invention can be similarly applied to a power semiconductor module employing a field effect transistor (junction FET, MOSFET). In this case, the collector and the emitter of the IGBT may be replaced with the drain and the source of the FET, and may be mounted on the insulating substrate by soldering.
【００１８】[0018]
【発明の効果】以上述べたように、本発明の構成によれ
ば、同じ絶縁基板上に配置したパワートランジスタとフ
リーホイーリングダイオードとが別々な導体パターン上
に振り分けてマウントされているので、通電時における
絶縁基板の発熱温度分布が平均化されて金属ベース板
（ヒートシンク）への集中的な伝熱が回避され、さらに
パワートランジスタとフリーホイーリングダイオードの
間の熱的干渉も少なく、これにより半導体素子内部の接
合温度上昇が低減され、従来構成と比べてパワー半導体
モジュールの仕様面での最大許容電流の増大化が図れ
る。As described above, according to the structure of the present invention, since the power transistor and the freewheeling diode arranged on the same insulating substrate are separately mounted on different conductor patterns, the power The heat generation temperature distribution of the insulating substrate at the time is averaged, intensive heat transfer to the metal base plate (heat sink) is avoided, and thermal interference between the power transistor and the freewheeling diode is also reduced, thereby making the semiconductor The rise in the junction temperature inside the element is reduced, and the maximum allowable current in the specification of the power semiconductor module can be increased as compared with the conventional configuration.
【００１９】また、請求項３のように、ダイオードチッ
プに対してそのアノード電極引出し側の主面の広い面域
にあらかじめ半田マウント可能な予備半田などの処理を
施した上で絶縁基板の導体パターンに半田マウントする
ことで、ダイオードチップと絶縁基板との間に高い伝熱
性を確保できる。さらに、請求項４でダイオードチップ
と絶縁基板のコレクタ導体パターンとの間の接続に導体
片を採用することにより、ワイヤボンディング法と比べ
て半田付けが簡単で、かつ接続部の寸法も小さくなって
モジュールが小型化できる。According to a third aspect of the present invention, the diode chip is preliminarily subjected to processing such as preliminary soldering capable of being solder-mounted on a wide area of the main surface on the anode electrode lead-out side, and then the conductor pattern of the insulating substrate is formed. By solder mounting, high heat conductivity can be secured between the diode chip and the insulating substrate. Furthermore, by employing a conductor piece for connection between the diode chip and the collector conductor pattern of the insulating substrate in claim 4, soldering is easier and the size of the connection portion is smaller than in the wire bonding method. Module can be downsized.
【図１】本発明の実施例１に対応するパワー半導体モジ
ュールのパワー回路組立体の構成斜視図FIG. 1 is a configuration perspective view of a power circuit assembly of a power semiconductor module according to a first embodiment of the present invention.
【図２】図１におけるフリーホイーリングダイオードの
接続部の詳細な構造図FIG. 2 is a detailed structural diagram of a connection portion of a freewheeling diode in FIG. 1;
【図３】本発明の実施例２に対応するパワー半導体モジ
ュールのパワー回路組立体の構成斜視図FIG. 3 is a configuration perspective view of a power circuit assembly of a power semiconductor module according to a second embodiment of the present invention.
【図４】本発明の実施対象例として例示した４個組パワ
ー半導体モジュールの従来構成図であり、(a) は分解斜
視図、(b) の組立状態の外観斜視図4A and 4B are conventional configuration diagrams of a four-package power semiconductor module exemplified as an embodiment of the present invention, wherein FIG. 4A is an exploded perspective view, and FIG.
【図５】図４におけるパワー回路組立体の構成斜視図FIG. 5 is a configuration perspective view of a power circuit assembly in FIG. 4;
【図６】図５におけるフリーホイーリングダイオードの
構造図6 is a structural diagram of the freewheeling diode in FIG.
【図７】図５の等価回路図FIG. 7 is an equivalent circuit diagram of FIG.
１ 金属ベース板 ２ パワー回路組立体 ３ 外囲樹脂ケース ４ 端子ブロック ５ 絶縁基板 ６ パワートランジスタ（ＩＧＢＴ） ７ フリーホイーリングダイオード ７Ａ アノード電極 ７Ｋ カソード電極 ８ コレクタ導体パターン ９ エミッタ導体パターン １０ ゲート導体パターン １１ ボンディングワイヤ １２ 接続導体片 １３ 予備半田 １４ 半田接合部 DESCRIPTION OF SYMBOLS 1 Metal base plate 2 Power circuit assembly 3 Outer resin case 4 Terminal block 5 Insulating substrate 6 Power transistor (IGBT) 7 Freewheeling diode 7A Anode electrode 7K Cathode electrode 8 Collector conductor pattern 9 Emitter conductor pattern 10 Gate conductor pattern 11 Bonding wire 12 Connection conductor piece 13 Pre-soldering 14 Solder joint
Claims (4)
パッケージに、パワートランジスタ，および該トランジ
スタに並列接続したフリーホイーリングダイオードのチ
ップ素子を組とする１ないし複数組のパワー半導体素子
を絶縁基板にマウントしたパワー回路組立体，外部導出
端子を組み込んで構成したパワー半導体モジュールにお
いて、前記のトランジスタチップとダイオードチップ
を、絶縁基板上に分離形成した導体パターン上に別々に
振り分けてマウントしたことを特徴とするパワー半導体
モジュール。An insulated package comprising a combination of an outer resin case and a metal base plate is provided with a power transistor and one or more sets of power semiconductor elements comprising a chip element of a freewheeling diode connected in parallel to the transistor. In a power semiconductor module including a power circuit assembly mounted on a substrate and an external lead terminal, the transistor chip and the diode chip are separately distributed and mounted on a conductor pattern separated and formed on an insulating substrate. Characteristic power semiconductor module.
おいて、絶縁基板上にパワートランジスタのコレクタ，
エミッタ，ゲートの各電極に対応する導体パターンを分
離形成した上で、トランジスタチップをコレクタ導体パ
ターン上に半田マウントするとともに、ダイオードチッ
プはアノード電極を絶縁基板に向けてエミッタ導体パタ
ーン上に半田マウントし、かつそのカソード電極とコレ
クタ導体パターンとの間を接続配線したことを特徴とす
るパワー半導体モジュール。2. The power semiconductor module according to claim 1, wherein a collector of the power transistor is provided on the insulating substrate.
After separately forming conductor patterns corresponding to the emitter and gate electrodes, the transistor chip is solder-mounted on the collector conductor pattern, and the diode chip is solder-mounted on the emitter conductor pattern with the anode electrode facing the insulating substrate. And a connection wiring between the cathode electrode and the collector conductor pattern.
おいて、ダイオードチップに対しそのアノード電極引出
し側の主面に、半田マウントが可能な半田との親和性の
良い金属膜を形成した上で、絶縁基板のエミッタ導体パ
ターンに半田マウントしたことを特徴とするパワー半導
体モジュール。3. A power semiconductor module according to claim 2, wherein a metal film having good affinity with solder capable of being solder-mounted is formed on a main surface of the diode chip on a side from which the anode electrode is drawn out, and then the insulation is performed. A power semiconductor module characterized by being solder-mounted on an emitter conductor pattern of a substrate.
おいて、ダイオードチップのカソード電極と絶縁基板の
コレクタ導体パターンとの相互間を導体片，もしくはワ
イヤで接続したことを特徴とするパワー半導体モジュー
ル。4. The power semiconductor module according to claim 2, wherein the cathode electrode of the diode chip and the collector conductor pattern of the insulating substrate are connected to each other by a conductor piece or a wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32144096A JP3644161B2 (en) | 1996-12-02 | 1996-12-02 | Power semiconductor module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32144096A JP3644161B2 (en) | 1996-12-02 | 1996-12-02 | Power semiconductor module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10163416A true JPH10163416A (en) | 1998-06-19 |
| JP3644161B2 JP3644161B2 (en) | 2005-04-27 |
Family
ID=18132590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32144096A Expired - Fee Related JP3644161B2 (en) | 1996-12-02 | 1996-12-02 | Power semiconductor module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3644161B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100347849C (en) * | 2003-09-12 | 2007-11-07 | 株式会社东芝 | Inverter device and method of manufacturing the device thereof, and electric automobile incorporating the inverter device thereof |
| EP1939937A2 (en) | 2006-12-28 | 2008-07-02 | Hitachi, Ltd. | Bidirectional switch module |
| CN112119492A (en) * | 2018-05-17 | 2020-12-22 | 京瓷株式会社 | Power semiconductor module |
| CN115911011A (en) * | 2022-11-10 | 2023-04-04 | 北京智慧能源研究院 | Power semiconductor device series connection voltage-sharing structure and power semiconductor device |
-
1996
- 1996-12-02 JP JP32144096A patent/JP3644161B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100347849C (en) * | 2003-09-12 | 2007-11-07 | 株式会社东芝 | Inverter device and method of manufacturing the device thereof, and electric automobile incorporating the inverter device thereof |
| EP1939937A2 (en) | 2006-12-28 | 2008-07-02 | Hitachi, Ltd. | Bidirectional switch module |
| US7750463B2 (en) | 2006-12-28 | 2010-07-06 | Renesas Technology Corp. | Bidirectional switch module |
| US8039954B2 (en) | 2006-12-28 | 2011-10-18 | Renesas Electronics Corporation | Bidirectional switch module |
| CN112119492A (en) * | 2018-05-17 | 2020-12-22 | 京瓷株式会社 | Power semiconductor module |
| CN115911011A (en) * | 2022-11-10 | 2023-04-04 | 北京智慧能源研究院 | Power semiconductor device series connection voltage-sharing structure and power semiconductor device |
| CN115911011B (en) * | 2022-11-10 | 2023-09-22 | 北京智慧能源研究院 | Series voltage equalizing structure of power semiconductor device and power semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3644161B2 (en) | 2005-04-27 |
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