JPH1012809A - Multichip module - Google Patents
Multichip moduleInfo
- Publication number
- JPH1012809A JPH1012809A JP8164247A JP16424796A JPH1012809A JP H1012809 A JPH1012809 A JP H1012809A JP 8164247 A JP8164247 A JP 8164247A JP 16424796 A JP16424796 A JP 16424796A JP H1012809 A JPH1012809 A JP H1012809A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- wiring board
- wiring
- electronic components
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
Description
【発明の属する技術分野】本発明は、複数の電子部品を
同一配線基板上に実装したマルチチップモジュールに関
し、特に、片面に格子上に配列した複数の外部端子を有
する配線基板を使用したマルチチップモジュールに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module having a plurality of electronic components mounted on the same wiring board, and more particularly to a multi-chip module using a wiring board having a plurality of external terminals arranged on one side in a lattice. About the module.
【０００１】[0001]
【従来の技術】従来、この種マルチチップモジュール
は、図４（ａ）、（ｂ）に示すように、配線基板１の表
面に電子部品２１、２２が実装されたものからなる。配
線基板１の裏面には、格子上に配列した複数の外部入出
力信号用導電パッド５が形成され、そのパッドの上には
球状の外部入出力信号端子３が半田等で形成されてい
る。外部入出力信号端子３と電子部品２１、２２の端子
とは、配線基板１の表面または内部で接続されている。
配線基板１には、外部入出力信号端子３と電子部品２
１、２２の端子とを接続する配線路の他に、電子部品２
１と２２の端子間を接続する配線路が形成される。2. Description of the Related Art Conventionally, as shown in FIGS. 4A and 4B, a multi-chip module of this type comprises a circuit board 1 on which electronic components 21 and 22 are mounted. A plurality of external input / output signal conductive pads 5 arranged on a lattice are formed on the back surface of the wiring board 1, and spherical external input / output signal terminals 3 are formed on the pads by soldering or the like. The external input / output signal terminal 3 and the terminals of the electronic components 21 and 22 are connected on the surface or inside the wiring board 1.
External input / output signal terminals 3 and electronic components 2
In addition to the wiring paths connecting the terminals 1 and 22, the electronic component 2
A wiring path connecting the terminals 1 and 22 is formed.
【０００２】[0002]
【発明が解決しようとする課題】第１の問題点は、マル
チチップモジュールを構成する各電子部品の全ての端子
の接続状態及び各端子からの電子部品の動作を検査する
ことができない点である。The first problem is that it is impossible to inspect the connection state of all terminals of each electronic component constituting the multi-chip module and the operation of the electronic component from each terminal. .
【０００３】その理由は、各電子部品間を接続する配線
路でかつ配線基板の外部入出力信号端子に接続する必要
のない配線路に対しては、外部接続端子がないからであ
る。The reason is that there is no external connection terminal for a wiring path connecting each electronic component and for a wiring path which does not need to be connected to an external input / output signal terminal of the wiring board.
【０００４】すなわち、従来は、外部入出力信号端子に
接続する電子部品の端子からしか接続状態を検査でき
ず、各電子部品間だけを接続する配線路の接続状態およ
びその配線路を通しての動作を検査することができない
という問題があった。That is, conventionally, the connection state can be checked only from the terminals of the electronic components connected to the external input / output signal terminals, and the connection state of the wiring path connecting only the electronic components and the operation through the wiring path can be checked. There was a problem that it could not be inspected.
【０００５】本発明の目的は、マルチチップモジュール
を構成する各電子部品の全ての端子の接続状態及び動作
を検査可能とするマルチチップモジュールを提供するこ
とにある。An object of the present invention is to provide a multi-chip module capable of inspecting connection states and operations of all terminals of each electronic component constituting the multi-chip module.
【０００６】本発明の更なる目的は、共通の検査フィク
スチャを使用できるマルチチップモジュールを提供する
ことにある。It is a further object of the present invention to provide a multi-chip module that can use a common test fixture.
【０００７】[0007]
【課題を解決するための手段】本発明によるマルチチッ
プモジュールは、複数の電子部品（図１（ａ）の２１、
２２）と、これら電子部品が実装され、外部信号導電端
子（図１（ａ）の５）と電子部品（２１、２２）の端子
とを接続する第１の配線路（図１（ａ）の１０）の他に
電子部品（２１と２２）の端子間を接続し外部との接続
の必要のない第２の配線路（図１（ａ）の１１）が形成
された配線基板（図１（ａ）の１）とを有するモジュー
ルであって、配線基板の表面に検査用導電端子（図１
（ａ）の４）を有し第２の配線路がその検査用導電端子
に接続された構成を有する。The multichip module according to the present invention comprises a plurality of electronic components (21 in FIG. 1 (a)).
22), and a first wiring path (see FIG. 1A) connecting these electronic components and connecting external signal conductive terminals (5 in FIG. 1A) and terminals of the electronic components (21, 22). 10) In addition to the wiring board (FIG. 1 (a)), a second wiring path (11 in FIG. 1 (a)) is formed which connects between the terminals of the electronic components (21 and 22) and does not need to be connected to the outside. a) 1), wherein a conductive terminal for inspection (FIG. 1) is provided on the surface of the wiring board.
(A) Item 4), wherein the second wiring path is connected to the inspection conductive terminal.
【０００８】この構成によって、マルチチップモジュー
ルを構成する各電子部品の全ての端子の接続状態及び動
作を検査可能とするマルチチップモジュールが得られ
る。With this configuration, a multi-chip module capable of inspecting connection states and operations of all terminals of each electronic component constituting the multi-chip module is obtained.
【０００９】本発明によれば、検査用導電端子は、配線
基板において外部信号導電端子と同一平面上に形成さ
れ、外部信号導電端子とともに同一格子上に配列された
ものでも良い。この場合、検査用導電端子が整然と配列
されるので、マルチチップモジュールの内部回路が変わ
った場合でも共通の検査フィクスチャを使用できる利点
が生じる。According to the present invention, the inspection conductive terminals may be formed on the same plane as the external signal conductive terminals on the wiring board, and may be arranged on the same grid with the external signal conductive terminals. In this case, since the test conductive terminals are arranged in an orderly manner, there is an advantage that a common test fixture can be used even when the internal circuit of the multi-chip module is changed.
【００１０】外部信号導電端子は外部入出力信号用導電
パッド、検査用導電端子は、検査用導電パッドでも良
い。外部信号導電端子は、導線性ボールが形成された外
部入出力信号用導電パッドでも良い。The external signal conductive terminal may be an external input / output signal conductive pad, and the test conductive terminal may be a test conductive pad. The external signal conductive terminal may be an external input / output signal conductive pad on which a conductive ball is formed.
【００１１】[0011]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して詳細に説明する。Next, embodiments of the present invention will be described in detail with reference to the drawings.
【００１２】図１（ａ）、（ｂ）は本発明のマルチチッ
プモジュールの第１の実施の形態を示し、（ａ）は断面
図、（ｂ）は配線基板の各導電パッド側からみた平面図
である。図において、マルチチップモジュールの配線基
板１の一方の面（表面側）には、電子部品２１と２２が
実装され、もう一方の面（裏面側）には外部入出力信号
用導電パッド５と検査用導電パッド４が形成されてい
る。1A and 1B show a first embodiment of a multi-chip module according to the present invention, wherein FIG. 1A is a cross-sectional view, and FIG. 1B is a plane view from the side of each conductive pad of a wiring board. FIG. In the figure, electronic components 21 and 22 are mounted on one surface (front surface side) of the wiring board 1 of the multi-chip module, and the external input / output signal conductive pads 5 are inspected on the other surface (back surface side). Conductive pad 4 is formed.
【００１３】電子部品２１、２２は、ベアチップ、テー
プキャリアパッケージ、モールドパッケージなどの半導
体集積回路であるが、その他に抵抗、コンデンサなどの
部品も含む。The electronic components 21 and 22 are semiconductor integrated circuits such as a bare chip, a tape carrier package, and a mold package, but also include components such as resistors and capacitors.
【００１４】配線基板１は、絶縁層と配線層からなる多
層配線基板で、外部入出力信号用導電パッド５と電子部
品２１、２２の端子とを接続する第１の配線路１０の他
に、電子部品２１と２２の端子間を接続する第２の配線
路１１が形成される。第１の配線路１０は、配線基板１
の表面あるいは内部に形成され、第２の配線路１１も配
線基板１の表面あるいは内部に形成される。第２の配線
路１１は、検査のために配線基板の内部で検査用導電パ
ッド４に接続される。The wiring board 1 is a multilayer wiring board comprising an insulating layer and a wiring layer. In addition to the first wiring path 10 for connecting the external input / output signal conductive pads 5 and the terminals of the electronic components 21 and 22, The second wiring path 11 that connects between the terminals of the electronic components 21 and 22 is formed. The first wiring path 10 is a wiring board 1
The second wiring path 11 is also formed on the surface or inside of the wiring board 1. The second wiring path 11 is connected to the inspection conductive pad 4 inside the wiring board for inspection.
【００１５】外部入出力信号端子３は、外部入出力信号
用導電パッド５の表面に形成された導電性ボールであ
る。その材料としては、半田ボールや、半田メッキを施
した動などの金属ボールが望ましい。The external input / output signal terminal 3 is a conductive ball formed on the surface of the external input / output signal conductive pad 5. The material is preferably a solder ball or a metal ball such as a solder-plated moving ball.
【００１６】検査用導電パッド４と外部入出力信号用導
電パッド５は、同一格子上に配置される。すなわち、検
査用導電パッド４は、配線基板１において外部入出力信
号用導電パッド５と同一平面上に形成され、外部入出力
信号用導電パッド５とともに同一格子上に配列されてい
る。図１（ｂ）では、検査用導電パッド４の外周に外部
入出力信号用導電パッド５が配置されているが、配置順
序はこれに限定されるものではない。検査用導電パッド
４と外部入出力信号用導電パッド５とを１パッドづつ交
互に配列しても良い。The test conductive pad 4 and the external input / output signal conductive pad 5 are arranged on the same grid. That is, the inspection conductive pads 4 are formed on the same plane as the external input / output signal conductive pads 5 on the wiring board 1 and are arranged on the same grid with the external input / output signal conductive pads 5. In FIG. 1B, the external input / output signal conductive pads 5 are arranged on the outer periphery of the inspection conductive pad 4, but the arrangement order is not limited to this. The test conductive pads 4 and the external input / output signal conductive pads 5 may be alternately arranged one by one.
【００１７】図２は図１（ａ）、（ｂ）のマルチチップ
モジュールの配線構成を示す回路図である。図におい
て、端子６ａ、６ｂ、６ｃは、電子部品２１に接続する
外部入出力信号用導電パッド５に対応し、端子６ｄ、６
ｅ、６ｆは、電子部品２２に接続する外部入出力信号用
導電パッド５に対応する。また、端子７ａ、７ｂ、７ｃ
は、それぞれ電子部品２１と２２の端子とを接続する第
２の配線路１１に接続する検査用導電パッド４に対応す
る。FIG. 2 is a circuit diagram showing a wiring configuration of the multi-chip module shown in FIGS. 1 (a) and 1 (b). In the figure, terminals 6a, 6b and 6c correspond to external input / output signal conductive pads 5 connected to the electronic component 21, and terminals 6d, 6b
e and 6f correspond to the external input / output signal conductive pads 5 connected to the electronic component 22. Also, terminals 7a, 7b, 7c
Corresponds to the conductive pad for inspection 4 connected to the second wiring path 11 connecting the terminals of the electronic components 21 and 22 respectively.
【００１８】検査用導電パッド４と外部入出力信号用導
電パッド５に相対する位置に検査プローブを配置した検
査フィクスチャを使用することにより、電子部品２１と
２２の全ての端子を検査することが可能となり、電子部
品の全ての端子の接続状態及び電子部品２１と２２を接
続したときの各端子からの動作状態を検査することがで
きる。特に、検査用導電パッド４からは、配線基板１に
おける電子部品間の配線状態を検査することができる。By using a test fixture in which a test probe is arranged at a position opposite to the test conductive pad 4 and the external input / output signal conductive pad 5, it is possible to test all terminals of the electronic components 21 and 22. This makes it possible to inspect the connection state of all terminals of the electronic component and the operation state from each terminal when the electronic components 21 and 22 are connected. In particular, the state of wiring between electronic components on the wiring board 1 can be inspected from the conductive pad 4 for inspection.
【００１９】具体的に検査方法を説明すると、端子６ａ
から６ｃと端子７ａから７ｃに検査フィクスチャの検査
プローブを当て、それら端子を使用して電子部品２１の
全ての端子の接続状態、動作状態を検査する。次に、端
子６ｄから６ｆと端子７ａから７ｃに検査フィクスチャ
の検査プローブを当て、それら端子を使用して電子部品
２２の全ての端子の接続状態、動作状態を検査する。こ
れにより、第１及び第２の配線路１０、１１の接続状態
を検査することができる。The inspection method will be described specifically.
To 6c and the terminals 7a to 7c are applied with the inspection probes of the inspection fixture, and the connection state and the operation state of all the terminals of the electronic component 21 are inspected using those terminals. Next, an inspection probe of an inspection fixture is applied to the terminals 6d to 6f and the terminals 7a to 7c, and the connection state and the operation state of all the terminals of the electronic component 22 are inspected using those terminals. Thereby, the connection state of the first and second wiring paths 10 and 11 can be inspected.
【００２０】図３（ａ）、（ｂ）は本発明のマルチチッ
プモジュールの第２の実施の形態を示し、（ａ）は断面
図、（ｂ）は配線基板の各導電パッド側からみた平面図
である。図において、第１の実施の形態との違いは、電
子部品２１、２２が、反対面側に実装されていること
と、外部入出力信号用導電パッド５及び検査用導電パッ
ド４の配列にある。そのほかは、図１（ａ）、（ｂ）と
同様である。この実施の形態の場合、電子部品２１、２
２が、外部入出力信号用導電パッド５及び検査用導電パ
ッド４と同一面上に実装されているので、導電パッドの
数が制限される。しかし、配線基板１の表面から電子部
品が見えないので、電子部品に埃等がつきにくい。FIGS. 3A and 3B show a second embodiment of the multichip module according to the present invention, wherein FIG. 3A is a sectional view, and FIG. 3B is a plan view of the wiring board viewed from each conductive pad side. FIG. In the figure, the difference from the first embodiment is that the electronic components 21 and 22 are mounted on the opposite surface side and that the arrangement of the external input / output signal conductive pad 5 and the test conductive pad 4 is provided. . Others are the same as those in FIGS. 1A and 1B. In the case of this embodiment, the electronic components 21 and 2
Since 2 is mounted on the same surface as the external input / output signal conductive pad 5 and the test conductive pad 4, the number of conductive pads is limited. However, since the electronic component cannot be seen from the surface of the wiring board 1, dust and the like are hardly attached to the electronic component.
【００２１】電子部品の実装は、以上の実施の形態に限
らず、例えば、配線基板１の中に埋め込まれても良い。The mounting of the electronic components is not limited to the above embodiment, and may be embedded in the wiring board 1, for example.
【００２２】[0022]
【実施例】次に本発明の実施例について図１（ａ）、
（ｂ）を参照して詳細に説明する。マルチチップモジュ
ールの配線基板１には、ガラスエポキシ基材に導配線パ
ターンを形成した基板をベースに、感光性絶縁樹脂上に
導配線パターンを形成したビルドアップ工法を用いたプ
リント配線基板を使用する。電子部品２１、２２は、半
導体集積回路ベアチップをフリップチップ実装で配線基
板１へ実装する。外部入出力信号端子３は、一般的な表
面実装部品と同様に、外部入出力信号用導電パッド５に
Ｓｎ−Ｐｂ共晶半田ペーストを印刷供給し、その上にＳ
ｎ−Ｐｂ共晶半田ボールを搭載し、リフロー方式により
溶融接合して形成する。外部入出力信号用導電パッド５
は、１格子エレメントあたり１．２７ｍｍの格子の外側
２列の枠上に配置される。検査用導電パッド４は、外部
入出力信号用導電パッド５の内側に２列の枠上に配置さ
れる。FIG. 1 (a) shows an embodiment of the present invention.
This will be described in detail with reference to FIG. As the wiring board 1 of the multi-chip module, a printed wiring board using a build-up method in which a conductive wiring pattern is formed on a photosensitive insulating resin based on a substrate in which a conductive wiring pattern is formed on a glass epoxy base material is used. . The electronic components 21 and 22 mount the semiconductor integrated circuit bare chip on the wiring board 1 by flip chip mounting. The external input / output signal terminal 3 prints and supplies the Sn-Pb eutectic solder paste to the external input / output signal conductive pad 5 as in the case of a general surface-mounted component.
It is formed by mounting an n-Pb eutectic solder ball and melting and joining by a reflow method. Conductive pad 5 for external input / output signal
Are arranged on the two outer rows of a grid of 1.27 mm per grid element. The inspection conductive pads 4 are arranged on two rows of frames inside the external input / output signal conductive pads 5.
【００２３】[0023]
【発明の効果】第１の効果は、マルチチップモジュール
を構成する各電子部品の全ての端子の接続状態および各
電子部品の動作を検査することが可能となることであ
る。The first effect is that it is possible to inspect the connection state of all terminals of each electronic component constituting the multi-chip module and the operation of each electronic component.
【００２４】その理由は、各電子部品間を接続する配線
路で、かつマルチチップモジュールの外部との接続が必
要のない第２の配線路に検査用導電端子を設けたからで
ある。The reason is that the inspection conductive terminal is provided in the wiring path connecting each electronic component and in the second wiring path which does not need to be connected to the outside of the multichip module.
【００２５】第２の効果は、検査フィクスチャの共通化
を図れることである。The second effect is that the inspection fixture can be shared.
【００２６】その理由は、外部信号導電端子と検査用導
電端子を同一格子上に配置したからである。The reason is that the external signal conductive terminals and the test conductive terminals are arranged on the same grid.
【図１】本発明のマルチチップモジュールの第１の実施
の形態を示し、（ａ）は断面図、（ｂ）は導電パッド側
からみた平面図である。FIGS. 1A and 1B show a first embodiment of a multi-chip module according to the present invention, wherein FIG. 1A is a sectional view and FIG. 1B is a plan view as seen from a conductive pad side.
【図２】図１（ａ）、（ｂ）のマルチチップモジュール
の回路構成を示す回路図である。FIG. 2 is a circuit diagram showing a circuit configuration of the multi-chip module shown in FIGS. 1 (a) and 1 (b).
【図３】本発明のマルチチップモジュールの第２の実施
の形態を示し、（ａ）は断面図、（ｂ）は導電パッド側
からみた平面図である。3A and 3B show a second embodiment of the multi-chip module of the present invention, wherein FIG. 3A is a cross-sectional view and FIG. 3B is a plan view seen from a conductive pad side.
【図４】従来のマルチチップモジュールを示し、（ａ）
は断面図、（ｂ）は導電パッド側からみた平面図であ
る。FIG. 4 shows a conventional multichip module, and (a)
Is a cross-sectional view, and (b) is a plan view as seen from the conductive pad side.
【符号の説明】 １ 配線基板 ３ 外部入出力信号端子 ４ 検査用導電パッド ５ 外部入出力信号用導電パッド １０ 第１の配線路 １１ 第２の配線路 ２１ 電子部品 ２２ 電子部品[Description of Signs] 1 Wiring board 3 External input / output signal terminal 4 Inspection conductive pad 5 External input / output signal conductive pad 10 First wiring path 11 Second wiring path 21 Electronic component 22 Electronic component
Claims (4)
装され、表面の外部信号導電端子と前記電子部品の端子
とを接続する第１の配線路の他に前記電子部品の端子間
を接続し外部との接続の必要のない第２の配線路が形成
された配線基板とを有するマルチチップモジュールにお
いて、前記配線基板の表面に検査用導電端子を有し、前
記第２の配線路がその検査用導電端子に接続されたこと
を特徴とするマルチチップモジュール。1. A plurality of electronic components, and these electronic components are mounted. In addition to a first wiring path connecting an external signal conductive terminal on a surface and a terminal of the electronic component, a connection is made between terminals of the electronic component. A multi-chip module having a wiring board on which a second wiring path that does not need to be connected to the outside is formed, wherein a conductive terminal for inspection is provided on the surface of the wiring board; A multi-chip module connected to a conductive terminal for inspection.
おいて前記外部信号導電端子と同一平面上に形成され、
前記外部信号導電端子とともに同一格子上に配列された
ことを特徴とする請求項１記載のマルチチップモジュー
ル。2. The test conductive terminal is formed on the same plane as the external signal conductive terminal on the wiring board,
2. The multi-chip module according to claim 1, wherein the external signal conductive terminals are arranged on the same grid.
号用導電パッドとそのパッドの上に形成された半田端子
とを有する請求項２記載のマルチチップモジュール。3. The multi-chip module according to claim 2, wherein said external signal conductive terminals include external input / output signal conductive pads and solder terminals formed on said pads.
層した積層配線基板であり、前記検査用導電端子は、前
記配線基板の内部で前記第２の配線路に接続することを
特徴とする請求項２記載のマルチチップモジュール。4. The wiring board is a laminated wiring board in which an insulating layer and a wiring layer are laminated, and the inspection conductive terminal is connected to the second wiring path inside the wiring board. The multi-chip module according to claim 2, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8164247A JP2907127B2 (en) | 1996-06-25 | 1996-06-25 | Multi-chip module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8164247A JP2907127B2 (en) | 1996-06-25 | 1996-06-25 | Multi-chip module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1012809A true JPH1012809A (en) | 1998-01-16 |
| JP2907127B2 JP2907127B2 (en) | 1999-06-21 |
Family
ID=15789479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8164247A Expired - Fee Related JP2907127B2 (en) | 1996-06-25 | 1996-06-25 | Multi-chip module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2907127B2 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2907127B2 (en) | 1999-06-21 |
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