JPH0992780A - Multi-layered wiring board and method for mounting surface mount electronic component - Google Patents
Multi-layered wiring board and method for mounting surface mount electronic componentInfo
- Publication number
- JPH0992780A JPH0992780A JP7274701A JP27470195A JPH0992780A JP H0992780 A JPH0992780 A JP H0992780A JP 7274701 A JP7274701 A JP 7274701A JP 27470195 A JP27470195 A JP 27470195A JP H0992780 A JPH0992780 A JP H0992780A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- multilayer wiring
- electronic component
- mounting
- recesses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【目次】以下の順序で本発明を説明する。 発明の属する技術分野 従来の技術（図１１〜図１５） 発明が解決しようとする課題（図１１〜図１５） 課題を解決するための手段（図１〜図６） 発明の実施の形態 （１）第１実施例 （１−１）実装基板の構成（図１及び図２） （１−２）多層配線基板の製造手順（図３〜図５） （１−３）表面実装型電子部品の実装手順（図６） （１−４）第１実施例の動作 （１−５）第１実施例の効果 （２）第２実施例 （２−１）実装基板の構成（図７） （２−２）表面実装型電子部品の実装手順（図８及び図
９） （２−３）第２実施例の動作 （２−４）第２実施例の効果 （３）他の実施例（図１０） 発明の効果[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD OF THE INVENTION Conventional Technology (FIGS. 11 to 15) Problems to be Solved by the Invention (FIGS. 11 to 15) Means for Solving the Problems (FIGS. 1 to 6) Embodiments of the Invention (1 ) First Example (1-1) Configuration of Mounting Substrate (FIGS. 1 and 2) (1-2) Manufacturing Procedure of Multilayer Wiring Board (FIGS. 3 to 5) (1-3) Surface Mount Electronic Component Mounting procedure (FIG. 6) (1-4) Operation of first embodiment (1-5) Effect of first embodiment (2) Second embodiment (2-1) Configuration of mounting board (FIG. 7) (2) -2) Mounting procedure of surface mount type electronic component (FIGS. 8 and 9) (2-3) Operation of the second embodiment (2-4) Effect of the second embodiment (3) Other embodiment (FIG. 10) ) The invention's effect
【０００２】[0002]
【発明の属する技術分野】本発明は多層配線基板及び表
面実装型電子部品の実装方法に関し、例えば複数の表面
実装型電子部品を実装する多層配線基板及びその多層配
線基板に対する表面実装型電子部品の実装方法に適用し
て好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board and a method for mounting a surface-mounting electronic component, for example, a multilayer wiring board for mounting a plurality of surface-mounting electronic components and a surface-mounting electronic component for the multilayer wiring board. It is suitable for application to the mounting method.
【０００３】[0003]
【従来の技術】従来、この種の多層配線基板において
は、所定の配線パターンが形成されていると共に、実装
対象となる表面実装型電子部品の複数の電極又はリード
にそれぞれ対応して複数の電極（以下、これをランドと
呼ぶ）が設けられて構成されており、これら各ランドと
表面実装型電子部品のそれぞれ対応する電極又はリード
を物理的及び電気的に接続することにより、当該表面実
装型電子部品を実装するようになされている。2. Description of the Related Art Conventionally, in a multilayer wiring board of this type, a predetermined wiring pattern is formed, and a plurality of electrodes corresponding to a plurality of electrodes or leads of a surface mount electronic component to be mounted are respectively provided. (Hereinafter, this is referred to as a land) is provided and configured, and by physically and electrically connecting each land and the corresponding electrode or lead of the surface mount type electronic component, the surface mount type It is designed to mount electronic components.
【０００４】この場合この種の多層配線基板に複数の表
面実装型電子部品を実装する方法としては、図１１に示
すように、多層配線基板１の一面１Ａのみに例えば半導
体チツプ２及び複数のリード付ＩＣ３及び４を表面実装
する第１の実装方法や、図１２に示すように、多層配線
基板５の一面５Ａ及び他面５Ｂの両面にそれぞれ例えば
半導体チツプ６及び複数のリード付ＩＣ７及び８を表面
実装する第２の実装方法等が広く用いられている。In this case, as a method of mounting a plurality of surface mount type electronic components on this kind of multilayer wiring board, as shown in FIG. 11, for example, only one surface 1A of the multilayer wiring board 1 is provided with, for example, a semiconductor chip 2 and a plurality of leads. A first mounting method for surface mounting the attached ICs 3 and 4 or, for example, as shown in FIG. 12, a semiconductor chip 6 and a plurality of leaded ICs 7 and 8 on one surface 5A and the other surface 5B of the multilayer wiring board 5, respectively. The second mounting method for surface mounting is widely used.
【０００５】またこの他、図１３に示すように、多層配
線基板１０の一面１０Ａに複数の半導体チツプ１１及び
１２を重ねて直接接続した状態に表面実装する、いわゆ
るチツプトウチツプ方式（Chip to Chip方式）による第
３の実装方法や、図１４に示すように、複数のテープキ
ヤリアパツケージ１５及び１６を樹脂１７によつて一体
に封止して多層配線基板１８の一面１８Ａに表面実装す
る第４の実装方法、及び図１５に示すように、複数のテ
ープキヤリアパツケージ２０、２１及び２２を積層した
状態で多層配線基板２３の一面２３Ａに表面実装する第
５の実装方法等もある。さらには１個の表面実装型電子
部品を多層配線基板に埋設させるようにして実装する第
６の実装方法もある（図示せず）。In addition, as shown in FIG. 13, a plurality of semiconductor chips 11 and 12 are surface-mounted in a state of being directly connected to one surface 10A of the multilayer wiring board 10 in a so-called chip-to-chip method. 14 or a fourth mounting method in which a plurality of tape carrier packages 15 and 16 are integrally sealed with a resin 17 and surface-mounted on one surface 18A of the multilayer wiring board 18 as shown in FIG. As shown in FIG. 15, there is also a fifth mounting method in which a plurality of tape carrier packages 20, 21 and 22 are surface-mounted on one surface 23A of the multilayer wiring board 23 in a stacked state. Furthermore, there is also a sixth mounting method (not shown) in which one surface-mounting electronic component is embedded and embedded in a multilayer wiring board.
【０００６】[0006]
【発明が解決しようとする課題】ところが上述のような
第１の実装方法においては、多層配線基板１の実装面が
一面１Ａだけであるため、実装される表面実装型電子部
品の数が増加すると、その増加した表面実装型電子部品
毎の形状及び大きさに応じた実装面積が必要となる。こ
の結果多層配線基板１が大型化して配線パターンが長く
なるため、高速特性及び高周波特性が劣化する問題があ
つた。However, in the first mounting method as described above, since the mounting surface of the multilayer wiring board 1 is only one surface 1A, the number of surface mounting type electronic components mounted increases. In addition, a mounting area corresponding to the increased shape and size of each surface mount electronic component is required. As a result, the multilayer wiring board 1 becomes large and the wiring pattern becomes long, so that there is a problem that the high-speed characteristics and the high-frequency characteristics deteriorate.
【０００７】また第２の実装方法においては、多層配線
基板５の一面５Ａ及び他面５Ｂの両面に表面実装型電子
部品を実装するため、上述した第１の実装方法に比べて
同数の表面実装型電子部品を実装する場合、多層配線基
板５の大きさを２分の１程度まで小型化することができ
る利点があるものの、多層配線基板５をデイジタル化に
対応させた場合、実装される表面実装型電子部品の数が
増加するため、多層配線基板５をそれ以上小型化するこ
とができない問題があつた。Further, in the second mounting method, since the surface mounting type electronic components are mounted on both the one surface 5A and the other surface 5B of the multilayer wiring board 5, the same number of surface mountings as in the first mounting method described above are mounted. In the case of mounting a die-type electronic component, there is an advantage that the size of the multilayer wiring board 5 can be reduced to about one half, but when the multilayer wiring board 5 is adapted to digitalization, the surface to be mounted is Since the number of mountable electronic components increases, there is a problem that the multilayer wiring board 5 cannot be further downsized.
【０００８】さらに第３、第４及び第５の実装方法にお
いては、多層配線基板１０、１８及び２３に実装される
複数の表面実装型電子部品を積層配置して実装するた
め、各表面実装型電子部品を電気的及び機械的に保護す
る必要があり、表面実装型電子部品のパツケージ構成が
制限される問題があつた。この結果これら第３、第４及
び第５の実装方法では、多層配線基板１０、１８及び２
３に対する各表面実装型電子部品の実装手順が煩雑にな
る問題があつた。Further, in the third, fourth and fifth mounting methods, since a plurality of surface mount type electronic components mounted on the multilayer wiring boards 10, 18 and 23 are stacked and mounted, each surface mount type is mounted. It is necessary to protect the electronic parts electrically and mechanically, and there is a problem that the package structure of the surface mount type electronic parts is limited. As a result, in these third, fourth and fifth mounting methods, the multilayer wiring boards 10, 18 and 2 are mounted.
There is a problem that the mounting procedure of each surface mount type electronic component for 3 is complicated.
【０００９】さらに第６の実装方法においては、複数の
表面実装型電子部品を多層配線基板に実装する場合、各
々の表面実装型電子部品をそれぞれ所定の部分に埋設す
るため、実装対象の表面実装型電子部品の数に応じた埋
設スペースが必要となり、多層配線基板を小型化し難い
問題があつた。Further, in the sixth mounting method, when a plurality of surface mount type electronic components are mounted on the multilayer wiring board, since each surface mount type electronic component is embedded in a predetermined portion, the surface mount target is mounted. There is a problem that it is difficult to reduce the size of the multilayer wiring board because an embedded space is required according to the number of mold electronic components.
【００１０】本発明は以上の点を考慮してなされたもの
で、表面実装型電子部品を高密度実装し得る多層配線基
板及び表面実装型電子部品の実装方法を提案しようとす
るものである。The present invention has been made in view of the above points, and an object thereof is to propose a multilayer wiring board and a mounting method of a surface mounting type electronic component capable of mounting the surface mounting type electronic component at a high density.
【００１１】[0011]
【課題を解決するための手段】かかる課題を解決するた
め第１の発明においては、所定の導体パターンを有する
配線層と、絶縁材からなる絶縁層とが順次交互に積層形
成されてなる多層配線基板において、各配線層にそれぞ
れ対応させて複数の段差面が設けられた逆錐台形状でな
る単数又は複数の凹部を設け、各凹部の各段差面に、こ
れら各凹部の各段差面にそれぞれ対応する配線層と導通
する単数又は複数のランドを設けるようにする。In order to solve such a problem, in the first invention, a multilayer wiring in which a wiring layer having a predetermined conductor pattern and an insulating layer made of an insulating material are sequentially and alternately laminated and formed. In the substrate, one or more recesses having an inverted frustum shape in which a plurality of step surfaces are provided corresponding to each wiring layer are provided, and each step surface of each recess is provided on each step surface of each recess. A single land or a plurality of lands that are electrically connected to the corresponding wiring layer are provided.
【００１２】また第２の発明においては、所定の導体パ
ターンを有する配線層と、絶縁材からなる絶縁層とを順
次交互に積層形成し、各配線層にそれぞれ対応する複数
の段差面が設けられると共に、当該各段差面にこれら各
段差面にそれぞれ対応する配線層と導通する単数又は複
数のランドが設けられる逆錐台形状でなる単数又は複数
の凹部を有する多層配線基板を形成する第１の工程と、
各凹部に設けられた各段差面の各ランドにそれぞれ対応
する表面実装型電子部品の単数又は複数の電極を物理的
及び電気的に接続することにより、各段差面にそれぞれ
対応する表面実装型電子部品を実装する第２の工程と、
各凹部に、当該各凹部の各段差面にそれぞれ実装された
表面実装型電子部品を一体に封止する絶縁性樹脂を充填
する第３の工程とを設けるようにする。In the second aspect of the invention, a wiring layer having a predetermined conductor pattern and an insulating layer made of an insulating material are sequentially and alternately laminated, and a plurality of step surfaces corresponding to the respective wiring layers are provided. At the same time, a first multilayer wiring board is formed which has an inverted frustum-shaped recess or recesses in which a land or a plurality of lands electrically connected to the wiring layers corresponding to the step surfaces are provided on the step surfaces. Process,
By physically and electrically connecting one or more electrodes of the surface mount type electronic component corresponding to each land on each step face provided in each recess to the surface mount type electronic device corresponding to each step face. A second step of mounting the components,
A third step of filling each recess with an insulating resin that integrally seals the surface-mounted electronic component mounted on each step surface of each recess is provided.
【００１３】第１の発明では、各配線層にそれぞれ対応
させて複数の段差面が設けられた逆錐台形状でなる単数
又は複数の凹部を設け、当該各凹部の各段差面に、これ
ら各凹部の各段差面にそれぞれ対応する配線層と導通す
る単数又は複数のランドを設けるようにしたことによ
り、多層配線基板の所定面積に対して実装される表面実
装型電子部品を増加させることができる。In the first aspect of the present invention, a single or a plurality of recesses having an inverted frustum shape are provided, each recess having a plurality of step surfaces corresponding to each wiring layer. By providing one or a plurality of lands that are electrically connected to the corresponding wiring layers on each step surface of the recess, it is possible to increase the number of surface mount electronic components mounted on a predetermined area of the multilayer wiring board. .
【００１４】また第２の発明では、所定の導体パターン
を有する配線層と、絶縁材からなる絶縁層とを順次交互
に積層形成し、各配線層にそれぞれ対応する複数の段差
面が設けられると共に、当該各段差面にこれら各段差面
にそれぞれ対応する配線層と導通する単数又は複数のラ
ンドが設けられる逆錐台形状でなる単数又は複数の凹部
を有する多層配線基板を形成し、次いで各凹部に設けら
れた各段差面の各ランドにそれぞれ対応する表面実装型
電子部品の単数又は複数の電極を物理的及び電気的に接
続することにより、各段差面にそれぞれ対応する表面実
装型電子部品を実装し、続いて各凹部に、当該各凹部の
各段差面にそれぞれ実装された表面実装型電子部品を一
体に封止する絶縁性樹脂を充填するようにしたことによ
り、多層配線基板の各凹部に複数の表面実装型電子部品
を積層配置するように実装することができる。According to the second aspect of the invention, a wiring layer having a predetermined conductor pattern and an insulating layer made of an insulating material are alternately laminated to form a plurality of step surfaces corresponding to the respective wiring layers. Forming a multi-layer wiring board having a single or a plurality of recesses in the shape of an inverted frustum in which a land or a plurality of lands that are electrically connected to the wiring layers corresponding to the step surfaces are provided on the step surfaces, and then the recesses are formed. By physically and electrically connecting one or more electrodes of the surface mount type electronic component corresponding to each land on each step face provided on the surface mount type electronic component corresponding to each step face, By mounting and then filling each recess with an insulating resin that integrally seals the surface-mounted electronic components mounted on each step surface of each recess, a multilayer wiring board is obtained. A plurality of surface mount electronic device can be implemented so as to laminate disposed in each recess.
【００１５】[0015]
【発明の実施の形態】以下図面について、本発明の一実
施例を詳述する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.
【００１６】（１）第１実施例 （１−１）実装基板の構成 図１において、３０は全体として第１実施例による実装
基板を示し、多層配線基板３１に複数の表面実装型電子
部品が実装されて構成されている。多層配線基板３１
は、一層毎にそれぞれ所定の導体パターン３２Ａ及び３
２Ｂが形成された３層構造でなり、複数層の導体パター
ン３２Ａ及び３２Ｂがそれぞれ所定の領域に露出された
段差面３１Ｂ及び３１Ｃを有するほぼ逆四角錐台状でな
る凹部３１Ａが設けられている。(1) First Embodiment (1-1) Structure of Mounting Board In FIG. 1, reference numeral 30 generally indicates a mounting board according to the first embodiment, and a plurality of surface mounting type electronic components are provided on a multilayer wiring board 31. Implemented and configured. Multilayer wiring board 31
Is a predetermined conductor pattern 32A and 3 for each layer.
It has a three-layer structure in which 2B is formed, and a plurality of layers of conductor patterns 32A and 32B are provided with recessed portions 31A having a substantially inverted truncated pyramid shape having step surfaces 31B and 31C exposed in predetermined regions, respectively. .
【００１７】この場合凹部３１Ａにおいては、段差面３
１Ｂ及び３１Ｃと多層配線基板３１の上面３１Ｄとによ
つてそれぞれ区切られる直方体形状でなる空間領域３３
Ａ及び３３Ｂがそれぞれ実装される半導体チツプ３４及
び３５の大きさ及び形状に応じて選定されている。In this case, the step surface 3 is formed in the recess 31A.
1B and 31C and the upper surface 31D of the multi-layer wiring board 31 are separated from each other by a space region 33 having a rectangular parallelepiped shape.
A and 33B are selected according to the size and shape of the semiconductor chips 34 and 35 on which they are mounted.
【００１８】ここで図１及び図２に示すように、この多
層配線基板３１の凹部３１Ａの空間領域３３Ａ内には、
半導体チツプ３４の回路面３４Ａの最外周に沿つて所定
ピツチに配設された複数のパツド（図示せず）にそれぞ
れ対向させて、底面となる段差面３１Ｂに複数のランド
３６が設けられていると共に、これら各ランド３６はそ
れぞれ段差面３１Ｂに露出された導体パターン３２Ａの
所定位置に電気的に接続されている。Here, as shown in FIGS. 1 and 2, in the space region 33A of the recess 31A of the multilayer wiring board 31,
A plurality of lands 36 are provided on a step surface 31B serving as a bottom surface so as to face a plurality of pads (not shown) arranged in a predetermined pitch along the outermost periphery of the circuit surface 34A of the semiconductor chip 34. At the same time, each of these lands 36 is electrically connected to a predetermined position of the conductor pattern 32A exposed on the step surface 31B.
【００１９】また空間領域３３Ｂには、半導体チツプ３
５の回路面３５Ａの最外周に沿つて所定ピツチに配設さ
れた複数のパツド（図示せず）にそれぞれ対向させて、
底面となる段差面３１Ｃに複数のランド３７が設けられ
ていると共に、これら各ランド３７はそれぞれ段差面３
１Ｃに露出された導体パターン３２Ｂの所定位置に電気
的に接続されている。さらに半導体チツプ３４及び３５
の回路面３４Ａ及び３５Ａに配設された各パツドには、
それぞれ例えばはんだでなる突起電極３８及び３９が形
成されており、かくして半導体チツプ３４及び３５をそ
れぞれ空間領域３３Ａ及び３３Ｂに嵌め込み、各突起電
極３８及び３９をそれぞれ対応するランド３６及び３７
と接合することにより、当該半導体チツプ３４及び３５
を多層配線基板３１の凹部３１Ａ内に積層配置するよう
に実装し得るようになされている。In the space area 33B, the semiconductor chip 3 is
5, facing a plurality of pads (not shown) arranged in a predetermined pitch along the outermost periphery of the circuit surface 35A of 5,
A plurality of lands 37 are provided on the step surface 31C serving as the bottom surface, and each of the lands 37 is provided on the step surface 3 respectively.
The conductor pattern 32B exposed at 1C is electrically connected to a predetermined position. Further, semiconductor chips 34 and 35
The pads arranged on the circuit surfaces 34A and 35A of
Protruding electrodes 38 and 39 made of, for example, solder are respectively formed. Thus, the semiconductor chips 34 and 35 are fitted into the space regions 33A and 33B, respectively, and the protruding electrodes 38 and 39 are respectively provided in corresponding lands 36 and 37.
The semiconductor chips 34 and 35 are bonded to the semiconductor chips 34 and 35.
Can be mounted so as to be stacked in the recess 31A of the multilayer wiring board 31.
【００２０】また多層配線基板３１の上面３１Ｄには、
半導体チツプ４０が半導体チツプ３４及び３５と積層配
置されるように当該半導体チツプ４０の回路面４０Ａの
最外周に沿つて所定ピツチに配設された複数のパツド
（図示せず）にそれぞれ対向させて複数のランド４１が
設けられている。さらに半導体チツプ４０には、回路面
４０Ａに配設された各パツドにそれぞれ例えばはんだで
なる突起電極４２が形成されており、かくして半導体チ
ツプ４０は各突起電極４２をそれぞれ対応する多層配線
基板３１の上面３１Ｄに設けられたランド４１と接合す
ることにより、当該半導体チツプ４０を多層配線基板３
１の上面３１Ｄに実装し得るようになされている。On the upper surface 31D of the multilayer wiring board 31,
The semiconductor chip 40 is arranged so as to be stacked with the semiconductor chips 34 and 35 so as to face a plurality of pads (not shown) arranged in a predetermined pitch along the outermost periphery of the circuit surface 40A of the semiconductor chip 40. A plurality of lands 41 are provided. Further, in the semiconductor chip 40, projecting electrodes 42 made of, for example, solder are formed on the respective pads arranged on the circuit surface 40A, and thus the semiconductor chip 40 is provided on the multilayer wiring substrate 31 corresponding to the projecting electrodes 42. By bonding the semiconductor chip 40 to the land 41 provided on the upper surface 31D, the semiconductor chip 40 is connected to the multilayer wiring board 3.
It can be mounted on the upper surface 31D of the No. 1 unit.
【００２１】さらにこの多層配線基板３１においては、
凹部３１Ａ及び上面３１Ｄにそれぞれ実装された半導体
チツプ３４、３５及び４０を凹部３１Ａに一体に封止す
るように絶縁性樹脂４３がその凹部３１Ａに充填されて
いる。この場合多層配線基板３１の凹部３１Ａには、段
差面３１Ｂから多層配線基板３１の下面３１Ｅまで貫通
する貫通孔３１Ｆが穿設されており、これにより絶縁性
樹脂４３を半導体チツプ４０の回路面４０Ａ側から充填
する際、当該凹部３１Ａ内部の空気が貫通孔３１Ｆを介
して外部に排出され、絶縁性樹脂４３を均一に充填し得
るようになされている。Further, in this multilayer wiring board 31,
Insulating resin 43 is filled in the recess 31A so as to integrally seal the semiconductor chips 34, 35 and 40 mounted in the recess 31A and the upper surface 31D, respectively. In this case, the concave portion 31A of the multilayer wiring board 31 is provided with a through hole 31F penetrating from the step surface 31B to the lower surface 31E of the multilayer wiring board 31, whereby the insulating resin 43 is connected to the circuit surface 40A of the semiconductor chip 40. When filling from the side, the air inside the recess 31A is discharged to the outside through the through hole 31F, and the insulating resin 43 can be uniformly filled.
【００２２】さらに多層配線基板３１の上面３１Ｄ及び
下面３１Ｅの所定位置には、それぞれ能動素子４４及び
リード付ＩＣ４５の複数の電極及びリードに対向させて
それぞれ複数のランド４６及び４７が設けられ、これに
より能動素子４４及びリード付ＩＣ４５の各電極及びリ
ードとそれぞれ対応するランド４６及び４７とを接合し
て、これら能動素子４４及びリード付ＩＣ４５をこの多
層配線基板３１上に実装し得るようになされている。Further, a plurality of lands 46 and 47 are provided at predetermined positions on the upper surface 31D and the lower surface 31E of the multilayer wiring board 31 so as to face the plurality of electrodes and leads of the active element 44 and the IC 45 with leads, respectively. The electrodes and leads of the active element 44 and the IC 45 with leads are connected to the corresponding lands 46 and 47, respectively, so that the active element 44 and the IC 45 with leads can be mounted on the multilayer wiring board 31. There is.
【００２３】かくしてこの多層配線基板３１では、段差
面３１Ｂ及び３１Ｃを有する凹部３１Ａに半導体チツプ
３４及び３５を積層配置するように実装し得るため、従
来の多層配線基板に比べて所定面積に対して実装される
表面実装型電子部品を増加し得るようになされている。Thus, in this multilayer wiring board 31, the semiconductor chips 34 and 35 can be mounted so as to be stacked in the recess 31A having the step surfaces 31B and 31C. The number of surface mount type electronic components to be mounted can be increased.
【００２４】（１−２）多層配線基板の製造手順 ここで、実際上この多層配線基板３１は、図３（Ａ）〜
図５に示す以下の手順により製造することができる。す
なわち、まず図３（Ａ）〜（Ｃ）に示すように、所定の
厚さでなる複数の軟性状態セラミクス（以下、これをグ
リーンシートと呼ぶ）５０、５１及び５２の所定領域
を、それぞれ所定の大きさ及び形状でなる打抜き面を有
する打抜きツール５３、５４及び５５を用いて打ち抜
き、グリーンシート５０、５１及び５２にそれぞれ穴部
５０Ａ、５１Ａ及び５２Ａを形成する。この場合グリー
ンシート５０及び５１には、それぞれ半導体チツプ３４
及び３５の大きさ及び形状に応じた穴部５０Ａ及び５１
Ａが形成される。またグリーンシート５２には、多層配
線基板３１の凹部３１Ａに絶縁性樹脂４３を充填した際
に、その凹部３１Ａ内部の空気を外部に排出するための
穴部５２Ａ（すなわち、貫通孔３１Ｆ）が形成される。(1-2) Manufacturing Procedure of Multilayer Wiring Board Here, in practice, this multilayer wiring board 31 is shown in FIG.
It can be manufactured by the following procedure shown in FIG. That is, first, as shown in FIGS. 3 (A) to 3 (C), predetermined regions of a plurality of soft state ceramics (hereinafter, referred to as green sheets) 50, 51, and 52 each having a predetermined thickness are set to predetermined regions. Using the punching tools 53, 54 and 55 having the punching surfaces of the size and shape described above, holes 50A, 51A and 52A are formed in the green sheets 50, 51 and 52, respectively. In this case, each of the green sheets 50 and 51 has a semiconductor chip 34.
50A and 51 corresponding to the sizes and shapes of
A is formed. Further, in the green sheet 52, a hole 52A (that is, a through hole 31F) for discharging the air inside the recess 31A to the outside when the insulating resin 43 is filled in the recess 31A of the multilayer wiring board 31 is formed. To be done.
【００２５】次いでグリーンシート５０、５１及び５２
に複数のビアホール（図示せず）をそれぞれ所定位置に
形成し、当該各ビアホールに導電性金属ペーストを充填
してビア（図示せず）を形成する。続いてグリーンシー
ト５０及び５１の一面及びグリーンシート５２の一面及
び他面に、スクリーン印刷法等の手法によりそれぞれ導
電性金属箔でなる所定の導体パターン（図示せず）を対
応する各ビアと電気的に接続させるように印刷する。こ
の後グリーンシート５０、５１及び５２に形成された各
ビアの各導電性金属ペースト及び各導体パターンの溶剤
を所定温度により蒸発させる。Next, the green sheets 50, 51 and 52
A plurality of via holes (not shown) are formed at predetermined positions, and the via holes are filled with a conductive metal paste to form vias (not shown). Then, on one surface and the other surface of the green sheets 50 and 51 and one surface and the other surface of the green sheet 52, a predetermined conductor pattern (not shown) made of a conductive metal foil is formed by a method such as a screen printing method, and the corresponding vias and the corresponding vias are electrically connected. Print so that they are connected properly. After that, the solvent of each conductive metal paste and each conductor pattern of each via formed on the green sheets 50, 51 and 52 is evaporated at a predetermined temperature.
【００２６】この場合グリーンシート５０の一面に印刷
された所定の導体パターンには、半導体チツプ４０の複
数のパツド及び能動素子４４の複数の電極にそれぞれ対
応したランド４１及び４６が形成される。またグリーン
シート５１の一面に印刷された所定の導体パターンに
は、半導体チツプ３５の複数のパツドにそれぞれ対応し
たランド３７が形成される。さらにグリーンシート５２
の一面に印刷された所定の導体パターンには、半導体チ
ツプ３４の複数のパツドにそれぞれ対応したランド３６
が形成されると共に、グリーンシート５２の他面に印刷
された所定の導体パターンには、リード付ＩＣ４５の複
数のリードに対応したランド４７が形成される。In this case, lands 41 and 46 corresponding to a plurality of pads of the semiconductor chip 40 and a plurality of electrodes of the active element 44 are formed on a predetermined conductor pattern printed on one surface of the green sheet 50. Further, lands 37 corresponding to a plurality of pads of the semiconductor chip 35 are formed on a predetermined conductor pattern printed on one surface of the green sheet 51. Further green sheet 52
A predetermined conductor pattern printed on one surface of the semiconductor chip 34 has lands 36 respectively corresponding to a plurality of pads of the semiconductor chip 34.
And a land 47 corresponding to a plurality of leads of the IC 45 with leads is formed on a predetermined conductor pattern printed on the other surface of the green sheet 52.
【００２７】続いて図４（Ａ）に示すように、グリーン
シート５０、５１及び５２を、当該グリーンシート５
０、５１及び５２の打ち抜かれた穴部５０Ａ、５１Ａ及
び５２Ａの面積が厚み方向に順次大きくなり、かつ実装
対象の半導体チツプ３４、３５及び４０の複数のパツド
に対応したランド３６、３７及び４１（図示せず）を有
する導体パターンが上面となるように積層配置する。Subsequently, as shown in FIG. 4 (A), the green sheets 50, 51 and 52 are replaced by the green sheet 5 concerned.
The lands 36, 37 and 41 corresponding to a plurality of pads of the semiconductor chips 34, 35 and 40 to be mounted have the areas of the punched holes 50A, 51A and 52A of 0, 51 and 52 sequentially increasing in the thickness direction. The conductor pattern having (not shown) is laminated so that the conductor pattern is on the upper surface.
【００２８】この後図４（Ｂ）に示すように、グリーン
シート５０、５１及び５２を積層配置して形成されるほ
ぼ逆四角錐台状でなる凹部に、当該凹部に対応した形状
でなる加圧用型材５６を嵌め込み所定の圧力で加圧する
と同時に、グリーンシート５２の下面に加圧用型材５７
の所定面を接触させ所定の圧力で加圧する。次いで図４
（Ｃ）及び図５に示すように、積層配置されたグリーン
シート５０、５１及び５２を所定温度で焼成することに
より硬化させて一体化する。これにより、各層にそれぞ
れ段差面３１Ｂ及び３１Ｃを有する凹部３１Ａが形成さ
れる共に、当該段差面３１Ｂ及び３１Ｃと上面３１Ｄと
にそれぞれ実装される半導体チツプ３４、３５及び４０
に対応したランド３６、３７及び４１が形成された多層
配線基板３１を製造することができる。After that, as shown in FIG. 4B, a concave portion having a substantially inverted truncated pyramid shape formed by stacking the green sheets 50, 51 and 52 is added to the concave portion having a shape corresponding to the concave portion. At the same time as the pressing mold member 56 is fitted and pressed with a predetermined pressure, the pressing mold member 57 is attached to the lower surface of the green sheet 52.
The predetermined surfaces are contacted and pressurized with a predetermined pressure. Then FIG.
As shown in (C) and FIG. 5, the stacked green sheets 50, 51 and 52 are baked at a predetermined temperature to be cured and integrated. Thereby, the recess 31A having the step surfaces 31B and 31C is formed in each layer, and the semiconductor chips 34, 35 and 40 mounted on the step surfaces 31B and 31C and the upper surface 31D, respectively.
It is possible to manufacture the multilayer wiring board 31 on which the lands 36, 37 and 41 corresponding to are formed.
【００２９】（１−３）表面実装型電子部品の実装手順 一方この実装基板３０においては、図６（Ａ）〜（Ｃ）
に示す以下の手順により複数の表面実装型電子部品を多
層配線基板３１に実装することができる。すなわち、ま
ず図６（Ａ）に示すように、複数の半導体チツプ３４、
３５及び４０の回路面３４Ａ、３５Ａ及び４０Ａに配設
された複数のパツド（図示せず）にそれぞれ突起電極３
８、３９及び４２を形成する。次いで半導体チツプ３４
及び３５をそれぞれ対応する多層配線基板３１の空間領
域３３Ａ及び３３Ｂに嵌め込むようにして、半導体チツ
プ３４及び３５の各突起電極３８及び３９と、当該各突
起電極３８及び３９とそれぞれ対応させて段差面３１Ｂ
及び３１Ｃに設けられたランド３６及び３７とを接触さ
せて位置合わせする。(1-3) Mounting procedure of surface mount type electronic component On the other hand, in this mount board 30, FIGS.
A plurality of surface mount electronic components can be mounted on the multilayer wiring board 31 by the following procedure shown in FIG. That is, first, as shown in FIG. 6A, a plurality of semiconductor chips 34,
A plurality of pads (not shown) arranged on the circuit surfaces 34A, 35A and 40A of the reference numerals 35 and 40 respectively have the protruding electrodes 3
8, 39 and 42 are formed. Next, the semiconductor chip 34
And 35 are fitted into the corresponding spatial regions 33A and 33B of the multilayer wiring board 31, respectively, and the bump electrodes 38 and 39 of the semiconductor chips 34 and 35 are made to correspond to the bump electrodes 38 and 39, respectively.
And the lands 36 and 37 provided on 31C are brought into contact with each other for alignment.
【００３０】続いて半導体チツプ４０の各突起電極４２
と、当該各突起電極４２にそれぞれ対応して多層配線基
板３１の上面３１Ｄに設けられたランド４１とを接触さ
せて位置合わせする。その後半導体チツプ３４、３５及
び４０の各突起電極３８、３９及び４２を加熱溶融（以
下、これをリフローと呼ぶ）し、当該半導体チツプ３４
及び３５を多層配線基板３１の凹部３１Ａに実装すると
同時に半導体チツプ４０を多層配線基板３１の上面３１
Ｄに実装する。Subsequently, each protruding electrode 42 of the semiconductor chip 40 is
And the lands 41 provided on the upper surface 31D of the multilayer wiring board 31 corresponding to the respective protruding electrodes 42 are brought into contact with each other and aligned. Thereafter, the protruding electrodes 38, 39 and 42 of the semiconductor chips 34, 35 and 40 are heated and melted (hereinafter referred to as reflow), and the semiconductor chips 34
And 35 are mounted in the concave portion 31A of the multilayer wiring board 31, and at the same time, the semiconductor chip 40 is mounted on the upper surface 31 of the multilayer wiring board 31.
Install it in D.
【００３１】次いで図６（Ｂ）に示すように、多層配線
基板３１の上面３１Ｄに実装された半導体チツプ４０の
回路面４０Ａ側から多層配線基板３１の凹部３１Ａに絶
縁性樹脂４３を充填し、当該半導体チツプ４０の上面４
０Ｂを露出させるように半導体チツプ３４、３５及び４
０を多層配線基板３１の凹部３１Ａに一体に封止する。
この場合多層配線基板３１の凹部３１Ａでは、絶縁性樹
脂４３の充填に応じて貫通孔３１Ｆから内部の空気が抜
けるため、半導体チツプ３４、３５及び４０を均一に封
止することができる。Then, as shown in FIG. 6B, the insulating resin 43 is filled into the recess 31A of the multilayer wiring board 31 from the circuit surface 40A side of the semiconductor chip 40 mounted on the upper surface 31D of the multilayer wiring board 31. Upper surface 4 of the semiconductor chip 40
Semiconductor chips 34, 35 and 4 so as to expose 0B.
0 is integrally sealed in the recess 31A of the multilayer wiring board 31.
In this case, in the recess 31A of the multilayer wiring board 31, the internal air escapes from the through hole 31F according to the filling of the insulating resin 43, so that the semiconductor chips 34, 35 and 40 can be uniformly sealed.
【００３２】続いて図６（Ｃ）に示すように、能動素子
４４の複数の電極と、当該各電極にそれぞれ対応して多
層配線基板３１の上面３１Ｄの所定位置に設けられたラ
ンド４６とを接合し、その能動素子４４を多層配線基板
３１の上面３１Ｄに実装すると共に、リード付ＩＣ４５
の複数のリードと、当該各リードにそれぞれ対応して多
層配線基板３１の下面３１Ｅの所定位置に設けられたラ
ンド４７とを接合し、そのリード付ＩＣ４５を多層配線
基板３１の下面３１Ｅに実装する。これにより実装基板
３０は、多層配線基板３１の凹部３１Ａ、上面３１Ｄ及
び下面３１Ｅにそれぞれ対応させて半導体チツプ３４、
３５、４０、能動素子４４及びリード付ＩＣ４５を実装
することができる。Subsequently, as shown in FIG. 6C, a plurality of electrodes of the active element 44 and a land 46 provided at a predetermined position on the upper surface 31D of the multilayer wiring board 31 corresponding to each electrode are provided. The active element 44 is bonded and mounted on the upper surface 31D of the multilayer wiring board 31, and the IC 45 with leads is mounted.
A plurality of leads and lands 47 provided at predetermined positions on the lower surface 31E of the multilayer wiring board 31 corresponding to the respective leads, and the ICs 45 with leads are mounted on the lower surface 31E of the multilayer wiring board 31. . As a result, the mounting substrate 30 has the semiconductor chip 34, the upper surface 31D and the lower surface 31E of the multilayer wiring board 31 corresponding to the recesses 31A, 31D and 31E, respectively.
35, 40, the active element 44, and the IC with lead 45 can be mounted.
【００３３】（１−４）第１実施例の動作 以上の構成において、まず段差面３１Ｂ及び３１Ｃを有
するほぼ逆四角錐台状でなる凹部３１Ａが形成された多
層配線基板３１を形成し（図３〜図５）、次いで複数の
半導体チツプ３４及び３５を多層配線基板３１における
凹部３１Ａのそれぞれ対応する空間領域３３Ａ及び３３
Ｂに嵌め込むようにして段差面３１Ｂ及び３１Ｃ上に実
装すると同時に、半導体チツプ４０を多層配線基板３１
の上面３１Ｄに実装する（図６（Ａ））。この後多層配
線基板３１の凹部３１Ａに絶縁性樹脂４３を充填し、当
該凹部３１Ａに半導体チツプ３４、３５及び４０を一体
に封止する（図６（Ｂ））。続いて能動素子４４を多層
配線基板３１の上面３１Ｄに実装すると共に、リード付
ＩＣ４５を多層配線基板３１の下面３１Ｅに実装する
（図６（Ｃ））。(1-4) Operation of the First Embodiment In the above-mentioned structure, first, the multilayer wiring board 31 is formed in which the recessed portion 31A having a stepped surface 31B and 31C and having a substantially inverted truncated pyramid shape is formed (see FIG. 3 to 5), and then, a plurality of semiconductor chips 34 and 35 are provided in corresponding spatial regions 33A and 33 of the recess 31A in the multilayer wiring board 31, respectively.
The semiconductor chip 40 is mounted on the stepped surfaces 31B and 31C so as to be fitted in B, and at the same time, the semiconductor chip 40 is mounted on the multilayer wiring board 31.
It is mounted on the upper surface 31D (FIG. 6 (A)). After that, the recess 31A of the multilayer wiring board 31 is filled with the insulating resin 43, and the semiconductor chips 34, 35 and 40 are integrally sealed in the recess 31A (FIG. 6B). Subsequently, the active element 44 is mounted on the upper surface 31D of the multilayer wiring board 31, and the IC with lead 45 is mounted on the lower surface 31E of the multilayer wiring board 31 (FIG. 6C).
【００３４】従つて、この実装基板３０における複数の
表面実装型電子部品を多層配線基板３１に実装する実装
手順においては、半導体チツプ３４及び３５を多層配線
基板３１における凹部３１Ａの空間領域３３Ａ及び３３
Ｂに嵌め込むようにし、また半導体チツプ４０を多層配
線基板３１の上面３１Ｄに載上し、半導体チツプ３４、
３５及び４０を一括に実装することができるため、従来
の多層配線基板における表面実装型電子部品の実装方法
に比べて複雑な位置合わせ等を必要とせず容易に実装す
ることができる。Therefore, in the mounting procedure for mounting a plurality of surface mount type electronic components on the mounting board 30 on the multilayer wiring board 31, the semiconductor chips 34 and 35 are arranged in the space regions 33A and 33 of the recess 31A in the multilayer wiring board 31.
B, and the semiconductor chip 40 is mounted on the upper surface 31D of the multilayer wiring board 31, and the semiconductor chip 34,
Since 35 and 40 can be mounted at once, they can be mounted easily without requiring complicated positioning and the like as compared with the conventional mounting method of the surface mount type electronic component in the multilayer wiring board.
【００３５】またこのようにして多層配線基板３１に複
数の表面実装型電子部品が実装された実装基板３０で
は、半導体チツプ３４、３５及び４０が積層配置するよ
うに多層配線基板３１の凹部３１Ａ及び上面３１Ｄに実
装されると共に、当該多層配線基板３１の各層にそれぞ
れ形成された導体パターン３２Ａ及び３２Ｂ間をビアに
より導通させるため、当該導体パターン３２Ａ及び３２
Ｂを短くすることができる。従つて多層配線基板３１は
高速特性及び高周波特性を向上させることができる。Further, in the mounting board 30 in which a plurality of surface mount type electronic components are mounted on the multilayer wiring board 31 in this way, the concave portions 31A and 31A of the multilayer wiring board 31 are arranged so that the semiconductor chips 34, 35 and 40 are stacked. The conductor patterns 32A and 32B are mounted on the upper surface 31D and are electrically connected by the vias between the conductor patterns 32A and 32B formed on the respective layers of the multilayer wiring board 31.
B can be shortened. Therefore, the multilayer wiring board 31 can improve high-speed characteristics and high-frequency characteristics.
【００３６】またこの実装基板３０においては、半導体
チツプ３４、３５及び４０が絶縁性樹脂４３により多層
配線基板３１の凹部３１Ａに一体に封止されるため、実
装される半導体チツプ３４、３５及び４０を絶縁性樹脂
４３及び多層配線基板３１により電気的及び機械的に保
護することができる。In the mounting board 30, the semiconductor chips 34, 35 and 40 are integrally sealed in the recess 31A of the multilayer wiring board 31 by the insulating resin 43, so that the semiconductor chips 34, 35 and 40 to be mounted are mounted. Can be electrically and mechanically protected by the insulating resin 43 and the multilayer wiring board 31.
【００３７】（１−５）第１実施例の効果 以上の構成によれば、多層配線基板３１に段差面３１Ｂ
及び３１Ｃを有するほぼ逆四角錐台状でなる凹部３１Ａ
を設けると共に、当該凹部３１Ａの空間領域３３Ａ及び
３３Ｂと多層配線基板３１の上面３１Ｄとで積層配置す
るようにそれぞれ半導体チツプ３４、３５及び４０を実
装するようにしたことにより、実装基板３０における多
層配線基板３１の所定面積に対して実装される表面実装
型電子部品を増加させることができ、かくして表面実装
型電子部品を高密度実装し得る多層配線基板を実現する
ことができる。(1-5) Effects of First Embodiment According to the above configuration, the stepped surface 31B is formed on the multilayer wiring board 31.
And a concave portion 31A having a substantially inverted truncated pyramid shape having 31C
And the semiconductor chips 34, 35, and 40 are mounted so as to be stacked and arranged in the space regions 33A and 33B of the recess 31A and the upper surface 31D of the multilayer wiring board 31, respectively. It is possible to increase the number of surface-mounted electronic components mounted on a predetermined area of the wiring board 31, and thus it is possible to realize a multilayer wiring board on which the surface-mounted electronic components can be mounted at high density.
【００３８】また以上の構成によれば、段差面３１Ｂ及
び３１Ｃを有するほぼ逆四角錐台状でなる凹部３１Ａが
形成された多層配線基板３１を形成し、当該凹部３１Ａ
の空間領域３３Ａ及び３３Ｂにそれぞれ半導体チツプ３
４及び３５を嵌め込むようにすると共に多層配線基板３
１の上面３１Ｄに半導体チツプ４０を載上した後、半導
体チツプ３４，３５及び４０を一括に実装するようにし
たことにより、多層配線基板３１の凹部３１Ａ及び上面
３１Ｄに複数の半導体チツプ３４、３５及び４０を積層
配置するように実装することができ、かくして表面実装
型電子部品を高密度実装し得る表面実装型電子部品の実
装方法を実現することができる。Further, according to the above configuration, the multilayer wiring board 31 is formed in which the concave portion 31A having a substantially inverted truncated pyramid shape having the step surfaces 31B and 31C is formed, and the concave portion 31A is formed.
Of the semiconductor chip 3 in the space regions 33A and 33B of
4 and 35 are fitted in the multilayer wiring board 3
After mounting the semiconductor chips 40 on the upper surface 31D of the first semiconductor chip 34, the semiconductor chips 34, 35, and 40 are collectively mounted, so that the plurality of semiconductor chips 34, 35 are formed in the recess 31A and the upper surface 31D of the multilayer wiring board 31. And 40 can be mounted so as to be stacked, and thus, a mounting method of a surface mount type electronic component capable of high density mounting of the surface mount type electronic component can be realized.
【００３９】（２）第２実施例 （２−１）実装基板の構成 図７は、第２実施例による実装基板６０を示し、多層配
線基板６１に複数の表面実装型電子部品が実装されて構
成されている。多層配線基板６１は、各層に所定の導体
パターン（図示せず）が形成された２層構造でなり、上
面６１Ａよりも一周り小さく最下層の導体パターンを所
定領域だけ露出させた段差面６１Ｂを有する凹部６１Ｃ
が設けられている。この場合凹部６１Ｃは、実装される
半導体チツプ６２の大きさ及び形状に応じて選定されて
おり、半導体チツプ６２の回路面６２Ａの最外周に沿つ
て所定ピツチに配設された複数のパツド（図示せず）に
それぞれ対向させて、底面となる段差面６１Ｂに複数の
ランド（図示せず）が形成されている。(2) Second Embodiment (2-1) Structure of Mounting Board FIG. 7 shows a mounting board 60 according to a second embodiment, in which a plurality of surface mounting type electronic components are mounted on a multilayer wiring board 61. It is configured. The multilayer wiring board 61 has a two-layer structure in which a predetermined conductor pattern (not shown) is formed in each layer, and has a step surface 61B that is one size smaller than the upper surface 61A and exposes the lowermost conductor pattern in a predetermined area. Recessed portion 61C
Is provided. In this case, the recess 61C is selected according to the size and shape of the semiconductor chip 62 to be mounted, and a plurality of pads arranged in a predetermined pitch along the outermost periphery of the circuit surface 62A of the semiconductor chip 62 (see FIG. A plurality of lands (not shown) are formed on the step surface 61B serving as the bottom surface so as to face each other (not shown).
【００４０】また多層配線基板６１の上面６１Ａには、
半導体チツプ６２に積層配置されるように実装される半
導体チツプ６３の回路面６３Ａの最外周に沿つて所定ピ
ツチに配設された複数のパツド（図示せず）にそれぞれ
対向させて複数のランド（図示せず）が形成されてい
る。さらに半導体チツプ６２及び６３の回路面６２Ａ及
び６３Ａに配設された各パツドにはそれぞれ例えばはん
だボール６４が形成されている。On the upper surface 61A of the multilayer wiring board 61,
A plurality of lands (not shown) are provided so as to face a plurality of pads (not shown) arranged in a predetermined pitch along the outermost periphery of the circuit surface 63A of the semiconductor chip 63 mounted so as to be stacked on the semiconductor chip 62. (Not shown) is formed. Further, for example, solder balls 64 are formed on the pads provided on the circuit surfaces 62A and 63A of the semiconductor chips 62 and 63, respectively.
【００４１】これにより多層配線基板６１は、凹部６１
Ｃ内に半導体チツプ６２を嵌め込むようにされ、当該半
導体チツプ６２の各はんだボール６４がそれぞれ段差面
６１Ｂの対応するランドに接合されると共に、半導体チ
ツプ６３の各はんだボール６４がそれぞれ上面６１Ａの
対応するランドに接合され、積層配置するように半導体
チツプ６２及び６３を実装し得るようになされている。As a result, the multi-layered wiring board 61 has the concave portion 61.
The semiconductor chip 62 is fitted in the C, each solder ball 64 of the semiconductor chip 62 is bonded to the corresponding land of the step surface 61B, and each solder ball 64 of the semiconductor chip 63 is on the upper surface 61A. The semiconductor chips 62 and 63 are bonded to the corresponding lands so that they can be mounted in a stacked arrangement.
【００４２】この場合実装基板６０は、多層配線基板６
１がその上面６１Ａに実装される半導体チツプ６３の外
周とほぼ同じ大きさ及び形状の外周でなると共に、多層
配線基板６１の凹部６１Ｃに半導体チツプ６２及び６３
を一体に封止する絶縁性樹脂６５が充填されているた
め、いわゆる半導体パツケージ（チツプサイズパツケー
ジ）を形成するようになされている。In this case, the mounting board 60 is the multilayer wiring board 6
1 has an outer periphery of substantially the same size and shape as the outer periphery of the semiconductor chip 63 mounted on the upper surface 61A thereof, and the semiconductor chips 62 and 63 are formed in the recess 61C of the multilayer wiring board 61.
Since it is filled with an insulating resin 65 that integrally seals the semiconductor chip, a so-called semiconductor package (chip size package) is formed.
【００４３】またこの多層配線基板６１は、下面６１Ｄ
に例えば球状形状のはんだでなる複数の外部接続用電極
６６が配設されており、当該各外部接続用電極６６は実
装された半導体チツプ６２及び６３の各パツドとそれぞ
れ導体パターンを介して電気的に接続されている。従つ
て実装基板６０は、多層配線基板６１の各外部接続用電
極６６をそれぞれ主配線基板（図示せず）の対応する電
極に接合することにより、この主配線基板に所定状態に
実装することができると共に、半導体チツプ６２及び６
３が多層配線基板６１の導体パターン及び外部接続用電
極６６を介して主配線基板から信号を入力し、又は信号
を出力し得るようになされている。The multilayer wiring board 61 has a lower surface 61D.
Is provided with a plurality of external connection electrodes 66 made of, for example, spherical solder, and each external connection electrode 66 is electrically connected to each pad of the mounted semiconductor chips 62 and 63 via a conductor pattern. It is connected to the. Therefore, the mounting board 60 can be mounted in a predetermined state on the main wiring board by bonding the external connection electrodes 66 of the multilayer wiring board 61 to the corresponding electrodes of the main wiring board (not shown). Semiconductor chips 62 and 6
3 can input or output a signal from the main wiring board via the conductor pattern of the multilayer wiring board 61 and the external connection electrode 66.
【００４４】このように実装基板６０においては、多層
配線基板６１が凹部６１Ｃ内及び上面６１Ａにそれぞれ
実装された半導体チツプ６２及び６３の大きさ及び形状
に応じてその凹部６１Ｃ及び外周が形成されていると共
に、絶縁性樹脂６５によつて多層配線基板６１の凹部６
１Ｃに半導体チツプ６２及び６３が一体に封止され、か
くして複数の表面実装型電子部品が高密度実装された小
型の半導体パツケージを構成し得るようになされてい
る。As described above, in the mounting substrate 60, the multi-layer wiring substrate 61 is formed with the recess 61C and the outer periphery according to the size and shape of the semiconductor chips 62 and 63 mounted in the recess 61C and the upper surface 61A, respectively. In addition, the insulating resin 65 prevents the concave portion 6 of the multilayer wiring board 61 from
The semiconductor chips 62 and 63 are integrally sealed in 1C so that a small semiconductor package in which a plurality of surface mount electronic components are mounted at high density can be configured.
【００４５】（２−２）表面実装型電子部品の実装手順 ここで、実際上この実装基板６０においては、図８
（Ａ）〜図９（Ｂ）に示す以下の手順により複数の表面
実装型電子部品を多層配線基板６１に実装することがで
きる。すなわち、まず第１の実施例において上述した多
層配線基板の製造手順と同様の手順により、図８（Ａ）
に示すように、複数の凹部６１Ｃが所定ピツチに形成さ
れた２層構造でなる多層配線基板６１を形成する。この
場合多層配線基板６１には、それぞれ隣り合う凹部６１
Ｃのほぼ中間に位置するように上面６１Ａに所定の深さ
でなる溝６７を形成する。(2-2) Mounting procedure of surface mount type electronic component Here, in practice, in this mounting board 60, as shown in FIG.
A plurality of surface mount type electronic components can be mounted on the multilayer wiring board 61 by the following procedures shown in FIGS. That is, first, according to a procedure similar to the procedure for manufacturing the multilayer wiring board described above in the first embodiment, FIG.
As shown in, a multi-layer wiring substrate 61 having a two-layer structure in which a plurality of recesses 61C are formed in a predetermined pitch is formed. In this case, the multi-layered wiring board 61 has the concave portions 61 adjacent to each other.
A groove 67 having a predetermined depth is formed on the upper surface 61A so as to be located substantially in the middle of C.
【００４６】続いて図８（Ｂ）に示すように、複数の半
導体チツプ６２及び６３の複数のパツド（図示せず）に
それぞれはんだボール６４を形成する。この後各半導体
チツプ６２の各はんだボール６４と、これら各はんだボ
ール６４にそれぞれ対応する多層配線基板６１の各凹部
６１Ｃの段差面６１Ｂに形成されたランド（図示せず）
とを接触させて位置合わせすると共に、各半導体チツプ
６３の各はんだボール６４と、これら各はんだボール６
４にそれぞれ対応する多層配線基板６１の上面６１Ａに
形成されたランドとを接触させて位置合わせする。この
後各半導体チツプ６２及び６３の各はんだボール６４を
リフローし、当該各半導体チツプ６２及び６３を多層配
線基板６１の各凹部６１Ｃ及びその上面６１Ａに実装す
る。Subsequently, as shown in FIG. 8B, solder balls 64 are formed on a plurality of pads (not shown) of the plurality of semiconductor chips 62 and 63, respectively. Thereafter, each solder ball 64 of each semiconductor chip 62 and a land (not shown) formed on the step surface 61B of each recess 61C of the multilayer wiring board 61 corresponding to each solder ball 64 respectively.
And the solder balls 64 of the semiconductor chips 63 and the solder balls 6 are aligned.
4 are brought into contact with the lands formed on the upper surface 61A of the multilayer wiring board 61 corresponding to each of No. 4 and aligned. Thereafter, the solder balls 64 of the semiconductor chips 62 and 63 are reflowed to mount the semiconductor chips 62 and 63 on the recesses 61C of the multilayer wiring board 61 and the upper surface 61A thereof.
【００４７】次いで図８（Ｃ）に示すように、多層配線
基板６１の上面６１Ａに実装した半導体チツプ６３の上
面６３Ｂを露出させるように当該半導体チツプ６３の回
路面６３Ａ側から凹部６１Ｃに絶縁性樹脂６５を充填し
て硬化させ、実装した各半導体チツプ６２及び６３をそ
れぞれ凹部６１Ｃに一体に封止する。Next, as shown in FIG. 8C, insulating is provided in the recess 61C from the circuit surface 63A side of the semiconductor chip 63 so that the upper surface 63B of the semiconductor chip 63 mounted on the upper surface 61A of the multilayer wiring board 61 is exposed. The resin 65 is filled and cured, and the mounted semiconductor chips 62 and 63 are integrally sealed in the recess 61C.
【００４８】続いて図９（Ａ）に示すように、多層配線
基板６１の上面６１Ａに実装した半導体チツプ６３の上
面６３Ｂが下面となるように多層配線基板６１を回転さ
せて固定して、これにより上方を向いた多層配線基板６
１の下面６１Ｄの所定位置に例えば球状はんだ転写装置
（図示せず）を用いて複数の外部接続用電極６６を供給
する。Subsequently, as shown in FIG. 9A, the multilayer wiring board 61 is rotated and fixed so that the upper surface 63B of the semiconductor chip 63 mounted on the upper surface 61A of the multilayer wiring board 61 becomes the lower surface. Multilayer wiring board 6 facing upward by
A plurality of external connection electrodes 66 are supplied to predetermined positions on the lower surface 61D of the No. 1 using, for example, a spherical solder transfer device (not shown).
【００４９】次いで図９（Ｂ）に示すように、多層配線
基板６１を当該多層配線基板６１の上面６１Ａに形成さ
れた溝６７に沿つてそれぞれ一つの凹部６１Ｃを有する
所定領域に分割する。これにより実装基板６０の多層配
線基板６１に各半導体チツプ６２及び６３を実装するこ
とができる。Next, as shown in FIG. 9B, the multilayer wiring board 61 is divided into predetermined regions each having one recess 61C along the groove 67 formed in the upper surface 61A of the multilayer wiring board 61. Thus, the semiconductor chips 62 and 63 can be mounted on the multilayer wiring board 61 of the mounting board 60.
【００５０】（２−３）第２実施例の動作 以上の構成において、この実装基板６０は、複数の凹部
６１Ｃが所定ピツチに形成された２層構造でなる多層配
線基板６１を形成し、それぞれ隣り合う凹部６１Ｃのほ
ぼ中間位置の上面６１Ａに溝６７を形成する（図８
（Ａ））。次いで多層配線基板６１の凹部６１Ｃ及び上
面６１Ａにそれぞれ半導体チツプ６２及び６３を実装す
る（図８（Ｂ））。この後多層配線基板６１の凹部６１
Ｃに絶縁性樹脂６５を充填して硬化させ、実装した各半
導体チツプ６２及び６３を凹部６１Ｃに一体に封止する
（図８（Ｃ））。続いて多層配線基板６１の下面６１Ｄ
の所定位置に複数の外部接続用電極６６を供給して（図
９（Ａ））、この後多層配線基板６１の上面６１Ａに形
成された溝６７に沿つてそれぞれ一つの凹部６１Ｃを有
する所定領域に多層配線基板６１を分割する（図９
（Ｂ））。(2-3) Operation of the Second Embodiment In the above structure, the mounting board 60 forms the multilayer wiring board 61 having a two-layer structure in which a plurality of concave portions 61C are formed in predetermined pitches, and A groove 67 is formed on the upper surface 61A at a substantially intermediate position between the adjacent recesses 61C (FIG. 8).
(A)). Next, the semiconductor chips 62 and 63 are mounted on the recess 61C and the upper surface 61A of the multilayer wiring board 61, respectively (FIG. 8B). After this, the concave portion 61 of the multilayer wiring board 61
C is filled with the insulating resin 65 and cured, and the mounted semiconductor chips 62 and 63 are integrally sealed in the recess 61C (FIG. 8C). Then, the lower surface 61D of the multilayer wiring board 61
A plurality of electrodes 66 for external connection are supplied to predetermined positions (FIG. 9 (A)), and then predetermined regions each having one recess 61C along the groove 67 formed on the upper surface 61A of the multilayer wiring board 61. The multilayer wiring board 61 is divided into
(B)).
【００５１】従つてこの実装基板６０における表面実装
型電子部品の実装手順においては，多層配線基板６１に
複数形成された凹部６１Ｃ及びその上面６１Ａにそれぞ
れ半導体チツプ６２及び６３を積層配置するように実装
した後、一つの凹部６１Ｃを有する所定領域に多層配線
基板６１を分割するため、複数の多層配線基板６１にそ
れぞれ一括して複数の半導体チツプ６２及び６３を実装
することができる。この結果多層配線基板６１に複数の
半導体チツプ６２及び６３が実装された実装基板６０の
生産性を向上させることができる。Therefore, in the mounting procedure of the surface mount type electronic component on the mounting board 60, the semiconductor chips 62 and 63 are mounted so as to be stacked on the concave portions 61C formed in the multilayer wiring board 61 and the upper surface 61A thereof. After that, since the multilayer wiring board 61 is divided into a predetermined region having one concave portion 61C, a plurality of semiconductor chips 62 and 63 can be collectively mounted on each of the plurality of multilayer wiring boards 61. As a result, it is possible to improve the productivity of the mounting board 60 in which the plurality of semiconductor chips 62 and 63 are mounted on the multilayer wiring board 61.
【００５２】またこのようにして多層配線基板６１に複
数の半導体チツプ６２及び６３が実装された実装基板６
０は、多層配線基板６１の凹部６１Ｃ内及び上面６１Ａ
にそれぞれ実装された半導体チツプ６２及び６３を絶縁
性樹脂６５によつて多層配線基板６１の凹部６１Ｃに一
体に封止されることにより、各半導体チツプ６２及び６
３を電気的及び機械的に保護することができる。In addition, the mounting board 6 in which the plurality of semiconductor chips 62 and 63 are mounted on the multilayer wiring board 61 in this manner.
0 indicates the inside of the concave portion 61C and the upper surface 61A of the multilayer wiring board 61.
The semiconductor chips 62 and 63 respectively mounted on the semiconductor chips 62 and 6 are integrally sealed with the insulating resin 65 in the recess 61C of the multilayer wiring board 61.
3 can be protected electrically and mechanically.
【００５３】（２−４）第２実施例の効果 以上の構成によれば、多層配線基板６１に形成された凹
部６１Ｃの段差面６１Ｂに半導体チツプ６２が実装され
ると共に、当該半導体チツプ６２に積層配置するように
多層配線基板６１の上面６１Ａに、当該上面６１Ａとほ
ぼ同じ大きさの半導体チツプ６３が実装されることによ
り、実装される半導体チツプ６２及び６３の大きさとほ
ぼ同じ大きさの半導体パツケージを実現することがで
き、かくして表面実装型電子部品を高密度実装し得ると
共に、極めて小さい半導体パツケージを形成し得る多層
配線基板を実現することができる。(2-4) Effects of Second Embodiment According to the above configuration, the semiconductor chip 62 is mounted on the step surface 61B of the recess 61C formed in the multilayer wiring board 61, and the semiconductor chip 62 is mounted on the semiconductor chip 62. By mounting the semiconductor chips 63 having substantially the same size as the upper surface 61A on the upper surface 61A of the multilayer wiring board 61 so as to be stacked, the semiconductor chips having the sizes substantially the same as the sizes of the semiconductor chips 62 and 63 to be mounted. It is possible to realize a package, and thus it is possible to realize a multilayer wiring board capable of mounting surface-mounting electronic components at a high density and forming an extremely small semiconductor package.
【００５４】また以上の構成によれば、複数の凹部６１
Ｃが形成された多層配線基板６１を形成し、当該多層配
線基板６１の各凹部６１Ｃの段差面６１Ｂにそれぞれ半
導体チツプ６２を実装すると共に、これら各半導体チツ
プ６２にそれぞれ積層配置するように多層配線基板６１
の上面６１Ａに複数の半導体チツプ６３を実装し、絶縁
性樹脂６４により各半導体チツプ６２及び６３をそれぞ
れ凹部６１Ｃに一体に封止した後、多層配線基板６１を
一つの凹部６１Ｃを有する所定領域に分割するようにし
たことにより、半導体チツプ６２及び６３が実装された
半導体パツケージを小型化することができ、かくして半
導体パツケージに表面実装型電子部品を高密度実装し得
る表面実装型電子部品の実装方法を実現することができ
る。Further, according to the above configuration, the plurality of concave portions 61
A multilayer wiring board 61 in which C is formed is formed, the semiconductor chips 62 are mounted on the step surfaces 61B of the recesses 61C of the multilayer wiring board 61, respectively, and the multilayer wiring is arranged so as to be stacked on each of the semiconductor chips 62. Board 61
After mounting a plurality of semiconductor chips 63 on the upper surface 61A of the semiconductor chip and integrally sealing the semiconductor chips 62 and 63 in the recess 61C with an insulating resin 64, the multilayer wiring board 61 is formed in a predetermined region having one recess 61C. By the division, the semiconductor package on which the semiconductor chips 62 and 63 are mounted can be downsized, and thus, the mounting method of the surface mounting type electronic component capable of high density mounting of the surface mounting type electronic component on the semiconductor package. Can be realized.
【００５５】（３）他の実施例 なお上述の第１実施例においては、多層配線基板３１に
実装された各半導体チツプ３４、３５及び４０を封止す
るために多層配線基板３１の上面３１Ｄに実装された半
導体チツプ４０の回路面４０Ａ側から絶縁性樹脂４３を
充填するようにして、多層配線基板３１の貫通孔３１Ｆ
から凹部３１Ａ内部の空気を排出するようにした場合に
ついて述べたが、本発明はこれに限らず、多層配線基板
３１の貫通孔３１Ｆから凹部３１Ａに絶縁性樹脂４３を
充填して、多層配線基板３１の上面３１Ｄに実装された
半導体チツプ４０の回路面４０Ａ側から空気を抜くよう
にしても良い。(3) Other Embodiments In the above-mentioned first embodiment, the upper surface 31D of the multilayer wiring board 31 is sealed to seal the semiconductor chips 34, 35 and 40 mounted on the multilayer wiring board 31. The through hole 31F of the multilayer wiring board 31 is filled with the insulating resin 43 from the circuit surface 40A side of the mounted semiconductor chip 40.
The case where the air inside the recess 31A is discharged from the above is described, but the present invention is not limited to this, and the insulating resin 43 is filled into the recess 31A from the through hole 31F of the multilayer wiring board 31 to form the multilayer wiring board. Air may be evacuated from the circuit surface 40A side of the semiconductor chip 40 mounted on the upper surface 31D of 31.
【００５６】また上述の第１実施例においては、多層配
線基板３１に実装された複数の半導体チツプ３４、３５
及び４０と、能動素子４４とを別々に実装するようにし
た場合について述べたが、本発明はこれに限らず、半導
体チツプ３４、３５及び４０と能動素子４４とを一括に
実装するようにしても良い。Further, in the above-described first embodiment, the plurality of semiconductor chips 34, 35 mounted on the multilayer wiring board 31.
, 40 and the active element 44 are separately mounted. However, the present invention is not limited to this, and the semiconductor chips 34, 35 and 40 and the active element 44 may be mounted together. Is also good.
【００５７】さらに上述の第１及び第２実施例において
は、多層配線基板３１及び６１に形成された凹部３１Ａ
及び６１Ｃにそれぞれ半導体チツプ３４、３５及び６２
を実装するようにした場合について述べたが、本発明は
これに限らず、多層配線基板に形成された凹部にリード
付ＩＣ等の種々の表面実装型電子部品を実装するように
しても良い。Further, in the above-described first and second embodiments, the recess 31A formed in the multilayer wiring boards 31 and 61 is used.
And 61C to the semiconductor chips 34, 35 and 62, respectively.
However, the present invention is not limited to this, and various surface mount electronic components such as ICs with leads may be mounted in the recesses formed in the multilayer wiring board.
【００５８】すなわち、図１０に示すように、実装基板
７０においては、多層配線基板７１に複数の段差面を有
するほぼ逆四角錐台状でなる凹部７１Ａが設けられ、当
該凹部７１Ａの段差面７１Ｂ及び７１Ｃと、多層配線基
板７１の上面７１Ｄによつてそれぞれ区切られる直方体
形状でなる空間領域７２Ａ及び７２Ｂを、実装される半
導体チツプ７３又はリード付ＩＣ７４の大きさ及び形状
に応じて選定する。これにより多層配線基板７１は、凹
部７１Ａの各空間領域７２Ａ及び７２Ｂにそれぞれ半導
体チツプ７３及びリード付ＩＣ７４を実装することがで
き、かくして従来の多層配線基板に実装された表面実装
型電子部品のようにパツケージ構成の制限を必要せず、
種々のパッケージ構成でなる表面実装型電子部品を凹部
に実装し得る多層配線基板を実現することができる。That is, as shown in FIG. 10, in the mounting substrate 70, the multi-layered wiring board 71 is provided with a recess 71A having a substantially inverted truncated pyramid shape having a plurality of step surfaces, and the step surface 71B of the recess 71A. And 71C and the space areas 72A and 72B each having a rectangular parallelepiped shape, which are partitioned by the upper surface 71D of the multilayer wiring board 71, are selected according to the size and shape of the mounted semiconductor chip 73 or the IC 74 with leads. As a result, the multilayer wiring board 71 can mount the semiconductor chip 73 and the leaded IC 74 in the respective space regions 72A and 72B of the recess 71A, and thus, like the surface mount type electronic component mounted on the conventional multilayer wiring board. No need to limit package structure to
It is possible to realize a multi-layer wiring board capable of mounting surface mount electronic components having various package configurations in the recess.
【００５９】さらに上述の第１及び第２実施例において
は、多層配線基板３１及び６１をグリーンシート５０、
５１及び５２（すなわち、セラミクス）により形成する
ようにした場合について述べたが、本発明はこれに限ら
ず、ガラスエポキシ基板等の種々の基板を用いて形成す
るようにしても良い。Further, in the above-described first and second embodiments, the multilayer wiring boards 31 and 61 are connected to the green sheet 50,
Although the case where it is formed by 51 and 52 (that is, ceramics) has been described, the present invention is not limited to this and may be formed by using various substrates such as a glass epoxy substrate.
【００６０】さらに上述の第１及び第２実施例において
は、多層配線基板３１及び６１の積層数をそれぞれ３層
及び２層構造にして凹部３１Ａ及び６１Ｃを形成するよ
うにした場合について述べたが、本発明はこれに限ら
ず、実装対象の表面実装型電子部品の数に応じて多層配
線基板の積層数を種々の所定積層数にすると共に、実装
対象の表面実装型電子部品の大きさ及び形状に応じた空
間領域を有する凹部を形成するようにしても良い。Further, in the above-described first and second embodiments, the case where the concave portions 31A and 61C are formed by forming the multilayer wiring boards 31 and 61 with a three-layer structure and a two-layer structure, respectively, has been described. The present invention is not limited to this, and the number of laminated layers of the multilayer wiring board is set to various predetermined numbers according to the number of surface-mounted electronic components to be mounted, and the size of the surface-mounted electronic components to be mounted and You may make it form the recessed part which has a space area according to a shape.
【００６１】さらに上述の第１及び第２実施例において
は、多層配線基板３１及び６１にそれぞれ半導体チツプ
３４、３５、４０、６２及び６３を実装する際、当該半
導体チツプ３４、３５、４０、６２及び６３を一括に実
装するようにした場合について述べたが、本発明はこれ
に限らず、多層配線基板３１及び６１にそれぞれ形成さ
れた凹部３１Ａ及び６１Ｃの最下層側から順次半導体チ
ツプを積層配置するように実装するようにしても良い。Further, in the above-mentioned first and second embodiments, when the semiconductor chips 34, 35, 40, 62 and 63 are mounted on the multilayer wiring boards 31 and 61, respectively, the semiconductor chips 34, 35, 40 and 62 are mounted. And 63 are collectively mounted, the present invention is not limited to this, and the semiconductor chips are sequentially stacked from the lowermost layer side of the concave portions 31A and 61C formed in the multilayer wiring boards 31 and 61, respectively. You may make it implement so that.
【００６２】[0062]
【発明の効果】上述のように本発明によれば、各配線層
にそれぞれ対応させて複数の段差面が設けられた逆錐台
形状でなる単数又は複数の凹部を設け、当該各凹部の各
段差面に、これら各凹部の各段差面にそれぞれ対応する
配線層と導通する単数又は複数のランドを設けるように
したことにより、多層配線基板の所定面積に対して実装
される表面実装型電子部品を増加させることができ、か
くして表面実装型電子部品を高密度実装し得る多層配線
基板を実現することができる。As described above, according to the present invention, a single or plural inverted frustum-shaped concave portions provided with a plurality of step surfaces corresponding to the respective wiring layers are provided. By providing the step surface with a single or a plurality of lands that are electrically connected to the wiring layers corresponding to the step surfaces of each of the recesses, a surface mount electronic component mounted on a predetermined area of the multilayer wiring board is provided. Therefore, it is possible to realize a multilayer wiring board on which surface mount electronic components can be mounted at high density.
【００６３】また上述のように本発明によれば、所定の
導体パターンを有する複数の配線層と絶縁材からなる複
数の絶縁層とを順次交互に積層形成し、各配線層にそれ
ぞれ対応する複数の段差面が設けられると共に、当該各
段差面にこれら各段差面にそれぞれ対応する配線層と導
通する単数又は複数のランドが設けられる逆錐台形状で
なる単数又は複数の凹部を有する多層配線基板を形成
し、次いで各凹部に設けられた各段差面の各ランドにそ
れぞれ対応する表面実装型電子部品の単数又は複数の電
極を物理的及び電気的に接続することにより、各段差面
にそれぞれ対応する表面実装型電子部品を実装し、続い
て各凹部に当該各凹部の各段差面にそれぞれ実装された
表面実装型電子部品を一体に封止する絶縁性樹脂を充填
するようにしたことにより、多層配線基板の各凹部に複
数の表面実装型電子部品を積層配置するように実装する
ことができ、かくして表面実装型電子部品を高密度実装
し得る表面実装型電子部品の実装方法を実現することが
できる。Further, as described above, according to the present invention, a plurality of wiring layers having a predetermined conductor pattern and a plurality of insulating layers made of an insulating material are sequentially and alternately laminated to form a plurality of wiring layers corresponding to the respective wiring layers. Multi-layer wiring board having a stepped surface and an inverted frustum-shaped recess or recesses provided on each stepped surface with one or more lands electrically connected to the wiring layers corresponding to the stepped surfaces. And then physically and electrically connecting one or more electrodes of the surface mount type electronic component corresponding to each land on each step surface provided in each recess to correspond to each step surface. The surface mount type electronic component is mounted, and subsequently each recess is filled with an insulating resin that integrally seals the surface mount type electronic component mounted on each step surface of each recess. As a result, a plurality of surface mount type electronic components can be mounted so as to be stacked in each concave portion of the multilayer wiring board, thus realizing a mounting method of the surface mount type electronic components capable of high density mounting of the surface mount type electronic components. can do.
【図１】本発明の第１実施例による多層配線基板に複数
の表面実装型電子部品が実装された実装基板の構成を示
す断面図である。FIG. 1 is a cross-sectional view showing a structure of a mounting board in which a plurality of surface mount electronic components are mounted on a multilayer wiring board according to a first embodiment of the present invention.
【図２】本発明の第１実施例による多層配線基板の凹部
に実装された半導体チツプの様子を示す一部を断じた斜
視図である。FIG. 2 is a partially cutaway perspective view showing a state of a semiconductor chip mounted in a recess of a multilayer wiring board according to a first embodiment of the present invention.
【図３】本発明の第１実施例による実装基板における多
層配線基板の製造手順を示す断面図である。FIG. 3 is a cross-sectional view showing the manufacturing procedure of the multilayer wiring board in the mounting board according to the first embodiment of the present invention.
【図４】本発明の第１実施例による実装基板における多
層配線基板の製造手順を示す断面図である。FIG. 4 is a cross-sectional view showing the procedure for manufacturing the multilayer wiring board in the mounting board according to the first embodiment of the present invention.
【図５】本発明の第１実施例による多層配線基板の製造
手順により製造された多層配線基板を示す一部を断じた
斜視図である。FIG. 5 is a partially cutaway perspective view showing a multilayer wiring board manufactured by a manufacturing procedure of a multilayer wiring board according to a first embodiment of the present invention.
【図６】本発明の第１実施例による実装基板における多
層配線基板に実装される表面実装型電子部品の実装手順
を示す断面図である。FIG. 6 is a cross-sectional view showing a mounting procedure of the surface mount electronic component mounted on the multilayer wiring board in the mounting board according to the first embodiment of the present invention.
【図７】本発明の第２実施例による多層配線基板に複数
の表面実装型電子部品が実装された実装基板の構成を示
す断面図である。FIG. 7 is a cross-sectional view showing a structure of a mounting board in which a plurality of surface mount electronic components are mounted on a multilayer wiring board according to a second embodiment of the present invention.
【図８】本発明の第２実施例による実装基板における表
面実装型電子部品の実装手順を示す断面図である。FIG. 8 is a sectional view showing a mounting procedure of a surface mount electronic component on a mounting board according to a second embodiment of the present invention.
【図９】本発明の第２実施例による実装基板における表
面実装型電子部品の実装手順を示す断面図である。FIG. 9 is a sectional view showing a mounting procedure of a surface mount electronic component on a mounting board according to a second embodiment of the present invention.
【図１０】本発明の他の実施例による実装基板の構成を
示す断面図である。FIG. 10 is a sectional view showing a configuration of a mounting board according to another embodiment of the present invention.
【図１１】従来の多層配線基板における表面実装型電子
部品の第１の実装方法の説明に供する断面図である。FIG. 11 is a cross-sectional view provided for explaining a first mounting method of a surface-mounted electronic component on a conventional multilayer wiring board.
【図１２】従来の多層配線基板における表面実装型電子
部品の第２の実装方法の説明に供する断面図である。FIG. 12 is a cross-sectional view for explaining a second mounting method of a surface-mounted electronic component on a conventional multilayer wiring board.
【図１３】従来の多層配線基板における表面実装型電子
部品の第３の実装方法の説明に供する断面図である。FIG. 13 is a cross-sectional view for explaining a third mounting method of a surface-mounted electronic component on a conventional multilayer wiring board.
【図１４】従来の多層配線基板における表面実装型電子
部品の第４の実装方法の説明に供する断面図である。FIG. 14 is a cross-sectional view for explaining a fourth mounting method of a surface-mounted electronic component on a conventional multilayer wiring board.
【図１５】従来の多層配線基板における表面実装型電子
部品の第５の実装方法の説明に供する断面図である。FIG. 15 is a cross-sectional view for explaining a fifth mounting method of a surface-mounted electronic component on a conventional multilayer wiring board.
１、５、１０、１８、２３、３１、６１、７１……多層
配線基板、２、６、１１、１２、３４、３５、４０、６
１、６２、７３……半導体チツプ、３、４、７、８、４
５、７４……リード付ＩＣ、３０、６０、７０……実装
基板、１５、１６、２０、２１、２２……テープキヤリ
アパツケージ、１７、４３、６５……絶縁性樹脂、３１
Ａ、６１Ｃ、７１Ａ……凹部、３１Ｂ、３１Ｃ、６１
Ｂ、７１Ｂ、７１Ｃ……段差面、３１Ｆ……貫通孔、３
２Ａ、３２Ｂ……導体パターン、３３Ａ、３３Ｂ、７２
Ａ、７２Ｂ……空間領域、４４……能動素子、３６、３
７、４１、４６、４７……電極、３８、３９、４２、６
７……突起電極、５０、５１、５２……グリーンシー
ト、５３、５４、５５……打抜きツール、５６、５７…
…加工用型材、６４……はんだボール、６６……外部接
続用電極、６７……溝。1, 5, 10, 18, 23, 31, 61, 71 ... Multilayer wiring board, 2, 6, 11, 12, 34, 35, 40, 6
1, 62, 73 ... Semiconductor chips 3, 4, 7, 8, 4
5, 74 ... Leaded IC, 30, 60, 70 ... Mounting board, 15, 16, 20, 21, 22 ... Tape carrier package, 17, 43, 65 ... Insulating resin, 31
A, 61C, 71A ... Recesses, 31B, 31C, 61
B, 71B, 71C ... stepped surface, 31F ... through hole, 3
2A, 32B ... Conductor pattern, 33A, 33B, 72
A, 72B ... spatial area, 44 ... active element, 36, 3
7, 41, 46, 47 ... Electrodes, 38, 39, 42, 6
7 ... Projection electrode, 50, 51, 52 ... Green sheet, 53, 54, 55 ... Punching tool, 56, 57 ...
… Processing mold material, 64 …… Solder balls, 66 …… External connection electrodes, 67 …… Grooves.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 25/07 Ｈ０５Ｋ 3/46 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 25/07 H05K 3/46
Claims (10)
縁材からなる絶縁層とが順次交互に積層形成されてなる
多層配線基板において、 各上記配線層にそれぞれ対応させて複数の段差面が設け
られた逆錐台形状でなる単数又は複数の凹部を具え、各
上記凹部の各上記段差面には、各上記凹部の各上記段差
面にそれぞれ対応する上記配線層と導通する単数又は複
数のランドが設けられていることを特徴とする多層配線
基板。1. A multilayer wiring board comprising a wiring layer having a predetermined conductor pattern and an insulating layer made of an insulating material, which are laminated alternately in sequence, and a plurality of step surfaces are provided corresponding to the respective wiring layers. An inverted frustum shape is provided to provide one or more recesses, and each step surface of each recess has a single or a plurality of sections electrically connected to the wiring layer corresponding to each step surface of each recess. A multi-layer wiring board having a land.
れ、各上記段差面に設けられた各上記ランドにそれぞれ
対応する上記表面実装型電子部品の単数又は複数の電極
が物理的及び電気的に接続されることにより、各上記段
差面にそれぞれ対応する上記表面実装型電子部品が実装
されることを特徴とする請求項１に記載の多層配線基
板。2. Each of the recesses is formed in accordance with the size and shape of each surface-mounted electronic component, and the singular of the surface-mounted electronic component corresponding to each of the lands provided on each step surface. Alternatively, the surface mounting type electronic component corresponding to each of the step surfaces is mounted by physically and electrically connecting a plurality of electrodes, and the multilayer wiring board according to claim 1.
ように上記配線層と上記絶縁層とが順次交互に積層形成
され、上記最上層及び又は上記最下層の一面にそれぞれ
単数又は複数の表面実装型電子部品が実装されることを
特徴とする請求項２に記載の多層配線基板。3. The wiring layers and the insulating layers are sequentially and alternately laminated so that the uppermost layer and / or the lowermost layer are the wiring layers, and one or a plurality of layers are formed on one surface of the uppermost layer and / or the lowermost layer, respectively. The multilayer wiring board according to claim 2, wherein the surface-mounted electronic component is mounted.
された単数の上記凹部とほぼ同じ大きさでなることを特
徴とする請求項２に記載の多層配線基板。4. The multilayer wiring board according to claim 2, which has substantially the same size as the single recessed portion on which a single or a plurality of surface-mounted electronic components are mounted.
でなる最下層に貫通する貫通孔を具えることを特徴とす
る請求項１に記載の多層配線基板。5. The multilayer wiring board according to claim 1, further comprising a through hole penetrating from each of the recesses to a lowermost layer formed of the wiring layer or the insulating layer.
縁材からなる絶縁層とを順次交互に積層形成し、各上記
配線層にそれぞれ対応する複数の段差面が設けられると
共に、当該各段差面に、それぞれ対応する上記配線層と
導通する単数又は複数のランドが設けられる逆錐台形状
でなる単数又は複数の凹部を有する多層配線基板を形成
する第１の工程と、 各上記凹部に設けられた各上記段差面の各上記ランドに
それぞれ対応する表面実装型電子部品の単数又は複数の
電極を物理的及び電気的に接続することにより、各上記
段差面にそれぞれ対応する表面実装型電子部品を実装す
る第２の工程と、 各上記凹部に、当該各凹部の各上記段差面にそれぞれ実
装された上記表面実装型電子部品を一体に封止する絶縁
性樹脂を充填する第３の工程とを具えることを特徴とす
る表面実装型電子部品の実装方法。6. A wiring layer having a predetermined conductor pattern and an insulating layer made of an insulating material are sequentially and alternately laminated to form a plurality of step surfaces corresponding to the respective wiring layers, and each step is formed. A first step of forming a multilayer wiring board having a single or a plurality of recesses in the shape of an inverted frustum in which a single or a plurality of lands each of which is electrically connected to the corresponding wiring layer are provided on the surface; By physically and electrically connecting one or more electrodes of the surface-mounted electronic component corresponding to the respective lands on the respective stepped surfaces, the surface-mounted electronic component corresponding to the respective stepped surfaces is physically and electrically connected. And a third step of filling each of the recesses with an insulating resin that integrally seals the surface-mounted electronic component mounted on each of the step surfaces of each of the recesses. To Surface mounted electronic part mounting method, wherein the obtaining.
状に応じて形成することを特徴とする請求項６に記載の
表面実装型電子部品の実装方法。7. The surface-mounted electronic component according to claim 6, wherein in the first step, the recesses are formed in accordance with the size and shape of the surface-mounted electronic component. How to implement.
各上記凹部が形成されている面と対向する面側に貫通孔
を穿設することを特徴とする請求項６に記載の表面実装
型電子部品の実装方法。8. The first step is characterized in that a through hole is formed from each of the recesses of the multilayer wiring board to a surface side of the multilayer wiring board opposite to a surface on which the recesses are formed. The method for mounting a surface mount electronic component according to claim 6.
は複数の上記表面実装型電子部品を実装することを特徴
とする請求項６に記載の表面実装型電子部品の実装方
法。9. The surface mounting according to claim 6, wherein in the second step, one or a plurality of the surface mounting type electronic components are mounted on one surface and / or the other surface of the multilayer wiring board, respectively. Type electronic parts mounting method.
有する所定の大きさに分割する第４の工程を具えること
を特徴とする請求項６に記載の表面実装型電子部品の実
装方法。10. The method for mounting a surface mount electronic component according to claim 6, further comprising a fourth step of dividing the multilayer wiring board into a predetermined size having a single concave portion. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27470195A JP3710003B2 (en) | 1995-09-27 | 1995-09-27 | Mounting board and manufacturing method of mounting board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27470195A JP3710003B2 (en) | 1995-09-27 | 1995-09-27 | Mounting board and manufacturing method of mounting board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0992780A true JPH0992780A (en) | 1997-04-04 |
| JP3710003B2 JP3710003B2 (en) | 2005-10-26 |
Family
ID=17545362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27470195A Expired - Fee Related JP3710003B2 (en) | 1995-09-27 | 1995-09-27 | Mounting board and manufacturing method of mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3710003B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1174648A (en) * | 1997-08-27 | 1999-03-16 | Kyocera Corp | Wiring board |
| JP2001015678A (en) * | 1999-06-29 | 2001-01-19 | Mitsubishi Electric Corp | High frequency module |
| JP2002076314A (en) * | 2000-08-30 | 2002-03-15 | Texas Instr Japan Ltd | Ultra-miniature imaging device |
| JP2002373966A (en) * | 2001-06-13 | 2002-12-26 | Matsushita Electric Ind Co Ltd | Mounting structure for semiconductor chip and method for manufacturing the same |
| JP2008277838A (en) * | 2008-05-21 | 2008-11-13 | Mitsubishi Electric Corp | High-frequency module |
| JP2010238923A (en) * | 2009-03-31 | 2010-10-21 | Tdk Corp | Module with built-in electronic component |
-
1995
- 1995-09-27 JP JP27470195A patent/JP3710003B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1174648A (en) * | 1997-08-27 | 1999-03-16 | Kyocera Corp | Wiring board |
| JP2001015678A (en) * | 1999-06-29 | 2001-01-19 | Mitsubishi Electric Corp | High frequency module |
| JP2002076314A (en) * | 2000-08-30 | 2002-03-15 | Texas Instr Japan Ltd | Ultra-miniature imaging device |
| JP2002373966A (en) * | 2001-06-13 | 2002-12-26 | Matsushita Electric Ind Co Ltd | Mounting structure for semiconductor chip and method for manufacturing the same |
| JP4536291B2 (en) * | 2001-06-13 | 2010-09-01 | パナソニック株式会社 | Semiconductor chip mounting structure and manufacturing method thereof |
| JP2008277838A (en) * | 2008-05-21 | 2008-11-13 | Mitsubishi Electric Corp | High-frequency module |
| JP2010238923A (en) * | 2009-03-31 | 2010-10-21 | Tdk Corp | Module with built-in electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3710003B2 (en) | 2005-10-26 |
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