JPH0982810A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPH0982810A
JPH0982810A JP7230972A JP23097295A JPH0982810A JP H0982810 A JPH0982810 A JP H0982810A JP 7230972 A JP7230972 A JP 7230972A JP 23097295 A JP23097295 A JP 23097295A JP H0982810 A JPH0982810 A JP H0982810A
Authority
JP
Japan
Prior art keywords
conductive
conductive portion
region
film
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7230972A
Other languages
Japanese (ja)
Inventor
Hiroshi Yamamoto
博士 山本
Takeshi Takahashi
剛 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7230972A priority Critical patent/JPH0982810A/en
Publication of JPH0982810A publication Critical patent/JPH0982810A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress the interdiffusion of the impurities having different conductive types without increasing cell area. SOLUTION: A P<+> type gate region 10 is formed on the expected region for formation of a P-MOS, an N<+> type gate region 11 is formed on the expected region for formation of an N-MOS, a semiconductor substrate 100, which is provided with the pattern 12 of a gate electrode formed by electrically connecting these regions 10 and 11, is prepared and an interlayer insulating film 14 is formed on the upper layer of the semiconductor substrate 100. Then, the first contact hole 15 is formed on the interlayer insulating film 14, and at the same time, the second contact hole 16 is formed on the position directly above the interfacial part 19 of the P<+> type gate region 10 and the N<+> type gate region 11. Then, a resist film 20 is formed, and a hole 21, which separates the P<+> type gate region 10 and the N<+> type gate region 11, is formed by etching on the position directly under the second contact hole 16. Then, a P<+> type gate electrode 22a and an N<+> type gate electrode 22b are obtained by heat treatment, and the inner surface of the first contact hole 15 and the hole 21 is covered by a wiring material film 23 respectively.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、第１導電型の第１
導電部を有する第１の半導体素子と第２導電型の第２導
電部を有する第２の半導体素子とを備え、これら第１導
電部と第２導電部とが電気的に連続してなる半導体装置
を製造する方法とその半導体装置に関し、特にCompleme
ntary ＭＯＳトランジスタ（ＣＭＯＳ）の製造に好適な
半導体装置の製造方法と半導体装置とに関するものであ
る。TECHNICAL FIELD The present invention relates to a first conductivity type first
A semiconductor including a first semiconductor element having a conductive portion and a second semiconductor element having a second conductive type second conductive portion, and the first conductive portion and the second conductive portion being electrically continuous. A method of manufacturing a device and its semiconductor device, particularly Compleme
The present invention relates to a semiconductor device manufacturing method and a semiconductor device suitable for manufacturing an ntary MOS transistor (CMOS).

【０００２】[0002]

【従来の技術】従来、この種の半導体装置としては、図
８に示すような、ＮチャネルＭＯＳＦＥＴ（ＮＭＯＳＦ
ＥＴ）５１とＰチャネルＭＯＳＦＥＴ（ＰＭＯＳＦＥ
Ｔ）５２との両者で構成されるＣＭＯＳ５０が知られて
いる。従来のＣＭＯＳ５０では、ＰＭＯＳＦＥＴ５２の
ゲート電極として、ＮＭＯＳＦＥＴ５１と同じくＮ+ 型
のポリシリコン（Poly−Ｓｉ）ゲート電極が用いられて
いた。ところが、ＬＳＩの微細化に伴って素子の高速
化、高性能化が求められているものの、Ｎ+ 型ゲート電
極ではＰＭＯＳＦＥＴの特性を確保するのが難しくなっ
てきており、最近では、ＰＭＯＳＦＥＴのゲート電極に
Ｐ+ 型を用いることが有効とされている。2. Description of the Related Art Conventionally, as a semiconductor device of this type, as shown in FIG.
ET) 51 and P-channel MOSFET (PMOSFE
A CMOS 50 is known which is composed of both T) 52. In the conventional CMOS 50, as the gate electrode of the PMOSFET 52, the N + type polysilicon (Poly-Si) gate electrode is used as in the NMOSFET 51. However, although higher speed and higher performance of the device are required with the miniaturization of the LSI, it has become difficult to secure the characteristics of the PMOSFET with the N + type gate electrode, and recently, the gate of the PMOSFET has become difficult. It is considered effective to use a P + type electrode.

【０００３】このような、ＮＭＯＳＦＥＴのPoly−Ｓｉ
ゲート電極にＮ+ 型の不純物を導入し、ＰＭＯＳＦＥＴ
のPoly−Ｓｉゲート電極にＰ+ 型の不純物を導入したＣ
ＭＯＳ、つまり同一の半導体基板上に異なる導電型のゲ
ート電極を形成したいわゆるデュアルゲート構造のＣＭ
ＯＳは、例えば以下のような方法で製造されている。Such an NMOSFET Poly-Si
Introducing N + type impurities into the gate electrode,
C in which P + type impurities are introduced into the Poly-Si gate electrode of
MOS, that is, a so-called dual gate structure CM in which gate electrodes of different conductivity types are formed on the same semiconductor substrate
The OS is manufactured by the following method, for example.

【０００４】まず図８に示すごとくＬＯＣＯＳ法により
素子分離領域５３が形成されたシリコン（Ｓｉ）基板５
４上に、Poly−Ｓｉ膜からなるゲート電極５５のパター
ンを形成する。次いで、ＮＭＯＳＦＥＴ５１の形成予定
領域におけるゲート電極５５のパターンにＮ型不純物
を、またＰＭＯＳＦＥＴ５２の形成予定領域におけるゲ
ート電極５５のパターンにＰ型不純物を、例えばイオン
注入法で打ち分けて導入する。このとき同時に、ＮＭＯ
ＳＦＥＴ５１の形成予定領域、ＰＭＯＳＦＥＴ５２の形
成予定領域のそれぞれのＳｉ基板５４にも、Ｎ型、Ｐ型
不純物を導入する。First, as shown in FIG. 8, a silicon (Si) substrate 5 having an element isolation region 53 formed by a LOCOS method.
A pattern of the gate electrode 55 made of a Poly-Si film is formed on the surface 4. Next, an N-type impurity is implanted into the pattern of the gate electrode 55 in the region where the NMOSFET 51 is to be formed, and a P-type impurity is implanted into the pattern of the gate electrode 55 in the region where the PMOSFET 52 is to be formed, for example, by ion implantation. At the same time, NMO
N-type and P-type impurities are also introduced into the Si substrate 54 in each of the formation planned region of the SFET 51 and the PMOSFET 52.

【０００５】次にアニール等の高温熱処理を行い、Ｓｉ
基板５４に導入した不純物を活性化してソース領域、ド
レイン領域（以下、ソース／ドレイン領域と記す）５６
を形成するとともに、ゲート電極５５のパターンに導入
したＮ型、Ｐ型不純物を拡散させてＮ+ 型ゲート電極５
５ａとＰ+ 型ゲート電極５５ｂとを形成する。その後、
ゲート電極５５を覆うようにしてＳｉ基板５４上に層間
絶縁膜（図示略）を形成し、次いで各ソース／ドレイン
領域５６に電気的に接続するコンタクト５７と、ゲート
電極５５に電気的に接続するコンタクト５８とを層間絶
縁膜に形成するとともに配線層（図示略）を形成する。Next, high temperature heat treatment such as annealing is performed to form Si.
Source regions and drain regions (hereinafter referred to as source / drain regions) 56 by activating the impurities introduced into the substrate 54.
And the N + and P type impurities introduced in the pattern of the gate electrode 55 are diffused to form the N + type gate electrode 5
5a and a P + type gate electrode 55b are formed. afterwards,
An interlayer insulating film (not shown) is formed on the Si substrate 54 so as to cover the gate electrode 55, and then the contact 57 electrically connected to each source / drain region 56 and the gate electrode 55 are electrically connected. The contact 58 is formed in the interlayer insulating film, and the wiring layer (not shown) is formed.

【０００６】[0006]

【発明が解決しようとする課題】ところが、上記した半
導体装置の製造方法では、ＣＭＯＳを製造する場合に、
Ｎ型のゲート電極とＰ型のゲート電極とを連続した一体
型の構造とすることが困難であるといった課題がある。
すなわち、ＮＭＯＳＦＥＴの形成予定領域、ＰＭＯＳＦ
ＥＴの形成予定領域のゲート電極のパターンに、それぞ
れＮ型、Ｐ型不純物をＣＶＤやイオン注入法で打ち分け
て導入しても、その後の不純物活性化のための高温熱処
理によって、Ｎ型不純物が導入されたゲート電極のパタ
ーンとＰ型不純物が導入されたゲート電極のパターンと
の界面部分において、Ｎ型、Ｐ型不純物が図８中矢印で
示すように相互拡散してしまうのである。However, in the method of manufacturing a semiconductor device described above, when a CMOS is manufactured,
There is a problem in that it is difficult to form an N-type gate electrode and a P-type gate electrode as a continuous and integrated structure.
That is, the NMOSFET formation planned region, the PMOSF
Even if N-type and P-type impurities are separately injected into the pattern of the gate electrode in the region where the ET is to be formed by CVD or ion implantation, the N-type impurities are removed by the high temperature heat treatment for activating the impurities thereafter. At the interface between the introduced gate electrode pattern and the P-type impurity introduced gate electrode pattern, the N-type and P-type impurities interdiffuse as indicated by the arrows in FIG.

【０００７】これらの相互拡散は、特に、ゲート電極が
Poly−Ｓｉ膜とこの上層に形成されたタングステンシリ
サイド（ＷＳｉ2 ）膜とからなるＷ−ポリサイド構造で
ある場合、ＷＳｉ膜中で顕著に起こる。そしてこのよう
な現象が起きると、Ｎ型、Ｐ型不純物が互いに補償し合
って、ゲート電極中の不純物濃度が低下するため、ＭＯ
ＳＦＥＴのしきい値電圧（Threshold Voltage;Ｖth) 、
特に上記界面部分に近いＮＭＯＳＦＥＴ、ＰＭＯＳＦＥ
ＴのＶthが変動してしまうことになる。These inter-diffusions are caused especially by the gate electrode.
In the case of a W-polycide structure composed of a Poly-Si film and a tungsten silicide (WSi 2 ) film formed on the Poly-Si film, this occurs remarkably in the WSi film. When such a phenomenon occurs, the N-type and P-type impurities compensate each other, and the impurity concentration in the gate electrode decreases, so that the MO concentration decreases.
Threshold voltage (Vth) of SFET,
Especially NMOSFET and PMOSFE near the above interface
The Vth of T will change.

【０００８】上記課題を解決する方法として、ＮＭＯＳ
ＦＥＴのゲート電極とＰＭＯＳＦＥＴのゲート電極とを
連続した一体型の構造とせず、物理的に分離して形成
し、高温熱処理後に配線層を介して２つのゲート電極を
電気的に連続させる方法がある。しかしながら、この方
法ではセル面積の増大を招くことになる。またゲート電
極の膜構造を変えて上記相互拡散を抑制する方法なども
提案されているが、その効果はまだ不十分なものであ
る。本発明は上記課題を解決するためになされたもので
あり、セル面積を増加させることなく互いに異なる導電
型の不純物の相互拡散を抑制でき、このことによりしき
い値電圧の変動が小さくかつ微細な半導体装置を製造す
ることができる半導体装置の製造方法と半導体装置とを
提供することを目的としている。As a method for solving the above problems, an NMOS
There is a method in which the gate electrode of the FET and the gate electrode of the PMOSFET are not formed as a continuous and integrated structure but are physically separated from each other, and the two gate electrodes are electrically continuous through the wiring layer after the high temperature heat treatment. . However, this method causes an increase in cell area. Further, a method of suppressing the mutual diffusion by changing the film structure of the gate electrode has been proposed, but the effect is still insufficient. The present invention has been made to solve the above problems, it is possible to suppress the mutual diffusion of impurities of different conductivity types without increasing the cell area, by which the variation of the threshold voltage is small and fine. An object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device capable of manufacturing a semiconductor device.

【０００９】[0009]

【課題を解決するための手段】請求項１の発明に係る半
導体装置の製造方法では、上記課題を解決するために、
まず第１の半導体素子の形成予定領域に、第１導電型の
不純物を導入して第１導電部領域を形成し、かつ第２の
半導体素子の形成予定領域に、第２導電型の不純物を導
入して第２導電部領域を形成することにより、これら第
１導電部領域と第２導電部領域とを電気的に連続させて
なる導電パターンを備えた半導体基体を用意する。次い
で、導電パターンを覆うようにして半導体基体上に層間
絶縁膜を形成し、続いてこの層間絶縁膜に、導電パター
ンに到達する第１コンタクトホールを形成すると同時
に、第１導電部領域と第２導電部領域との界面部分の直
上位置に第２コンタクトホールを形成する。次に、第１
コンタクトホールを覆い、かつ第２コンタクトホールを
露出させて層間絶縁膜上にレジスト膜を形成し、その
後、エッチングによって第２コンタクトホール直下位置
に第１導電部領域と第２導電部領域とを分離する孔を形
成する。その後、熱処理によって第１導電部領域に第１
導電型の不純物を拡散させて第１導電部を得るととも
に、第２導電部領域に第２導電型の不純物を拡散させて
第２導電部を得る。そして、第１コンタクトホールの内
面と孔の内面とをそれぞれ配線材料膜で覆い、第１導電
部と第２導電部とを電気的に連続させる。In order to solve the above-mentioned problems, in the method of manufacturing a semiconductor device according to the invention of claim 1,
First, an impurity of the first conductivity type is introduced into a region in which the first semiconductor element is to be formed to form a first conductive portion region, and an impurity of the second conductivity type is included in a region in which the second semiconductor element is to be formed. By introducing and forming the second conductive portion region, a semiconductor substrate having a conductive pattern formed by electrically connecting the first conductive portion region and the second conductive portion region is prepared. Then, an interlayer insulating film is formed on the semiconductor substrate so as to cover the conductive pattern, and subsequently, a first contact hole reaching the conductive pattern is formed in the interlayer insulating film, and at the same time, the first conductive portion region and the second conductive portion region are formed. A second contact hole is formed immediately above the interface with the conductive portion region. Then the first
A resist film is formed on the interlayer insulating film so as to cover the contact hole and expose the second contact hole, and thereafter, the first conductive portion region and the second conductive portion region are separated at a position directly below the second contact hole by etching. To form a hole. Then, a first heat treatment is applied to the first conductive portion region.
The conductive type impurities are diffused to obtain the first conductive portion, and the second conductive type impurities are diffused to the second conductive portion region to obtain the second conductive portion. Then, the inner surface of the first contact hole and the inner surface of the hole are covered with a wiring material film, respectively, to electrically connect the first conductive portion and the second conductive portion.

【００１０】請求項２の発明に係る半導体装置では、第
１の半導体素子の第１導電部と第２半導体素子の第２導
電部との間に、この第１導電部と第２導電部とを分離す
る状態で孔が形成されているとともに、孔の内面を覆う
ようにして配線材料膜が形成されており、さらにこの配
線材料膜が、第１導電部と第２導電部との拡散係数より
も小さい拡散係数を有する材料からなることを上記課題
の解決手段としている。In the semiconductor device according to the second aspect of the present invention, the first conductive portion and the second conductive portion are provided between the first conductive portion of the first semiconductor element and the second conductive portion of the second semiconductor element. And the wiring material film is formed so as to cover the inner surface of the hole. Further, the wiring material film has a diffusion coefficient between the first conductive portion and the second conductive portion. A material having a smaller diffusion coefficient is used as a means for solving the above problems.

【００１１】請求項３の発明に係る半導体装置の製造方
法では、上記課題を解決するために、まず第１の半導体
素子の形成予定領域に、第１導電型の不純物を導入して
なる下層膜と、金属または金属化合物からなるとともに
下層膜上に配設された上層膜とから構成された第１導電
部領域を形成し、かつ第２の半導体素子の形成予定領域
に、第２導電型の不純物を導入してなる下層膜と、金属
または金属化合物からなるとともに下層膜上に配設され
た上層膜とから構成された第２導電部領域を形成するこ
とにより、これら第１導電部領域と第２導電部領域とが
電気的に連続させてなる導電パターンを備えた半導体基
体を用意する。次いで、この導電パターンを覆うように
して半導体基体上に層間絶縁膜を形成し、続いて層間絶
縁膜に、導電パターンに到達する第１コンタクトホール
を形成すると同時に、第１導電部領域と第２導電部領域
との界面部分の直上位置に第２コンタクトホールを形成
する。次いで、エッチングによって第２コンタクトホー
ル直下位置に第１導電部領域の上層膜と第２導電部領域
の上層膜とを分離する孔を形成する。その後、熱処理に
よって第１導電部領域に第１導電型の不純物を拡散させ
て第１導電部を得るとともに、第２導電部領域に第２導
電型の不純物を拡散させて第２導電部を得る。そして、
第１コンタクトホールの内面と孔の内面とをそれぞれ配
線材料膜で覆い、第１導電部の上層膜と第２導電部の上
層膜とを電気的に連続させる。In the method of manufacturing a semiconductor device according to a third aspect of the present invention, in order to solve the above problems, first, a lower layer film is formed by introducing an impurity of the first conductivity type into a region where a first semiconductor element is to be formed. And an upper layer film made of a metal or a metal compound and disposed on the lower layer film, the first conductive portion region is formed, and the second conductive type region is formed in the region where the second semiconductor element is to be formed. By forming a second conductive portion region composed of a lower layer film into which impurities are introduced and an upper layer film made of a metal or a metal compound and provided on the lower layer film, these first conductive portion regions are formed. A semiconductor substrate having a conductive pattern electrically connected to the second conductive portion region is prepared. Then, an interlayer insulating film is formed on the semiconductor substrate so as to cover the conductive pattern, and then a first contact hole reaching the conductive pattern is formed in the interlayer insulating film, and at the same time, the first conductive portion region and the second conductive portion region are formed. A second contact hole is formed immediately above the interface with the conductive portion region. Then, a hole for separating the upper layer film of the first conductive portion region and the upper layer film of the second conductive portion region is formed immediately below the second contact hole by etching. Then, by heat treatment, the first conductive type impurity is diffused into the first conductive portion region to obtain the first conductive portion, and the second conductive type impurity is diffused into the second conductive portion region to obtain the second conductive portion. . And
The inner surface of the first contact hole and the inner surface of the hole are respectively covered with a wiring material film, and the upper layer film of the first conductive portion and the upper layer film of the second conductive portion are electrically continuous.

【００１２】請求項４の発明に係る半導体装置では、第
１導電型の下層膜と、金属または金属化合物からなると
ともにその下層膜上に配設された上層膜とから構成され
た第１導電部と、第１導電部の下層膜と同一の導電材料
で形成された第２導電型の下層膜と、金属または金属化
合物からなるとともにその下層膜上に配設された上層膜
とから構成された第２導電部とを備え、第１導電部と第
２導電部との間に、第１導電部の上層膜と第２導電部の
上層膜とを分離する状態で孔が形成されているととも
に、孔の内面を覆うようにして配線材料膜が形成されて
おり、さらに配線材料膜が、第１導電部と第２導電部と
の拡散係数よりも小さい拡散係数を有する材料からなる
ことを上記課題の解決手段としている。According to another aspect of the semiconductor device of the present invention, the first conductive portion includes a lower layer film of the first conductivity type and an upper layer film made of a metal or a metal compound and disposed on the lower layer film. And a second conductive type lower layer film formed of the same conductive material as that of the lower conductive layer of the first conductive portion, and an upper layer film made of a metal or a metal compound and disposed on the lower layer film. A second conductive portion, and a hole is formed between the first conductive portion and the second conductive portion in a state of separating the upper layer film of the first conductive portion and the upper layer film of the second conductive portion. The wiring material film is formed so as to cover the inner surface of the hole, and the wiring material film is made of a material having a diffusion coefficient smaller than that of the first conductive portion and the second conductive portion. It is used as a solution to the problem.

【００１３】請求項５の発明に係る半導体装置の製造方
法では、上記課題を解決するために、まず、素子分離領
域と、この素子分離領域に囲まれた複数の素子形成予定
領域とからなりかつ素子分離領域の上面位置が素子形成
予定領域の上面位置よりも高い半導体基体の全面に導電
部材料膜を形成する。次いで素子分離領域の上面が露出
する位置まで導電部材料膜を除去して、第１の半導体素
子の形成予定領域に第１導電部領域を形成するととも
に、第２の半導体素子の形成予定領域に第２導電部領域
を形成する。続いて第１導電部領域に第１導電型の不純
物を導入するとともに、第２導電部領域に第２導電型の
不純物を導入する。次いで、熱処理によって、第１導電
部領域に第１導電型の不純物を拡散させるとともに、第
２導電部領域に第２導電型の不純物を拡散させ、その
後、第１導電部領域上と第２導電部領域上に、これら第
１導電部領域と第２導電部領域との間の半導体基体上と
に、第１導電部領域と第２導電部領域とを電気的に連続
させる状態で金属膜または金属化合物膜を形成し、第１
導電部と第２導電部とを得る。In the method of manufacturing a semiconductor device according to the present invention, in order to solve the above-mentioned problems, first, an element isolation region and a plurality of element formation planned regions surrounded by the element isolation region are formed. A conductive part material film is formed on the entire surface of the semiconductor substrate in which the upper surface position of the element isolation region is higher than the upper surface position of the element formation planned region. Then, the conductive part material film is removed to a position where the upper surface of the element isolation region is exposed to form the first conductive part region in the first semiconductor element formation planned region and the second semiconductor element formation planned region. A second conductive portion region is formed. Then, a first conductivity type impurity is introduced into the first conductive part region, and a second conductivity type impurity is introduced into the second conductive part region. Then, by heat treatment, the impurities of the first conductivity type are diffused into the first conductive portion region and the impurities of the second conductivity type are diffused into the second conductive portion region, and thereafter, on the first conductive portion region and the second conductive portion. A metal film in a state in which the first conductive portion region and the second conductive portion region are electrically continuous on the partial region and on the semiconductor substrate between the first conductive portion region and the second conductive portion region. Forming a metal compound film,
A conductive part and a second conductive part are obtained.

【００１４】請求項１に係る半導体装置の製造方法で
は、第１導電部領域と第２導電部領域との界面部分に、
これらの領域を分離する孔を形成し、その後、熱処理を
行うため、第１導電部領域と第２導電部領域との間で不
純物が相互拡散することがない。また第１導電部領域第
２導電部領域とを電気的にかつ物理的に連続させてなる
導電パターンを形成し、これらの領域の界面部分に孔を
形成するので、第１導電部領域と第２導電部領域とを最
初から物理的に分離して形成する場合と異なり、セル面
積の増加が最小限に抑えられる。また第１コンタクトホ
ールの形成と同時に孔を形成するための第２コンタクト
ホールを形成するとともに、第１コンタクトホールを覆
うレジスト膜を形成した後行うエッチングだけで上記孔
を形成し、さらに第１コンタクトホール内面を配線材料
膜で覆うと同時に孔の内面も配線材料膜で覆うことによ
り、第１導電部と第２導電部とを電気的に連続させるの
で、工程が複雑とならない。In the method of manufacturing a semiconductor device according to the first aspect, the interface portion between the first conductive portion region and the second conductive portion region is provided with
Since holes for separating these regions are formed and then heat treatment is performed, impurities do not mutually diffuse between the first conductive portion region and the second conductive portion region. In addition, since a conductive pattern that is electrically and physically continuous with the first conductive portion region and the second conductive portion region is formed and a hole is formed in the interface portion of these regions, the first conductive portion region and the first conductive portion region are formed. Unlike the case where the two conductive part regions are physically separated from the beginning, the increase in cell area can be suppressed to a minimum. At the same time when the first contact hole is formed, a second contact hole for forming the hole is formed, and the hole is formed only by etching after forming a resist film covering the first contact hole. By covering the inner surface of the hole with the wiring material film and simultaneously covering the inner surface of the hole with the wiring material film, the first conductive portion and the second conductive portion are electrically connected, so that the process is not complicated.

【００１５】よって上記方法により得られる請求項２の
発明に係る半導体装置では、その製造に際して行う熱処
理時に、第１導電部領域と第２導電部領域とに導入され
た不純物の相互拡散が防止されるため、それぞれ所定の
導電型の不純物を高濃度に維持した第１導電部と第２導
電部とを備えたものとなる。また第１導電部と第２導電
部とを分離する孔が、これらの導電部間に形成されてい
ることから、セル面積の増加が最小限に抑えられたもの
となる。さらに、孔の内面を覆う配線材料膜は、第１導
電部と第２導電部との拡散係数より小さい拡散係数を有
する材料からなるため、後の工程にて高温熱処理が行わ
れても、その熱処理の際に不純物の相互拡散が起きにく
い。Therefore, in the semiconductor device according to the second aspect of the present invention obtained by the above method, mutual diffusion of impurities introduced into the first conductive portion region and the second conductive portion region is prevented during the heat treatment performed during the manufacturing thereof. Therefore, it is provided with the first conductive portion and the second conductive portion each of which maintains a high concentration of impurities of a predetermined conductivity type. Further, since the holes for separating the first conductive portion and the second conductive portion are formed between these conductive portions, the increase in the cell area is suppressed to the minimum. Further, since the wiring material film covering the inner surface of the hole is made of a material having a diffusion coefficient smaller than that of the first conductive portion and the second conductive portion, even if a high temperature heat treatment is performed in a later step, Mutual diffusion of impurities hardly occurs during heat treatment.

【００１６】請求項３の発明に係る半導体装置の製造方
法では、第１導電部領域と第２導電部領域との界面部分
に、これらの領域の上層膜を分離する孔を形成し、その
後、熱処理を行うことから、第１導電部領域と第２導電
部領域との不純物が上層膜中で相互拡散することがな
い。例えば上層膜が下層膜よりも拡散係数が大きく、し
たがって拡散速度の速い金属膜または金属化合物膜から
なる場合には、上記相互拡散が最小限に抑制される。ま
た請求項１の発明と同様に、セル面積の増加が抑制さ
れ、かつ製造工程が簡易であるという作用が得られる。In the method of manufacturing a semiconductor device according to the third aspect of the present invention, a hole is formed at the interface between the first conductive portion region and the second conductive portion region to separate the upper layer film of these regions, and thereafter, Since the heat treatment is performed, impurities in the first conductive portion region and the second conductive portion region do not mutually diffuse in the upper layer film. For example, when the upper layer film has a diffusion coefficient larger than that of the lower layer film and therefore is made of a metal film or a metal compound film having a high diffusion rate, the above mutual diffusion is suppressed to a minimum. Further, similar to the invention of claim 1, it is possible to obtain an effect that an increase in cell area is suppressed and the manufacturing process is simple.

【００１７】よって、上記方法により得られる請求項４
の発明に係る半導体装置では、その製造に際して行う熱
処理時に、第１導電部領域の上層膜と第２導電部領域の
上層膜とにおいて不純物の相互拡散が防止されるため、
それぞれ所定の導電型の不純物を高濃度に維持した第１
導電部と第２導電部とを備えたものとなる。また第１導
電部と第２導電部とを分離する孔が、これらの導電部間
に形成されていることから、セル面積の増加が最小限に
抑えられたものとなる。さらに孔の内面を覆う配線材料
膜は、第１導電部と第２導電部との拡散係数より小さい
拡散係数を有する材料からなるため、後の工程にて高温
熱処理が行われても、その熱処理の際に不純物の相互拡
散が起きにくい。Therefore, the method according to claim 4 obtained by the above method.
In the semiconductor device according to the invention described above, since mutual diffusion of impurities is prevented in the upper layer film of the first conductive portion region and the upper layer film of the second conductive portion region during the heat treatment performed during manufacturing,
Each of which maintains a high concentration of impurities of a predetermined conductivity type
It is provided with a conductive portion and a second conductive portion. Further, since the holes for separating the first conductive portion and the second conductive portion are formed between these conductive portions, the increase in the cell area is suppressed to the minimum. Further, since the wiring material film covering the inner surface of the hole is made of a material having a diffusion coefficient smaller than that of the first conductive portion and the second conductive portion, even if the high temperature heat treatment is performed in a later step, the heat treatment is performed. In that case, mutual diffusion of impurities hardly occurs.

【００１８】請求項５の発明に係る半導体装置の製造方
法では、素子分離領域の上面が露出する位置まで導電部
材料膜を除去することから、導電部材料膜が自己整合的
に、第１の半導体素子の形成予定領域と第２の半導体素
子の形成予定領域とに分離されるので、この分離のため
のリソグラフィ等を行う必要がなく、工程数の増加が最
小限に抑えられる。また導電部材料膜を、第１の半導体
素子の形成予定領域と第２の半導体素子の形成予定領域
とに分離した後に、熱処理を行うため、第１導電部領
域、第２導電部領域に導入された不純物が上記熱処理の
際に、導電部材料膜中で相互拡散することがない。In the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, the conductive material film is removed to the position where the upper surface of the element isolation region is exposed. Since the semiconductor element formation-scheduled region and the second semiconductor element formation-scheduled region are separated, there is no need to perform lithography or the like for this separation, and an increase in the number of steps can be minimized. Further, since the heat treatment is performed after the conductive portion material film is separated into the first semiconductor element formation planned region and the second semiconductor element formation planned region, the conductive portion material film is introduced into the first conductive portion region and the second conductive portion region. The generated impurities do not interdiffuse in the conductive part material film during the heat treatment.

【００１９】[0019]

【発明の実施の形態】以下、本発明に係る半導体装置の
製造方法および半導体装置の実施形態を図面に基づいて
詳しく説明する。本実施形態では、本発明をＮＭＯＳＦ
ＥＴとＰＭＯＳＦＥＴとから構成されるＣＭＯＳに適用
し、本発明における導電部をゲート電極とした場合につ
いて述べる。図１、図２は請求項１の発明に係る半導体
装置の製造方法の一実施形態を工程順に説明する図であ
り、図３は請求項２の発明に係る半導体装置の一実施形
態を示す平面図である。この実施形態においてＣＭＯＳ
を製造するには、まず図１（ａ）〜（ｃ）に示す工程を
行って半導体基体１００を用意する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device manufacturing method and a semiconductor device according to the present invention will be described below in detail with reference to the drawings. In this embodiment, the present invention is applied to the NMOSF.
A case will be described in which the present invention is applied to a CMOS composed of ET and PMOSFET, and the conductive portion in the present invention is used as a gate electrode. 1 and 2 are views for explaining an embodiment of a method for manufacturing a semiconductor device according to the invention of claim 1 in the order of steps, and FIG. 3 is a plan view showing an embodiment of a semiconductor device according to the invention of claim 2. It is a figure. CMOS in this embodiment
1A to 1C, the semiconductor substrate 100 is prepared by performing the steps shown in FIGS.

【００２０】すなわち図１（ａ）に示しように、一般的
なプロセス、例えばＬＯＣＯＳ分離技術により、Ｓｉ基
板１に、本発明の第１の半導体素子となるＰＭＯＳＦＥ
Ｔの形成予定領域（以下、ＰＭＯＳ形成予定領域と記
す）３、本発明の第２の半導体素子となるＮＭＯＳＦＥ
Ｔの形成予定領域（以下、ＮＭＯＳ形成予定領域と記
す）４をそれぞれ囲むようにして素子分離領域２を３０
０ｎｍ程度の厚みに形成する。次に例えば熱酸化法によ
り、ＰＭＯＳ形成予定領域３とＮＭＯＳ形成予定領域４
とのＳｉ基板１表面にそれぞれゲート酸化膜５を１０ｎ
ｍ程度の厚みに形成する。That is, as shown in FIG. 1A, the PMOS FE which is the first semiconductor element of the present invention is formed on the Si substrate 1 by a general process, for example, the LOCOS isolation technique.
A region where T is to be formed (hereinafter referred to as a region where PMOS is to be formed) 3 and an NMOSFE which becomes the second semiconductor element of the present invention
The element isolation region 2 is formed so as to surround each of the regions where T is to be formed (hereinafter referred to as an NMOS formation region) 4 respectively.
It is formed to a thickness of about 0 nm. Next, for example, by a thermal oxidation method, a PMOS formation planned region 3 and an NMOS formation planned region 4 are formed.
And a gate oxide film 5 of 10 n each on the surface of the Si substrate 1
It is formed to a thickness of about m.

【００２１】次いで例えばＣＶＤ法により、Ｓｉ基板１
上に、ゲート電極の下層膜形成用のPoly−Ｓｉ膜６と、
ゲート電極の上層膜形成用のＷＳｉ2 膜７とをこの順に
堆積する。この際、例えばPoly−Ｓｉ膜６を７０ｎｍ程
度の厚みに形成し、ＷＳｉ2膜７を５０ｎｍ程度の厚み
に形成する。なお、上記ゲート酸化膜５の形成工程とPo
ly−Ｓｉ膜６の形成工程との間には、必要に応じて、Ｐ
ＭＯＳ形成予定領域３、ＮＭＯＳ形成予定領域４のＳｉ
基板１にそれぞれ、しきい値調整のためのイオン注入や
ショートチャネル効果を抑制するためのイオン注入、さ
らにチャネルストップを目的としたイオン注入工程を行
う。Then, the Si substrate 1 is formed by, for example, the CVD method.
Poly-Si film 6 for forming the lower layer film of the gate electrode, and
A WSi 2 film 7 for forming an upper layer film of the gate electrode is deposited in this order. At this time, for example, the Poly-Si film 6 is formed with a thickness of about 70 nm, and the WSi 2 film 7 is formed with a thickness of about 50 nm. Note that the gate oxide film 5 formation process and Po
Between the step of forming the ly-Si film 6, if necessary, P
Si in the MOS formation planned region 3 and the NMOS formation planned region 4
Each of the substrates 1 is subjected to ion implantation for adjusting the threshold value, ion implantation for suppressing the short channel effect, and an ion implantation step for the purpose of channel stop.

【００２２】次に、リソグラフィによってパターニング
を行ったレジスト膜８をマスクとし、ＰＭＯＳ形成予定
領域３のPoly−Ｓｉ膜６に、Ｐ型（第１導電型）の不純
物として例えばホウ素イオン（Ｂ+ ) を、イオンエネル
ギーを例えば２０ｋｅＶ、ドーズ量を５×１０15ｃｍ-2
とした条件でイオン注入し、Ｐ+ 型ゲート領域（第１導
電部領域）１０を形成する。その後、レジスト膜８を剥
離する。続いて図１（ｂ）に示すように、リソグラフィ
によりパターニングを行ったレジスト膜９をマスクと
し、ＮＭＯＳ形成予定領域４のPoly−Ｓｉ膜６に、Ｎ型
（第２導電型）の不純物として例えばリンイオン
（Ｐ+ ) を、イオンエネルギーを例えば２０ｋｅＶ、ド
ーズ量を５×１０15ｃｍ-2とした条件でイオン注入し、
Ｎ + 型ゲート領域１１（第２導電部領域）を形成する。
その後、レジスト膜９を剥離する。Next, patterning is performed by lithography.
Scheduled PMOS formation using the resist film 8
Impurity of P type (first conductivity type) is formed on the Poly-Si film 6 in the region 3.
For example, boron ions (B+) Is the ion energy
Gee is, for example, 20 keV, and dose is 5 × 10.Fifteencm-2
Ion implantation under the conditions+Type gate region (first conductor
The electric part area 10 is formed. After that, the resist film 8 is removed.
Let go. Then, as shown in FIG.
The resist film 9 patterned by
The N-type is formed on the Poly-Si film 6 in the NMOS formation planned region 4.
As the (second conductivity type) impurity, for example, phosphorus ions
(P+), The ion energy is, for example, 20 keV,
5 × 10Fifteencm-2Ion implantation under the conditions
N +The type gate region 11 (second conductive portion region) is formed.
Then, the resist film 9 is peeled off.

【００２３】そしてリソグラフィおよびドライエッチン
グにより、Poly−Ｓｉ膜６およびＷＳｉ2 膜７をパター
ニングし、図１（ｃ）に示すように、Ｐ+ 型ゲート領域
１０とＮ+ 型ゲート領域１１とを電気的にかつ物理的に
連続させてなるゲート電極のパターン（導電パターン）
１２を形成する。Then, the Poly-Si film 6 and the WSi 2 film 7 are patterned by lithography and dry etching to electrically connect the P + type gate region 10 and the N + type gate region 11 to each other as shown in FIG. And physically continuous gate electrode pattern (conductive pattern)
12 is formed.

【００２４】こうして半導体基体１００を得た後は、Ｓ
ｉ基板１のＰＭＯＳ形成予定領域３にＰ型不純物をイオ
ン注入し、Ｎ型のＬＤＤ領域（図示略）を形成するとと
もに、Ｓｉ基板１のＮＭＯＳ形成予定領域４にＮ型不純
物をイオン注入し、Ｐ型のＬＤＤ領域（図示略）を形成
する。次いで、例えばＣＶＤ法により、ゲート電極のパ
ターンを覆うようにして半導体基体１００全面に酸化膜
を１５０ｎｍ程度堆積した後、全面をエッチバックし、
ゲート電極のパターン１２の側壁にサイドウォール（図
示略）を形成する。続いて、Ｓｉ基板１のＰＭＯＳ形成
予定領域３とＮＭＯＳ形成予定領域４とにそれぞれ、ソ
ース／ドレイン領域１３（図３参照）を形成するための
Ｐ型不純物、Ｎ型不純物をそれぞれイオン注入し、不純
物導入層１３ａを形成する。After the semiconductor substrate 100 is obtained in this way, S
P-type impurities are ion-implanted into the PMOS formation region 3 of the i substrate 1 to form an N-type LDD region (not shown), and N-type impurities are ion-implanted into the NMOS formation region 4 of the Si substrate 1. A P-type LDD region (not shown) is formed. Then, an oxide film of about 150 nm is deposited on the entire surface of the semiconductor substrate 100 so as to cover the pattern of the gate electrode by, for example, a CVD method, and then the entire surface is etched back.
A sidewall (not shown) is formed on the sidewall of the pattern 12 of the gate electrode. Subsequently, P-type impurities and N-type impurities for forming the source / drain regions 13 (see FIG. 3) are ion-implanted into the PMOS formation planned region 3 and the NMOS formation planned region 4 of the Si substrate 1, respectively. The impurity introduction layer 13a is formed.

【００２５】次いで図２（ｄ）に示すように、ＣＶＤ法
により、ゲート電極のパターン１２を覆うようにして半
導体基体１００上に酸化膜からなる層間絶縁膜１４を３
００ｎｍ程度の厚みに形成し、その後、層間絶縁膜１４
上にレジスト膜１８を形成する。続いてリソグラフィに
よって、レジスト膜１８に、後述する第１コンタクトホ
ール１５、第２コンタクトホール１６および第３コンタ
クトホール１７を形成するための開口１８ａを形成す
る。Then, as shown in FIG. 2D, an interlayer insulating film 14 made of an oxide film is formed on the semiconductor substrate 100 by CVD so as to cover the pattern 12 of the gate electrode.
It is formed to a thickness of about 00 nm, and then the interlayer insulating film 14 is formed.
A resist film 18 is formed on top. Subsequently, an opening 18a for forming a first contact hole 15, a second contact hole 16 and a third contact hole 17 described later is formed in the resist film 18 by lithography.

【００２６】次に、レジスト膜１８をマスクとしたエッ
チングによって、図２（ｅ）に示すように、層間絶縁膜
１４にゲート電極のパターン１２に到達する第１コンタ
クトホール１５を形成すると同時に、Ｐ+ 型ゲート領域
１０とＮ+ 型ゲート領域１１との界面部分１９の直上位
置に界面部分１９に到達する第２コンタクトホール１６
を形成する。また同時に、Ｓｉ基板１の不純物導入層１
３ａに到達する第３コンタクトホール１７を形成する。
なお、図２においてＳｉ基板１に形成されたソース／ド
レイン領域１３形成のための不純物導入層１３ａは、Ｎ
ＭＯＳ形成予定領域４のそれが示されてある。その後、
レジスト膜１８を剥離する。Next, by etching using the resist film 18 as a mask, a first contact hole 15 reaching the pattern 12 of the gate electrode is formed in the interlayer insulating film 14 as shown in FIG. The second contact hole 16 reaching the interface portion 19 at a position directly above the interface portion 19 between the + type gate region 10 and the N + type gate region 11.
To form At the same time, the impurity introduction layer 1 of the Si substrate 1
A third contact hole 17 reaching 3a is formed.
In FIG. 2, the impurity introduction layer 13a for forming the source / drain regions 13 formed on the Si substrate 1 is N
It is shown in the MOS formation planned region 4. afterwards,
The resist film 18 is peeled off.

【００２７】次いで、第１コンタクトホール１５と第３
コンタクトホール１７とを覆い、かつ第２コンタクトホ
ール１６を露出させて層間絶縁膜１４上にレジスト膜２
０を形成する。その後、ドライエッチングによって、図
２（ｆ）に示すように第２コンタクトホール１６の直下
位置に、Ｐ+ 型ゲート領域１０とＮ+ 型ゲート領域１１
とを完全に分離する孔２１、つまりPoly−Ｓｉ膜６およ
びＷＳｉ2 膜７を領域１０、１１毎に分離する孔２１を
形成し、レジスト膜２０を剥離する。Next, the first contact hole 15 and the third
The resist film 2 is formed on the interlayer insulating film 14 so as to cover the contact hole 17 and expose the second contact hole 16.
Form 0. After that, by dry etching, as shown in FIG. 2F, the P + -type gate region 10 and the N + -type gate region 11 are formed immediately below the second contact hole 16.
A hole 21 that completely separates the poly-Si film 6 and the WSi 2 film 7 is formed in each of the regions 10 and 11, and the resist film 20 is peeled off.

【００２８】次に熱処理として、例えば１０００℃、１
０秒の条件の急速加熱アニール（Rapid Tharmal Annea
l; ＲＴＡ）を行って、Ｐ+ 型ゲート領域１０のＰ型不
純物をこのゲート領域１０中に拡散させ、Ｐ+ 型ゲート
電極（第１導電部）２２ａを得る。同時に、Ｎ+ 型ゲー
ト領域１１のＮ型不純物をこのゲート領域１１中に拡散
させ、Ｎ+ 型ゲート電極（第２導電部）２２ｂを得る。
またこの熱処理では、ＰＭＯＳ形成予定領域３とＮＭＯ
Ｓ形成予定領域４とのＳｉ基板１に形成された不純物拡
散層１３ａが活性化され、ソース／ドレイン領域１３が
形成される。Next, as heat treatment, for example, 1000 ° C., 1
Rapid thermal anneal under 0 second condition (Rapid Tharmal Annea
l; RTA) to diffuse the P-type impurities in the P + -type gate region 10 into the gate region 10 to obtain the P + -type gate electrode (first conductive portion) 22a. At the same time, the N-type impurity of the N + -type gate region 11 is diffused into the gate region 11 to obtain the N + -type gate electrode (second conductive portion) 22b.
Further, in this heat treatment, the PMOS formation planned region 3 and the NMO are formed.
The impurity diffusion layer 13a formed in the Si substrate 1 and the S formation planned region 4 are activated, and the source / drain regions 13 are formed.

【００２９】次いで図２（ｇ）に示すように、第１コン
タクトホール１５、孔２１、第３コンタクトホール１７
内面にそれぞれ、Ｐ+ 型ゲート電極２２ａとＮ+ 型ゲー
ト電極２２ｂとの拡散係数より小さい、つまりPoly−Ｓ
ｉ膜６およびＷＳｉ2 膜７の拡散係数より小さい拡散係
数を有する材料からなる配線材料膜２３を形成する。Then, as shown in FIG. 2G, the first contact hole 15, the hole 21, and the third contact hole 17 are formed.
The inner surface has a diffusion coefficient smaller than that of the P + type gate electrode 22a and the N + type gate electrode 22b, that is, Poly-S.
A wiring material film 23 made of a material having a diffusion coefficient smaller than that of the i film 6 and the WSi 2 film 7 is formed.

【００３０】ここでは第１コンタクトホール１５、孔２
１、第３コンタクトホール１７内面を覆うようにして層
間絶縁膜１４上にチタン（Ｔｉ）を５０ｎｍ程度、窒化
チタン（ＴｉＮ）を１００ｎｍ程度この順に堆積してバ
リアメタル２３ａを形成し、さらにバリアメタル２３ａ
上に第１コンタクトホール１５、孔２１、第３コンタク
トホール１７内を埋め込むようにしてタングステン
（Ｗ）膜２３ｂを堆積する。そして、層間絶縁膜１４の
上面が露出する位置までエッチバックして、第１コンタ
クトホール１５、孔２１、第３コンタクトホール１７内
をバリアメタル２３ａとＷ膜２３ｂとからなる配線材料
膜２３で埋め込む。Here, the first contact hole 15 and the hole 2
1. Titanium (Ti) of about 50 nm and titanium nitride (TiN) of about 100 nm are deposited in this order on the interlayer insulating film 14 so as to cover the inner surface of the third contact hole 17 to form the barrier metal 23a. 23a
A tungsten (W) film 23b is deposited on the first contact hole 15, the hole 21, and the third contact hole 17 so as to be embedded therein. Then, etching back is performed to a position where the upper surface of the interlayer insulating film 14 is exposed, and the first contact hole 15, the hole 21, and the third contact hole 17 are filled with the wiring material film 23 including the barrier metal 23a and the W film 23b. .

【００３１】孔２１内の埋め込みによって、Ｐ+ 型ゲー
ト電極２２ａとＮ+ 型ゲート電極２２ｂとが電気的に連
続してなるゲート電極２２が形成される。また、第１コ
ンタクトホール１５内の埋め込みによって、ゲート電極
２２に電気的に通じるコンタクト２５が形成され、第３
コンタクトホール１７内の埋め込みによって、ソース／
ドレイン領域１３に電気的に通じるコンタクト２６が形
成される。さらに、層間絶縁膜１４上に配線材料となる
アルミニウム（Ａｌ）膜を成膜し、リソグラフィとエッ
チングとによってＡｌからなる配線２７を形成する。そ
の後は、従来の半導体装置の製造と同様にして、上層の
層間絶縁膜や配線、コンタクトホールを形成し、さらに
電極の形成やシンタリング処理等を行う。By filling the inside of the hole 21, the gate electrode 22 in which the P + type gate electrode 22a and the N + type gate electrode 22b are electrically continuous is formed. In addition, the contact 25 electrically connected to the gate electrode 22 is formed by filling the first contact hole 15 with the third contact hole 15.
By embedding in the contact hole 17, the source /
A contact 26 electrically connected to the drain region 13 is formed. Further, an aluminum (Al) film as a wiring material is formed on the interlayer insulating film 14, and the wiring 27 made of Al is formed by lithography and etching. After that, the upper interlayer insulating film, the wiring, and the contact hole are formed, and the formation of the electrode and the sintering process are performed in the same manner as in the conventional manufacturing of a semiconductor device.

【００３２】以上の工程により、図２（ｇ）および図３
に示すごとく半導体基体１００に、Ｐ+ 型ゲート電極２
２ａを備えたＰＭＯＳＦＥＴ２８とＮ+ 型ゲート電極２
２ｂを備えたＮＭＯＳＦＥＴ２９とが形成され、これに
より請求項２の発明に係る半導体装置の一実施形態とな
るＣＭＯＳ３０が得られる。Through the above steps, FIG. 2G and FIG.
The semiconductor body 100 as shown in, P + -type gate electrode 2
PMOSFET 28 with 2a and N + type gate electrode 2
The NMOSFET 29 including 2b is formed, and thereby the CMOS 30 which is an embodiment of the semiconductor device according to the invention of claim 2 is obtained.

【００３３】上記した実施形態の方法では、Ｐ+ 型ゲー
ト領域１０とＮ+ 型ゲート領域１１との界面部分１９
に、これらの領域１０、１１を完全に分離する孔２１を
形成し、その後、熱処理を行ってそれぞれの領域１０、
１１にＰ型不純物、Ｎ型不純物を拡散させるため、これ
らの不純物がPoly−Ｓｉ膜６中、ＷＳｉ2 膜７中で相互
拡散するのを確実に防止することができる。よって相互
拡散により、Ｎ型、Ｐ型不純物が互いに補償し合うのを
防止することができることから、所定の導電型の不純物
を高濃度に維持したＰ+ 型ゲート電極２２ａ、Ｎ+ 型ゲ
ート電極２２ｂを形成することができるので、ＰＭＯＳ
ＦＥＴ２８、ＮＭＯＳＦＥＴ２９のしきい値電圧の小さ
いデュアルゲート構造のＣＭＯＳ３０を製造することが
できる。In the method of the above embodiment, the interface portion 19 between the P + type gate region 10 and the N + type gate region 11 is formed.
A hole 21 that completely separates the regions 10 and 11 from each other, and then heat treatment is performed to form each of the regions 10 and 11.
Since P-type impurities and N-type impurities are diffused in 11, it is possible to reliably prevent these impurities from interdiffusing in the Poly-Si film 6 and the WSi 2 film 7. Therefore, it is possible to prevent the N-type and P-type impurities from compensating each other by the mutual diffusion. Therefore, the P + -type gate electrode 22a and the N + -type gate electrode 22b in which the impurities of a predetermined conductivity type are maintained at a high concentration Can be formed so that the PMOS
It is possible to manufacture a CMOS 30 having a dual gate structure in which the threshold voltages of the FET 28 and the NMOSFET 29 are small.

【００３４】また、Ｐ+ 型ゲート領域１０とＮ+ 型ゲー
ト領域１１とを電気的にかつ物理的に連続させてなるゲ
ート電極のパターン１２を形成し、これらの領域１０、
１１の界面部分１９に孔２１を形成するので、つまり従
来のように、Ｐ+ 型ゲート領域とＮ+ 型ゲート領域とを
物理的に分離した状態で形成しないので、セル面積の増
加を最小限に抑えることができる。しかも、第１コンタ
クトホール１５および第３コンタクトホール１７の形成
と同時に、上記孔２１を形成するための第２コンタクト
ホール１６を形成することができるとともに、上記孔２
１を、第１コンタクトホール１５および第３コンタクト
ホール１７を覆うレジスト膜２０を形成した後、エッチ
ングを行うだけで形成できるので、簡易にかつわずかな
工程数の増加で形成することができる。Further, a gate electrode pattern 12 is formed by electrically and physically connecting the P + -type gate region 10 and the N + -type gate region 11, and these regions 10,
Since the hole 21 is formed in the interface portion 19 of the cell 11, that is, the P + -type gate region and the N + -type gate region are not physically separated from each other unlike the conventional case, the increase of the cell area is minimized. Can be suppressed to Moreover, the second contact hole 16 for forming the hole 21 can be formed at the same time when the first contact hole 15 and the third contact hole 17 are formed, and the hole 2 can be formed.
1 can be formed simply by performing etching after forming the resist film 20 covering the first contact hole 15 and the third contact hole 17, so that it can be formed easily and with a slight increase in the number of steps.

【００３５】さらに第１コンタクトホール１５および第
３コンタクトホール１７への配線材料膜２３の埋め込み
と同時に孔２１内に配線材料膜２３を埋め込むことがで
き、このことによりＰ+ 型ゲート電極２２ａとＮ+ 型ゲ
ート電極２２ｂとを電気的に連続させることができるの
で、工程が複雑とならない。また、このような方法によ
り得られたＣＭＯＳ３０は、不純物を高濃度に維持した
Ｐ+ 型ゲート電極２２ａとＮ+ 型ゲート電極２２ｂとを
備え、かつセル面積の増加が最小限に抑えられたものと
なるので、ＰＭＯＳＦＥＴ２８、ＮＭＯＳＦＥＴ２９の
しきい値変動が小さく、微細な装置となる。Furthermore, the wiring material film 23 can be buried in the hole 21 at the same time when the wiring material film 23 is buried in the first contact hole 15 and the third contact hole 17, whereby the P + type gate electrodes 22a and N are formed. Since the + type gate electrode 22b can be electrically continuous, the process is not complicated. Further, the CMOS 30 obtained by such a method is provided with a P + type gate electrode 22a and an N + type gate electrode 22b in which impurities are maintained at a high concentration, and an increase in cell area is suppressed to a minimum. Therefore, the threshold variation of the PMOSFET 28 and the NMOSFET 29 is small, and the device becomes a fine device.

【００３６】さらにＣＭＯＳ３０では、Ｐ+ 型ゲート電
極２２ａとＮ+ 型ゲート電極２２ｂとを接続する配線材
料膜２３が、Ｐ+ 型ゲート電極２２ａとＮ+ 型ゲート電
極２２ｂとの拡散係数より小さい拡散係数を有する材料
からなることから、たとえ後の工程にて高温熱処理が行
われても、Ｐ+ 型ゲート電極２２ａとＮ+ 型ゲート電極
２２ｂとの間で不純物の相互拡散が起きにくいので、安
定したしきい値を有するものとなる。Furthermore the CMOS30, the P + -type gate electrode 22a and the N + -type gate electrode 22b and the wiring material film 23 for connecting the diffusion coefficient smaller than the diffusion of the P + -type gate electrode 22a and the N + -type gate electrode 22b Since it is made of a material having a coefficient, even if a high temperature heat treatment is performed in a later step, mutual diffusion of impurities is unlikely to occur between the P + type gate electrode 22a and the N + type gate electrode 22b. Will have the threshold value set.

【００３７】次に、請求項３の発明に係る半導体装置の
製造方法の一実施形態を図４を用いて説明する。なお、
図において上記実施形態と同一の形成要素には同一の符
号を付すこととする。この実施形態において、上記実施
形態と相違するのは、Ｐ+ 型ゲート領域１０とＮ+ 型ゲ
ート領域１１との界面部分１９に形成する孔３１が、こ
れらの領域１０、１１を構成するPoly−Ｓｉ膜６とＷＳ
ｉ2 膜７とのうち、上層膜のＷＳｉ2膜７のみを分離す
るように形成する点である。Next, an embodiment of a method of manufacturing a semiconductor device according to the invention of claim 3 will be described with reference to FIG. In addition,
In the figure, the same reference numerals are given to the same forming elements as those in the above-described embodiment. In this embodiment, the difference from the above embodiment is that the holes 31 formed in the interface portion 19 between the P + type gate region 10 and the N + type gate region 11 form the Poly- type which forms these regions 10 and 11. Si film 6 and WS
The point is that only the upper layer film WSi 2 film 7 of the i 2 film 7 is formed so as to be separated.

【００３８】すなわち、図１（ａ）から図２（ｄ）ま
で、上記実施形態と同様の工程を行い、レジスト膜１８
に開口１８ａを形成した後、レジスト膜１８をマスクと
したエッチングによって、第１コンタクトホール１５、
第２コンタクトホール１６および第３コンタクトホール
１７を形成し、レジスト膜１８を剥離する。次いで第３
コンタクトホール１７を覆い、かつ第１コンタクトホー
ル１５と第２コンタクトホール１６とを露出させて層間
絶縁膜１４上にレジスト膜（図示略）を形成する。That is, steps similar to those in the above-described embodiment are performed from FIG. 1A to FIG.
After the opening 18a is formed in the first contact hole 15, etching is performed using the resist film 18 as a mask,
The second contact hole 16 and the third contact hole 17 are formed, and the resist film 18 is peeled off. Then the third
A resist film (not shown) is formed on the interlayer insulating film 14 so as to cover the contact hole 17 and expose the first contact hole 15 and the second contact hole 16.

【００３９】続いて図４（ｅ）に示すように、層間絶縁
膜１４をマスクとしたドライエッチングによって、第２
コンタクトホール１６の直下位置に、つまり界面部分１
９に、Ｐ+ 型ゲート領域１０のＷＳｉ2 膜７とＮ+ 型ゲ
ート領域１１のＷＳｉ2 膜７とを分離する孔３１を形成
する。このとき、第１コンタクトホール１５の直下位置
のＷＳｉ2 膜７もエッチングされ、第１コンタクトホー
ル１５に連続するコンタクトホール３２が形成される。
その後、レジスト膜を剥離する。Then, as shown in FIG. 4E, a second etching process is performed by dry etching using the interlayer insulating film 14 as a mask.
Directly below the contact hole 16, that is, the interface portion 1
A hole 31 for separating the WSi 2 film 7 in the P + type gate region 10 and the WSi 2 film 7 in the N + type gate region 11 is formed in the substrate 9. At this time, the WSi 2 film 7 immediately below the first contact hole 15 is also etched, and the contact hole 32 continuous with the first contact hole 15 is formed.
Then, the resist film is peeled off.

【００４０】そして、この後は上記実施形態と同様の工
程を経る。すなわち、熱処理としてＲＴＡを行って、Ｐ
+ 型ゲート電極２２ａを得ると同時に、Ｎ+ 型ゲート電
極２２ｂを得、かつソース／ドレイン領域１３を形成す
る。次いで図４（ｆ）に示すように、第１コンタクトホ
ール１５およびこれに連続するコンタクトホール３２、
孔３１、第３コンタクトホール１７内をバリアメタル２
３ａとＷ膜２３ｂとからなる配線材料膜２３で埋め込
む。After that, the same steps as those in the above embodiment are performed. That is, RTA is performed as heat treatment, and P
At the same time as the + type gate electrode 22a is obtained, the N + type gate electrode 22b is obtained and the source / drain regions 13 are formed. Next, as shown in FIG. 4F, the first contact hole 15 and the contact hole 32 continuous with the first contact hole 15,
The barrier metal 2 is formed in the hole 31 and the third contact hole 17.
The wiring material film 23 including 3a and the W film 23b is embedded.

【００４１】孔３１内の埋め込みによって、Ｐ+ 型ゲー
ト電極２２ａのＷＳｉ2 膜７とＮ+型ゲート電極２２ｂ
のＷＳｉ2 膜７とが電気的に連続してなるゲート電極２
２が得られ、また第１コンタクトホール１５およびコン
タクトホール２３内、第３コンタクトホール１７内の埋
め込みによってコンタクト２５、２６が形成される。そ
して図４（ｇ）に示すように、層間絶縁膜１４上にＡｌ
からなる配線２７を形成し、さらに上層の層間絶縁膜や
配線、コンタクトホールの形成、電極の形成やシンタリ
ング処理等を行う。By embedding in the hole 31, the WSi 2 film 7 of the P + type gate electrode 22a and the N + type gate electrode 22b are formed.
Gate electrode 2 which is electrically continuous with the WSi 2 film 7 of
2 is obtained, and the contacts 25 and 26 are formed by embedding in the first contact hole 15 and the contact hole 23, and the third contact hole 17. Then, as shown in FIG. 4G, Al is formed on the interlayer insulating film 14.
Is formed, and then an interlayer insulating film and wiring in the upper layer, a contact hole, an electrode, a sintering process, and the like are performed.

【００４２】以上の工程により、図４（ｇ）に示すよう
に、半導体基体１００に、Ｐ+ 型ゲート電極２２ａを備
えたＰＭＯＳＦＥＴ２８とＮ+ 型ゲート電極２２ｂを備
えたＮＭＯＳＦＥＴ２９とが形成され、これにより請求
項４の発明に係る半導体装置の一実施形態となるＣＭＯ
Ｓ３３が得られる。なお、こうして得られたＣＭＯＳ３
３は、前述の実施形態と同様、図３に示す平面構造を有
するものとなる。Through the above steps, as shown in FIG. 4G, the PMOSFET 28 having the P + type gate electrode 22a and the NMOSFET 29 having the N + type gate electrode 22b are formed on the semiconductor substrate 100. According to the present invention, a CMO which is an embodiment of a semiconductor device according to the invention of claim 4
S33 is obtained. The CMOS3 thus obtained
3 has the planar structure shown in FIG. 3 as in the above-described embodiment.

【００４３】上記した実施形態の方法では、Ｐ+ 型ゲー
ト領域１０とＮ+ 型ゲート領域１１との界面部分１９
に、これらの領域１０、１１のＷＳｉ2 膜７を分離する
孔３１を形成し、その後、熱処理を行ってそれぞれの領
域１０、１１にＰ型不純物、Ｎ型不純物を拡散させるの
で、不純物がＷＳｉ2 膜７中で相互拡散するのを確実に
防止することができる。前述したように、Ｐ+ 型ゲート
領域１０とＮ+ 型ゲート領域１１とにおける不純物の相
互拡散は、Poly−Ｓｉ膜６に比較して拡散係数が大き
く、したがって拡散速度の速いＷＳｉ2 膜７に特に顕著
に起こるため、このようにＷＳｉ2 膜７中での不純物の
相互拡散を防止できることにより、Ｎ型、Ｐ型不純物が
互いに補償し合うのを最小限に抑制することができる。
よって、ＰＭＯＳＦＥＴ２８、ＮＭＯＳＦＥＴ２９のし
きい値電圧の小さいＣＭＯＳ３３を製造することができ
る。In the method of the above embodiment, the interface portion 19 between the P + type gate region 10 and the N + type gate region 11 is formed.
At this time, a hole 31 for separating the WSi 2 film 7 in these regions 10 and 11 is formed, and then heat treatment is performed to diffuse P-type impurities and N-type impurities into the regions 10 and 11, respectively. It is possible to reliably prevent mutual diffusion in the two films 7. As described above, the mutual diffusion of impurities in the P + type gate region 10 and the N + type gate region 11 has a larger diffusion coefficient than that of the Poly-Si film 6, and thus the WSi 2 film 7 having a high diffusion rate. Since it occurs particularly remarkably, the mutual diffusion of the impurities in the WSi 2 film 7 can be prevented in this way, so that the N-type and P-type impurities can be suppressed from compensating each other to a minimum.
Therefore, the CMOS 33 having a small threshold voltage of the PMOSFET 28 and the NMOSFET 29 can be manufactured.

【００４４】しかも前述した実施形態と同様、セル面積
の増大を防止でき、かつ製造工程が簡易である等の効果
を得ることができる。また、このような方法により得ら
れたＣＭＯＳ３３は、不純物を高濃度に維持したＰ+ 型
ゲート電極２２ａとＮ+ 型ゲート電極２２ｂとを備え、
かつセル面積の増加が最小限に抑えられたものとなるの
で、ＰＭＯＳＦＥＴ２８、ＮＭＯＳＦＥＴ２９のしきい
値変動が小さく、微細な装置となる。Moreover, similar to the above-described embodiment, it is possible to obtain an effect that the cell area can be prevented from increasing and the manufacturing process is simple. Further, the CMOS 33 obtained by such a method includes a P + type gate electrode 22a and an N + type gate electrode 22b in which impurities are maintained at a high concentration,
In addition, since the increase in cell area is suppressed to a minimum, the threshold variation of the PMOSFET 28 and the NMOSFET 29 is small, and the device is fine.

【００４５】さらにＣＭＯＳ３０においても、配線材料
膜２３がＰ+ 型ゲート電極２２ａとＮ+ 型ゲート電極２
２ｂとの拡散係数より小さい拡散係数を有する材料から
なることから、たとえ後の工程にて高温熱処理が行われ
ても不純物の相互拡散が起きにくく、安定したしきい値
を有するものとなる。Further, also in the CMOS 30, the wiring material film 23 has the P + type gate electrode 22a and the N + type gate electrode 2
Since it is made of a material having a diffusion coefficient smaller than that of 2b, even if a high temperature heat treatment is performed in a later step, mutual diffusion of impurities hardly occurs, and a stable threshold value is obtained.

【００４６】なお、上記２つの実施形態では、本発明に
おける導電部がゲート電極である場合について説明した
が、これに限定されるものではなく配線層であってもよ
いのはもちろんである。また本発明における配線材料膜
が、Ｔｉ膜、ＴｉＮ膜およびＷＳｉ2 膜からなる場合に
ついて述べたが、配線材料膜は第１導電部と第２導電部
との拡散係数よりも小さい拡散係数を有する材料からな
る膜であればよく、上記例に限定されない。例えばチタ
ンシリサイド（ＴｉＳｉ2 ）、酸窒化チタン（ＴｉＯ
Ｎ）、コバルト（Ｃｏ）、コバルトシリサイド（ＣｏＳ
ｉ2 ）、タングステン（Ｗ）、窒化タングステン（Ｔｉ
Ｗ）等の高融点金属膜を単層で、またはそれらを積層し
た膜を用いることもできる。In the above two embodiments, the case where the conductive portion in the present invention is the gate electrode has been described, but the present invention is not limited to this and may be a wiring layer. The case where the wiring material film in the present invention is made of a Ti film, a TiN film and a WSi 2 film has been described, but the wiring material film has a diffusion coefficient smaller than that of the first conductive portion and the second conductive portion. The film is not limited to the above example as long as it is a film made of a material. For example, titanium silicide (TiSi 2 ), titanium oxynitride (TiO 2
N), cobalt (Co), cobalt silicide (CoS
i 2 ), tungsten (W), tungsten nitride (Ti
A high melting point metal film such as W) may be used as a single layer or a film obtained by stacking them.

【００４７】また上記実施形態では、第１導電部、第２
導電部の上層膜としてＷＳｉ2 膜を形成した場合につい
て説明したが、他の高融点金属シリサイド等の金属化合
物膜であってもよく、またＷＳｉ2 膜を金属膜に替える
こともできる。In the above embodiment, the first conductive portion and the second conductive portion
Although the case where the WSi 2 film is formed as the upper layer film of the conductive portion has been described, it may be a metal compound film such as another refractory metal silicide, or the WSi 2 film may be replaced with a metal film.

【００４８】次に、請求項５の発明に係る半導体装置の
製造方法の一実施形態を図５および図６を用いて説明す
る。なお、図５および図６において、（ロ）は平面図、
（イ）は（ロ）におけるＡ−Ａ線矢視断面図、（ハ）は
（ロ）におけるＢ−Ｂ線矢視断面図である。また、図５
および図６において上記実施形態と同一の形成要素には
同一の符号を付すこととする。Next, an embodiment of a method of manufacturing a semiconductor device according to the invention of claim 5 will be described with reference to FIGS. 5 and 6, (B) is a plan view,
(A) is a sectional view taken along the line AA of (B), and (C) is a sectional view taken along the line B-B of (B). Also, FIG.
In addition, in FIG. 6, the same forming elements as those in the above-described embodiment are denoted by the same reference numerals.

【００４９】この実施形態においてＣＭＯＳを製造する
には、まず素子分離技術を用いて、素子分離領域と、素
子分離領域に囲まれた複数の素子形成予定領域とからな
る半導体基体を形成する。この際、素子分離領域の上面
位置が、素子形成予定領域の上面位置よりも高くなるよ
うに半導体基体を形成する。ここでは、図５（ａ）に示
すように、例えばＬＯＣＯＳ分離技術により、Ｓｉ基板
１にＰＭＯＳ形成予定領域３、ＮＭＯＳ形成予定領域４
をそれぞれ囲むようにして素子分離領域２を形成し、半
導体基体４０を得る。このＬＯＣＯＳ分離技術により、
素子分離領域２の上面位置は、ＰＭＯＳ形成予定領域
３、ＮＭＯＳ形成予定領域４の上面位置よりも、例えば
１００ｎｍ〜２００ｎｍ程度高く設定される。In order to manufacture the CMOS in this embodiment, first, a semiconductor substrate including an element isolation region and a plurality of element formation planned regions surrounded by the element isolation region is formed by using the element isolation technique. At this time, the semiconductor substrate is formed such that the upper surface position of the element isolation region is higher than the upper surface position of the element formation planned region. Here, as shown in FIG. 5A, the PMOS formation scheduled region 3 and the NMOS formation scheduled region 4 are formed on the Si substrate 1 by, for example, the LOCOS isolation technique.
The element isolation region 2 is formed so as to surround each of the above, and the semiconductor substrate 40 is obtained. With this LOCOS separation technology,
The upper surface position of the element isolation region 2 is set higher than the upper surface positions of the PMOS formation planned region 3 and the NMOS formation planned region 4 by, for example, about 100 nm to 200 nm.

【００５０】次に図５（ｂ）に示すように、ＰＭＯＳ形
成予定領域３とＮＭＯＳ形成予定領域４とのＳｉ基板１
表面にそれぞれゲート酸化膜５を形成し、続いてＳｉ基
板１上に、本発明の導電部材料膜となるゲート電極の下
層膜形成用のPoly−Ｓｉ膜６を堆積する。なお、図５の
（ロ）では、Poly−Ｓｉ膜６をハッチングで示してあ
る。また、上記ゲート酸化膜５の形成工程とPoly−Ｓｉ
膜６の形成工程との間には、必要に応じて、ＰＭＯＳ形
成予定領域３、ＮＭＯＳ形成予定領域４のＳｉ基板１に
それぞれ、しきい値調整のためのイオン注入やショート
チャネル効果を抑制するためのイオン注入、さらにチャ
ネルストップを目的としたイオン注入工程を行う。Next, as shown in FIG. 5B, the Si substrate 1 including the PMOS formation planned region 3 and the NMOS formation planned region 4 is formed.
A gate oxide film 5 is formed on each surface, and then a Poly-Si film 6 for forming a lower layer film of a gate electrode, which is a conductive part material film of the present invention, is deposited on the Si substrate 1. In addition, in FIG. 5B, the Poly-Si film 6 is shown by hatching. In addition, the step of forming the gate oxide film 5 and Poly-Si
Between the step of forming the film 6, if necessary, the ion implantation for adjusting the threshold and the short channel effect are suppressed in the Si substrate 1 in the PMOS formation planned region 3 and the NMOS formation planned region 4, respectively. And an ion implantation step for the purpose of channel stop are performed.

【００５１】次にＣＭＰ（化学的機械的研磨）技術によ
り、図５（ｃ）に示すように、素子分離領域２の上面が
露出する位置までPoly−Ｓｉ膜６を除去し、半導体基体
４０の表面を平坦化する。この工程により、ＰＭＯＳ形
成予定領域３、ＮＭＯＳ形成予定領域４のＳｉ基板１上
のみにPoly−Ｓｉ膜６が残る。つまり、Poly−Ｓｉ膜６
が自己整合的に、ＰＭＯＳ形成予定領域３とＮＭＯＳ形
成予定領域４とに分離される。次いで、リソグラフィお
よびドライエッチングにより、図５（ｄ）に示すよう
に、Poly−Ｓｉ膜６をゲート電極のパターンに形成し、
トランジスタのゲート長を確定する。Next, the CMP (Chemical Mechanical Polishing) technique is used to remove the Poly-Si film 6 to a position where the upper surface of the element isolation region 2 is exposed, as shown in FIG. Flatten the surface. By this step, the Poly-Si film 6 remains only on the Si substrate 1 in the PMOS formation planned region 3 and the NMOS formation planned region 4. That is, the Poly-Si film 6
Are self-aligned and separated into a PMOS formation planned region 3 and an NMOS formation planned region 4. Then, as shown in FIG. 5D, a Poly-Si film 6 is formed into a gate electrode pattern by lithography and dry etching.
Determine the gate length of the transistor.

【００５２】さらにＳｉ基板１のＰＭＯＳ形成予定領域
３、ＮＭＯＳ形成予定領域４にそれぞれＰ型、Ｎ型不純
物をイオン注入してＬＤＤ領域４１を形成し、その後、
ゲート電極パターン形状のPoly−Ｓｉ膜６の側壁にサイ
ドウォール４２を形成する。続いて、Ｓｉ基板１のＰＭ
ＯＳ形成予定領域３とＮＭＯＳ形成予定領域４とにそれ
ぞれ、ソース／ドレイン領域を形成するためのＰ型不純
物、Ｎ型不純物をそれぞれイオン注入し、不純物拡散層
（図示略）を形成する。このイオン注入では、ＰＭＯＳ
形成予定領域３、ＮＭＯＳ形成予定領域４のゲート電極
パターン形状のPoly−Ｓｉ膜６にもそれぞれ、Ｐ型不純
物、Ｎ型不純物が導入され、Ｐ+ 型ゲート領域４３とＮ
+ 型ゲート領域４４とが形成される。Further, an LDD region 41 is formed by ion-implanting P-type and N-type impurities into the PMOS formation planned region 3 and the NMOS formation planned region 4 of the Si substrate 1, respectively.
Sidewalls 42 are formed on the sidewalls of the poly-Si film 6 having the gate electrode pattern shape. Then, PM of Si substrate 1
P-type impurities and N-type impurities for forming the source / drain regions are ion-implanted into the OS formation planned region 3 and the NMOS formation planned region 4, respectively, to form an impurity diffusion layer (not shown). In this ion implantation, the PMOS
Forming region 3, respectively in Poly-Si film 6 of the gate electrode pattern of the NMOS forming region 4, P-type impurity, the N-type impurity is introduced, P + -type gate region 43 and the N
A + type gate region 44 is formed.

【００５３】次いで、熱処理としてＲＴＡを行って、Ｐ
+ 型ゲート領域４３のＰ型不純物をこのゲート領域４３
中に拡散させると同時に、Ｎ+ 型ゲート領域４４のＮ型
不純物をこのゲート領域４４中に拡散させる。またこの
熱処理では、ＰＭＯＳ形成予定領域３とＮＭＯＳ形成予
定領域４とのＳｉ基板１に形成された不純物拡散層が活
性化され、ソース／ドレイン領域１３が形成される。次
に例えばＣＶＤ法により、半導体基体４０全面にＴｉ膜
を成膜し、続いて６００℃〜７００℃程度の比較的低い
温度で熱処理することによって、Ｔｉ膜の下地のソース
／ドレイン領域１３のＳｉ基板１と各ゲート領域４３、
４４のPoly−Ｓｉ膜６とを反応させ、チタンシリサイド
（ＴｉＳｉ2 ）膜を形成する。Then, RTA is carried out as a heat treatment, and P
The P-type impurities in the + -type gate region 43 are removed from the gate region 43.
At the same time, the N type impurities of the N + type gate region 44 are diffused into the gate region 44. Also, in this heat treatment, the impurity diffusion layers formed in the Si substrate 1 in the PMOS formation planned region 3 and the NMOS formation planned region 4 are activated, and the source / drain regions 13 are formed. Next, a Ti film is formed on the entire surface of the semiconductor substrate 40 by, for example, the CVD method, and then heat treatment is performed at a relatively low temperature of about 600 ° C. to 700 ° C. Substrate 1 and each gate region 43,
The poly-Si film 6 of 44 is reacted to form a titanium silicide (TiSi 2 ) film.

【００５４】その後は、ウエットエッチングによって自
己整合的にＴｉＳｉ2 膜を残すのが一般的であるが、こ
のようにするとＰ+ 型ゲート領域４３とＮ+ 型ゲート領
域４４とが電気的に連続した状態とならない。よって、
Ｐ+ 型ゲート領域４３とＮ+型ゲート領域４４との間の
半導体基体４０上に、Ｐ+ 型ゲート領域４３とＮ+ 型ゲ
ート領域４４とを電気的に連続させる状態でＴｉ膜が残
るように、Ｔｉ膜をウエットエッチングする。ここで
は、Ｐ+ 型ゲート領域４３とＮ+ 型ゲート領域４４との
間と、後の工程で形成するコンタクトの下地となる箇所
とをレジスト膜で覆い、この後にウエットエッチングを
行って、レジスト膜で覆っていない未反応のＴｉ膜を除
去し、ＴｉＳｉ2 膜とレジスト膜で覆った部分のＴｉ膜
を残す。After that, it is general to leave the TiSi 2 film in a self-aligned manner by wet etching. In this case, the P + type gate region 43 and the N + type gate region 44 are electrically continuous. Not in a state. Therefore,
The semiconductor body 40 on between the P + -type gate region 43 and the N + -type gate region 44, so that the Ti film remains in a state in which electrically continuous and P + -type gate region 43 and the N + -type gate region 44 Then, the Ti film is wet-etched. Here, the space between the P + -type gate region 43 and the N + -type gate region 44, and the portion that will be the base of the contact formed in a later step are covered with a resist film, and then wet etching is performed to form a resist film. The unreacted Ti film not covered with is removed, leaving the Ti film covered with the TiSi 2 film and the resist film.

【００５５】こうすることにより、図６（ｅ）に示すよ
うにソース／ドレイン領域１３上の半導体基体４０上
と、Ｐ+ 型ゲート領域４３およびＮ+ 型ゲート領域４４
上とにＴｉＳｉ2 膜４５ａが形成されるとともに、Ｐ+
型ゲート領域４３とＮ+ 型ゲート領域４４との間の半導
体基体４０上にこれらを電気的に接続させるＴｉ膜４５
ｂが形成される。またコンタクトの下地となる箇所に
も、Ｐ+ 型ゲート領域４３およびＮ+ 型ゲート領域４４
上のＴｉＳｉ2 膜４５ａに電気的に連続したＴｉ膜４５
ｂが形成される。そして、Ｐ+ 型のPoly−Ｓｉ膜６とＴ
ｉＳｉ2 膜４５ａとからなるＰ+ 型ゲート電極４６ａ
と、Ｎ+ 型のPoly−Ｓｉ膜６とＴｉＳｉ2 膜４５ａとか
らなるＮ+ 型ゲート電極４６ｂとが得られる。By doing so, as shown in FIG. 6E, the semiconductor substrate 40 on the source / drain regions 13 and the P + type gate regions 43 and the N + type gate regions 44 are formed.
A TiSi 2 film 45a is formed on the upper surface and P +
A Ti film 45 for electrically connecting the type gate region 43 and the N + type gate region 44 to each other on the semiconductor substrate 40.
b is formed. In addition, the P + type gate region 43 and the N + type gate region 44 are also formed on the base of the contact.
A Ti film 45 electrically continuous to the upper TiSi 2 film 45a
b is formed. Then, the P + type Poly-Si film 6 and the T
P + type gate electrode 46a composed of iSi 2 film 45a
And an N + type gate electrode 46b composed of the N + type Poly-Si film 6 and the TiSi 2 film 45a is obtained.

【００５６】その後は、８００℃〜９００℃程度の熱処
理を行って、ＴｉＳｉ2 膜４５ａを低抵抗化し、この後
通常の半導体装置の製造方法と同様、層間絶縁膜や配
線、コンタクトホールの形成、電極の形成やシンタリン
グ処理等を行う。以上の工程によって、Ｐ+ 型ゲート電
極４６ａを備えたＰＭＯＳＦＥＴ４７と、Ｎ+ 型ゲート
電極４６ｂを備えたＮＭＯＳＦＥＴ４８とを有するＣＭ
ＯＳ４９が得られる。After that, a heat treatment at about 800 ° C. to 900 ° C. is performed to reduce the resistance of the TiSi 2 film 45a, and thereafter, the interlayer insulating film, the wiring, and the contact hole are formed in the same manner as in the usual semiconductor device manufacturing method. The formation of electrodes and the sintering process are performed. Through the above steps, the CM having the PMOSFET 47 having the P + type gate electrode 46a and the NMOSFET 48 having the N + type gate electrode 46b
OS49 is obtained.

【００５７】上記した実施形態の方法では、素子分離領
域２の上面が露出する位置までPoly−Ｓｉ膜６を除去す
ることにより、Poly−Ｓｉ膜６を自己整合的に、ＰＭＯ
Ｓ形成予定領域３とＮＭＯＳ形成予定領域４とに分離す
ることができるので、この分離のためのリソグラフィ等
を行う必要がなく、工程数の増加が最小限に抑えられて
工程的に非常に有利となる。In the method of the above-described embodiment, the Poly-Si film 6 is removed to a position where the upper surface of the element isolation region 2 is exposed, so that the Poly-Si film 6 is self-aligned and the PMO is removed.
Since the S formation planned region 3 and the NMOS formation planned region 4 can be separated, it is not necessary to perform lithography or the like for this separation, and the increase in the number of steps is minimized, which is very advantageous in the process. Becomes

【００５８】またPoly−Ｓｉ膜６を、ＰＭＯＳ形成予定
領域３とＮＭＯＳ形成予定領域４とに物理的に分離した
後に、熱処理を行ってＰ+ 型ゲート領域４３、Ｎ+ 型ゲ
ート領域４４にＰ型不純物、Ｎ型不純物を拡散させるた
め、この熱処理の際にこれらの不純物がPoly−Ｓｉ膜６
中で相互拡散するのを確実に防止することができる。よ
って相互拡散により、Ｎ型、Ｐ型不純物が互いに補償し
合うのを防止することができることから、所定の導電型
の不純物を高濃度に維持したＰ+ 型ゲート電極４６ａ、
Ｎ+ 型ゲート電極４６ｂを形成することができるので、
ＰＭＯＳＦＥＴ４７、ＮＭＯＳＦＥＴ４８のしきい値の
変動の小さいＣＭＯＳ４９を製造することができる。Further, after the Poly-Si film 6 is physically separated into the PMOS formation planned region 3 and the NMOS formation planned region 4, the P + type gate region 43 and the N + type gate region 44 are P-typed by heat treatment. -Type impurities and N-type impurities are diffused, so that during the heat treatment, these impurities are not included in the Poly-Si film 6.
It is possible to reliably prevent mutual diffusion in the inside. Therefore, it is possible to prevent the N-type and P-type impurities from compensating each other by the mutual diffusion, so that the P + -type gate electrode 46a in which the impurity of a predetermined conductivity type is maintained at a high concentration,
Since the N + type gate electrode 46b can be formed,
It is possible to manufacture the CMOS 49 in which the threshold fluctuations of the PMOSFET 47 and the NMOSFET 48 are small.

【００５９】また、素子分離領域２の上面位置と、ＰＭ
ＯＳ形成予定領域３、ＮＭＯＳ形成予定領域４の上面位
置との差を利用して、Poly−Ｓｉ膜６を分離しているの
で、セル面積の増加を最小限に抑えることができる。ま
た、ＴｉＳｉ2 膜４５ａ、Ｔｉ膜４５ｂの形成後に、Ｔ
ｉＳｉ2 膜４５ａを低抵抗化するための熱処理を行う
が、この熱処理はそれほど高温でないこと、Ｐ + 型ゲー
ト領域４３とＮ+ 型ゲート領域４４との間に形成される
膜が拡散係数の小さいＴｉ膜４５ｂであること、Ｐ+ 型
ゲート領域４３のPoly−Ｓｉ膜６とＮ+型ゲート領域４
４のPoly−Ｓｉ膜６とが分離状態にあることから、この
熱処理の際の不純物の相互拡散を防止することができ
る。Further, the upper surface position of the element isolation region 2 and PM
Top surface positions of the OS formation planned region 3 and the NMOS formation planned region 4
The Poly-Si film 6 is separated by utilizing the difference between
Thus, the increase in cell area can be minimized. Ma
Titanium2After forming the film 45a and the Ti film 45b, T
iSi2Heat treatment is performed to reduce the resistance of the film 45a.
However, this heat treatment is not so high, P +Type game
Area 43 and N+Formed between the mold gate region 44
The film is a Ti film 45b having a small diffusion coefficient, P+Type
Poly-Si film 6 and N in the gate region 43+Mold gate region 4
Since the Poly-Si film 6 of 4 is in a separated state,
Can prevent mutual diffusion of impurities during heat treatment
You.

【００６０】なお、上記実施形態では、素子分離技術と
してＬＯＣＯＳ分離技術を用いた場合について述べた
が、近年、素子の微細化に伴い検討されている、トレン
チおよび埋め込み技術、ＣＭＰ等の平坦化技術を組み合
わせたトレンチ素子分離技術を用いてもよく、この技術
によっても素子分離領域の上面位置を素子形成予定領域
の上面位置よりも高く形成することができる。また本発
明における導電部がゲート電極である場合について説明
したが、これに限定されるものではなく配線層であって
もよいのはもちろんである。In the above embodiment, the case where the LOCOS isolation technique is used as the element isolation technique has been described, but in recent years, trench and burying techniques, flattening techniques such as CMP, which have been studied along with the miniaturization of elements, have been described. It is also possible to use a trench element isolation technique in which the above are combined, and this technique can also form the upper surface position of the element isolation region higher than the upper surface position of the element formation planned region. Although the case where the conductive portion is the gate electrode has been described in the present invention, the present invention is not limited to this and may be a wiring layer.

【００６１】さらに上記実施形態では、本発明における
第１導電部領域上、第２導電部領域上およびこれらの領
域の間の半導体基体上に、Ｔｉ膜、ＴｉＳｉ2 膜を形成
した場合について説明したが、上記例に限定されず、例
えばＣｏ、Ｗ等の高融点金属からなる金属膜や、ＴｉＳ
ｉ2 、ＣｏＳｉ2 等のＳｉと高融点金属との金属化合物
膜を用いることもできる。Further, in the above embodiment, the case where the Ti film and the TiSi 2 film are formed on the first conductive portion region, the second conductive portion region and the semiconductor substrate between these regions has been described in the present invention. However, the present invention is not limited to the above example, and for example, a metal film made of a refractory metal such as Co or W, or TiS.
It is also possible to use a metal compound film of Si and a refractory metal such as i 2 and CoSi 2 .

【００６２】例えばＷＳｉ2 膜を用いる場合には、半導
体基体４０全面にＷＳｉ2 膜を形成し、次いでＰ+ 型ゲ
ート領域４３、Ｎ+ 型ゲート領域４４、これらの領域４
３、４４間、後の工程で形成するコンタクトの下地とな
る箇所、および必要に応じてソース／ドレイン領域１３
をレジスト膜で覆う。この際、Ｐ+ 型ゲート領域４３、
Ｎ+ 型ゲート領域４４とソース／ドレイン領域１３とが
つながらないようにレジスト膜を形成する。その後、エ
ッチングを行って、レジスト膜で覆っていない部分のＷ
Ｓｉ2 膜を除去する。For example, when the WSi 2 film is used, the WSi 2 film is formed on the entire surface of the semiconductor substrate 40, and then the P + type gate region 43, the N + type gate region 44, and these regions 4 are formed.
3, 44, a portion which will be a base of a contact formed in a later step, and the source / drain region 13 as necessary.
Is covered with a resist film. At this time, the P + type gate region 43,
A resist film is formed so that the N + type gate region 44 and the source / drain region 13 are not connected. After that, etching is performed, and W of the portion not covered with the resist film is etched.
The Si 2 film is removed.

【００６３】図７はＷＳｉ2 膜を用いてＰ+ 型ゲート領
域４３とＮ+ 型ゲート領域４４とを接続した状態を示す
図であり、（ロ）は平面図、（イ）は（ロ）におけるＡ
−Ａ線矢視断面図、（ハ）は（ロ）におけるＢ−Ｂ線矢
視断面図である。図７に示すように上記エッチングによ
って、ソース／ドレイン領域１３上の半導体基体４０上
と、Ｐ+ 型ゲート領域４３およびＮ+ 型ゲート領域４４
上とにＷＳｉ2 膜４５ｃが形成されるとともに、これら
の領域４３、４４との間の半導体基体４０上とに、Ｐ+
型ゲート領域４３上のＷＳｉ2 膜４５ｃおよびＮ+ 型ゲ
ート領域４４のＷＳｉ2 膜４５ｃを電気的に接続させる
ＷＳｉ2 膜４５ｃが形成される。FIG. 7 is a diagram showing a state in which the P + type gate region 43 and the N + type gate region 44 are connected by using a WSi 2 film, (B) is a plan view, and (B) is (B). At A
-A line arrow sectional view, (c) is a BB line arrow sectional view in (b). As shown in FIG. 7, by the above etching, the P + type gate region 43 and the N + type gate region 44 are formed on the semiconductor substrate 40 on the source / drain regions 13.
A WSi 2 film 45c is formed on the semiconductor substrate 40 between these regions 43 and 44, and P +
WSi 2 film 45c to a WSi 2 film 45c of WSi 2 film 45c and the N + -type gate region 44 of the type gate region 43 is electrically connected is formed.

【００６４】なお、この場合もその後、ＷＳｉ2 膜４５
ｃを低抵抗化するための熱処理を行うため、該熱処理の
際にＷＳｉ2 のグレインが成長するが、通常〜７００℃
程度の比較的低温処理であることから、この熱処理の際
の不純物の相互拡散を防止することができる。In this case as well, after that, the WSi 2 film 45 is formed.
Since a heat treatment for reducing the resistance of c is performed, grains of WSi 2 grow during the heat treatment, but the temperature is usually up to 700 ° C.
Since the treatment is performed at a relatively low temperature, the mutual diffusion of impurities during this heat treatment can be prevented.

【００６５】[0065]

【発明の効果】以上説明したように請求項１に係る半導
体装置の製造方法によれば、第１導電部領域と第２導電
部領域との界面部分に、これらの領域を分離する孔を形
成した後に熱処理を行うことから、不純物の相互拡散を
防止でき、第１導電型の不純物、第２導電型の不純物が
補償し合うことを防止できるので、所定の導電型の不純
物を高濃度に維持した第１導電部、第２導電部を得るこ
とができる。また、第１導電部領域と第２導電部領域と
を電気的に連続させてなる導電パターンを形成し、これ
らの領域の界面部分に孔を形成することから、セル面積
の増加を最小限に抑えることができる。さらに第１コン
タクトホールの形成と同時に孔を形成するための第２コ
ンタクトホールを形成でき、かつ第１コンタクトホール
内面を配線材料膜で覆うと同時に孔の内面も配線材料膜
で覆うことにより、第１導電部と第２導電部とを電気的
に連続させることができることから簡易な工程で製造す
ることができる。As described above, according to the method of manufacturing the semiconductor device of the first aspect, the hole for separating these regions is formed at the interface between the first conductive portion region and the second conductive portion region. Since the heat treatment is performed after that, it is possible to prevent the mutual diffusion of the impurities and prevent the impurities of the first conductivity type and the impurities of the second conductivity type from compensating each other, so that the impurities of the predetermined conductivity type are maintained at a high concentration. The first conductive portion and the second conductive portion can be obtained. Further, since the conductive pattern is formed by electrically connecting the first conductive portion region and the second conductive portion region and the hole is formed at the interface portion of these regions, the increase of the cell area is minimized. Can be suppressed. Furthermore, the second contact hole for forming the hole can be formed at the same time when the first contact hole is formed, and the inner surface of the first contact hole is covered with the wiring material film, and at the same time, the inner surface of the hole is covered with the wiring material film. Since the first conductive portion and the second conductive portion can be electrically continuous, they can be manufactured by a simple process.

【００６６】また、上記方法により得られる請求項２の
発明に係る半導体装置によれば、その製造に際して行う
熱処理時に、第１導電部領域と第２導電部領域とに導入
された不純物の相互拡散を防止できるので、所定の導電
型の不純物を高濃度に維持した第１導電部と第２導電部
とを備え、かつセル面積の増加が最小限に抑えられて製
造されたものとなる。また孔の内面を覆う配線材料膜
が、第１導電部と第２導電部との拡散係数より小さい拡
散係数を有する材料からなるため、後の工程にて高温熱
処理が行われても、その熱処理の際に不純物の相互拡散
を起きにくくできる。According to the semiconductor device of the second aspect of the present invention obtained by the above method, the mutual diffusion of the impurities introduced into the first conductive portion region and the second conductive portion region during the heat treatment performed during the manufacturing thereof. Since it is possible to prevent the above, the semiconductor device is manufactured by including the first conductive portion and the second conductive portion in which the impurities of the predetermined conductive type are maintained at a high concentration, and suppressing the increase in the cell area to the minimum. Further, since the wiring material film covering the inner surface of the hole is made of a material having a diffusion coefficient smaller than that of the first conductive portion and the second conductive portion, even if the high temperature heat treatment is performed in a later step, the heat treatment is performed. In this case, mutual diffusion of impurities can be suppressed.

【００６７】請求項３の発明に係る半導体装置の製造方
法によれば、第１導電部領域と第２導電部領域との界面
部分に、これらの領域の上層膜を分離する孔を形成し、
その後、熱処理を行うことから、例えば上層膜が下層膜
よりも拡散係数が大きく、したがって拡散速度の速い金
属膜または金属化合物膜からなる場合には、第１導電部
領域と第２導電部領域との不純物の相互拡散を最小限に
抑制することができる。また請求項１の発明と同様に、
セル面積の増加を抑制できかつ半導体装置を簡易に製造
することができる。According to the method of manufacturing a semiconductor device of the third aspect of the present invention, a hole is formed at the interface between the first conductive portion region and the second conductive portion region to separate the upper layer film of these regions,
After that, since heat treatment is performed, for example, when the upper layer film is made of a metal film or a metal compound film having a larger diffusion coefficient than the lower layer film and therefore a high diffusion rate, the first conductive portion region and the second conductive portion region are Mutual diffusion of impurities can be suppressed to a minimum. Further, similarly to the invention of claim 1,
An increase in cell area can be suppressed and a semiconductor device can be easily manufactured.

【００６８】また、上記方法により得られる請求項３の
発明に係る半導体装置によれば、その製造に際して行う
熱処理時に、第１導電部領域の上層膜と第２導電部領域
の上層膜とにおいて不純物の相互拡散を防止できるの
で、例えば上層膜が下層膜よりも拡散速度の速い金属膜
または金属化合物膜からなる場合には、所定の導電型の
不純物を高濃度に維持した第１導電部、第２導電部を得
ることができる。また請求項３の発明と同様、セル面積
の増加を最小限に抑えて製造できるとともに、孔の内面
を覆う配線材料膜により、後の工程にて高温熱処理が行
われても、その熱処理の際に不純物の相互拡散を起きに
くいものとなる。According to the semiconductor device of the third aspect of the present invention obtained by the above method, impurities are removed from the upper layer film of the first conductive portion region and the upper layer film of the second conductive portion region during the heat treatment for manufacturing the semiconductor device. Therefore, when the upper layer film is composed of a metal film or a metal compound film having a faster diffusion rate than the lower layer film, for example, the first conductive portion and the first conductive portion which maintain a high concentration of impurities of a predetermined conductivity type, Two conductive parts can be obtained. Further, similarly to the invention of claim 3, the manufacturing can be performed with the increase of the cell area being suppressed to a minimum, and even if a high temperature heat treatment is performed in a later step by the wiring material film covering the inner surface of the hole, the heat treatment is performed. In addition, mutual diffusion of impurities is unlikely to occur.

【００６９】請求項５の発明に係る半導体装置の製造方
法によれば、素子分離領域の上面が露出する位置まで導
電部材料膜を除去することから、導電部材料膜が自己整
合的に、第１の半導体素子の形成予定領域と第２の半導
体素子の形成予定領域とに分離できるので、工程数の増
加が最小限に抑えることができる。また導電部材料膜
を、第１の半導体素子の形成予定領域と第２の半導体素
子の形成予定領域とに分離した後に、熱処理を行うこと
から、この熱処理の際に第１導電部領域、第２導電部領
域に導入された不純物が相互拡散することを防止できる
ので、所定の導電型の不純物を高濃度に維持した第１導
電部、第２導電部を得ることができる。したがって、本
発明によれば、例えば半導体装置がＣＭＯＳの場合に
は、異なる導電型の不純物を高濃度に維持した、しきい
値変動の小さい微細なデュアルゲート構造のＣＭＯＳを
形成することができる。According to the method of manufacturing a semiconductor device of the fifth aspect, the conductive material film is removed to the position where the upper surface of the element isolation region is exposed. Since the first semiconductor element formation-scheduled region and the second semiconductor element formation-scheduled region can be separated, an increase in the number of steps can be minimized. Moreover, since the heat treatment is performed after the conductive portion material film is separated into the first semiconductor element formation planned region and the second semiconductor element formation planned region, during the heat treatment, the first conductive portion region Since the impurities introduced into the second conductive portion region can be prevented from mutually diffusing, it is possible to obtain the first conductive portion and the second conductive portion in which the impurities of a predetermined conductive type are maintained at a high concentration. Therefore, according to the present invention, for example, when the semiconductor device is a CMOS, it is possible to form a CMOS having a fine dual gate structure in which impurities of different conductivity types are maintained at a high concentration and the threshold fluctuation is small.

【図面の簡単な説明】[Brief description of drawings]

【図１】（ａ）〜（ｃ）は、請求項１の発明に係る半導
体装置の製造方法の一実施形態を工程順に説明するため
の要部側断面図（その１）である。1A to 1C are side cross-sectional views (No. 1) of a main part for explaining an embodiment of a method for manufacturing a semiconductor device according to the invention of claim 1 in the order of steps.

【図２】（ｄ）〜（ｇ）は、請求項１の発明に係る半導
体装置の製造方法の一実施形態を工程順に説明するため
の要部側断面図（その２）である。2 (d) to (g) are side cross-sectional views (No. 2) for explaining an embodiment of the method for manufacturing a semiconductor device according to the invention of claim 1 in order of steps.

【図３】請求項２記載の発明に係る半導体装置の一実施
形態を示す平面図である。FIG. 3 is a plan view showing an embodiment of a semiconductor device according to the invention of claim 2;

【図４】（ｅ）〜（ｇ）は、請求項３の発明に係る半導
体装置の製造方法の一実施形態を工程順に説明するため
の要部側断面図である。4 (e) to (g) are side cross-sectional views for explaining an embodiment of the method of manufacturing a semiconductor device according to the invention of claim 3 in order of steps.

【図５】（ａ）〜（ｄ）は、請求項５の発明に係る半導
体装置の製造方法の一実施形態を工程順に説明する図
（その１）であり、（ロ）は平面図、（イ）は（ロ）に
おけるＡ−Ａ線矢視断面図、（ハ）は（ロ）におけるＢ
−Ｂ線矢視断面図である。5 (a) to 5 (d) are views (No. 1) for explaining one embodiment of the method for manufacturing a semiconductor device according to the invention of claim 5 in the order of steps, in which (b) is a plan view; (A) is a sectional view taken along the line A-A in (b), and (c) is a B in (b).
FIG. 4 is a cross-sectional view taken along line B.

【図６】（ｅ）は、請求項５の発明に係る半導体装置の
製造方法の一実施形態を工程順に説明する図（その２）
であり、（ロ）は平面図、（イ）は（ロ）におけるＡ−
Ａ線矢視断面図、（ハ）は（ロ）におけるＢ−Ｂ線矢視
断面図である。FIG. 6E is a view for explaining the embodiment of the method for manufacturing the semiconductor device according to the invention of claim 5 in the order of steps (No. 2);
Where (b) is a plan view, and (b) is A- in (b).
A sectional view taken along the line A, and (c) is a sectional view taken along the line BB in (b).

【図７】金属膜または金属化合物膜の他の形成例を説明
する図であり、（ロ）は平面図、（イ）は（ロ）におけ
るＡ−Ａ線矢視断面図、（ハ）は（ロ）におけるＢ−Ｂ
線矢視断面図である。7A and 7B are diagrams illustrating another example of forming a metal film or a metal compound film, in which (B) is a plan view, (A) is a cross-sectional view taken along the line AA in (B), and (C) is. BB in (b)
FIG.

【図８】従来の半導体装置の一例を示す平面図である。FIG. 8 is a plan view showing an example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

２ 素子分離領域 ３ ＰＭＯＳ
形成予定領域 ４ ＮＭＯＳ形成予定領域 ６ Poly−Ｓ
ｉ膜 ７、４５ｃ ＷＳｉ2 膜 １０、４３
Ｐ+ 型ゲート領域 １１、４４ Ｎ+ 型ゲート領域 １２ ゲート
電極のパターン １４ 層間絶縁膜 １５ 第１コ
ンタクトホール １６ 第２コンタクトホール １９ 界面部
分 ２０ レジスト膜 ２１、３１
孔 ２２ａ、４６ａ Ｐ+ 型ゲート電極 ２２ｂ、４６
ｂ Ｎ+ 型ゲート電極 ２３ 配線材料膜 ２８、４７
ＰＭＯＳＦＥＴ ２９、４８ ＮＭＯＳＦＥＴ ３０、３３、
４９ ＣＭＯＳ ４０、１００ 半導体基体 ４５ａ Ｔｉ
Ｓｉ2 膜 ４５ｂ Ｔｉ膜2 element isolation region 3 PMOS
Area to be formed 4 Area to be formed NMOS 6 Poly-S
i film 7,45c WSi 2 film 10,43
P + type gate region 11, 44 N + type gate region 12 Gate electrode pattern 14 Interlayer insulating film 15 First contact hole 16 Second contact hole 19 Interface portion 20 Resist film 21, 31
Holes 22a, 46a P + type gate electrodes 22b, 46
b N + type gate electrode 23 wiring material film 28, 47
PMOSFET 29, 48 NMOSFET 30, 33,
49 CMOS 40, 100 Semiconductor substrate 45a Ti
Si 2 film 45b Ti film

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 半導体基体に、第１導電型の第１導電部
を備えた第１の半導体素子と、第２導電型の第２導電部
を備えた第２の半導体素子とを前記第１および第２導電
部を電気的に連続させた状態で形成するとともに、該第
１および第２導電部を覆うようにして前記半導体基体上
に層間絶縁膜を形成し、該層間絶縁膜に、前記電気的に
連続させた第１および第２導電部に到達する第１コンタ
クトホールを形成してなる半導体装置を製造する方法で
あって、 前記第１の半導体素子の形成予定領域に、前記第１導電
型の不純物を導入して第１導電部領域を形成し、かつ前
記第２の半導体素子の形成予定領域に、前記第２導電型
の不純物を導入して第２導電部領域を形成することによ
り、これら第１導電部領域と第２導電部領域とを電気的
に連続させてなる導電パターンを備えた前記半導体基体
を用意し、 前記導電パターンを覆うようにして前記半導体基体上に
前記層間絶縁膜を形成し、 該層間絶縁膜に、前記導電パターンに到達する前記第１
コンタクトホールを形成すると同時に、前記第１導電部
領域と前記第２導電部領域との界面部分の直上位置に第
２コンタクトホールを形成し、 前記第１コンタクトホールを覆い、かつ前記第２コンタ
クトホールを露出させて前記層間絶縁膜上にレジスト膜
を形成し、 エッチングによって前記第２コンタクトホール直下位置
に前記第１導電部領域と前記第２導電部領域とを分離す
る孔を形成し、 熱処理によって、前記第１導電部領域に前記第１導電型
の不純物を拡散させて前記第１導電部を得るとともに、
前記第２導電部領域に前記第２導電型の不純物を拡散さ
せて前記第２導電部を得、 前記第１コンタクトホールの内面と前記孔の内面とをそ
れぞれ配線材料膜で覆い、前記第１導電部と第２導電部
とを電気的に連続させることを特徴とする半導体装置の
製造方法。1. A first semiconductor element having a first conductive portion of a first conductive type and a second semiconductor element having a second conductive portion of a second conductive type are provided on a semiconductor substrate. And the second conductive portion are formed in an electrically continuous state, and an interlayer insulating film is formed on the semiconductor substrate so as to cover the first and second conductive portions. A method of manufacturing a semiconductor device, comprising forming first contact holes reaching electrically continuous first and second conductive portions, wherein the first semiconductor element is formed in a region where the first semiconductor element is to be formed. Introducing a conductivity type impurity to form a first conductive part region, and introducing a second conductive type impurity to a region where the second semiconductor element is to be formed to form a second conductive part region. To electrically connect the first conductive portion region and the second conductive portion region. Said semiconductor substrate having a conductive pattern made of Te prepared, so as to cover the conductive pattern forming said interlayer insulating film on the semiconductor substrate, the interlayer insulating film, the first to reach the conductive pattern
At the same time as forming the contact hole, a second contact hole is formed immediately above the interface between the first conductive portion region and the second conductive portion region, covers the first contact hole, and also the second contact hole. To expose a resist film on the interlayer insulating film, and a hole for separating the first conductive portion region and the second conductive portion region is formed immediately below the second contact hole by etching. While diffusing the impurity of the first conductivity type into the first conductive part region to obtain the first conductive part,
The second conductive portion is obtained by diffusing the second conductive type impurity into the second conductive portion region, and the inner surface of the first contact hole and the inner surface of the hole are covered with a wiring material film, respectively. A method of manufacturing a semiconductor device, comprising electrically connecting a conductive portion and a second conductive portion. 【請求項２】 第１導電型の第１導電部を備えた第１の
半導体素子と、第２導電型の第２導電部を備えかつ該第
２導電部が前記第１導電部と同一の導電材料で形成され
てなる第２の半導体素子とを有し、前記第１導電部と前
記第２導電部とが電気的に連続してなる半導体装置にお
いて、 前記第１導電部と第２導電部との間には、該第１導電部
と第２導電部とを分離する状態で孔が形成されていると
ともに、該孔の内面を覆うようにして配線材料膜が形成
されてなり、 該配線材料膜は、前記第１導電部と第２導電部との拡散
係数よりも小さい拡散係数を有する材料からなることを
特徴とする半導体装置。2. A first semiconductor element having a first conductive type first conductive portion and a second conductive type second conductive portion, wherein the second conductive portion is the same as the first conductive portion. A semiconductor device having a second semiconductor element formed of a conductive material, wherein the first conductive portion and the second conductive portion are electrically continuous, the first conductive portion and the second conductive portion A hole is formed between the portion and the first conductive portion and the second conductive portion in a separated state, and a wiring material film is formed so as to cover the inner surface of the hole. The semiconductor device, wherein the wiring material film is made of a material having a diffusion coefficient smaller than that of the first conductive portion and the second conductive portion. 【請求項３】 半導体基体に、第１導電型の第１導電部
を備えた第１の半導体素子と、第２導電型の第２導電部
を備えた第２の半導体素子とを前記第１および第２導電
部を電気的に連続させた状態で形成するとともに、該第
１および第２導電部を覆うようにして前記半導体基体上
に層間絶縁膜を形成し、該層間絶縁膜に、前記電気的に
連続させた第１導電部と前記第２導電部とに到達する第
１コンタクトホールを形成してなる半導体装置を製造す
る方法であって、 前記第１の半導体素子の形成予定領域に、前記第１導電
型の不純物を導入してなる下層膜と、金属または金属化
合物からなるとともに前記下層膜上に配設された上層膜
とから構成された第１導電部領域を形成し、かつ前記第
２の半導体素子の形成予定領域に、前記第２導電型の不
純物を導入してなる下層膜と、金属または金属化合物か
らなるとともに前記下層膜上に配設された上層膜とから
構成された第２導電部領域を形成することにより、これ
ら第１導電部領域と第２導電部領域とが電気的に連続さ
せてなる導電パターンを備えた前記半導体基体を用意
し、 前記導電パターンを覆うようにして前記半導体基体上に
前記層間絶縁膜を形成し、 該層間絶縁膜に、前記導電パターンに到達する前記第１
コンタクトホールを形成すると同時に、前記第１導電部
領域と前記第２導電部領域との界面部分の直上位置に第
２コンタクトホールを形成し、 エッチングによって前記第２コンタクトホール直下位置
に前記第１導電部領域の上層膜と前記第２導電部領域の
上層膜とを分離する孔を形成し、 熱処理によって、前記第１導電部領域に前記第１導電型
の不純物を拡散させて前記第１導電部を得るとともに、
前記第２導電部領域に前記第２導電型の不純物を拡散さ
せて前記第２導電部を得、 前記第１コンタクトホールの内面と前記孔の内面とをそ
れぞれ配線材料膜で覆い、前記第１導電部の上層膜と前
記第２導電部の上層膜とを電気的に連続させることを特
徴とする半導体装置の製造方法。3. A semiconductor substrate having a first semiconductor element having a first conductive type first conductive portion and a second semiconductor element having a second conductive type second conductive portion. And the second conductive portion are formed in an electrically continuous state, and an interlayer insulating film is formed on the semiconductor substrate so as to cover the first and second conductive portions. A method of manufacturing a semiconductor device comprising forming a first contact hole reaching an electrically continuous first conductive portion and a second conductive portion, the method comprising: Forming a first conductive portion region composed of a lower layer film into which an impurity of the first conductivity type is introduced, and an upper layer film made of a metal or a metal compound and disposed on the lower layer film, and In the region where the second semiconductor element is to be formed, the second conductivity type These first conductive portion regions are formed by forming a second conductive portion region composed of a lower layer film into which a substance is introduced and an upper layer film made of a metal or a metal compound and disposed on the lower layer film. And the second conductive portion region are electrically connected to each other to prepare the semiconductor substrate, and the interlayer insulating film is formed on the semiconductor substrate so as to cover the conductive pattern. A first insulating layer that reaches the conductive pattern;
At the same time when the contact hole is formed, a second contact hole is formed immediately above the interface between the first conductive portion region and the second conductive portion region, and the first conductive portion is formed immediately below the second contact hole by etching. A hole for separating the upper layer film of the partial region and the upper layer film of the second conductive portion region is formed, and the first conductive type impurity is diffused into the first conductive portion region by heat treatment to thereby diffuse the first conductive type impurity. With
The second conductive portion is obtained by diffusing the second conductive type impurity into the second conductive portion region, and the inner surface of the first contact hole and the inner surface of the hole are covered with a wiring material film, respectively. A method of manufacturing a semiconductor device, comprising electrically connecting an upper layer film of a conductive portion and an upper layer film of the second conductive portion. 【請求項４】 第１導電型の第１導電部を備えた第１の
半導体素子と、第２導電型の第２導電部を備えた第２の
半導体素子とを有し、前記第１導電部と第２導電部とが
電気的に連続してなり、 前記第１導電部が、前記第１導電型の下層膜と、金属ま
たは金属化合物からなるとともに前記下層膜上に配設さ
れた上層膜とから構成され、 前記第２導電部が、前記第１導電部の下層膜と同一の導
電材料で形成されてなる前記第２導電型の下層膜と、金
属または金属化合物からなるとともに前記下層膜上に配
設された上層膜とから構成されてなる半導体装置におい
て、 前記第１導電部と第２導電部との間には、前記第１導電
部の上層膜と前記第２導電部の上層膜とを分離する状態
で孔が形成されているとともに、該孔の内面を覆うよう
にして配線材料膜が形成されてなり、 該配線材料膜は、前記第１導電部と第２導電部との拡散
係数よりも小さい拡散係数を有する材料からなることを
特徴とする半導体装置。4. A first semiconductor element having a first conductive portion of a first conductivity type, and a second semiconductor element having a second conductive portion of a second conductivity type, wherein the first conductive element has the first conductive element. Section and the second conductive section are electrically continuous, the first conductive section is an upper layer formed of the first conductive type lower layer film and a metal or a metal compound, and disposed on the lower layer film. And a second conductive type lower layer film in which the second conductive portion is formed of the same conductive material as that of the lower layer film of the first conductive portion, and a lower layer formed of a metal or a metal compound. In a semiconductor device including an upper layer film disposed on a film, an upper layer film of the first conductive unit and a second conductive unit are provided between the first conductive unit and the second conductive unit. A hole is formed so as to be separated from the upper layer film, and a wiring material is formed so as to cover the inner surface of the hole. A semiconductor device, wherein a film is formed, and the wiring material film is made of a material having a diffusion coefficient smaller than a diffusion coefficient of the first conductive portion and the second conductive portion. 【請求項５】 素子分離領域と、該素子分離領域に囲ま
れた複数の素子形成予定領域とからなりかつ前記素子分
離領域の上面位置が前記素子形成予定領域の上面位置よ
りも高い半導体基体を形成するとともに、前記素子形成
領域に第１導電型の第１導電部を備えた第１の半導体素
子を形成し、かつ該第１の半導体素子とは異なる前記素
子形成領域に第２導電型の第２導電部を備えた第２の半
導体素子を形成し、前記第１および第２導電部を電気的
に連続させる半導体装置の製造方法であって、 前記半導体基体の全面に導電部材料膜を形成し、次いで
前記素子分離領域の上面が露出する位置まで前記導電部
材料膜を除去する工程と、 前記第１の半導体素子の形成予定領域の前記導電部材料
膜に前記第１導電型の不純物を導入して第１導電部領域
を形成するとともに、前記第２の半導体素子の形成予定
領域に前記第２導電型の不純物を導入して第２導電部領
域を形成する工程と、 熱処理によって、前記第１導電部領域に前記第１導電型
の不純物を拡散させるとともに、前記第２導電部領域に
前記第２導電型の不純物を拡散させる工程と、 前記第１導電部領域上と、前記第２導電部領域上と、こ
れら第１導電部領域と第２導電部領域との間の前記半導
体基体上とに、該第１導電部領域と第２導電部領域とを
電気的に連続させる状態で金属膜または金属化合物膜を
形成し、前記第１導電部と前記第２導電部とを得る工程
とを備えていることを特徴とする半導体装置の製造方
法。5. A semiconductor substrate comprising an element isolation region and a plurality of element formation planned regions surrounded by the element isolation region, and an upper surface position of the element isolation region being higher than an upper surface position of the element formation planned region. Forming and forming a first semiconductor element having a first conductive type first conductive portion in the element forming area, and forming a second conductive type in an element forming area different from the first semiconductor element. A method of manufacturing a semiconductor device, comprising forming a second semiconductor element having a second conductive portion and electrically connecting the first and second conductive portions, wherein a conductive portion material film is formed on the entire surface of the semiconductor substrate. Forming, and then removing the conductive part material film to a position where the upper surface of the element isolation region is exposed; and impurities of the first conductivity type in the conductive part material film in the region where the first semiconductor element is to be formed. To introduce the first conductive region Forming and forming a second conductive portion region by introducing the second conductive type impurity into a formation planned region of the second semiconductor element; and heat treating the first conductive portion region to the first conductive portion region. Diffusing conductivity type impurities and diffusing the second conductivity type impurities in the second conductive portion region; on the first conductive portion region; on the second conductive portion region; A metal film or a metal compound film is formed on the semiconductor substrate between the conductive part region and the second conductive part region in a state where the first conductive part region and the second conductive part region are electrically continuous. And a step of obtaining the first conductive portion and the second conductive portion.
JP7230972A 1995-09-08 1995-09-08 Semiconductor device and manufacture thereof Pending JPH0982810A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7230972A JPH0982810A (en) 1995-09-08 1995-09-08 Semiconductor device and manufacture thereof

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Application Number Priority Date Filing Date Title
JP7230972A JPH0982810A (en) 1995-09-08 1995-09-08 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0982810A true JPH0982810A (en) 1997-03-28

Family

ID=16916216

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Application Number Title Priority Date Filing Date
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Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6559542B1 (en) 1999-07-13 2003-05-06 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
US6693001B2 (en) 1997-03-14 2004-02-17 Renesas Technology Corporation Process for producing semiconductor integrated circuit device
US6858484B2 (en) 2000-02-04 2005-02-22 Hitachi, Ltd. Method of fabricating semiconductor integrated circuit device
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Publication number Priority date Publication date Assignee Title
US7314830B2 (en) 1997-03-14 2008-01-01 Renesas Technology Corp. Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt
US7214577B2 (en) 1997-03-14 2007-05-08 Renesas Technology Corp. Method of fabricating semiconductor integrated circuit device
US7553766B2 (en) 1997-03-14 2009-06-30 Renesas Technology Corp. Method of fabricating semiconductor integrated circuit device
US8034715B2 (en) 1997-03-14 2011-10-11 Renesas Electronics Corporation Method of fabricating semiconductor integrated circuit device
US6693001B2 (en) 1997-03-14 2004-02-17 Renesas Technology Corporation Process for producing semiconductor integrated circuit device
US6559542B1 (en) 1999-07-13 2003-05-06 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
US6858484B2 (en) 2000-02-04 2005-02-22 Hitachi, Ltd. Method of fabricating semiconductor integrated circuit device
WO2007060938A1 (en) * 2005-11-22 2007-05-31 Nec Corporation Semiconductor device and production method thereof
US20090267158A1 (en) * 2005-11-22 2009-10-29 Nec Corporation Semiconductor device and manufacturing process therefor
JP5088139B2 (en) * 2005-11-22 2012-12-05 日本電気株式会社 Manufacturing method of semiconductor device
US8330234B2 (en) * 2005-11-22 2012-12-11 Nec Corporation Semiconductor device and manufacturing process therefor
US20130062705A1 (en) * 2005-11-22 2013-03-14 Nec Corporation Semiconductor device and manufacturing process therefor
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US7911004B2 (en) 2006-06-19 2011-03-22 Nec Corporation Semiconductor device and manufacturing method of the same

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