JPH09510069A - 結合ビットレート制御を用いるディジタルビデオ信号エンコーダのバッファリング - Google Patents
結合ビットレート制御を用いるディジタルビデオ信号エンコーダのバッファリングInfo
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- JPH09510069A JPH09510069A JP8520318A JP52031896A JPH09510069A JP H09510069 A JPH09510069 A JP H09510069A JP 8520318 A JP8520318 A JP 8520318A JP 52031896 A JP52031896 A JP 52031896A JP H09510069 A JPH09510069 A JP H09510069A
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- Mathematical Analysis (AREA)
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Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.各入力チャネルにおいて受信された2又はそれ以上の伝送信号を符号化する ビデオ信号符号化装置であって、 受信したビデオ信号を予め定めたコード化スキムに基き符号化されたビデオ フレーム当たりのデータビットの特定された数として符号化し、前記受信したビ デオ信号を前記特定された数により決定したビットレートを有するデータ流とし て出力するように動作する各チャネルのエンコーダ段と、 前記エンコーダ段に結合され、各エンコーダ段についてのビデオフレーム又 はフレーム群あたりの前記特定された数を、各エンコーダ段出力ビットレートの 和がほぼ一定になるように設定するように構成した目標設定手段と、 前記各エンコーダ段からの可変ビットレートデータ流を受信するように結合 され、格納したデータ信号をそれぞれ特定されたビットレートで出力するように 構成した各バッファ手段とを具えるビデオ信号符号化装置において、 前記各バッファ手段が単一のメモリ装置中にそれぞれメモリ領域を具え、各 チャネルの格納要件を、各チャネル格納入力ビットレートと出力ビットレートと の間の差異から決定すると共に各格納要件により決定した比率でメモリ領域をチ ャネルに割り当てるように構成したメモリ管理手段を具えるビデオ信号符号化装 置。 2.請求項1に記載の装置において、前記全メモリ領域が、各エンコーダ段出力 ビットレートの和に関係すると共にチャネルの最大瞬時格納要件とチャネル数と の積以下とした装置。 3.請求項1又は2に記載の装置において、エンコーダ段出力信号を受信するよ うに結合されると共に、この出力信号のビットレートを決定し、前記エンコーダ 段出力ビットレートに逆比例する割合として別のビットレートを計算し、各チャ ネルバッファ出力ビットレートを前記別のビットレートで制御するように動作す るバッファ出力ビットレート取り出し手段を具える装置。 4.請求項1から3までのいずれか1項に記載の装置において、前記目標設定手 段が、各入力チャネルの入力ビデオ信号をて受信するように結合されると共に 、各チャネルで受信されたビデオ画像フレームの各情報内容と関連する比率を取 り出し、前記特定された数を前記比率に基づきビットの予め定めた全数の一部と して設定するように動作する比較手段を含む装置。 5.請求項1から4までのいずれか1項に記載の装置において、各バッファ出力 信号をその後伝送するための単一のデータ流に結合する手段をさらに具える装置 。 6.請求項5に記載の装置匂い手、前記バッファ出力を結合する手段をマルチプ レクサとした装置。 7.請求項1から7までのいずれか1項に記載の装置共に用いられる受信機装置 であって、 信号データ流を受信し、このデータ流を符号化された個別のチャネルに対応 するデータ流に分離するように動作する手段と、 前記データ流をユーザ入力に応じて選択し出力するチャネル選択手段と、 前記選択されたデータ流を受信すると共に別のデータ流を出力するように結 合したデコーダバッファと、 前記バッファデータ流を受信すると共に前記予め定めたコード化スキムに基 づき復号化するデコーダ段とを具える受信機装置。 8.受信した各ビット信号を予め定めたコード化スキムに基づいて符号化された ビデオフレーム当たりのデータビットの特定された数として個別に符号化し、前 記受信したビット信号を、前記特定の数により決定したビットレートを有するデ ータ流として出力する工程と、 チャネル当たりの各ビデオフレーム又はフレーム群を符号化する特定された ビットの数を、各符号化された手信号のビットレートの和がほぼ一定になるよう に設定する工程と、 各符号化された可変ビットレートデータ流を格納し、格納されたデータ信号 をそれぞれ特定された出力ビットレートで出力する工程とを具え、各個別のチャ ネルで受信された2個又はそれ以上の伝送ビット信号を符号化するに当たり、 前記各符号化された可変ビットレートデータ流を単一のメモリ装置の各メモ リ領域に格納し、各チャネルの格納要件を各チャネル格納入力ビットレートと 出力ビットレートとの間の差異から決定し、前記メモリ領域を各格納要件により 決定した比率で割り当てることを特徴とする符号化方法。 9.請求項8に記載の方法において、符号化された信号のビットレートを決定し 、前記符号化された信号出力ビットレートに逆比例する割合として別のビットレ ートを計算し、各チャネルバッファ出力ビットレートを前記別のビットレートで 制御する方法。 10.請求項8又は9に記載の方法において、前記特定された数を、各チャネル で受信されたビデオ画像フレームの各情報内容に関係する比率に基づき予め定め さ全数の一部とした方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/366,340 US5606369A (en) | 1994-12-28 | 1994-12-28 | Buffering for digital video signal encoders using joint bit-rate control |
US08/366,340 | 1994-12-28 | ||
PCT/IB1995/001038 WO1996020568A2 (en) | 1994-12-28 | 1995-11-21 | Buffering for digital video signal encoders using joint bit-rate control |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09510069A true JPH09510069A (ja) | 1997-10-07 |
Family
ID=23442604
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8520318A Ceased JPH09510069A (ja) | 1994-12-28 | 1995-11-21 | 結合ビットレート制御を用いるディジタルビデオ信号エンコーダのバッファリング |
Country Status (9)
Country | Link |
---|---|
US (1) | US5606369A (ja) |
EP (1) | EP0748567B1 (ja) |
JP (1) | JPH09510069A (ja) |
KR (1) | KR100381826B1 (ja) |
CN (1) | CN1133330C (ja) |
AU (1) | AU695550B2 (ja) |
DE (1) | DE69515027T2 (ja) |
MY (1) | MY113111A (ja) |
WO (1) | WO1996020568A2 (ja) |
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JPS5832822B2 (ja) * | 1975-09-22 | 1983-07-15 | 富士通株式会社 | ガゾウシンゴウタジユウカデンソウホウシキ |
JPS58145284A (ja) * | 1982-02-23 | 1983-08-30 | Fujitsu Ltd | 画像信号多重化方式 |
US5115309A (en) * | 1990-09-10 | 1992-05-19 | At&T Bell Laboratories | Method and apparatus for dynamic channel bandwidth allocation among multiple parallel video coders |
US5233606A (en) * | 1991-08-02 | 1993-08-03 | At&T Bell Laboratories | Arrangement for controlling shared-buffer-memory overflow in a multi-priority environment |
JPH0568243A (ja) * | 1991-09-09 | 1993-03-19 | Hitachi Ltd | 可変長符号化制御方式 |
JPH0622215A (ja) * | 1992-07-06 | 1994-01-28 | Toshiba Corp | 映像送信方法、該方法に用いる映像送信装置および映像受信装置 |
US5410355A (en) * | 1993-04-02 | 1995-04-25 | Rca Thomson Licensing Corporation | Video signal processor including input codeword buffer for providing stored codewords to codeword priority analysis circuit |
US5461619A (en) * | 1993-07-06 | 1995-10-24 | Zenith Electronics Corp. | System for multiplexed transmission of compressed video and auxiliary data |
US5398072A (en) * | 1993-10-25 | 1995-03-14 | Lsi Logic Corporation | Management of channel buffer in video decoders |
US5481297A (en) * | 1994-02-25 | 1996-01-02 | At&T Corp. | Multipoint digital video communication system |
-
1994
- 1994-12-28 US US08/366,340 patent/US5606369A/en not_active Expired - Lifetime
-
1995
- 1995-11-21 DE DE69515027T patent/DE69515027T2/de not_active Expired - Fee Related
- 1995-11-21 JP JP8520318A patent/JPH09510069A/ja not_active Ceased
- 1995-11-21 WO PCT/IB1995/001038 patent/WO1996020568A2/en active IP Right Grant
- 1995-11-21 KR KR1019960704804A patent/KR100381826B1/ko not_active IP Right Cessation
- 1995-11-21 CN CN95192458A patent/CN1133330C/zh not_active Expired - Fee Related
- 1995-11-21 EP EP95936072A patent/EP0748567B1/en not_active Expired - Lifetime
- 1995-11-21 AU AU38146/95A patent/AU695550B2/en not_active Ceased
- 1995-12-26 MY MYPI95004094A patent/MY113111A/en unknown
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US5606369A (en) | 1997-02-25 |
MY113111A (en) | 2001-11-30 |
DE69515027D1 (de) | 2000-03-16 |
EP0748567B1 (en) | 2000-02-09 |
KR100381826B1 (ko) | 2003-07-12 |
AU695550B2 (en) | 1998-08-13 |
CN1145153A (zh) | 1997-03-12 |
WO1996020568A3 (en) | 1996-09-06 |
EP0748567A1 (en) | 1996-12-18 |
AU3814695A (en) | 1996-07-19 |
CN1133330C (zh) | 2003-12-31 |
DE69515027T2 (de) | 2000-09-14 |
WO1996020568A2 (en) | 1996-07-04 |
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