JPH09331043A - Fabrication of semiconductor memory - Google Patents
Fabrication of semiconductor memoryInfo
- Publication number
- JPH09331043A JPH09331043A JP8168418A JP16841896A JPH09331043A JP H09331043 A JPH09331043 A JP H09331043A JP 8168418 A JP8168418 A JP 8168418A JP 16841896 A JP16841896 A JP 16841896A JP H09331043 A JPH09331043 A JP H09331043A
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- Prior art keywords
- film
- polycrystalline silicon
- capacitor
- silicon film
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体記憶装置の製
造方法に関し、特に、ダイナミックランダムアクセスメ
モリ（Dynamic Random Access Memory: 以下ＤＲＡＭと
記す）の円筒形キャパシタの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a cylindrical capacitor of a dynamic random access memory (hereinafter referred to as DRAM).
【０００２】[0002]
【従来の技術】図４及び図５に、従来の円筒形キャパシ
タの製造方法を示す。例えば、ＬＯＣＯＳ法などの公知
の方法で、半導体基板１上に素子分離酸化膜２を形成
し、ゲート絶縁膜となるSiO2膜３、及びゲート電極４と
なる多結晶Si膜を成膜する。そして、その後に、公知の
フォトリソグラフィー技術及びエッチング技術を用いて
ゲート電極４を形成する。2. Description of the Related Art FIGS. 4 and 5 show a conventional method for manufacturing a cylindrical capacitor. For example, the element isolation oxide film 2 is formed on the semiconductor substrate 1 by a known method such as the LOCOS method, and the SiO 2 film 3 to be the gate insulating film and the polycrystalline Si film to be the gate electrode 4 are formed. Then, after that, the gate electrode 4 is formed by using the known photolithography technique and etching technique.
【０００３】次に、前記ゲート電極４を他の導体と絶縁
するための絶縁膜となるSiO2膜５を公知の化学的気相成
長法（ＣＶＤ法）により形成し、公知のイオン注入法に
より不純物拡散層６を形成する。次に、前記不純物拡散
層６に接触する多結晶Si膜７のパターンを形成する。Next, a SiO 2 film 5 serving as an insulating film for insulating the gate electrode 4 from other conductors is formed by a known chemical vapor deposition method (CVD method), and a known ion implantation method is used. The impurity diffusion layer 6 is formed. Next, a pattern of the polycrystalline Si film 7 that contacts the impurity diffusion layer 6 is formed.
【０００４】次に、半導体基板１上の全面にフォトレジ
スト９を回転塗布し、所定の領域にレジストパターンを
形成するとともに、前記形成したレジストパターンをマ
スクとしてエッチングを行い、多結晶Si膜７のパターン
を形成する（図４（ａ））。Next, a photoresist 9 is spin-coated on the entire surface of the semiconductor substrate 1 to form a resist pattern in a predetermined area, and etching is performed by using the formed resist pattern as a mask to form a polycrystalline Si film 7. A pattern is formed (FIG. 4A).
【０００５】次に、半導体基板１上の全面に絶縁物質よ
りなる平坦化層８を形成するとともに、前記平坦化層８
上の全面にフォトレジスト９を回転塗布し、その後、キ
ャパシタの下部電極となる予定の領域のフォトレジスト
９を選択的に除去する。次に、平坦化層８をフォトリソ
グラフィー技術とドライエッチング技術とを用いて選択
的に除去して平坦化層８にホール１０を形成する（図４
（ｂ））。Next, a flattening layer 8 made of an insulating material is formed on the entire surface of the semiconductor substrate 1, and the flattening layer 8 is formed.
The photoresist 9 is spin-coated on the entire upper surface, and then the photoresist 9 in a region to be the lower electrode of the capacitor is selectively removed. Next, the flattening layer 8 is selectively removed by using a photolithography technique and a dry etching technique to form a hole 10 in the flattening layer 8 (FIG. 4).
(B)).
【０００６】次に、フォトレジスト９を除去する（図４
（ｃ））。次に、半導体基板１上の全面に公知のＬＰ
（低圧）ＣＶＤ法により多結晶Si膜１１、SiO2膜１３を
形成する（図４（ｄ））。Next, the photoresist 9 is removed (see FIG. 4).
(C)). Next, a known LP is formed on the entire surface of the semiconductor substrate 1.
A polycrystalline Si film 11 and a SiO 2 film 13 are formed by (low pressure) CVD method (FIG. 4D).
【０００７】次に、キャパシタの下部電極となる領域以
外の多結晶Si膜１１が露出するまでSiO2膜１３の全面を
エッチングする（図５（ａ））。次に、キャパシタの下
部電極となる領域以外の多結晶Si膜１１をエッチングに
より除去する（図５（ｂ））。Next, the entire surface of the SiO 2 film 13 is etched until the polycrystalline Si film 11 other than the region to be the lower electrode of the capacitor is exposed (FIG. 5A). Next, the polycrystalline Si film 11 other than the region to be the lower electrode of the capacitor is removed by etching (FIG. 5B).
【０００８】次に、SiO2膜８及びSiO2膜１３をエッチン
グ除去して、円筒形の多結晶Si膜１１′のパターンを形
成し、キャパシタの下部電極１６とする（図５
（ｃ））。Next, the SiO 2 film 8 and the SiO 2 film 13 are removed by etching to form a pattern of the cylindrical polycrystalline Si film 11 ', which is used as the lower electrode 16 of the capacitor (FIG. 5).
(C)).
【０００９】次いで、キャパシタ誘電体となる誘電膜
（これは、膜厚ｎｍ程度で極めて薄いため、図示してい
ない）をＣＶＤ法により多結晶Si膜１１′上に形成し、
更にＣＶＤ法により誘電膜上に多結晶Si膜１４を形成
し、キャパシタの上部電極とする（図５（ｄ））。Next, a dielectric film (which is not shown because it is extremely thin with a film thickness of about nm) serving as a capacitor dielectric is formed on the polycrystalline Si film 11 'by a CVD method,
Further, a polycrystalline Si film 14 is formed on the dielectric film by the CVD method to form an upper electrode of the capacitor (FIG. 5 (d)).
【００１０】[0010]
【発明が解決しようとする課題】上記従来技術では、キ
ャパシタの下部電極となる予定の領域以外の領域の多結
晶Si膜１１をエッチングする際に、多結晶Si膜７のパタ
ーンの保護材としてSiO2膜１３を用いているが、SiO2膜
のエッチレートは基板面内でバラツキが生じる。In the above prior art, when etching the polycrystalline Si film 11 in a region other than the region to be the lower electrode of the capacitor, SiO is used as a protective material for the pattern of the polycrystalline Si film 7. Although the two films 13 are used, the etching rate of the SiO 2 film varies within the substrate surface.
【００１１】そのため、基板面内の一部の領域でキャパ
シタの下部電極となる予定の領域以外の多結晶Si膜１１
上にSiO2膜１３が残ってしまい、このSiO2膜１３が多結
晶Si膜１１のエッチング時にマスクとなり、キャパシタ
の下部電極となる予定の領域以外の領域に多結晶Si膜１
１の残渣が発生する。前記発生した残渣によりキャパシ
タ電極同志が短絡してしまうことがあり、これが半導体
記憶装置の歩留りの低下の原因となっていた。Therefore, the polycrystalline Si film 11 other than the region to be the lower electrode of the capacitor in a partial region in the substrate surface is formed.
The SiO 2 film 13 remains on the upper surface of the polycrystalline Si film 1. The SiO 2 film 13 serves as a mask when the polycrystalline Si film 11 is etched, and the polycrystalline Si film 1 is formed in a region other than the region which will be the lower electrode of the capacitor.
A residue of 1 is generated. The generated residue may cause a short circuit between the capacitor electrodes, which causes a decrease in the yield of the semiconductor memory device.
【００１２】本発明は上述の問題点にかんがみ、キャパ
シタ電極を精度良く形成できるようにして、歩留りを向
上させることができる半導体記憶装置の製造方法を提供
することを目的とする。In view of the above-mentioned problems, it is an object of the present invention to provide a method of manufacturing a semiconductor memory device capable of forming a capacitor electrode with high accuracy and improving the yield.
【００１３】[0013]
【課題を解決するための手段】本発明の半導体記憶装置
の製造方法は、半導体基板上に形成されたゲート電極
と、前記ゲート電極の端部近傍の下に位置する半導体基
板の表層に形成された拡散層と、前記拡散層に接して形
成された第１の多結晶シリコン膜とを有する半導体記憶
装置の製造方法において、前記半導体基板、ゲート電極
及び第１の多結晶シリコン膜上に、前記第１の多結晶シ
リコン膜の膜厚よりも厚い膜厚を持つ絶縁膜を形成する
第１の工程と、前記第１の多結晶シリコン膜が露出する
ように前記絶縁膜を除去して、前記絶縁膜の側面を内壁
として前記第１の多結晶シリコン膜を底部に含む開孔部
を形成する第２の工程と、前記絶縁膜の上面、及び前記
開孔部内の絶縁膜の側面と前記第１の多結晶シリコン膜
とを覆うように第２の多結晶シリコン膜を形成する第３
の工程と、前記開孔部が埋まるように、前記第２の多結
晶シリコン膜上にポジ型フォトレジストを塗布する第４
の工程と、前記開孔部の内部は前記ポジ型フォトレジス
トで埋められ、前記絶縁膜の上面は前記第２の多結晶シ
リコン膜が露出するように前記ポジ型フォトレジストを
除去する第５の工程と、前記第５の工程後に、前記露出
している第２の多結晶シリコン膜を除去する第６の工程
と、前記第６の工程後、前記絶縁膜を除去する第７の工
程と、前記第７の工程後、前記第２の多結晶シリコン膜
の表面を覆うように誘電体膜を形成する第８の工程と、
前記誘電体膜上に第３の多結晶シリコン膜を形成する第
９の工程とを備えることを特徴としている。According to a method of manufacturing a semiconductor memory device of the present invention, a gate electrode formed on a semiconductor substrate and a surface layer of the semiconductor substrate located below an end portion of the gate electrode are formed. In the method of manufacturing a semiconductor memory device having a diffusion layer and a first polycrystalline silicon film formed in contact with the diffusion layer, the semiconductor substrate, the gate electrode, and the first polycrystalline silicon film are formed on the semiconductor substrate, A first step of forming an insulating film having a thickness larger than that of the first polycrystalline silicon film, and removing the insulating film so that the first polycrystalline silicon film is exposed, A second step of forming an opening having a bottom portion including the first polycrystalline silicon film having a side surface of the insulating film as an inner wall; an upper surface of the insulating film; and a side surface of the insulating film in the opening and the first Second so as to cover the first polycrystalline silicon film Third forming a polycrystalline silicon film
And the step of applying a positive photoresist on the second polycrystalline silicon film so as to fill the opening.
And the inside of the opening is filled with the positive photoresist, and the positive photoresist is removed so that the upper surface of the insulating film exposes the second polycrystalline silicon film. A step of removing the exposed second polycrystalline silicon film after the fifth step, and a seventh step of removing the insulating film after the sixth step, An eighth step of forming a dielectric film so as to cover the surface of the second polycrystalline silicon film after the seventh step,
And a ninth step of forming a third polycrystalline silicon film on the dielectric film.
【００１４】また、本発明の他の特徴とするところは、
前記第４の工程後、前記開孔部の内部は前記ポジ型フォ
トレジストで埋められ、前記絶縁膜の上面は前記第２の
多結晶シリコン膜が露出するように前記ポジ型フォトレ
ジストを露光する第１０の工程を更に含むことを特徴と
している。Another feature of the present invention is that:
After the fourth step, the inside of the opening is filled with the positive photoresist and the upper surface of the insulating film is exposed to the positive photoresist so that the second polycrystalline silicon film is exposed. It is characterized by further including a tenth step.
【００１５】また、本発明のその他の特徴とするところ
は、前記第４の工程後、前記開孔部の内部は前記ポジ型
フォトレジストで埋められ、前記絶縁膜の上面は前記第
２の多結晶シリコン膜が露出するように前記ポジ型フォ
トレジストを、Ｏ2 を用いてアッシング処理する第１１
の工程を更に含むことを特徴としている。Another feature of the present invention is that after the fourth step, the inside of the opening is filled with the positive photoresist, and the upper surface of the insulating film is covered with the second multi-layer. An ashing process is performed on the positive photoresist using O 2 so that the crystalline silicon film is exposed.
It is characterized by further including the step of.
【００１６】本発明は上記技術手段よりなるので、従
来、SiO2膜の成膜、及び前記SiO2膜のエッチングの２工
程で形成していたキャパシタ電極の保護材を、開孔部を
形成する工程のみの１工程で形成することができるよう
になるので、半導体記憶装置を製造するための工程を簡
略化することができる。[0016] Since the present invention having the above technical means, conventional, film formation of the SiO 2 film, and the protective material of the SiO 2 film capacitor electrode which has been formed in two steps of etching to form an opening Since it can be formed in only one step, the steps for manufacturing a semiconductor memory device can be simplified.
【００１７】また、Ｏ2 プラズマ処理を用いた場合も、
大幅なスループットの向上が実現できる。また、ステッ
プアンドリピート方式の縮小投影露光法を用いると、従
来のSiO2膜のエッチングに比べて基板面内のバラツキが
少なく、基板面内の一部の領域でキャパシタの下部電極
となる予定の領域以外の領域の多結晶Si膜上にフォトレ
ジストが薄く残ってしまうことがないため、キャパシタ
電極同志が短絡することがなくなり、半導体記憶装置の
歩留りが向上する。Also, when O 2 plasma treatment is used,
A significant improvement in throughput can be realized. In addition, when the step-and-repeat reduction projection exposure method is used, there is less variation within the substrate surface compared to conventional etching of the SiO 2 film, and it is planned that it will become the lower electrode of the capacitor in a part of the area within the substrate surface. Since the photoresist does not remain thin on the polycrystalline Si film in the regions other than the regions, the capacitor electrodes are not short-circuited with each other, and the yield of the semiconductor memory device is improved.
【００１８】更に、ポジ型フォトレジストをＬＰＣＶＤ
装置で高温処理する工程がないので、フォトレジストの
除去性の低下や、コンタミネーションによる半導体記憶
装置の歩留りの低下の問題がなくなる。Further, a positive photoresist is LPCVD-processed.
Since there is no step of performing high temperature processing in the apparatus, there is no problem of deterioration of the removability of the photoresist and deterioration of the yield of the semiconductor memory device due to contamination.
【００１９】[0019]
【発明の実施の形態】以下、本発明の半導体記憶装置の
製造方法の第１の実施の形態について、図１を用いて説
明する。図１は、本発明にかかる半導体記憶装置の製造
方法を表す、製造工程順断面図である。まず、ＬＯＣＯ
Ｓ法などの公知の方法で、半導体基板１上に素子分離酸
化膜２を形成する。次に、ゲート絶縁膜となる厚さ１１
ｎｍのSiO2膜３を成膜するとともに、ゲート電極４とな
る厚さ２００ｎｍの多結晶Si膜を成膜し、その後に、公
知のフォトリソグラフィー技術及びエッチング技術を用
いて、ゲート電極４を形成する。BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of a method of manufacturing a semiconductor memory device of the present invention will be described below with reference to FIG. 1A to 1D are cross-sectional views in order of manufacturing steps showing a method for manufacturing a semiconductor memory device according to the present invention. First, LOCO
The element isolation oxide film 2 is formed on the semiconductor substrate 1 by a known method such as the S method. Next, the thickness 11 to be the gate insulating film
nm SiO 2 film 3 and a 200 nm-thick polycrystalline Si film to be the gate electrode 4 are formed, and then the gate electrode 4 is formed by using a known photolithography technique and etching technique. To do.
【００２０】次に、ゲート電極４を他の導体と絶縁する
ための絶縁膜となるSiO2膜５を、公知の化学的気相成長
法（ＣＶＤ法）により形成し、公知のイオン注入法によ
り不純物拡散層６を形成する。Next, a SiO 2 film 5 serving as an insulating film for insulating the gate electrode 4 from other conductors is formed by a known chemical vapor deposition method (CVD method), and a known ion implantation method is used. The impurity diffusion layer 6 is formed.
【００２１】次に、前記不純物拡散層６に接触する多結
晶Si膜７のパターンを形成する。これは、まず、半導体
基板１上の全面にフォトレジストを回転塗布し、所定の
領域にレジストパターンを形成し、前記レジストパター
ンをマスクとしてエッチングを行い、多結晶Si膜７のパ
ターンを形成する（図１（ａ））。Next, a pattern of the polycrystalline Si film 7 that contacts the impurity diffusion layer 6 is formed. First, a photoresist is spin-coated on the entire surface of the semiconductor substrate 1, a resist pattern is formed in a predetermined region, and etching is performed using the resist pattern as a mask to form a pattern of the polycrystalline Si film 7 ( FIG. 1 (a)).
【００２２】次に、半導体基板１上の全面に絶縁物質よ
りなる平坦化層８を形成する。次に、前記平坦化層８上
の全面にフォトレジスト９を回転塗布し、キャパシタの
下部電極となる予定の領域のフォトレジスト９を選択的
に除去し、平坦化層８をフォトリソグラフィー技術とド
ライエッチング技術とを用いて選択的に除去して平坦化
層８にホール１０を形成する（図１（ｂ））。次に、フ
ォトレジスト９を除去する（図１（ｃ））。Next, a flattening layer 8 made of an insulating material is formed on the entire surface of the semiconductor substrate 1. Next, a photoresist 9 is spin-coated on the entire surface of the flattening layer 8 to selectively remove the photoresist 9 in a region to be a lower electrode of the capacitor, and the flattening layer 8 is formed by a photolithography technique and a dry process. A hole 10 is formed in the flattening layer 8 by selectively removing it using an etching technique (FIG. 1B). Next, the photoresist 9 is removed (FIG. 1C).
【００２３】次に、半導体基板１上の全面にＬＰＣＶＤ
法により膜厚１００ｎｍ程度の多結晶Si膜１１を形成
し、膜厚１．２μｍ程度のフォトレジスト膜１２を回転
塗布法により形成する（図１（ｄ））。Next, LPCVD is performed on the entire surface of the semiconductor substrate 1.
Then, a polycrystalline Si film 11 having a film thickness of about 100 nm is formed by a method, and a photoresist film 12 having a film thickness of about 1.2 μm is formed by a spin coating method (FIG. 1D).
【００２４】次に、フォトレジスト膜１２の全面の露光
現像を行う（図２（ａ））。一般に、フォトレジストを
感光させる際の露光のドーズ量と、現像後のレジスト膜
厚は、図３（ａ）のような関係となり、露光現像後のフ
ォトレジスト膜厚が０μｍとなる最低の露光量はEth と
表される。Next, the entire surface of the photoresist film 12 is exposed and developed (FIG. 2A). Generally, the dose amount of exposure when exposing the photoresist to light and the resist film thickness after development have a relationship as shown in FIG. 3A, and the minimum exposure amount at which the photoresist film thickness after exposure and development becomes 0 μm. Is represented as Eth.
【００２５】通常のエッチングに先だっての露光におい
ては、図３（ａ）におけるEth 付近の、−（フォトレジ
スト膜厚の変化量）／（レジスト露光ドーズ量の変化
量）＝γの絶対値をできるだけ大きくして、現像残りの
発生を防止している。In the exposure before the normal etching, the absolute value of − (change amount of photoresist film thickness) / (change amount of resist exposure dose amount) = γ near Eth in FIG. The size is increased to prevent the development residue.
【００２６】本実施の形態にて用いるフォトレジスト
は、感光剤の量を減らす等の手法で図３（ｂ）に示すよ
うにγの絶対値を小さくして、露光後にフォトレジスト
膜厚がホール１０を埋める程度の膜厚となる露光ドーズ
量E1(E0<E1<Eth) と、各露光ドーズ量EO、Eth との各間
隔を大きくすることにより、露光ドーズ量E1を制御しや
すくして、露光ドーズ量E1にて露光現像する。In the photoresist used in this embodiment, the absolute value of γ is reduced as shown in FIG. 3 (b) by a method such as reducing the amount of the photosensitizer so that the photoresist film thickness after exposure is a hole. By increasing the interval between the exposure dose amount E1 (E0 <E1 <Eth) and the exposure dose amounts EO and Eth, which are enough to fill the film thickness of 10, the exposure dose amount E1 can be easily controlled. Exposure and development are performed with an exposure dose amount E1.
【００２７】次に、半導体基板１の全面をドライエッチ
ングすることにより、平坦部１５の多結晶Si膜１１をエ
ッチング除去した後に、フォトレジスト１２をＯ2 アッ
シングにより除去する（図２（ｂ））。次に、SiO2膜８
をエッチング除去して、円筒形の多結晶Siパターン１
１′を形成し、キャパシタの下部電極１６とする（図２
（ｃ））。Next, the entire surface of the semiconductor substrate 1 is dry-etched to remove the polycrystalline Si film 11 in the flat portion 15 by etching, and then the photoresist 12 is removed by O 2 ashing (FIG. 2B). . Next, the SiO 2 film 8
By etching away the cylindrical polycrystalline Si pattern 1
1'is formed to be the lower electrode 16 of the capacitor (see FIG. 2).
(C)).
【００２８】次いで、キャパシタ誘電体となる誘電膜
（膜厚数ｎｍ程度で極めて薄いため、図示していない）
をＣＶＤ法によりキャパシタの下部電極１６上に形成
し、更にＣＶＤ法により誘電膜上に厚さ６０ｎｍの多結
晶Si膜１４を形成し、キャパシタの上部電極とする（図
２（ｄ））。Next, a dielectric film serving as a capacitor dielectric (not shown because it is extremely thin with a film thickness of several nm).
Is formed on the lower electrode 16 of the capacitor by the CVD method, and the polycrystalline Si film 14 having a thickness of 60 nm is further formed on the dielectric film by the CVD method to form the upper electrode of the capacitor (FIG. 2D).
【００２９】次に、本発明の第２の実施の形態を説明す
る。図１（ｄ）に示す工程までは、第１の実施の形態と
同様にして行う。次に、Ｏ2 プラズマ処理を施し、図２
（ａ）に示すように、ホール１０の中のみにフォトレジ
スト１２を残留させる。その後の工程は第１の実施の形
態と同様である。Next, a second embodiment of the present invention will be described. The steps up to the step shown in FIG. 1D are performed in the same manner as in the first embodiment. Next, O 2 plasma treatment was performed, and
As shown in (a), the photoresist 12 remains only in the hole 10. The subsequent steps are the same as those in the first embodiment.
【００３０】[0030]
【発明の効果】本発明は上述したように、本発明によれ
ば、縮小投影露光法を用いて円筒形キャパシタの下部電
極を形成することにより、キャパシタの下部電極となる
予定の領域以外の基板面内の領域で多結晶Si膜上にフォ
トレジストが残らないので、キャパシタ電極同志が短絡
しないようにすることができ、半導体記憶装置の歩留り
を向上させることができる。As described above, according to the present invention, the lower electrode of the cylindrical capacitor is formed by using the reduction projection exposure method, so that the substrate other than the region to be the lower electrode of the capacitor is formed. Since no photoresist remains on the polycrystalline Si film in the in-plane region, it is possible to prevent the capacitor electrodes from short-circuiting each other and improve the yield of the semiconductor memory device.
【図１】本発明にかかる半導体記憶装置の製造方法を説
明するための製造工程順縦断面図である。FIG. 1 is a vertical cross-sectional view in order of manufacturing steps, for illustrating a method for manufacturing a semiconductor memory device according to the present invention.
【図２】本発明にかかる半導体記憶装置の製造方法を説
明するための製造工程順縦断面図である。FIG. 2 is a vertical cross-sectional view in order of manufacturing steps, for illustrating the method for manufacturing the semiconductor memory device according to the present invention.
【図３】露光後のフォトレジスト膜厚と露光ドーズ量と
の関係を表す図である。FIG. 3 is a diagram showing a relationship between a photoresist film thickness after exposure and an exposure dose amount.
【図４】従来の半導体記憶装置の製造方法を説明するた
めの製造工程順縦断面図である。FIG. 4 is a vertical cross-sectional view in order of manufacturing steps, for illustrating a conventional method for manufacturing a semiconductor memory device.
【図５】従来の半導体記憶装置の製造方法を説明するた
めの製造工程順縦断面図である。FIG. 5 is a vertical cross-sectional view in order of manufacturing steps, for illustrating a conventional method for manufacturing a semiconductor memory device.
１ 半導体基板 ４ ゲート電極 ６ 不純物拡散層 ７ 多結晶Si膜 ８ 平坦化層 ９ フォトレジスト １０ ホール １１ 多結晶Si膜 １２ フォトレジスト １４ 多結晶Si膜 １５ 平坦部 １６ キャパシタの下部電極 1 Semiconductor Substrate 4 Gate Electrode 6 Impurity Diffusion Layer 7 Polycrystalline Si Film 8 Flattening Layer 9 Photoresist 10 Hole 11 Polycrystalline Si Film 12 Photoresist 14 Polycrystalline Si Film 15 Flat Area 16 Lower Electrode of Capacitor
Claims (3)
と、前記ゲート電極の端部近傍の下に位置する半導体基
板の表層に形成された拡散層と、前記拡散層に接して形
成された第１の多結晶シリコン膜とを有する半導体記憶
装置の製造方法において、 前記半導体基板、ゲート電極及び第１の多結晶シリコン
膜上に、前記第１の多結晶シリコン膜の膜厚よりも厚い
膜厚を持つ絶縁膜を形成する第１の工程と、 前記第１の多結晶シリコン膜が露出するように前記絶縁
膜を除去して、前記絶縁膜の側面を内壁として前記第１
の多結晶シリコン膜を底部に含む開孔部を形成する第２
の工程と、 前記絶縁膜の上面、及び前記開孔部内の絶縁膜の側面と
前記第１の多結晶シリコン膜とを覆うように第２の多結
晶シリコン膜を形成する第３の工程と、 前記開孔部が埋まるように、前記第２の多結晶シリコン
膜上にポジ型フォトレジストを塗布する第４の工程と、 前記開孔部の内部は前記ポジ型フォトレジストで埋めら
れ、前記絶縁膜の上面は前記第２の多結晶シリコン膜が
露出するように前記ポジ型フォトレジストを除去する第
５の工程と、 前記第５の工程後に、前記露出している第２の多結晶シ
リコン膜を除去する第６の工程と、 前記第６の工程後、前記絶縁膜を除去する第７の工程
と、 前記第７の工程後、前記第２の多結晶シリコン膜の表面
を覆うように誘電体膜を形成する第８の工程と、 前記誘電体膜上に第３の多結晶シリコン膜を形成する第
９の工程とを備えることを特徴とする半導体記憶装置の
製造方法。1. A gate electrode formed on a semiconductor substrate, a diffusion layer formed on a surface layer of the semiconductor substrate located below an end portion of the gate electrode, and a first diffusion layer formed in contact with the diffusion layer. 1. A method of manufacturing a semiconductor memory device having a first polycrystalline silicon film, wherein the first polycrystalline silicon film has a thickness greater than that of the semiconductor substrate, the gate electrode, and the first polycrystalline silicon film. A first step of forming an insulating film having: and removing the insulating film so that the first polycrystalline silicon film is exposed, and using the side surface of the insulating film as an inner wall.
Forming an opening including the bottom of the polycrystalline silicon film of
And a third step of forming a second polycrystalline silicon film so as to cover the upper surface of the insulating film, the side surface of the insulating film in the opening, and the first polycrystalline silicon film, A fourth step of applying a positive photoresist on the second polycrystalline silicon film so as to fill the opening, and the inside of the opening is filled with the positive photoresist, A fifth step of removing the positive photoresist so that the upper surface of the film exposes the second polycrystalline silicon film, and the exposed second polycrystalline silicon film after the fifth step. A sixth step of removing the insulating film, a seventh step of removing the insulating film after the sixth step, and a dielectric layer covering the surface of the second polycrystalline silicon film after the seventh step. An eighth step of forming a body film, and a third multi-layered structure on the dielectric film. 9. A method of manufacturing a semiconductor memory device, comprising: a ninth step of forming a crystalline silicon film.
前記ポジ型フォトレジストで埋められ、前記絶縁膜の上
面は前記第２の多結晶シリコン膜が露出するように前記
ポジ型フォトレジストを露光する第１０の工程を更に含
むことを特徴とする請求項１に記載の半導体記憶装置の
製造方法。2. After the fourth step, the inside of the opening is filled with the positive photoresist, and the positive type photoresist is exposed on the upper surface of the insulating film so that the second polycrystalline silicon film is exposed. The method of manufacturing a semiconductor memory device according to claim 1, further comprising a tenth step of exposing the photoresist.
前記ポジ型フォトレジストで埋められ、前記絶縁膜の上
面は前記第２の多結晶シリコン膜が露出するように前記
ポジ型フォトレジストを、Ｏ2 を用いてアッシング処理
する第１１の工程を更に含むことを特徴とする請求項１
に記載の半導体記憶装置の製造方法。3. After the fourth step, the inside of the opening is filled with the positive photoresist, and the upper surface of the insulating film is exposed to the second polysilicon film. The method further comprising an eleventh step of ashing the photoresist with O 2.
A method for manufacturing a semiconductor memory device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8168418A JPH09331043A (en) | 1996-06-07 | 1996-06-07 | Fabrication of semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8168418A JPH09331043A (en) | 1996-06-07 | 1996-06-07 | Fabrication of semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09331043A true JPH09331043A (en) | 1997-12-22 |
Family
ID=15867765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8168418A Withdrawn JPH09331043A (en) | 1996-06-07 | 1996-06-07 | Fabrication of semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09331043A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2348740A (en) * | 1999-02-23 | 2000-10-11 | Nec Corp | Process for forming a lower electrode of a cylindrical capacitor |
| US6248625B1 (en) | 1999-05-07 | 2001-06-19 | Nec Corporation | Manufacturing method of cylindrical-capacitor lower electrode |
| KR100324818B1 (en) * | 1999-06-30 | 2002-02-28 | 박종섭 | Forming method for capacitor of semiconductor device |
| JP2006157002A (en) * | 2004-11-29 | 2006-06-15 | Samsung Electronics Co Ltd | Manufacturing method of capacitor, and manufacturing method of semiconductor device |
-
1996
- 1996-06-07 JP JP8168418A patent/JPH09331043A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2348740A (en) * | 1999-02-23 | 2000-10-11 | Nec Corp | Process for forming a lower electrode of a cylindrical capacitor |
| US6315912B1 (en) | 1999-02-23 | 2001-11-13 | Nec Corporation | Process for forming a lower electrode of a cylindrical capacitor |
| US6248625B1 (en) | 1999-05-07 | 2001-06-19 | Nec Corporation | Manufacturing method of cylindrical-capacitor lower electrode |
| KR100324818B1 (en) * | 1999-06-30 | 2002-02-28 | 박종섭 | Forming method for capacitor of semiconductor device |
| JP2006157002A (en) * | 2004-11-29 | 2006-06-15 | Samsung Electronics Co Ltd | Manufacturing method of capacitor, and manufacturing method of semiconductor device |
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