JPH09321045A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the sameInfo
- Publication number
- JPH09321045A JPH09321045A JP13714496A JP13714496A JPH09321045A JP H09321045 A JPH09321045 A JP H09321045A JP 13714496 A JP13714496 A JP 13714496A JP 13714496 A JP13714496 A JP 13714496A JP H09321045 A JPH09321045 A JP H09321045A
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- Japan
- Prior art keywords
- film
- wiring
- insulating film
- copper
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置およびそ
の製造方法に関し、特に銅配線を有する半導体装置とそ
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having copper wiring and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】ＬＳＩの微細化・高集積化に伴い、低抵
抗でエレクトロマイグレーション耐性の高い銅（Ｃｕ）
の配線が用いられるようになってきている。銅配線を用
いた第１の従来例としては、ノブヨシ アワヤ、ヨシノ
ブ アリタ（Ｎｏｂｕｙｏｓｈｉ Ａｗａｙａ ａｎｄ
Ｙｏｓｈｉｎｏｂｕ Ａｒｉｔａ）によりジャーナル
オブ エレクトロニック マテリアルズ（Ｊｏｕｒｎａ
ｌ ｏｆ Ｅｌｅｃｔｒｏｎｉｃ Ｍａｔｅｒｉａｌ
ｓ）Ｖｏｌ．２１，Ｎｏ．１０，１９９２，ｐｐ９５９
−９５４）に報告されたものがある。以下図３に示した
断面図を用いて説明する。2. Description of the Related Art With the miniaturization and high integration of LSI, copper (Cu) having low resistance and high electromigration resistance has been developed.
Are being used. A first conventional example using copper wiring is Nobuyoshi Awaya and Nobuyoshi Awaya and Nobuyoshi Awaya.
Journal of Electronic Materials (Journa) by Yoshinobu Arita
l of Electronic Material
s) Vol. 21, No. 10, 1992, pp959
-954). This will be described below with reference to the cross-sectional view shown in FIG.
【０００３】まず図３（ａ）に示すように、シリコン
（Ｓｉ）基板１１上に形成され、銅（以下Ｃｕ）に対す
るバリア性とＣｕの酸化防止能力の高いＳｉ窒化膜１２
Ａの上層に、Ｃｕの拡散防止と下地との密着性改善を目
的としたクロム（Ｃｒ）より構成されるバリア膜３Ａと
Ｃｕ膜４及びＣｒより構成されるバリア膜３Ｂを形成
し、パターニングして３つの導電層よりなる配線を形成
する。First, as shown in FIG. 3A, a Si nitride film 12 is formed on a silicon (Si) substrate 11 and has a high barrier property against copper (hereinafter referred to as Cu) and a high Cu oxidation preventing ability.
A barrier film 3A composed of chromium (Cr) and a barrier film 3B composed of Cu film 4 and Cr for the purpose of preventing Cu diffusion and improving the adhesion to the base are formed on the upper layer of A and patterned. To form a wiring composed of three conductive layers.
【０００４】次に図３（ｂ）に示すように、配線の上層
にＳｉ窒化膜１２Ｂを形成し、Ｃｕ配線の耐酸化性、耐
食性、密着性を改善するものである。Next, as shown in FIG. 3B, a Si nitride film 12B is formed on the wiring to improve the oxidation resistance, corrosion resistance and adhesion of the Cu wiring.
【０００５】一方、竹脇らはＣｕ配線周囲の耐酸化性を
高める構造とその製法を示している（１９９５年電子情
報通信学会エレクトロニクスソサイエティ大会講演論文
集２、講演番号Ｃ−４１８、ｐｐ１１５−１１６）。以
下この製造方法を第２の従来例とし、図４の断面図を用
いて説明する。On the other hand, Takewaki et al. Show a structure for improving oxidation resistance around a Cu wiring and a manufacturing method thereof (1995 IEICE Electronics Society Conference Proceedings 2, Lecture No. C-418, pp. 115-116). . Hereinafter, this manufacturing method will be described as a second conventional example with reference to the sectional view of FIG.
【０００６】まず図４（ａ）に示すように、Ｓｉ基板１
１上にＳｉ酸化膜より構成される第１絶縁膜１４を形成
したのち、その上にＣｕ膜４より構成される配線を形成
する。続いてＳｉ基板１１を加熱しながらモノシラン
（ＳｉＨ4 ）ガス６に曝して、ＣｕとＳｉＨ4 ガス中の
Ｓｉを反応させ、図４（ｂ）に示すように、配線の周囲
にＣｕシリサイド層（Ｃｕx Ｓｉy ）７を形成し、この
Ｃｕシリサイド層７によりＣｕの酸化を防止している。[0006] First, as shown in FIG.
After a first insulating film 14 composed of a Si oxide film is formed on the substrate 1, a wiring composed of a Cu film 4 is formed thereon. Subsequently, the Si substrate 11 is exposed to the monosilane (SiH 4 ) gas 6 while heating, so that Cu and Si in the SiH 4 gas react with each other. As shown in FIG. 4B, a Cu silicide layer ( Cu x Si y ) 7 is formed, and the Cu silicide layer 7 prevents oxidation of Cu.
【０００７】また、宮崎らはＣｕ配線上への層間絶縁膜
形成時のＣｕの酸化を防止する手法を提唱している（１
９９５年電子情報通信学会エレクトロニクスソサイエテ
ィ大会講演論文集２、講演番号Ｃ−４１９、ｐｐ１１７
−１１８）。以下この方法を第３の従来例として図５の
断面図を用いて説明する。Also, Miyazaki et al. Have proposed a method of preventing oxidation of Cu when forming an interlayer insulating film on Cu wiring (1).
Proc. Of the IEICE Electronics Society Conference, 995, Lecture No. C-419, pp117
-118). This method will be described below as a third conventional example with reference to the sectional view of FIG.
【０００８】まず図５（ａ）に示すように、Ｓｉ基板１
１上に形成されたＰＳＧ膜より構成される第１絶縁膜１
４上に、タングステン（Ｗ）より構成されるバリア膜１
３ＡとＣｕ膜４及びＷより構成されるバリア膜１３Ｂを
順次形成し、絶縁膜をエッチングマスク（図示せず）と
し、四塩化シリコン（ＳｉＣｌ4 ）＋窒素（Ｎ2 ）＋酸
素（Ｏ2 ）の混合ガスをエッチングガスとした、２５０
℃の高温での反応性イオンエッチング法により、上述の
３つの導電層を順次エッチングしてＷ膜、Ｃｕ膜、Ｗ膜
の積層膜より構成されるＣｕ配線を形成する。First, as shown in FIG. 5A, the Si substrate 1
First insulating film 1 composed of PSG film formed on 1
4, a barrier film 1 made of tungsten (W)
A barrier film 13B composed of 3A, a Cu film 4 and W is sequentially formed, an insulating film is used as an etching mask (not shown), and silicon tetrachloride (SiCl 4 ) + nitrogen (N 2 ) + oxygen (O 2 ) 250 was used as the etching gas.
The above-mentioned three conductive layers are sequentially etched by a reactive ion etching method at a high temperature of ° C. to form a Cu wiring composed of a W film, a Cu film, and a laminated film of the W film.
【０００９】次に図５（ｂ）のごとく、テトラ・エトキ
シ・シラン（Ｔｅｔｒａ−Ｅｔｈｏｘｙ−Ｓｉｌａｎ
ｅ、以下ＴＥＯＳと記す）＋Ｏ2 混合ガスを用いたプラ
ズマＣＶＤ法により、Ｃｕ配線上にＳｉ酸化膜であるプ
ラズマＴＥＯＳ酸化膜１５を形成するものである。Next, as shown in FIG. 5B, tetra-ethoxy-silan is used.
e, hereinafter referred to as TEOS). A plasma TEOS oxide film 15, which is a Si oxide film, is formed on a Cu wiring by a plasma CVD method using + O 2 mixed gas.
【００１０】この高温の反応性イオンエッチング工程で
はＣｕ配線側壁部にシリコン酸化膜系の側壁保護膜が形
成され、さらにＴＥＯＳ存在下ではＣｕの酸化が非常に
遅いため、絶縁膜形成時のＣｕの酸化は実用上問題とは
ならないとしている。In this high-temperature reactive ion etching step, a silicon oxide film-based side wall protective film is formed on the side wall of the Cu wiring. Further, in the presence of TEOS, oxidation of Cu is very slow. Oxidation does not pose a practical problem.
【００１１】一方岡部らは、Ｃｕを酸化させずにＣｕ膜
の表面に自己整合的にＳｉ酸化膜を形成する方法を明ら
かにしている（１９９３年秋季応用物理学会学術講演会
２９ｐ−ＺＥ−５）。以下この方法を第４の従来例とし
図６を用いて説明する。On the other hand, Okabe et al. Have clarified a method of forming a Si oxide film on the surface of a Cu film in a self-aligned manner without oxidizing Cu (Academic Lecture Meeting of Autumn Applied Physics Society, 1993, 29p-ZE-5). ). Hereinafter, this method will be described as a fourth conventional example with reference to FIG.
【００１２】まず図６（ａ）のように、Ｓｉ基板１１上
に形成した第１絶縁膜１４の上に合金ターゲットを用い
たスパッタ法により、ＣｕにＳｉが１．０〜５．０重量
％含まれたＣｕ−Ｓｉ合金膜４Ａを５００ｎｍの厚みで
形成する。First, as shown in FIG. 6A, 1.0 to 5.0% by weight of Si is added to Cu by sputtering using an alloy target on a first insulating film 14 formed on a Si substrate 11. The contained Cu-Si alloy film 4A is formed with a thickness of 500 nm.
【００１３】次に図６（ｂ）のごとく、Ｓｉ基板１１を
Ｎ2 −７ｐｐｍＯ2 雰囲気中で５００℃１時間の熱処理
を行ってＣｕ−Ｓｉ合金膜４Ａ中のＳｉを外方拡散さ
せ、Ｃｕ−Ｓｉ合金膜表面でＯ2 と反応させることによ
ってＣｕを酸化させる事なくＣｕ−Ｓｉ合金膜表面にＳ
ｉ酸化膜１６を形成するものである。Next, as shown in FIG. 6 (b), the Si substrate 11 is subjected to a heat treatment at 500 ° C. for 1 hour in an N 2 -7 ppm O 2 atmosphere to diffuse Si in the Cu—Si alloy film 4A outwardly, Reacting with O 2 on the surface of the Cu—Si alloy film to oxidize Cu,
The i-oxide film 16 is formed.
【００１４】[0014]
【発明が解決しようとする課題】上述した第１の従来例
の半導体装置は、Ｓｉ窒化膜をＣｕ配線の上下に形成し
ている為、Ｃｕの酸化、Ｃｕの拡散、Ｃｕの腐食のすべ
てを防止する事ができる。In the first prior art semiconductor device described above, since the Si nitride film is formed above and below the Cu wiring, all of oxidation of Cu, diffusion of Cu, and corrosion of Cu are suppressed. Can be prevented.
【００１５】しかしＳｉ窒化膜の比誘電率はＳｉ酸化膜
よりも２倍近く大きいため、層間絶縁膜の容量が大幅に
増加して、この容量増加による信号遅延が大きくなり半
導体装置の性能低下をもたらす。特に微細な半導体装置
では、回路全体の遅延におよぼす層間膜容量に起因する
遅延の占める割合が高くなるため、この遅延の影響は深
刻になり、Ｃｕを使用するメリットをなくしてしまうと
言う欠点がある。However, since the relative permittivity of the Si nitride film is nearly twice as large as that of the Si oxide film, the capacitance of the interlayer insulating film is significantly increased, and the signal delay due to the increase in capacitance is increased, resulting in deterioration of the performance of the semiconductor device. Bring In particular, in a fine semiconductor device, the ratio of the delay due to the interlayer film capacitance to the delay of the entire circuit increases, so that the influence of the delay becomes serious and the merit of using Cu is lost. is there.
【００１６】第２の従来例のように、配線の周囲にＣｕ
シリサイド層を形成した場合、Ｃｕ配線の耐酸化性、耐
食性及び耐エレクトロマイグレーション性の改善効果が
あり、しかも層間絶縁膜にＳｉ窒化膜を使用する必要が
なくなるため層間容量も増加しない。しかし配線全体の
表面積に対する高抵抗なＣｕシリサイド層の比表面積が
大きくなるため、配線抵抗が増加する。As in the second conventional example, Cu
When the silicide layer is formed, there is an effect of improving the oxidation resistance, corrosion resistance and electromigration resistance of the Cu wiring, and the interlayer capacitance does not increase because it is not necessary to use a Si nitride film for the interlayer insulating film. However, the specific surface area of the high-resistance Cu silicide layer with respect to the surface area of the entire wiring is increased, so that the wiring resistance is increased.
【００１７】さらに配線の微細化にともない、配線の体
積に対する表面積の割合はより高くなるために配線抵抗
の増加率はさらに高くなり、半導体装置の特性低下が生
じる。従って抵抗の低いＣｕを配線の主導電層に採用す
るメリットがなくなる。また、ＣｕとＳｉＨ4 との反応
は比較的速いために制御は簡単ではない。そのためシリ
サイド層の膜厚制御も難しく、ウェーハ面内やロット内
で均一な配線抵抗を得る事が難しく、安定した電気特性
の半導体装置を得にくいと言う欠点がある。Further, as the wiring becomes finer, the ratio of the surface area to the volume of the wiring becomes higher, so that the rate of increase in the wiring resistance further increases, and the characteristics of the semiconductor device deteriorate. Therefore, there is no merit of adopting Cu having low resistance for the main conductive layer of the wiring. Further, since the reaction between Cu and SiH 4 is relatively fast, control is not easy. Therefore, it is difficult to control the thickness of the silicide layer, it is difficult to obtain a uniform wiring resistance in a wafer surface or in a lot, and it is difficult to obtain a semiconductor device having stable electric characteristics.
【００１８】第３の従来例のように、エッチング時にＣ
ｕ配線の側壁部にＳｉ酸化膜系の保護膜を形成し、次で
ＴＥＯＳソースを用いてＳｉ酸化膜をＣｕ配線上に形成
する手法では、絶縁膜形成時のＣｕの酸化を防止でき、
配線抵抗も増加しない。また層間容量の増加による遅延
も起こらない。As in the third conventional example, when etching, C
The method of forming a Si oxide film-based protective film on the side wall of the u wiring and then forming the Si oxide film on the Cu wiring by using the TEOS source can prevent Cu oxidation during the formation of the insulating film.
The wiring resistance does not increase. Also, there is no delay due to an increase in interlayer capacitance.
【００１９】しかしＣｕ配線側壁部の保護膜は導電膜の
プラズマエッチング中の非平衡状態下で形成される熱的
安定性の低いものであり、Ｃｕの拡散防止能力の高いも
のではない、さらにＴＥＯＳソースのプラズマＣＶＤ法
により形成したＳｉ酸化膜もＣｕに対するバリア性があ
まり高いものではないため、配線を多層化する際に施さ
れる複数回の熱処理によりＣｕの拡散や酸化が進行して
配線間の電流リーク不良や配線抵抗上昇が発生する可能
性があり、高い製造歩留や長期信頼性が得にくいと言う
欠点がある。However, the protective film on the side wall of the Cu wiring has a low thermal stability formed under a non-equilibrium state during plasma etching of the conductive film and does not have a high ability to prevent the diffusion of Cu. Since the Si oxide film formed by the source plasma CVD method also does not have a very high barrier property against Cu, diffusion and oxidation of Cu progress due to a plurality of heat treatments performed when multi-layering the wiring, so that the inter-wiring However, there is a possibility that a current leakage failure and an increase in wiring resistance may occur, and it is difficult to obtain a high production yield and long-term reliability.
【００２０】第４の従来例のように、Ｃｕ−Ｓｉ合金膜
表面に自己整合的にＳｉ酸化膜を形成する方法では、Ｃ
ｕにＳｉを添加する事によってＣｕの電気抵抗が３μΩ
ｃｍ以上にまで増加するため、Ｃｕ配線の利点が失われ
る。さらにＳｉ酸化膜を形成するのに５００℃と言う高
い温度と、１時間と言う長い時間がかかるため、製造コ
ストが増加するという欠点がある。As in the fourth conventional example, in a method of forming a Si oxide film on the surface of a Cu—Si alloy film in a self-aligned manner, C
By adding Si to u, the electric resistance of Cu becomes 3μΩ
cm, the advantage of Cu wiring is lost. Further, since a high temperature of 500 ° C. and a long time of one hour are required to form a Si oxide film, there is a disadvantage that manufacturing costs increase.
【００２１】本発明の目的は、Ｃｕ配線の電気抵抗増大
を最小限に抑制しながら、Ｃｕ配線の耐酸化性、耐食
性、耐エレクトロマイグレーション性、耐ストレスマイ
グレーション性などの長期信頼性や製造歩留を向上させ
ることのできる半導体装置およびその製造方法を提供す
ることにある。An object of the present invention is to minimize the increase in the electrical resistance of a Cu wiring while minimizing the long-term reliability of Cu wiring such as oxidation resistance, corrosion resistance, electromigration resistance, and stress migration resistance, and manufacturing yield. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can improve the performance.
【００２２】[0022]
【課題を解決するための手段】第１の発明の半導体装置
は、半導体基板上に設けられた第１絶縁膜と、前記第１
絶縁膜上に順次設けられた第１導電膜と第２導電膜およ
び前記銅膜の側面に設けられた銅珪素化合物層より構成
される配線と、前記第１絶縁膜および前記配線の上に設
けられた第２絶縁膜とを含む事を特徴とするものであ
る。A semiconductor device according to a first invention comprises a first insulating film provided on a semiconductor substrate and the first insulating film.
A wiring formed of a first conductive film and a second conductive film sequentially provided on the insulating film and a copper silicon compound layer provided on a side surface of the copper film, and a wiring provided on the first insulating film and the wiring. It is characterized in that it includes a formed second insulating film.
【００２３】第２の発明の半導体装置は、半導体基板上
に設けられた第１絶縁膜と、前記第１絶縁膜に形成され
た配線溝と、前記配線溝中に設けられた銅膜と前記銅膜
の底部および側壁部に設けられた第１導電膜および前記
銅膜の表面に設けられた銅珪素化合物層より構成される
配線と、前記第１絶縁膜および前記配線上に設けられた
第２絶縁膜とを含む事を特徴とするものである。A semiconductor device according to a second aspect of the present invention is a semiconductor device comprising: a first insulating film provided on a semiconductor substrate; a wiring groove formed in the first insulating film; a copper film provided in the wiring groove; A wiring formed of a first conductive film provided on the bottom and side walls of the copper film and a copper silicon compound layer provided on the surface of the copper film, and a first insulating film and a wiring provided on the wiring. It is characterized by including two insulating films.
【００２４】第３の発明の半導体装置の製造方法は、半
導体基板上に第１絶縁膜を形成する工程と、前記第１絶
縁膜上に第１導電膜と銅膜と第２導電膜を順次形成する
工程と、前記第２導電膜と前記銅膜及び前記第１導電膜
をパターニングし配線を形成する工程と、前記配線の側
壁部の露出した銅膜表面を銅珪素化合物にする工程と、
前記第１絶縁膜および前記配線上に第２絶縁膜を形成す
る工程とを有する事を特徴とするものである。In the method of manufacturing a semiconductor device of the third invention, a step of forming a first insulating film on a semiconductor substrate, and a first conductive film, a copper film and a second conductive film are sequentially formed on the first insulating film. A step of forming, a step of patterning the second conductive film, the copper film and the first conductive film to form a wiring, and a step of forming an exposed copper film surface of a sidewall portion of the wiring into a copper silicon compound,
And a step of forming a second insulating film on the first insulating film and the wiring.
【００２５】第４の発明の半導体装置の製造方法は、半
導体基板上に第１絶縁膜を形成する工程と、前記第１絶
縁膜に配線溝を形成する工程と、前記配線溝上を含む全
面に第１導電膜および銅膜を順次形成し、前記配線溝を
埋める工程と、前記配線溝外部の前記第１導電膜および
前記銅膜を除去し前記第１導電膜および前記銅膜より構
成される配線を形成する工程と、前記配線上部の露出し
た銅膜表面を銅珪素化合物層にする工程と、前記銅珪素
化合物層表面を含む全面に第２絶縁膜を形成する工程と
を有する事を特徴とするものである。According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which includes a step of forming a first insulating film on a semiconductor substrate, a step of forming a wiring groove in the first insulating film, and an entire surface including the wiring groove. A step of sequentially forming a first conductive film and a copper film to fill the wiring groove, and a step of removing the first conductive film and the copper film outside the wiring groove to form the first conductive film and the copper film The method comprises: forming a wiring; forming a copper silicon compound layer on the exposed copper film surface above the wiring; and forming a second insulating film on the entire surface including the copper silicon compound layer surface. It is what
【００２６】[0026]
【作用】本発明によれば、配線の周囲がＣｕの酸化防
止、Ｃｕの拡散防止、Ｃｕの耐エレクトロマイグレーシ
ョン性や耐ストレスマイグレーション性の改善に効果的
なバリア膜とＣｕシリサイド層により被覆されたＣｕ配
線を、高い制御性、高い均一性および高い再現性のもと
で形成できる。According to the present invention, the periphery of the wiring is covered with a barrier film and a Cu silicide layer which are effective for preventing Cu oxidation, preventing Cu diffusion, and improving the electromigration resistance and stress migration resistance of Cu. Cu wiring can be formed with high controllability, high uniformity, and high reproducibility.
【００２７】そのためＣｕ配線上にＳｉ窒化膜よりも非
誘電率は低いが成膜時にＣｕを酸化させてしまう可能性
のあるＳｉ酸化膜などの絶縁膜を形成した場合でもＣｕ
は酸化はされず、Ｃｕ配線の長期信頼性が改善される。
さらにＣｕ配線多層化のために複数回の熱処理が加わっ
た場合でも配線や絶縁膜の特性劣化が生じないため、高
い性能と高い長期信頼性を有する半導体装置を高い歩留
で製造できる。Therefore, even if an insulating film such as a Si oxide film having a lower non-dielectric constant than the Si nitride film but having the possibility of oxidizing Cu is formed on the Cu wiring, Cu
Is not oxidized, and the long-term reliability of the Cu wiring is improved.
Further, even when heat treatment is performed a plurality of times for multilayering the Cu wiring, the characteristics of the wiring and the insulating film are not deteriorated, so that a semiconductor device having high performance and high long-term reliability can be manufactured with high yield.
【００２８】[0028]
【発明の実施の形態】次に本発明について図面を参照し
て説明する。図１（ａ）〜（ｄ）は本発明の第１の実施
の形態を説明する為の製造工程順に示した半導体チップ
の断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps for explaining a first embodiment of the present invention.
【００２９】まず図１（ａ）に示す通り、Ｓｉ基板１上
にＳｉ酸化膜より構成される第１絶縁膜２Ａを熱酸化法
又はＳｉＨ4 と亜酸化窒素（Ｎ2 Ｏ）、あるいはＴＥＯ
ＳとＯ2 を用いたプラズマＣＶＤ法により約５００ｎｍ
の厚さに形成する。First, as shown in FIG. 1A, a first insulating film 2A made of a Si oxide film is formed on a Si substrate 1 by a thermal oxidation method or by using SiH 4 and nitrous oxide (N 2 O) or TEO.
About 500 nm by the plasma CVD method using S and O 2
Formed to a thickness of
【００３０】この第１絶縁膜はＳｉ酸化膜に限定される
ものではなく、これ以外にＳｉ酸化膜にリン（Ｐ）やボ
ロン（Ｂ）が含まれたＰＳＧ膜やＢＰＳＧ膜、あるいは
ポリイミドなどの有機膜でも構わない。またその形成方
法についてもプラズマＣＶＤ法に限られるものではな
い。続いて窒化チタン膜（以下ＴｉＮ膜）より構成され
るバリア膜３Ａを、チタンターゲットを用いた反応性ス
パッタ法により、パワー２．５〜５．０ｋＷ、圧力２〜
１０ｍＴｏｒｒの条件で２５〜１００ｎｍの厚みで形成
する。The first insulating film is not limited to the Si oxide film, but other than this, a PSG film or a BPSG film containing phosphorus (P) or boron (B) in the Si oxide film, a polyimide film, or the like. It may be an organic film. Also, the forming method is not limited to the plasma CVD method. Subsequently, a barrier film 3A composed of a titanium nitride film (hereinafter referred to as a TiN film) is formed by a reactive sputtering method using a titanium target at a power of 2.5 to 5.0 kW and a pressure of 2 to 2.
It is formed with a thickness of 25 to 100 nm under the condition of 10 mTorr.
【００３１】次にこのバリア膜３Ａ上にＣｕ膜４をスパ
ッタ法により、成膜パワー２．０〜５．０ｋＷ、成膜圧
力２〜１０ｍＴｏｒｒの条件の下、２５０〜５００ｎｍ
の厚みで形成する。次でこのＣｕ膜４上にＴｉＮ膜より
構成されるバリア膜３Ｂをバリア膜３Ａと同様の条件に
より２５〜１００ｎｍの厚みで形成する。Next, a Cu film 4 is formed on the barrier film 3A by a sputtering method under the conditions of a film forming power of 2.0 to 5.0 kW and a film forming pressure of 2 to 10 mTorr in a thickness of 250 to 500 nm.
Formed with a thickness of Next, a barrier film 3B made of a TiN film is formed on the Cu film 4 with a thickness of 25 to 100 nm under the same conditions as the barrier film 3A.
【００３２】バリア膜３Ａ，３ＢはＴｉＮ膜に限らず、
その他にチタン（Ｔｉ）、バナジウム（Ｖ）、クロム
（Ｃｒ）、ジルコニウム（Ｚｒ）、ニオブ（Ｎｂ）、モ
リブデン（Ｍｏ）、ハフニウム（Ｈｆ）、タンタル（Ｔ
ａ）、タングステン（Ｗ）やこれらのケイ化物、ホウ化
物、窒化物、炭化物、およびこれらを含有する合金を用
いる事ができる。The barrier films 3A and 3B are not limited to TiN films.
In addition, titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (T
a), tungsten (W), silicides, borides, nitrides, carbides thereof, and alloys containing these can be used.
【００３３】このバリア膜は、配線の主導電層であるＣ
ｕの酸化やＣｕの絶縁膜中への拡散の防止、および下層
に存在する第１絶縁膜との間の密着性を確保する事を目
的として形成される。This barrier film is made of C, which is the main conductive layer of the wiring.
It is formed for the purpose of preventing oxidation of u, diffusion of Cu into the insulating film, and ensuring adhesion with the underlying first insulating film.
【００３４】次に、ＴＥＯＳ＋Ｏ2 をソースとして用い
たプラズマＣＶＤ法により、バリア膜３Ｂ上に厚さ３０
０〜５００ｎｍの酸化膜を形成して、フォトレジストを
マスクとした反応性イオンエッチング法によりパターニ
ングし、配線加工時のエッチング用のマスク５とする。Next, a thickness of 30 nm is formed on the barrier film 3B by a plasma CVD method using TEOS + O 2 as a source.
An oxide film having a thickness of 0 to 500 nm is formed, and is patterned by a reactive ion etching method using a photoresist as a mask to form an etching mask 5 at the time of wiring processing.
【００３５】次に図１（ｂ）に示すように、ＳｉＣ
ｌ4 、塩素（Ｃｌ2 ）、アンモニア（ＨＮ3 ）及びＮ2
を用いた反応性イオンエッチング法により、温度２８０
℃、圧力＝２Ｐａ、ＳｉＣｌ4 ＝２０ｓｃｃｍ、Ｃｌ2
＝２０ｓｃｃｍ、ＨＮ3 ＝１０〜３０ｓｃｃｍ、Ｎ2 ＝
８０ｓｃｃｍ、Ｎ2 ＝８０ｓｃｃｍ、ＲＦパワー＝２０
０Ｗの条件でバリア膜３Ｂ，Ｃｕ膜４およびバリア膜３
Ａを順次エッチグして配線を形成する。続いてバリア膜
３Ｂの上部に残ったマスク５を、炭素−フッ素系ガスを
用いた反応性イオンエッチング法により除去する。Next, as shown in FIG.
l 4 , chlorine (Cl 2 ), ammonia (HN 3 ) and N 2
Temperature of 280 by a reactive ion etching method using
° C, pressure = 2 Pa, SiCl 4 = 20 sccm, Cl 2
= 20sccm, HN 3 = 10~30sccm, N 2 =
80 sccm, N 2 = 80 sccm, RF power = 20
Under the condition of 0 W, the barrier film 3B, the Cu film 4 and the barrier film 3
A is sequentially etched to form a wiring. Subsequently, the mask 5 remaining on the barrier film 3B is removed by a reactive ion etching method using a carbon-fluorine-based gas.
【００３６】次に図１（ｃ）に示すように、Ｓｉ基板１
を３００℃〜４００℃に恒温保持された真空室に導入
し、圧力５０〜５００ＰａでＳｉＨ4 ガス、あるいはア
ルゴン（Ａｒ）などの不活性ガスやＮ2 で希釈したＳｉ
Ｈ4 ガス６を真空室に導入し、Ｓｉ基板１をＳｉＨ4 ガ
ス６雰囲気に曝す。そして配線の側壁部の露出したＣｕ
膜とＳｉＨ4 ガスを反応させ、厚さ１０〜２０ｎｍのＣ
ｕシリサイド層７（Ｃｕx Ｓｉy 化合物、ｘ，ｙは整
数）を配線側壁部に形成する。Next, as shown in FIG.
Is introduced into a vacuum chamber maintained at a constant temperature of 300 ° C. to 400 ° C., and SiH 4 gas or Si diluted with an inert gas such as argon (Ar) or N 2 at a pressure of 50 to 500 Pa.
The H 4 gas 6 is introduced into the vacuum chamber, and the Si substrate 1 is exposed to the atmosphere of the SiH 4 gas 6. Then, the exposed Cu on the side wall of the wiring
The film reacts with the SiH 4 gas to form a C film having a thickness of 10 to 20 nm.
u silicide layer 7 (Cu x Si y compound, x, y are integers) to form a wiring side wall.
【００３７】配線側壁部に形成されるＣｕシリサイド層
７の組成や膜厚は、圧力、温度、曝露時間、ＳｉＨ4 ガ
スの濃度および分圧などにより決定されるが、およそ１
分の処理で厚さ５〜２０ｎｍのＣｕシリサイド層が形成
できる。モノシラン以外にも、同じくＳｉ−Ｈ結合を有
するジシラン（Ｓｉ2 Ｈ6 ）や、Ｆの結合も有するジフ
ロルシラン（ＳｉＨ2 Ｆ2 ）などを用いることができ
る。減圧雰囲気下で希釈したＳｉＨ4 ガスを用いてＣｕ
をシリサイド化させる場合、シリサイド化の反応速度を
遅くできる。そのため、薄いＣｕシリサイド膜を高い均
一性と制御性のもとで形成でき、Ｃｕ配線の電気特性も
安定したものとなる。The composition and thickness of the Cu silicide layer 7 formed on the side wall of the wiring are determined by the pressure, temperature, exposure time, concentration of SiH 4 gas, partial pressure and the like.
A Cu silicide layer having a thickness of 5 to 20 nm can be formed by a minute treatment. In addition to monosilane, disilane (Si 2 H 6 ) having a Si—H bond, difluorsilane (SiH 2 F 2 ) also having an F bond, or the like can be used. Cu using diluted SiH 4 gas under reduced pressure atmosphere
When silicidation is used, the reaction rate of silicidation can be reduced. Therefore, a thin Cu silicide film can be formed with high uniformity and controllability, and the electrical characteristics of the Cu wiring become stable.
【００３８】この工程において配線側壁部のＣｕが酸化
されていたり、配線側壁部にＳｉ酸化膜系の堆積物が存
在するとＣｕとＳｉＨ4 ガスが反応しにくくなる。その
ためＣｕが酸化されている場合、前処理としてＳｉＨ4
導入前に水素（Ｈ2 ）ガスを導入して４００℃程度に加
熱してやれば、Ｃｕの酸化物をＣｕに還元でき、後のシ
リサイド化反応を促進できる。この前処理はＳｉＨ4 ガ
スを導入する真空室で行ってもよいし、別の真空室で行
ってから真空を破らずにＳｉＨ4 ガスを導入する真空室
に搬送しても良い。In this step, if Cu on the wiring side wall is oxidized or Si oxide film-based deposits are present on the wiring side wall, it is difficult for Cu to react with the SiH 4 gas. Therefore, when Cu is oxidized, SiH 4
If a hydrogen (H 2 ) gas is introduced before the introduction and heated to about 400 ° C., the Cu oxide can be reduced to Cu, and the subsequent silicidation reaction can be promoted. This pretreatment may be performed in a vacuum chamber for introducing SiH 4 gas, or may be performed in another vacuum chamber and then transferred to a vacuum chamber for introducing SiH 4 gas without breaking vacuum.
【００３９】配線側壁にＳｉ酸化膜系の堆積物が存在す
る場合には、前処理としてＳｉＨ4導入前に別の真空室
でフッ酸（ＨＦ）ガスを導入・曝露してやれば、Ｓｉ酸
化膜系の堆積物の除去が可能であり、後のシリサイド化
反応を促進できる。この際Ｃｕはエッチングされない
が、バリア膜はエッチングされる可能性があるため、バ
リア膜と堆積物のエッチングレートを考慮して前処理条
件を決定する必要がある。If Si oxide film-based deposits are present on the wiring side walls, hydrofluoric acid (HF) gas is introduced and exposed in a separate vacuum chamber before introducing SiH 4 as pretreatment. Can be removed, and the subsequent silicidation reaction can be promoted. At this time, Cu is not etched, but the barrier film may be etched. Therefore, it is necessary to determine pretreatment conditions in consideration of the etching rate of the barrier film and the deposit.
【００４０】この前処理は腐食性の強いＨＦガスを用い
るため、ＳｉＨ4 ガスを導入する真空室とは別の真空室
で行い、その後真空を破らずにＳｉＨ4 ガスを導入する
真空室に搬送する。配線側壁部に薄いＣｕシリサイド層
が形成されると、配線の耐酸化性は大幅に改善され、さ
らにＣｕシリサイド層の膜厚は充分に薄いため、配線抵
抗はほとんど増加しない。The conveying Therefore pretreatment using highly corrosive HF gas, performed in another vacuum chamber and vacuum chamber to introduce SiH 4 gas, a vacuum chamber for introducing the SiH 4 gas without subsequent breaking the vacuum I do. When a thin Cu silicide layer is formed on the side wall of the wiring, the oxidation resistance of the wiring is greatly improved, and the thickness of the Cu silicide layer is sufficiently thin, so that the wiring resistance hardly increases.
【００４１】続いて図１（ｄ）に示すように、真空を破
ることなくＴＥＯＳ＋Ｏ2 をソースとして用いたプラズ
マＣＶＤ法により、配線上にＳｉ酸化膜より構成される
第２絶縁膜２Ｂを５００〜１０００ｎｍの厚みで堆積す
る。この絶縁膜の堆積はＣｕシリサイド層を形成した真
空室と同じ真空室で行っても、別の真空室に搬送してか
ら行ってもよい。従来例で示したように、ＴＥＯＳをソ
ースとしたプラズマＣＶＤではＣｕの酸化が遅く、さら
にＣｕ表面はシリサイド化されているため、第２絶縁膜
の堆積時に配線の側壁部はほとんど酸化されない。Subsequently, as shown in FIG. 1D, the second insulating film 2B made of a silicon oxide film is formed on the wiring by a plasma CVD method using TEOS + O 2 as a source without breaking the vacuum to 500 to 500 μm. Deposit with a thickness of 1000 nm. The deposition of the insulating film may be performed in the same vacuum chamber as the vacuum chamber in which the Cu silicide layer is formed, or after being transferred to another vacuum chamber. As shown in the conventional example, in the plasma CVD using TEOS as a source, Cu is slowly oxidized and the Cu surface is silicified, so that the side wall of the wiring is hardly oxidized when the second insulating film is deposited.
【００４２】配線側壁部のシリサイド化による表面保護
と絶縁膜の堆積を連続プロセスで行うと、工程数を増加
させる事なく上述のメリットが得られる。しかし装置の
構成上の問題などで、Ｃｕのシリサイド化と絶縁膜堆積
の連続真空処理ができない場合や、Ｃｕを酸化しやすい
ＳｉＨ4 ＋Ｎ2 Ｏを用いたプラズマＣＶＤ法により連続
真空処理を行う場合には、Ｓｉ基板を大気に曝露した時
の配線表面の吸着Ｏ2やＮ2 Ｏ成分により、絶縁膜堆積
時にＣｕシリサイド層の酸化が起こりやすくなる。その
場合は絶縁膜の堆積温度を下げるなどの条件の最適化な
どが必要となるが、絶対に連続真空処理でなければ不可
能と言うわけではない。When the surface protection by silicidation of the wiring side wall and the deposition of the insulating film are performed in a continuous process, the above advantages can be obtained without increasing the number of steps. However, continuous vacuum processing of silicidation of Cu and deposition of an insulating film cannot be performed due to a problem in the configuration of the apparatus, or continuous vacuum processing is performed by a plasma CVD method using SiH 4 + N 2 O, which easily oxidizes Cu. In this case, the O 2 or N 2 O component adsorbed on the wiring surface when the Si substrate is exposed to the air tends to cause oxidation of the Cu silicide layer during the deposition of the insulating film. In that case, it is necessary to optimize conditions such as lowering the deposition temperature of the insulating film, but this is not necessarily impossible unless continuous vacuum processing is used.
【００４３】この第２絶縁膜２Ｂは必ずしもＴＥＯＳ＋
Ｏ2 のプラズマＣＶＤ法により形成されたＳｉ酸化膜で
ある必要はなく、ＳｉＨ4 ＋Ｎ2 Ｏを用いたプラズマＣ
ＶＤ法により形成したＳｉ酸化膜、ＴＥＯＳ＋Ｏ2 にフ
ォスフィン（ＰＨ3 ）やジボラン（Ｂ2 Ｈ6 ）を加えた
ソースを用いたプラズマＣＶＤ法により形成されたＰＳ
Ｇ膜やＢＰＳＧ膜であってもよい。また、塗布法により
比誘電率の小さなポリイミドなどの有機系材料を形成し
てもよく、この手法は層間容量の低減に有効である。The second insulating film 2B is not necessarily made of TEOS +
It is not necessary to use a Si oxide film formed by the O 2 plasma CVD method, and the plasma C using SiH 4 + N 2 O is used.
Si oxide film formed by VD method, PS formed by plasma CVD method using a source in which phosphine (PH 3 ) or diborane (B 2 H 6 ) is added to TEOS + O 2.
It may be a G film or a BPSG film. Further, an organic material such as polyimide having a small relative dielectric constant may be formed by a coating method, and this method is effective for reducing the interlayer capacitance.
【００４４】上述した第１の実施の形態で製造した半導
体装置は、Ｃｕ配線の上下と側壁がＣｕの酸化防止、Ｃ
ｕの拡散防止、Ｃｕの耐エレクトロマイグレーション性
や耐ストレスマイグレーション性の改善に効果的なバリ
ア膜３Ａ，３ＢとＣｕシリサイド層７により被覆されて
いる。そのため、Ｃｕ配線上にＳｉ窒化膜よりも比誘電
率は低いが、成膜時にＣｕを酸化させてしまう可能性の
あるＳｉ酸化膜などの絶縁膜を形成した場合でもＣｕは
酸化されず、Ｃｕ配線の長期信頼性が改善される。In the semiconductor device manufactured in the first embodiment described above, the upper and lower sides and side walls of the Cu wiring prevent Cu oxidation,
The barrier films 3A and 3B and the Cu silicide layer 7 are effective for preventing the diffusion of u and improving the electromigration resistance and the stress migration resistance of Cu. Therefore, even when an insulating film such as a Si oxide film, which has a lower relative dielectric constant than the Si nitride film on the Cu wiring but may oxidize Cu during film formation, is not oxidized, Cu is not oxidized. The long-term reliability of wiring is improved.
【００４５】またその製造工程において、Ｃｕ配線の多
層化のために複数回の熱処理が加わった場合でも配線や
絶縁膜の特性劣化が生じないため、高い性能と高い長期
信頼性を有する半導体装置を高い制御性、均一性及び再
現性そして高い歩留で製造できる。In the manufacturing process, even if heat treatment is performed a plurality of times for multilayering the Cu wiring, the characteristics of the wiring and the insulating film are not deteriorated, so that a semiconductor device having high performance and high long-term reliability is provided. Can be manufactured with high controllability, uniformity and reproducibility and high yield.
【００４６】上述した半導体装置とその製造方法は、Ｍ
ＯＳ、バイポーラ等の半導体装置の種類を選ばず適用す
る事ができる。The semiconductor device described above and the method of manufacturing the same
The present invention can be applied irrespective of the type of the semiconductor device such as the OS and the bipolar.
【００４７】図２（ａ）〜（ｄ）は本発明の第２の実施
の形態を説明する為の製造工程順に示した半導体チップ
の断面図である。FIGS. 2A to 2D are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps for explaining a second embodiment of the present invention.
【００４８】まず図２（ａ）に示すように、Ｓｉ基板１
上に厚さ５００〜１５００ｎｍのＳｉ酸化膜より構成さ
れる第１絶縁膜２Ａを既知の手法であるプラズマＣＶＤ
法により形成し、続いてフォトレジスト膜をマスクとし
た反応性イオンエッチング法により第１絶縁膜２Ａをエ
ッチングして深さ３００〜８００ｎｍの配線溝８を形成
する。次でこの配線溝８を含む全面にＴｉＮ膜より構成
されるバリア膜３をチタンターゲットを用いた反応性ス
パッタ法により、パワー２．５〜５．０ｋＷ、圧力２〜
１０ｍＴｏｒｒの条件で２５〜１００ｎｍの厚みで形成
する。First, as shown in FIG.
A first insulating film 2A composed of an Si oxide film having a thickness of 500 to 1500 nm is formed thereon by plasma CVD which is a known method.
Then, the first insulating film 2A is etched by a reactive ion etching method using a photoresist film as a mask to form a wiring groove 8 having a depth of 300 to 800 nm. Next, a barrier film 3 composed of a TiN film is formed on the entire surface including the wiring groove 8 by a reactive sputtering method using a titanium target at a power of 2.5 to 5.0 kW and a pressure of 2 to 2.5 kW.
It is formed with a thickness of 25 to 100 nm under the condition of 10 mTorr.
【００４９】次に図２（ｂ）に示すように、バリア膜３
上にＣｕ（ＨＦＡ）（ＴＭＶＳ）（Ｃｏｐｐｅｒ Ｈｅ
ｘａ Ｆｌｕｏｒｏ Ａｔｈｅｔｈｙｌａｃｅｔｏｎａ
ｔｅＴｒｉ−Ｍｅｔｈｙｌ Ｖｉｎｙｌ Ｓｉｌａｎ
ｅ、Ｃｕ（Ｃ5 ＨＦ6 Ｏ2 ）（Ｃ5 Ｈ12Ｓｉ））を原料
とした有機ソースを用いるＣｕ−ＣＶＤ法により厚さ５
００〜１０００ｎｍのＣｕ膜４を形成し、配線溝８がバ
リア膜３とＣｕ膜４で充填されるようにする。Ｃｕ−Ｃ
ＶＤ法は原料ソース２０〜５０ｓｃｃｍ、キャリアＨ2
ガス５０〜２００ｓｃｃｍ、温度１５０〜２５０℃、圧
力５．０〜２０．０Ｐａの条件で行うと、平滑で高いス
テップカバレッジのＣｕ膜を形成する事ができる。Next, as shown in FIG.
Cu (HFA) (TMVS) (Copper He
xa Fluor Athethylacetona
teTri-Methyl Vinyl Silan
e, Cu (C 5 HF 6 O 2) (C 5 H 12 Si)) thick by Cu-CVD method using an organic source as a raw material 5
A Cu film 4 having a thickness of 100 to 1000 nm is formed so that the wiring groove 8 is filled with the barrier film 3 and the Cu film 4. Cu-C
The VD method uses a raw material source of 20 to 50 sccm and a carrier H 2.
When the gas is 50 to 200 sccm, the temperature is 150 to 250 ° C., and the pressure is 5.0 to 20.0 Pa, a Cu film having a smooth and high step coverage can be formed.
【００５０】次でアルミナ（Ａｌ2 Ｏ3 ）微粉末と過酸
化水素（Ｈ2 Ｏ2 ）を主成分としたスラリーを用いた化
学的機械研磨法（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃ
ａｌＰｏｌｉｓｈｉｎｇ、以下ＣＭＰ法）により、配線
溝以外の部分に露出したＣｕ膜４とバリア膜３を研磨・
除去し、バリア膜３とＣｕ膜４より構成される溝埋め込
みのＣｕ配線を形成する。Next, a chemical mechanical polishing method (Chemical Mechanical) using a slurry containing alumina (Al 2 O 3 ) fine powder and hydrogen peroxide (H 2 O 2 ) as main components.
The Cu film 4 and the barrier film 3 exposed in portions other than the wiring trenches are polished by an alPolishing (hereinafter, CMP method).
After removal, a trench-filled Cu wiring composed of the barrier film 3 and the Cu film 4 is formed.
【００５１】次に図２（ｃ）のごとく、Ｓｉ基板１を３
００〜４００℃に恒温保持された真空室に導入し、圧力
５０〜５００ＰａでＳｉＨ4 ガス、あるいはＡｒなどの
不活性ガスやＮ2 で希釈したＳｉＨ4 ガス６を真空室に
導入し、Ｓｉ基板１をＳｉＨ4 ガス６雰囲気に曝す。そ
して配線上部の露出したＣｕ膜４とＳｉＨ4 ガスを反応
させ、厚さ１０〜２０ｎｍのＣｕシリサイド層７をＣｕ
配線の上部のみに形成する。配線の上部に形成されるＣ
ｕシリサイド層７の組成や膜厚は、圧力、温度、曝露時
間、ＳｉＨ4 ガスの温度および分圧などにより決定され
るが、およそ１分の処理で形成できる。Next, as shown in FIG.
SiH 4 gas is introduced into a vacuum chamber kept at a constant temperature of 00 to 400 ° C., SiH 4 gas at a pressure of 50 to 500 Pa, or SiH 4 gas 6 diluted with N 2 or an inert gas such as Ar is introduced into the vacuum chamber, and a Si substrate 1 is exposed to a SiH 4 gas 6 atmosphere. Then, the exposed Cu film 4 above the wiring is reacted with the SiH 4 gas to form a Cu silicide layer 7 having a thickness of 10 to 20 nm.
It is formed only above the wiring. C formed on top of wiring
The composition and thickness of the u-silicide layer 7 are determined by the pressure, temperature, exposure time, temperature and partial pressure of the SiH 4 gas, and can be formed by processing for about 1 minute.
【００５２】シリサイド層７の形成にはＳｉＨ4 以外
に、同じくＳｉ−Ｈ結合を有するジシラン（Ｓｉ
6 Ｈ6 ）や、Ｆの結合も有するジフロルシラン（ＳｉＨ
2 Ｆ2 ）などを用いてもよい。減圧雰囲気下で希釈した
ＳｉＨ4 ガスを用いてＣｕをシリサイド化させる場合、
シリサイド化の反応速度を遅くできる。そのため、薄い
Ｃｕシリサイド層を高い均一性と制御性のもとで形成で
きる。この工程において溝埋め込みのＣｕ配線上部のＣ
ｕが酸化されているとＳｉＨ4 ガスと反応しにくくな
る。特にＣＭＰ工程ではスラリー中に酸化力の強いＨ2
Ｏ2 が含まれているため、配線上部のＣｕ表面が酸化さ
れている可能性が高い。その場合、前処理としてＳｉＨ
4 導入前に水素ガスを導入して４００℃程度に加熱して
やれば、Ｃｕの酸化物をＣｕに還元でき、後のシリサイ
ド化反応を促進できる。この前処理はＳｉＨ4 ガスを導
入する真空室で行ってもよいし、別の真空室で行ってか
ら真空を破らずにＳｉＨ4 ガスを導入する真空室に搬送
しても良い。Ｃｕ配線の上部に薄いＣｕシリサイド層が
形成されると、配線のＣｕ露出部の耐酸化性が大幅に改
善される。しかしＣｕシリサイド層の膜厚は充分に薄い
ため、配線抵抗はほとんど増加しない。For forming the silicide layer 7, in addition to SiH 4 , disilane (Si) having a Si—H bond is also used.
6 H 6 ) and difluorsilane (SiH
2 F 2) or the like may be used. When Cu is silicided using a SiH 4 gas diluted under a reduced pressure atmosphere,
The reaction rate of silicidation can be reduced. Therefore, a thin Cu silicide layer can be formed with high uniformity and controllability. In this step, C on the upper portion of the Cu wiring
If u is oxidized, it becomes difficult to react with SiH 4 gas. Particularly in the CMP process, H 2 having strong oxidizing power is contained in the slurry.
Since O 2 is contained, it is highly possible that the Cu surface on the wiring is oxidized. In that case, SiH
(4) If hydrogen gas is introduced before the introduction and heated to about 400 ° C., Cu oxide can be reduced to Cu and the subsequent silicidation reaction can be promoted. This pretreatment may be performed in a vacuum chamber for introducing SiH 4 gas, or may be performed in another vacuum chamber and then transferred to a vacuum chamber for introducing SiH 4 gas without breaking vacuum. When a thin Cu silicide layer is formed on the upper part of the Cu wiring, the oxidation resistance of the exposed Cu portion of the wiring is greatly improved. However, since the Cu silicide layer is sufficiently thin, the wiring resistance hardly increases.
【００５３】次に図２（ｄ）のように、Ｃｕ配線上に、
ＴＥＯＳ＋Ｏ2 をソースとしたプラズマＣＶＤ法により
Ｓｉ酸化膜より構成される第２絶縁膜２Ｂを５００〜１
０００ｎｍの厚みで形成する。第２の実施の形態におい
て適用できる第２絶縁膜の種類や堆積条件は、第１の実
施の形態の場合と同様で、Ｓｉ酸化膜以外にもＰＳＧ
膜、ＢＰＳＧ膜、ポリイミドなども適用可能である。Next, as shown in FIG. 2D, on the Cu wiring,
The TEOS + O 2 composed of Si oxide film by a plasma CVD method using a source second insulating film 2B 500 to 1
It is formed with a thickness of 000 nm. The type and deposition conditions of the second insulating film applicable in the second embodiment are the same as those in the first embodiment, and the PSG is not limited to the Si oxide film.
A film, a BPSG film, a polyimide, or the like is also applicable.
【００５４】上述の方法で製造した半導体装置は、溝埋
め込みＣｕ配線の底部と側壁がバリア膜、配線上部がＣ
ｕシリサイドにより被覆されている。そのため、成膜時
にＣｕを酸化させてしまう可能性のあるＳｉ酸化膜など
の絶縁膜を形成した場合でもＣｕは酸化されず、Ｃｕ配
線の長期信頼性が改善される。In the semiconductor device manufactured by the above method, the bottom and side walls of the trench-embedded Cu wiring are barrier films, and the wiring upper portion is C.
coated with u-silicide. Therefore, even when an insulating film such as a Si oxide film that may oxidize Cu is formed during film formation, Cu is not oxidized, and the long-term reliability of the Cu wiring is improved.
【００５５】またその製造工程において、Ｃｕ配線を多
層化するために複数回の熱処理が加わった場合でも配線
や絶縁膜には特性劣化が生じないため、高性能と高長期
信頼性の半導体装置を高い制御性，均一性及び再現性そ
して高い歩留で製造できる。In the manufacturing process, even if heat treatment is performed a plurality of times in order to multilayer the Cu wiring, the characteristics of the wiring and the insulating film are not deteriorated. It can be manufactured with high controllability, uniformity and reproducibility and high yield.
【００５６】上述した半導体装置とその製造方法は、第
１の実施の形態の場合と同様にＭＯＳ、バイポーラ等の
半導体装置の種類を選ばず適用する事ができる。The above-described semiconductor device and its manufacturing method can be applied irrespective of the type of semiconductor device, such as a MOS or bipolar device, as in the case of the first embodiment.
【００５７】[0057]
【発明の効果】以上説明したように本発明の半導体装置
および製造方法は、配線の周囲がＣｕの酸化防止、Ｃｕ
の拡散防止、Ｃｕの耐エレクトロマイグレーション性や
耐ストレスマイグレーション性の改善に効果的なバリア
膜とＣｕシリサイド層により被覆された構造のＣｕ配線
を高い制御性、高い均一性および高い再現性のもとで形
成できる。As described above, according to the semiconductor device and the manufacturing method of the present invention, in the periphery of the wiring, the oxidation of Cu is prevented,
Of Cu wiring having a structure covered with a barrier film and a Cu silicide layer, which is effective in preventing diffusion of Cu and improving electromigration resistance and stress migration resistance of Cu, is highly controlled, highly uniform, and highly reproducible. Can be formed with.
【００５８】そのためＣｕ配線上にＳｉ窒化膜よりも比
誘電率は低いが成膜時にＣｕを酸化させてしまう可能性
のあるＳｉ酸化膜などの絶縁膜を形成した場合でもＣｕ
は酸化はされず、Ｃｕ配線の長期信頼性が改善される。
さらにＣｕ配線多層化のために複数回の熱処理が加わっ
た場合でも配線や絶縁膜の特性劣化が生じないため、高
い性能と高い長期信頼性を有する半導体装置を高い歩留
で製造できる効果を有する。For this reason, even when an insulating film such as a Si oxide film having a lower dielectric constant than the Si nitride film but having a possibility of oxidizing Cu is formed on the Cu wiring, the Cu film may be formed.
Is not oxidized, and the long-term reliability of the Cu wiring is improved.
Furthermore, even when heat treatment is performed a plurality of times for multilayering the Cu wiring, the characteristics of the wiring and the insulating film are not deteriorated, so that a semiconductor device having high performance and high long-term reliability can be manufactured at a high yield. .
【図１】本発明の第１の実施の形態を説明する為の半導
体チップの断面図。FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention.
【図２】本発明の第２の実施の形態を説明する為の半導
体チップの断面図。FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.
【図３】第１の従来例を説明する為の半導体チップの断
面図。FIG. 3 is a sectional view of a semiconductor chip for explaining a first conventional example.
【図４】第２の従来例を説明する為の半導体チップの断
面図。FIG. 4 is a sectional view of a semiconductor chip for explaining a second conventional example.
【図５】第３の従来例を説明する為の半導体チップの断
面図。FIG. 5 is a sectional view of a semiconductor chip for explaining a third conventional example.
【図６】第４の従来例を説明する為の半導体チップの断
面図。FIG. 6 is a sectional view of a semiconductor chip for explaining a fourth conventional example.
１，１１ Ｓｉ基板 ２Ａ 第１絶縁膜 ２Ｂ 第２絶縁膜 ３Ａ，３Ｂ バリア膜 ４ Ｃｕ膜 ４Ａ Ｃｕ−Ｓｉ合金膜 ５ マスク ６ シランガス ７ Ｃｕシリサイド層 ８ 溝 １２Ａ，１２Ｂ Ｓｉ窒化膜 １３Ａ，１３Ｂ バリア膜 １４ 第１絶縁膜 １５ プラズマＴＥＯＳ酸化膜 １６ Ｓｉ酸化膜 1,11 Si substrate 2A First insulating film 2B Second insulating film 3A, 3B Barrier film 4 Cu film 4A Cu-Si alloy film 5 Mask 6 Silane gas 7 Cu silicide layer 8 Groove 12A, 12B Si nitride film 13A, 13B Barrier film 14 First insulating film 15 Plasma TEOS oxide film 16 Si oxide film
Claims (10)
と、前記第１絶縁膜上に順次設けられた第１導電膜と第
２導電膜および前記銅膜の側面に設けられた銅珪素化合
物層より構成される配線と、前記第１絶縁膜および前記
配線の上に設けられた第２絶縁膜とを含む事を特徴とす
る半導体装置。1. A first insulating film provided on a semiconductor substrate, a first conductive film and a second conductive film sequentially provided on the first insulating film, and copper silicon provided on side surfaces of the copper film. A semiconductor device comprising: a wiring composed of a compound layer; and a second insulating film provided on the first insulating film and the wiring.
と、前記第１絶縁膜に形成された配線溝と、前記配線溝
中に設けられた銅膜と前記銅膜の底部および側壁部に設
けられた第１導電膜および前記銅膜の表面に設けられた
銅珪素化合物層より構成される配線と、前記第１絶縁膜
および前記配線上に設けられた第２絶縁膜とを含む事を
特徴とする半導体装置。2. A first insulating film provided on a semiconductor substrate, a wiring groove formed in the first insulating film, a copper film provided in the wiring groove, and a bottom portion and a sidewall portion of the copper film. A wiring composed of a first conductive film provided on the surface and a copper silicon compound layer provided on the surface of the copper film, and a second insulating film provided on the first insulating film and the wiring. A semiconductor device characterized by:
程と、前記第１絶縁膜上に第１導電膜と銅膜と第２導電
膜を順次形成する工程と、前記第２導電膜と前記銅膜及
び前記第１導電膜をパターニングし配線を形成する工程
と、前記配線の側壁部の露出した銅膜表面を銅珪素化合
物にする工程と、前記第１絶縁膜および前記配線上に第
２絶縁膜を形成する工程とを有する事を特徴とする半導
体装置の製造方法。3. A step of forming a first insulating film on a semiconductor substrate, a step of sequentially forming a first conductive film, a copper film and a second conductive film on the first insulating film, and the second conductive film. And a step of patterning the copper film and the first conductive film to form a wiring, a step of forming a copper silicon compound on the exposed copper film surface of the side wall portion of the wiring, and a step of forming a wiring on the first insulating film and the wiring. And a step of forming a second insulating film.
程と、前記第１絶縁膜に配線溝を形成する工程と、前記
配線溝上を含む全面に第１導電膜および銅膜を順次形成
し、前記配線溝を埋める工程と、前記配線溝外部の前記
第１導電膜および前記銅膜を除去し前記第１導電膜およ
び前記銅膜より構成される配線を形成する工程と、前記
配線上部の露出した銅膜表面を銅珪素化合物層にする工
程と、前記銅珪素化合物層表面を含む全面に第２絶縁膜
を形成する工程とを有する事を特徴とする半導体装置の
製造方法。4. A step of forming a first insulating film on a semiconductor substrate, a step of forming a wiring groove in the first insulating film, and a step of sequentially forming a first conductive film and a copper film over the entire surface including the wiring groove. The step of filling the wiring groove, the step of removing the first conductive film and the copper film outside the wiring groove to form a wiring composed of the first conductive film and the copper film, and the wiring upper portion. And a step of forming a second insulating film over the entire surface including the surface of the copper silicon compound layer, and a method of manufacturing a semiconductor device.
ウム（Ｖ）、クロム（Ｃｒ）、ジルコニウム（Ｚｒ）、
ニオブ（Ｎｂ）、モリブデン（Ｍｏ） 、ハフニウム
（Ｈｆ）、タンタル（Ｔａ）、タングステン（Ｗ）や、
これらの珪化物、ホウ化物、窒化物、炭化物およびこれ
らを含有する合金より構成される単層膜である請求項１
又は請求項２記載の半導体装置。5. The first conductive film comprises titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr),
Niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W),
A single layer film composed of these silicides, borides, nitrides, carbides and alloys containing them.
Alternatively, the semiconductor device according to claim 2.
あるいはＴｉとＴｉのホウ素化合物からなる２層の膜で
ある請求項１又は請求項２記載の半導体装置。6. The semiconductor device according to claim 1, wherein the first conductive film is a two-layer film composed of Ti and a nitrogen compound of Ti or a boron compound of Ti and Ti.
ウム（Ｖ）、クロム（Ｃｒ）、ジルコニウム（Ｚｒ）、
ニオブ（Ｎｂ）、モリブデン（Ｍｏ）、ハフニウム（Ｈ
ｆ）、タンタル（Ｔａ）、タングステン（Ｗ）や、これ
らの珪化物、ホウ化物、窒化物、炭化物およびこれらを
含有する合金より構成される単層膜である請求項１記載
の半導体装置。7. The second conductive film comprises titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr),
Niobium (Nb), molybdenum (Mo), hafnium (H
The semiconductor device according to claim 1, wherein the semiconductor device is a single-layer film composed of f), tantalum (Ta), tungsten (W), and their silicides, borides, nitrides, carbides and alloys containing them.
あるいはＴｉとＴｉのホウ素化合物からなる２層の膜で
ある請求項１記載の半導体装置。8. The semiconductor device according to claim 1, wherein the second conductive film is a two-layer film composed of Ti and a nitrogen compound of Ti or a boron compound of Ti and Ti.
スとの反応により形成される請求項３又は請求項４記載
の半導体装置の製造方法。9. The method of manufacturing a semiconductor device according to claim 3, wherein the copper silicon compound is formed by a reaction of copper and a gas containing silicon.
いはジシランである請求項９記載の半導体装置の製造方
法。10. The method for manufacturing a semiconductor device according to claim 9, wherein the gas containing silicon is monosilane or disilane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8137144A JP2809196B2 (en) | 1996-05-30 | 1996-05-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8137144A JP2809196B2 (en) | 1996-05-30 | 1996-05-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09321045A true JPH09321045A (en) | 1997-12-12 |
| JP2809196B2 JP2809196B2 (en) | 1998-10-08 |
Family
ID=15191852
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|---|---|---|---|
| JP8137144A Expired - Fee Related JP2809196B2 (en) | 1996-05-30 | 1996-05-30 | Method for manufacturing semiconductor device |
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| US6504234B2 (en) | 2000-02-04 | 2003-01-07 | Nec Corporation | Semiconductor device with interlayer film comprising a diffusion prevention layer to keep metal impurities from invading the underlying semiconductor substrate |
| JP2003045960A (en) * | 2001-08-01 | 2003-02-14 | Matsushita Electric Ind Co Ltd | Semiconductor device and method of manufacturing same |
| US6818992B1 (en) | 1999-04-23 | 2004-11-16 | International Business Machines Corporation | Self-aligned copper silicide formation for improved adhesion/electromigration |
| JP2006196744A (en) * | 2005-01-14 | 2006-07-27 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof |
| JP2006287022A (en) * | 2005-04-01 | 2006-10-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| US7229921B2 (en) | 2002-03-13 | 2007-06-12 | Nec Electronics Corporation | Semiconductor device and manufacturing method for the same |
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| US7687918B2 (en) | 2002-12-27 | 2010-03-30 | Nec Electronics Corporation | Semiconductor device and method for manufacturing same |
| JP2010245415A (en) * | 2009-04-09 | 2010-10-28 | Nec Corp | Magnetoresistive storage device and method of manufacturing the same |
| JP2012253148A (en) * | 2011-06-01 | 2012-12-20 | Toshiba Corp | Semiconductor device and manufacturing method of the same |
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| JPH09255687A (en) * | 1995-03-20 | 1997-09-30 | Matsushita Electric Ind Co Ltd | Material for forming membrane and formation of wiring |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09255687A (en) * | 1995-03-20 | 1997-09-30 | Matsushita Electric Ind Co Ltd | Material for forming membrane and formation of wiring |
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| JP2001244266A (en) * | 2000-02-28 | 2001-09-07 | Lg Philips Lcd Co Ltd | Substrate for electronic element and its manufacturing apparatus |
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