JPH09298889A - Inverter - Google Patents
InverterInfo
- Publication number
- JPH09298889A JPH09298889A JP8107579A JP10757996A JPH09298889A JP H09298889 A JPH09298889 A JP H09298889A JP 8107579 A JP8107579 A JP 8107579A JP 10757996 A JP10757996 A JP 10757996A JP H09298889 A JPH09298889 A JP H09298889A
- Authority
- JP
- Japan
- Prior art keywords
- power switching
- switching element
- mounting
- semiconductor power
- mounting portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Inverter Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】半導体パワースイッチング素
子を用いたインバータ装置における漏れ電流を抑制し、
ラジオノイズを低減したインバータ装置に関する。BACKGROUND OF THE INVENTION Leakage current in an inverter device using a semiconductor power switching element is suppressed,
The present invention relates to an inverter device that reduces radio noise.
【０００２】[0002]
【従来の技術】図４は従来の三相インバータ装置の回路
構成を示す図、図５は従来のインバータ装置における半
導体パワースイッチング素子の実装例を示す概要図であ
る。図４において、１１はダイオードで構成される整流
回路部で、交流電源を整流して直流電圧に変換する。１
２は平滑コンデンサであり、整流した直流電流の平滑、
およびインバータ部１３からのリップル電流を吸収す
る。１３はインバータ部であり、ＩＧＢＴあるいはパワ
ーＭＯＳＦＥＴと逆並列ダイオードからなる複数の半導
体パワースィッチング素子で構成されている。１０は、
これら整流回路部１１、平滑コンデンサ１２、インバー
タ部１３より成るインバータ装置である。１４は半導体
パワースイッチング素子のドライブ回路、１５はインバ
ータ部１３のための制御回路、１６はインバータ装置１
０が駆動するモータである。2. Description of the Related Art FIG. 4 is a diagram showing a circuit configuration of a conventional three-phase inverter device, and FIG. 5 is a schematic diagram showing a mounting example of a semiconductor power switching element in the conventional inverter device. In FIG. 4, reference numeral 11 is a rectifying circuit unit composed of diodes, which rectifies an AC power source and converts it into a DC voltage. 1
2 is a smoothing capacitor, which smoothes the rectified direct current,
Also, the ripple current from the inverter unit 13 is absorbed. Reference numeral 13 denotes an inverter section, which is composed of a plurality of semiconductor power switching elements including an IGBT or a power MOSFET and an antiparallel diode. 10 is
The inverter device includes the rectifying circuit unit 11, the smoothing capacitor 12, and the inverter unit 13. Reference numeral 14 is a drive circuit for the semiconductor power switching element, 15 is a control circuit for the inverter unit 13, and 16 is an inverter device 1.
0 is a driven motor.
【０００３】最近、インバータ装置を用いて駆動するモ
ータから発生する騒音を低減するため、半導体パワース
イッチング素子としては高速でＯＮ、ＯＦＦすることが
できるＩＧＢＴあるいはパワーＭＯＳＦＥＴを使用し、
キャリア周波数を十数ＫHZとしている。また、図５にお
いて、２０はインバータ装置の筐体の一部、２１は半導
体パワースイッチング素子の取付台であり、冷却フィン
と兼用して一体構成される。この取付台２１にはダイオ
ードおよび複数の半導体パワースイッチング素子２２〜
２５で構成された整流回路部１１およびインバータ部１
３が取り付けられている。半導体パワースイッチング素
子は、後述のように、その電極と冷却面とがセラミック
スなどの絶縁材によって絶縁されている。取付台２１は
半導体パワースイッチング素子２２〜２５からの熱を冷
却フィン側ヘ効率よく伝達する必要があるため、一般に
熱伝達率の高いアルミニウム系の材料が使用されてい
る。また、取付台に一体構成した冷却フィンはインバー
タ装置の筐体２０のアース端子と接続され、接地線２６
で模擬的に示すように大地に接地される。この接地は人
体ヘの感電を防ぐために必要である。Recently, in order to reduce noise generated from a motor driven by an inverter device, an IGBT or a power MOSFET which can be turned on and off at high speed is used as a semiconductor power switching element.
The carrier frequency is set to over ten KHZ. Further, in FIG. 5, 20 is a part of the housing of the inverter device, and 21 is a mounting base for the semiconductor power switching element, which is also configured integrally as a cooling fin. A diode and a plurality of semiconductor power switching elements 22 to
Rectifier circuit section 11 and inverter section 1 composed of 25
3 is attached. As will be described later, the semiconductor power switching element has its electrodes and a cooling surface insulated from each other by an insulating material such as ceramics. Since the mounting base 21 needs to efficiently transfer the heat from the semiconductor power switching elements 22 to 25 to the cooling fin side, an aluminum-based material having a high heat transfer coefficient is generally used. Further, the cooling fin integrally formed on the mount is connected to the ground terminal of the case 20 of the inverter device, and the ground wire 26
It is grounded to the ground as shown in the simulation. This grounding is necessary to prevent electric shock to the human body.
【０００４】図６は半導体パワースイッチング素子の実
装の分解図で、同図の様に、取付台２１に取付けられる
放熱板３１の上に基板３２を載せ、この基板３２の上に
半導体のチップ３３を実装し、さらにターミナルホルダ
３４およびケース３５を載せる。また、基板３２は熱伝
導率の高い放熱板３１の上に接着した構成である。基板
３２はセラミック板上に銅の回路板を張り合わせてある
ため、チツプ３３、ターミナルホルダ３４と放熱板３１
は電気的に絶縁されている。従って、放熱板に接触する
冷却フィン（取付台）と半導体パワースイッチング素子
の間には絶縁材が存在することになり、静電容量すなは
ち浮遊容量が発生する。FIG. 6 is an exploded view of the mounting of the semiconductor power switching element. As shown in FIG. 6, a substrate 32 is placed on a heat dissipation plate 31 mounted on a mounting base 21, and a semiconductor chip 33 is mounted on the substrate 32. Then, the terminal holder 34 and the case 35 are placed. Further, the substrate 32 is configured to be adhered on the heat dissipation plate 31 having high thermal conductivity. Since the board 32 is a ceramic circuit board and a copper circuit board bonded together, the chip 33, the terminal holder 34 and the heat sink 31 are
Are electrically insulated. Therefore, an insulating material is present between the cooling fin (mounting table) and the semiconductor power switching element that are in contact with the heat dissipation plate, and electrostatic capacitance or stray capacitance is generated.
【０００５】[0005]
【発明が解決しようとする課題】ところが、従来技術で
は前述のように半導体パワースイッチング素子の取付台
および冷却フィンは、半導体から発生する電力損失によ
る温度上昇を低減するため、熱伝導度の高いアルミニウ
ムあるいは、その合金を使用している。このアルミニウ
ムあるいは、その合金は熱伝導率が高いと同時に電気抵
抗が低い。従って、半導体パワースイッチング素子のチ
ップ３３と放熱板３１、および取付台２１との間には浮
遊容量が発生する。また、各部を接続する配線と取付台
との間にも同様に浮遊容量が発生する。半導体パワース
イッチング素子が制御回路（図４参照）からの信号によ
って導通、非導通を繰り返すと、半導体パワースイッチ
ング素子と取付台との間に高い電圧の変化（ｄＶ／ｄ
ｔ）が発生し、この電圧の変化が原因となり、前記浮遊
容量のために半導体チツプや配線などの導体から冷却フ
ィンへ電流が流れる。この電流はｉ＝ｋＣ・ｄＶ／ｄｔ
で表わされる。Ｃは浮遊容量、ｋは定数である。However, in the prior art, as described above, the mounting base and the cooling fins of the semiconductor power switching element reduce the temperature rise due to the power loss generated from the semiconductor, so that aluminum having high thermal conductivity is used. Alternatively, the alloy is used. This aluminum or its alloy has a high thermal conductivity and a low electric resistance. Therefore, stray capacitance is generated between the chip 33 of the semiconductor power switching element, the heat dissipation plate 31, and the mounting base 21. In addition, stray capacitance is similarly generated between the wiring connecting each part and the mounting base. When the semiconductor power switching element is repeatedly turned on and off by a signal from the control circuit (see FIG. 4), a high voltage change (dV / d) occurs between the semiconductor power switching element and the mounting base.
t) occurs, and due to this change in voltage, a current flows from the conductor such as a semiconductor chip or wiring to the cooling fin due to the stray capacitance. This current is i = kC · dV / dt
Is represented by C is a stray capacitance and k is a constant.
【０００６】図７はインバータ装置が電源に接続されて
モータを駆動する場合の使用例である。同図において、
４４は電源トランスで二次側が接地線４３で接地されて
いる。また、モータ１６もそのフレームが接地線４２で
接地されている。ここで４１を浮遊容量Ｃとすると、実
線４５あるいは４６で示す閉回路が構成され、半導体チ
ップ→冷却フィン→浮遊容量Ｃ→接地線２６→大地→電
源（回路４５）あるいはモータ１６の接地線４２から構
成される電気回路（回路４６）を通って漏れ電流とな
る。この電流は図７の回路の各部から高周波数のラジオ
ノイズを放射し、近接する計測器やラジオ受信器に電波
障害を与える事がある。そこで、本発明は、従来技術の
上記問題に鑑み、半導体パワースイッチング素子と冷却
フィン間の浮遊容量を低減し、あるいは冷却フィンとイ
ンバータの筐体との間の電気抵抗を高くして、高い電圧
変化による漏れ電流を抑制して、ラジオノイズを低減す
ることを目的とする。FIG. 7 shows an example of use when the inverter device is connected to a power source to drive a motor. In the figure,
A power transformer 44 is grounded on the secondary side by a ground wire 43. The frame of the motor 16 is also grounded by the ground wire 42. Here, when 41 is a stray capacitance C, a closed circuit shown by a solid line 45 or 46 is formed, and the semiconductor chip → cooling fin → stray capacitance C → ground line 26 → ground → power supply (circuit 45) or ground line 42 of the motor 16 Through the electric circuit (circuit 46) composed of This current may radiate high-frequency radio noise from each part of the circuit of FIG. 7, and may cause radio interference to a measuring instrument or a radio receiver in the vicinity. In view of the above problems of the prior art, the present invention reduces the stray capacitance between the semiconductor power switching element and the cooling fin, or increases the electric resistance between the cooling fin and the casing of the inverter to increase the high voltage. The purpose is to suppress the leakage current due to the change and reduce the radio noise.
【０００７】[0007]
【課題を解決するための手段】上記問題を解決するため
に、本発明は、接地される筐体内に取付部を介して取付
けた複数の半導体パワースイッチング素子にＯＮ、ＯＦ
Ｆ信号を印加し、その導通時間を可変することにより必
要な電圧・電流を供給制御するインバータ装置におい
て、半導体パワースイッチング素子を取り付ける誘電率
が小さい高絶縁高熱伝導材料からなる取付部と、前記取
付部に一体に構成した冷却フィンを有する。また、半導
体パワースイッチング素子を取り付ける高熱伝導材料か
らなる取付部と、前記取付部に一体に構成した冷却フィ
ンと、据付られる前記取付部と据付ける前記筐体との間
に介在する絶縁部材を有する。In order to solve the above-mentioned problems, the present invention turns on and off a plurality of semiconductor power switching elements mounted via a mounting portion in a grounded housing.
In an inverter device in which an F signal is applied and the conduction time is varied to supply and control necessary voltage and current, a semiconductor power switching element is mounted on a mounting portion made of a highly insulating and highly heat-conductive material having a low dielectric constant, and the mounting. The cooling fin is integrally formed with the section. In addition, the semiconductor power switching device includes a mounting portion made of a high heat conductive material, a cooling fin integrally formed with the mounting portion, and an insulating member interposed between the mounting portion to be mounted and the housing to be mounted. .
【０００８】また、半導体パワースイッチング素子を取
り付ける取付部と、前記取付けられる半導体パワースイ
ッチング素子と取付部との間に挟持した誘電率が小さく
熱伝導の良い絶縁シートを有する。Further, it has a mounting portion for mounting the semiconductor power switching element, and an insulating sheet sandwiched between the mounting semiconductor power switching element and the mounting portion and having a small dielectric constant and good heat conduction.
【０００９】[0009]
【発明の実施の形態】本発明について図面を参照しなが
ら説明する。図１は本発明の第１実施例を示す構成図で
ある。この例は、冷却フィンを一体に構成した取付台が
誘電率の小さい高熱伝導率高電気絶縁材料（例えば、窒
化アルミニウム系セラミックス）を用いてなるインバー
タ装置である。図１において、複数の半導体パワースイ
ッチング素子３は誘電率が小さく絶縁抵抗の高い取付台
２の上に取り付けられる。また取付台には冷却フィンが
一体に構成されている。従って、半導体パワースイッチ
ング素子が、ＯＮ、ＯＦＦすることにより発生する高ｄ
Ｖ／ｄｔの電圧が半導体パワースイッチング素子のチツ
プと放熱板間に印加され、チップと放熱板間の浮遊容量
Ｃによる電流ｉ＝ｋＣ・ｄＶ／ｄｔがチップから放熱板
ヘ発生する。しかし、放熱板が取り付けられている取付
台の電気抵抗が高く、誘電率が小さいために浮遊容量が
小さい。したがって、この漏れ電流は小さく、接地線か
らのラジオノイズが低減される。DETAILED DESCRIPTION OF THE INVENTION The present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing a first embodiment of the present invention. This example is an inverter device in which a mounting base integrally configured with cooling fins uses a high thermal conductivity and high electric insulation material (for example, aluminum nitride ceramics) having a small dielectric constant. In FIG. 1, a plurality of semiconductor power switching elements 3 are mounted on a mounting base 2 having a small dielectric constant and a high insulation resistance. A cooling fin is integrally formed on the mount. Therefore, the high d generated when the semiconductor power switching element is turned on and off
A voltage of V / dt is applied between the chip of the semiconductor power switching element and the heat sink, and a current i = kC · dV / dt due to the stray capacitance C between the chip and the heat sink is generated from the chip to the heat sink. However, the mounting table to which the heat dissipation plate is mounted has a high electric resistance and a small dielectric constant, so that the stray capacitance is small. Therefore, this leakage current is small, and radio noise from the ground line is reduced.
【００１０】以上より、高ｄＶ／ｄｔによる漏れ電流は
抑制され、また一方、上記の取付台は高熱伝導率という
性質を持っているため、半導体パワースイッチング素子
に発生した熱を効率よく冷却フィン部ヘ導き、半導体パ
ワースイッチング素子と冷却フィン部間の温度差は極め
て低くなる。図２は本発明の第２実施例を示す構成図で
ある。この例は、図２に示すように、半導体パワースイ
ッチング素子を実装した取付台（冷却フィンを一体構
成）をインバータ装置の筐体に取り付ける構成におい
て、筐体１と取付台２との間に絶縁材料で作られたスペ
ーサ４を挿入し、さらに絶縁材料で構成した取付けボル
ト５により取付台２と筐体１を接続する。また、大地ヘ
の接地は接地線２６により行う。From the above, the leakage current due to high dV / dt is suppressed, and, on the other hand, since the above-mentioned mounting base has the property of high thermal conductivity, the heat generated in the semiconductor power switching element is efficiently cooled by the cooling fin portion. F, the temperature difference between the semiconductor power switching element and the cooling fin portion becomes extremely low. FIG. 2 is a block diagram showing a second embodiment of the present invention. In this example, as shown in FIG. 2, in a configuration in which a mounting base (cooling fins are integrally configured) on which a semiconductor power switching element is mounted is mounted on a housing of an inverter device, insulation is provided between the housing 1 and the mounting base 2. The spacer 4 made of a material is inserted, and the mounting base 2 and the housing 1 are connected by the mounting bolt 5 made of an insulating material. Further, grounding to the ground is performed by the grounding wire 26.
【００１１】この構成方法によれば、半導体パワースイ
ツチング素子と取付台との間の浮遊容量は変わらない
が、取付台と筐体との間の電気抵抗が増加するため、漏
れ電流の回路、例えば図７の回路４５あるいは４６の抵
抗が大きくなり、漏れ電流が抑制され、ラジオノイズが
減少する。さらに、図３は本発明の第３実施例を示す構
成図である。これは、図３に示すように、半導体パワー
スイチング素子３と冷却フィンを一体構成した取付台２
の間に誘電率が小さく、熱伝導率が良い絶縁シート６を
挿入した例である。図１と同様に浮遊容量が小さくなる
ため、漏れ電流が抑制され、従って、ラジオノイズが低
減される。According to this construction method, the stray capacitance between the semiconductor power switching element and the mounting base does not change, but the electric resistance between the mounting base and the housing increases, so that a circuit of leakage current, For example, the resistance of the circuit 45 or 46 in FIG. 7 is increased, the leakage current is suppressed, and the radio noise is reduced. Further, FIG. 3 is a block diagram showing a third embodiment of the present invention. As shown in FIG. 3, this is a mounting base 2 in which a semiconductor power switching element 3 and cooling fins are integrally configured.
This is an example in which an insulating sheet 6 having a small dielectric constant and good thermal conductivity is inserted between the two. As in the case of FIG. 1, the stray capacitance is reduced, so that the leakage current is suppressed and thus the radio noise is reduced.
【００１２】[0012]
【発明の効果】以上述ベたように、本発明によれは、イ
ンバータの半導体パワースイッチング素子のＯＮ、ＯＦ
Ｆによる高ｄＶ／ｄｔが印加されても誘電率が小さい高
絶縁材料の冷却フィンを使用するために浮遊容量が小さ
くなるため、漏れ電流を抑制することができる。従っ
て、ラジオノイズを低減することができる。As described above, according to the present invention, the semiconductor power switching element of the inverter is turned on and off.
Even if a high dV / dt is applied by F, the stray capacitance is reduced because the cooling fin made of a highly insulating material having a small dielectric constant is used, so that the leakage current can be suppressed. Therefore, radio noise can be reduced.
【図１】本発明の第１実施例を示す構成図FIG. 1 is a configuration diagram showing a first embodiment of the present invention.
【図２】本発明の第２実施例を示す構成図FIG. 2 is a configuration diagram showing a second embodiment of the present invention.
【図３】本発明の第３実施例を示す構成図FIG. 3 is a configuration diagram showing a third embodiment of the present invention.
【図４】従来の三相インバータ装置の回路構成を示す図FIG. 4 is a diagram showing a circuit configuration of a conventional three-phase inverter device.
【図５】従来のインバータ装置の半導体パワースイッチ
ング素子の実装例を示す概要図FIG. 5 is a schematic diagram showing a mounting example of a semiconductor power switching element of a conventional inverter device.
【図６】半導体パワースイッチング素子の実装の分解図FIG. 6 is an exploded view of mounting of a semiconductor power switching element
【図７】従来の三相インバータ装置の使用例での漏れ電
流回路の形成を示す概念図FIG. 7 is a conceptual diagram showing formation of a leakage current circuit in a usage example of a conventional three-phase inverter device.
１ 筐体 ２ 取付台（冷却フィン兼用） ３ 半導体パワースイッチング素子 ４ スペーサ ５ ボルト ６ 絶縁シート １０ インバータ装置 １１ 整流回路部 １２ 平滑コンデンサ １３ インバータ部 １４ ドライブ回路 １５ 制御回路 １６ モータ ２０ 筐体 ２１ 取付台（冷却フィン兼用） ２２〜２５ 半導体パワースイッチング素子 ２６ 接地線 ３１ 放熱板 ３２ 基板 ３３ 半導体チップ ３４ ターミナルホルダ ３５ ケース ４１ 浮遊容量 ４２、４３ 接地線 ４４ 電源トランス（二次側） ４５、４６ 漏れ電流回路 DESCRIPTION OF SYMBOLS 1 Housing 2 Mounting base (also serving as cooling fin) 3 Semiconductor power switching element 4 Spacer 5 Volt 6 Insulating sheet 10 Inverter device 11 Rectifying circuit part 12 Smoothing capacitor 13 Inverter part 14 Drive circuit 15 Control circuit 16 Motor 20 Housing 21 Mounting base (Also used as cooling fin) 22 to 25 semiconductor power switching element 26 ground wire 31 heat sink 32 substrate 33 semiconductor chip 34 terminal holder 35 case 41 stray capacitance 42, 43 ground wire 44 power transformer (secondary side) 45, 46 leakage current circuit
Claims (3)
けた複数の半導体パワースイッチング素子にＯＮ、ＯＦ
Ｆ信号を印加し、その導通時間を可変することにより必
要な電圧・電流を供給制御するインバータ装置におい
て、 半導体パワースイッチング素子を取り付ける誘電率が小
さい高絶縁高熱伝導材料からなる取付部と、前記取付部
に一体に構成した冷却フィンを有することを特徴とする
インバ−タ装置。1. An ON / OF switch for a plurality of semiconductor power switching elements mounted via a mounting portion in a grounded housing.
In an inverter device that controls the supply of necessary voltage and current by applying an F signal and varying the conduction time of the F signal, a mounting portion for mounting a semiconductor power switching element, the mounting portion being made of a high insulating and high thermal conductive material having a small dielectric constant, and the mounting. An inverter device characterized in that it has a cooling fin formed integrally with the section.
けた複数の半導体パワースイッチング素子にＯＮ、ＯＦ
Ｆ信号を印加し、その導通時間を可変することにより必
要な電圧・電流を供給制御するインバータ装置におい
て、 半導体パワースイッチング素子を取り付ける高熱伝導材
料からなる取付部と、前記取付部に一体に構成した冷却
フィンと、据付られる前記取付部と据付ける前記筐体と
の間に介在する絶縁部材を有することを特徴とするイン
バータ装置。2. A plurality of semiconductor power switching elements mounted on a grounded housing via mounting portions are turned on and off.
In an inverter device in which an F signal is applied and a necessary voltage / current is controlled by varying its conduction time, a mounting portion made of a high thermal conductive material for mounting a semiconductor power switching element, and the mounting portion are integrally formed. An inverter device comprising: a cooling fin; and an insulating member interposed between the mounting portion to be installed and the housing to be installed.
けた複数の半導体パワースイッチング素子にＯＮ、ＯＦ
Ｆ信号を印加し、その導通時間を可変することにより必
要な電圧・電流を供給制御するインバータ装置におい
て、 半導体パワースイッチング素子を取り付ける取付部と、
前記取付けられる半導体パワースイッチング素子と取付
部との間に挟持した誘電率が小さく熱伝導の良い絶縁シ
ートを有することを特徴とするインバータ装置。3. ON and OF to a plurality of semiconductor power switching elements mounted via a mounting portion in a grounded housing
In an inverter device for controlling supply of necessary voltage / current by applying F signal and varying conduction time thereof, a mounting portion for mounting a semiconductor power switching element,
An inverter device comprising an insulating sheet sandwiched between the semiconductor power switching element to be mounted and the mounting portion and having a small dielectric constant and good thermal conductivity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10757996A JP3649259B2 (en) | 1996-04-26 | 1996-04-26 | Inverter device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10757996A JP3649259B2 (en) | 1996-04-26 | 1996-04-26 | Inverter device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09298889A true JPH09298889A (en) | 1997-11-18 |
| JP3649259B2 JP3649259B2 (en) | 2005-05-18 |
Family
ID=14462753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10757996A Expired - Fee Related JP3649259B2 (en) | 1996-04-26 | 1996-04-26 | Inverter device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3649259B2 (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005278384A (en) * | 2004-02-24 | 2005-10-06 | Fuji Electric Systems Co Ltd | Semiconductor power converter |
| JP2009027840A (en) * | 2007-07-19 | 2009-02-05 | Fuji Electric Device Technology Co Ltd | Power converter |
| JP2014053468A (en) * | 2012-09-07 | 2014-03-20 | Mitsubishi Heavy Ind Ltd | Insulated mounting structure of semiconductor device |
| US9214406B2 (en) | 2013-12-26 | 2015-12-15 | Denso Corporation | Electronic control device |
| JP2017041493A (en) * | 2015-08-18 | 2017-02-23 | 富士電機株式会社 | Electronic/electric device |
| WO2017051925A1 (en) * | 2015-09-24 | 2017-03-30 | アイシン・エィ・ダブリュ株式会社 | Vehicle control device |
| US10244617B2 (en) | 2015-06-30 | 2019-03-26 | Omron Corporation | Power converter |
| JP2019062234A (en) * | 2018-12-25 | 2019-04-18 | 富士電機株式会社 | Electronic/electric device |
| US10361628B2 (en) | 2015-06-30 | 2019-07-23 | Omron Corporation | Power converter |
| JP2020048404A (en) * | 2018-09-14 | 2020-03-26 | 富士電機株式会社 | Electronic and electrical apparatus |
| EP3968742A1 (en) | 2020-09-11 | 2022-03-16 | Toyota Jidosha Kabushiki Kaisha | Power converter |
| EP4312475A1 (en) * | 2022-07-25 | 2024-01-31 | Mazda Motor Corporation | Inverter |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101380743B1 (en) * | 2007-12-21 | 2014-04-03 | 삼성전자 주식회사 | Power supply for preventing a power element from being broken due to a short circuit |
| JP5798412B2 (en) | 2011-08-25 | 2015-10-21 | 日産自動車株式会社 | Semiconductor module |
| JP6582718B2 (en) | 2015-08-18 | 2019-10-02 | 富士電機株式会社 | Electronic electrical equipment |
-
1996
- 1996-04-26 JP JP10757996A patent/JP3649259B2/en not_active Expired - Fee Related
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005278384A (en) * | 2004-02-24 | 2005-10-06 | Fuji Electric Systems Co Ltd | Semiconductor power converter |
| JP2009027840A (en) * | 2007-07-19 | 2009-02-05 | Fuji Electric Device Technology Co Ltd | Power converter |
| JP2014053468A (en) * | 2012-09-07 | 2014-03-20 | Mitsubishi Heavy Ind Ltd | Insulated mounting structure of semiconductor device |
| US9214406B2 (en) | 2013-12-26 | 2015-12-15 | Denso Corporation | Electronic control device |
| US10361628B2 (en) | 2015-06-30 | 2019-07-23 | Omron Corporation | Power converter |
| US10244617B2 (en) | 2015-06-30 | 2019-03-26 | Omron Corporation | Power converter |
| CN106469695A (en) * | 2015-08-18 | 2017-03-01 | 富士电机株式会社 | Electronic electric equipment |
| JP2017041493A (en) * | 2015-08-18 | 2017-02-23 | 富士電機株式会社 | Electronic/electric device |
| WO2017051925A1 (en) * | 2015-09-24 | 2017-03-30 | アイシン・エィ・ダブリュ株式会社 | Vehicle control device |
| US10510639B2 (en) | 2015-09-24 | 2019-12-17 | Aisin Aw Co., Ltd. | Vehicle control device |
| JP2020048404A (en) * | 2018-09-14 | 2020-03-26 | 富士電機株式会社 | Electronic and electrical apparatus |
| JP2019062234A (en) * | 2018-12-25 | 2019-04-18 | 富士電機株式会社 | Electronic/electric device |
| EP3968742A1 (en) | 2020-09-11 | 2022-03-16 | Toyota Jidosha Kabushiki Kaisha | Power converter |
| EP4312475A1 (en) * | 2022-07-25 | 2024-01-31 | Mazda Motor Corporation | Inverter |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3649259B2 (en) | 2005-05-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3649259B2 (en) | Inverter device | |
| JP4054137B2 (en) | Power semiconductor element power supply and heat dissipation device | |
| US7035106B2 (en) | Heat dissipation system for semiconductor device | |
| JP3555742B2 (en) | Electronic circuit device | |
| JP2008042124A (en) | Semiconductor power module | |
| US7567446B2 (en) | Power conversion apparatus including a rectifier circuit and an inverter circuit | |
| JP2001168253A (en) | Packaging structure of semiconductor device and power supply side charging device | |
| JP2005235929A (en) | Power converter | |
| US6295201B1 (en) | Bus bar having embedded switching device | |
| JP2007324016A (en) | Induction heating apparatus | |
| JP2023505240A (en) | Inverter with compact design | |
| JPH0719166Y2 (en) | Element mounting structure for power converter | |
| JPWO2018185805A1 (en) | Switching element drive unit | |
| US6310439B1 (en) | Distributed parallel semiconductor device spaced for improved thermal distribution and having reduced power dissipation | |
| JP2000058746A (en) | Device for cooling inside of module | |
| JP3928694B2 (en) | Electronic circuit equipment | |
| JP6265459B2 (en) | Electronic component mounting structure | |
| JP3507444B2 (en) | One system module | |
| JPS6342531Y2 (en) | ||
| JP2016101071A (en) | Semiconductor device | |
| JP4103411B2 (en) | Power converter | |
| JP4385393B2 (en) | Connection structure between printed circuit board and heat sink | |
| JP3512013B2 (en) | Power supply for magnetron drive | |
| JP5034143B2 (en) | Power converter | |
| JP5669917B1 (en) | Power supply |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20041117 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20041124 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20041228 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20050126 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20050208 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090225 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100225 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110225 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120225 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120225 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130225 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140225 Year of fee payment: 9 |
|
| LAPS | Cancellation because of no payment of annual fees |