JPH09291323A - Metallic substrate material for semiconductor packaging - Google Patents

Metallic substrate material for semiconductor packaging

Info

Publication number
JPH09291323A
JPH09291323A JP8108232A JP10823296A JPH09291323A JP H09291323 A JPH09291323 A JP H09291323A JP 8108232 A JP8108232 A JP 8108232A JP 10823296 A JP10823296 A JP 10823296A JP H09291323 A JPH09291323 A JP H09291323A
Authority
JP
Japan
Prior art keywords
metal substrate
strength
semiconductor chip
thermal conductivity
copper alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8108232A
Other languages
Japanese (ja)
Inventor
Yasuo Tomioka
靖夫 富岡
Junji Miyake
淳司 三宅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nikko Kinzoku KK
Original Assignee
Nikko Kinzoku KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikko Kinzoku KK filed Critical Nikko Kinzoku KK
Priority to JP8108232A priority Critical patent/JPH09291323A/en
Publication of JPH09291323A publication Critical patent/JPH09291323A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the strength and thermal conductivity of a metallic substrate for a plastic package formed by sealing the semiconductor chips, bonded to a metallic substrate, with thermosetting resin. SOLUTION: The copper alloy has a composition consisting of 0.05-1.0% Cr, 0.03-0.8% Zr, and the balance Cu with inevitable impurities and containing, if necessary, (a) 0.01-1.0%, in total, of Ti, Ni, Sn, Fe, In, Mn, P, Mg and/or Si and (b) 0.01-2.0% Zn and/or containing (c) 0.05-1.8% Fe and (d) 0.05-0.8% Ti.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、銅合金からなる半
導体パッケージング用金属基板材料に関するものであ
り、さらに詳しく述べるならば、パッケージが半導体チ
ップを接着した金属基板と半導体チップを封止する熱硬
化性樹脂とからなり、金属基板の強度及び熱放散性が要
求されるパッケージの金属基板材料の改良に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal substrate material for semiconductor packaging, which is made of a copper alloy. More specifically, the package is a metal substrate to which a semiconductor chip is adhered and a heat for sealing the semiconductor chip. The present invention relates to an improvement of a metal substrate material of a package which is composed of a curable resin and which requires strength and heat dissipation of the metal substrate.

【０００２】[0002]

【従来の技術】半導体プラスチックパッケージの構造と
しては、以前はリード挿入実装デバイスであるＤＩＰ
（デュアルインラインパッケージ）が主流であったが、
実装密度の向上の要求から、表面実装デバイスであるＳ
ＯＰ（スモールアウトラインパッケージ）、ＱＦＰ（ク
ワッドフラットパッケージ）等が次第に主流になり、特
に入出力信号の増加に対応可能なＱＦＰは多用されてい
る。これらのパッケージにおいては通常リードフレーム
が使用され、チップをそのダイパット上に接着し樹脂に
より封止する場合が多い。2. Description of the Related Art As a structure of a semiconductor plastic package, a DIP which is a lead insertion mounting device was used before.
(Dual inline package) was the mainstream,
Due to the demand for higher packaging density, the S
OP (Small Outline Package), QFP (Quad Flat Package), etc. are gradually becoming the mainstream, and especially QFP which can cope with an increase in input / output signals is widely used. A lead frame is usually used in these packages, and the chip is often adhered onto the die pad and sealed with a resin.

【０００３】一方最近においてはＢＧＡ（ボールグリッ
ドアレイ）を始めるとする表面実装型のエリアパッケー
ジが開発され、マイクロプロセッサーあるいは高速のロ
ジック系の半導体用として採用されており、今後急速に
その用途が伸びると期待されている。そのエリアパッケ
ージにおいては半導体チップをプリント基板に接着する
場合、またＴＡＢ（テープオートメイティドボンディン
グ）の方式で実装する場合などの他に、放熱性の観点か
らチップを従来のセラミックではなく金属基板上に接着
するパッケージングがある。その一例を以下説明する。On the other hand, recently, surface mount type area packages such as BGA (ball grid array) have been developed and adopted for microprocessors or high-speed logic semiconductors, and their applications will grow rapidly in the future. Is expected. In the area package, in addition to the case where the semiconductor chip is bonded to the printed circuit board, the case where the chip is mounted by the TAB (tape automated bonding) method, the chip is mounted on the metal substrate instead of the conventional ceramic from the viewpoint of heat dissipation. There is packaging to adhere to. An example will be described below.

【０００４】図１及び図２はマイクロプロセッサー用プ
ラスチックパッケージの一例であり、パッケージ断面の
模式図を示す。図１はワイヤーボンディングを使ったＰ
ＧＡ（ピングリッドアレイ）およびＢＧＡであり、図２
はフリップチップ接続を使ったＢＧＡである。双方とも
にヒートスプレッダーと称される金属基板１に半導体チ
ップ２が接着されている（日経マイクロデバイス、１９
９６年４月号、９０〜９６頁より引用）。図中、３は封
止樹脂、４はプリント基板、５はピン、６はバンプ、７
はボンディングワイヤ、矢印は熱流である。図１、２に
示される金属基板１は半導体チップ担持と放熱機能をも
っている。金属基板１は放熱特性が通常の基板用セラミ
ックよりも優れていることを利用してプラスチックパッ
ケージに組み込まれているのである。1 and 2 show an example of a plastic package for a microprocessor, which is a schematic view of a cross section of the package. Figure 1 shows P using wire bonding
GA (pin grid array) and BGA, as shown in FIG.
Is a BGA using flip chip connection. A semiconductor chip 2 is adhered to a metal substrate 1 which is called a heat spreader (Nikkei Microdevice, 19
(Quoted from the April 1996 issue, pp. 90-96). In the figure, 3 is a sealing resin, 4 is a printed circuit board, 5 is a pin, 6 is a bump, 7
Is the bonding wire and the arrow is the heat flow. The metal substrate 1 shown in FIGS. 1 and 2 has a semiconductor chip support and a heat dissipation function. The metal substrate 1 is incorporated in the plastic package by utilizing the fact that the heat dissipation characteristic is superior to that of the usual ceramics for substrates.

【０００５】また、一方従来からのパッケージにおいて
も放熱性の観点からチップをリードフレームとは形状が
異なる金属基板上に接着する場合がある。このように従
来のパッケージとは異なり、いわゆるリードフレームで
はない金属基板上にチップを接着し封止するいくつもの
パッケージが提案され、実用化されている。On the other hand, in a conventional package, the chip may be adhered to a metal substrate having a shape different from that of the lead frame from the viewpoint of heat dissipation. Thus, unlike conventional packages, several packages have been proposed and put into practical use in which a chip is bonded and sealed on a metal substrate that is not a so-called lead frame.

【０００６】[0006]

【発明が解決しようとする課題】本発明者は、この種の
パッケージに今後課せられる要請につき次のように考察
した。まず前述の半導体チップから発生した熱を十分に
放散することが要求されるが、樹脂パッケージ材料の熱
放散性が改善されたことにより、上記パッケージが実用
化されたとの背景があり、しかも熱伝導性が一般的にす
ぐれた金属を熱放散媒体として使用することにより、か
なりの熱放散性が達成されているとの面はある。しかし
ながら、半導体チップの高集積化及び微細化により半導
体チップからの発熱量が一層多くなることが予想される
ので、半導体チップの裏面全体から放散される熱を如何
に効率的に放散するかとの観点からのサーマルマネージ
メントが重要になると考えられる。半導体チップから放
熱させるためには、接着している金属基板に十分な熱伝
導性があり、半導体チップと基板が十分に接合している
ことが必要であり、これらが欠けるとチップの温度上昇
が著しく、機能を損なう恐れがある。DISCLOSURE OF THE INVENTION The inventor of the present invention has considered the demands to be imposed on this type of package in the following manner. First, it is required to sufficiently dissipate the heat generated from the above-mentioned semiconductor chip, but there is the background that the above package has been put into practical use due to the improved heat dissipation of the resin package material. There is an aspect that a considerable heat dissipation property is achieved by using a metal having excellent properties as a heat dissipation medium. However, it is expected that the amount of heat generated from the semiconductor chip will increase due to the higher integration and miniaturization of the semiconductor chip. Therefore, it is necessary to efficiently dissipate the heat radiated from the entire back surface of the semiconductor chip. It is thought that the thermal management from will be important. In order to dissipate heat from the semiconductor chip, it is necessary that the adhered metal substrate has sufficient thermal conductivity and the semiconductor chip and the substrate are sufficiently bonded. If these are missing, the temperature of the chip will rise. Significantly, the function may be impaired.

【０００７】また一方ではパッケージング工程あるいは
作動中に伴う温度上昇にさらされる金属基板は、半導体
チップを接合する樹脂もしくは封止樹脂と熱膨張率が異
なるので、この結果金属基板内部に応力が発生し、金属
基板が微妙に変形する可能性があり、パッケージの信頼
性が損なわれる恐れがある。さらに組立加工中において
金属基板の材料強度が弱いと金属基板が平坦度を失うた
めに、樹脂との接着面が不完全になり放熱性や接着強度
が劣化する可能性もある。このようなことから、この金
属基板材料には十分な強度も要求される。On the other hand, the metal substrate exposed to a temperature rise during the packaging process or during operation has a different coefficient of thermal expansion from the resin or sealing resin for joining the semiconductor chips, and as a result, stress is generated inside the metal substrate. However, the metal substrate may be subtly deformed, and the reliability of the package may be impaired. Further, if the material strength of the metal substrate is weak during the assembly process, the metal substrate loses the flatness, so that the adhesive surface with the resin becomes incomplete and the heat dissipation and adhesive strength may deteriorate. For this reason, the metal substrate material is also required to have sufficient strength.

【０００８】本発明は、上述のような要請に対処してな
されたもので、パッケージの熱放散性に有利でしかも十
分な強度を有したＣｕ合金を用いて半導体パッケージを
提供することを目的としている。The present invention has been made in response to the above demands, and an object thereof is to provide a semiconductor package using a Cu alloy which is advantageous in heat dissipation of the package and has sufficient strength. There is.

【０００９】基板の性能の一つである熱伝導性はヴィー
デマン・フランツの法則により電気伝導度と正比例関係
をもっているために、多くの電気伝導度データより銅基
板の放熱特性を予測することができる。基板の他の性能
である強度を高めるためには、添加元素を加えれば良い
が、この場合電気伝導度が低下する。本発明の合金組成
はこのように一方の特性を向上すると他方は低下すると
の関係がある性質を高いレベルで両立するべく鋭意検討
した上で選定されたものである。Since the thermal conductivity, which is one of the performances of the substrate, has a direct proportional relationship with the electrical conductivity according to Wiedemann-Franz's law, it is possible to predict the heat dissipation characteristic of the copper substrate from many electrical conductivity data. . An additional element may be added in order to increase strength, which is another performance of the substrate, but in this case, the electric conductivity decreases. The alloy composition of the present invention was selected after careful investigation to achieve a high level of both properties in which one property is improved and the other is decreased.

【００１０】[0010]

【課題を解決するための手段】そこで、本発明者らは、
半導体チップを接着した金属基板とこれらを封止する熱
硬化性樹脂とからなるパッケージ（以下「樹脂封止パッ
ケージ」という）の金属基板として適する銅合金を開発
するための研究を重ねたところ、Ｃｕ−Ｃｒ−Ｚｒ系合
金の成分調整を行った上で、必要に応じてこれに（イ）
Ｚｎ，（ロ）Ｔｉ，Ｎｉ，Ｓｎ，Ｆｅ，Ｉｎ，Ｍｎ，
Ｐ，Ｍｇおよび／またはＳｎ，（ハ）Ｆｅおよび／また
はＴｉを含有させることで、樹脂封止パッケージング用
金属基板材料に好適な素材を提供できることを見出し
た。Means for Solving the Problems Accordingly, the present inventors have:
As a result of repeated research to develop a copper alloy suitable for a metal substrate of a package (hereinafter referred to as “resin-encapsulated package”) including a metal substrate to which a semiconductor chip is bonded and a thermosetting resin that seals these, Cu After adjusting the composition of the --Cr--Zr alloy, (a)
Zn, (b) Ti, Ni, Sn, Fe, In, Mn,
It has been found that by containing P, Mg and / or Sn, (c) Fe and / or Ti, a material suitable for a metal substrate material for resin-sealed packaging can be provided.

【００１１】本発明は、上記知見を基にして完成された
ものであり、銅合金においてＣｒを０．０５〜１．０重
量％（以下百分率は特に断らない限り重量％を意味す
る）は，Ｚｒを０．０３〜０．８％含有し、必要に応じ
て（ａ）Ｚｎを０．０１〜２．０％含有し、さらに必要
に応じて（ｂ）０．０５〜１．８％のＦｅおよび０．０
５〜０．８％のＴｉを含有し、さらに必要に応じて
（ｃ）Ｎｉ，Ｓｎ，Ｉｎ，Ｍｎ，Ｐ，ＭｇおよびＳｉの
うち１種以上を総量で０．０１〜１．０％を含有し、−
但し、（ｂ）の元素を含有させないときは（ｃ）にＦ
ｅ，Ｔｉを包含させることができる−残部がＣｕおよび
その不可避的不純物になるように調整することにより、
半導体パッケージング用基板材料として十分な熱伝導性
と強度を兼備せしめたことを特徴とする銅合金に関す
る。次に本発明において銅合金の成分組成を前記の如く
に限定した理由をその作用とともに説明する。The present invention has been completed on the basis of the above findings, and 0.05 to 1.0% by weight of Cr in copper alloys (the percentages below refer to% by weight unless otherwise specified), Zr content of 0.03 to 0.8%, (a) Zn content of 0.01 to 2.0%, and (b) 0.05 to 1.8% if necessary. Fe and 0.0
5 to 0.8% of Ti is added, and if necessary, (c) one or more of Ni, Sn, In, Mn, P, Mg and Si is added in a total amount of 0.01 to 1.0%. Contains, −
However, when the element of (b) is not contained, F is added to (c).
e, Ti can be included-by adjusting the balance to be Cu and its unavoidable impurities,
The present invention relates to a copper alloy which has sufficient thermal conductivity and strength as a substrate material for semiconductor packaging. Next, the reason why the component composition of the copper alloy is limited as described above in the present invention will be explained together with its action.

【００１２】Ｃｒ Ｃｒは、合金を溶体化処理後、時効させることにより母
相中に析出して強度を向上させる作用をするが、その含
有量が０．０５％未満では前記作用による所望の効果が
得られず、一方、１．０％を超えて含有させると導電率
が低下し、また加工性が劣化することから、Ｃｒ含有量
を０．０５〜１．０％と定めた。 Cr Cr has the function of precipitating in the mother phase by solution aging after solution treatment of the alloy and improving the strength, but if the content is less than 0.05%, the desired effect due to the above-mentioned effect is obtained. However, if the content exceeds 1.0%, the conductivity decreases and the workability deteriorates. Therefore, the Cr content is set to 0.05 to 1.0%.

【００１３】Ｚｒ Ｚｒには、時効処理によりＣｕと化合物を形成して母材
中に析出しこれを強化する作用および、耐熱性を向上す
る作用があるが、その含有量が０．０３％未満では前記
作用による所望の効果が得られず、一方０．８％を超え
てＺｒを含有させると、導電率が低下し、また加工性が
劣化することから、Ｚｒ含有量は０．０３〜０．８％と
定めた。 Zr Zr has a function of forming a compound with Cu by aging treatment to precipitate in the base material and strengthening it, and a function of improving heat resistance, but the content thereof is less than 0.03%. However, the desired effect due to the above-mentioned action cannot be obtained, and when Zr is contained in excess of 0.8%, the conductivity decreases and the workability deteriorates. Therefore, the Zr content is 0.03 to 0. It was set at 8%.

【００１４】Ｚｎ Ｚｎは、半田の耐熱剥離性を向上させる作用を有してい
るため必要により添加される成分であるが、その含有量
が０．０１％未満では前記作用による所望の効果が得ら
れず、一方２．０％を超えてＺｎを含有させると導電率
が劣化することから、Ｚｎ含有量は０．０１〜２．０％
と定めた。 Zn Zn is a component added as necessary because it has an effect of improving the heat-resistant peeling property of the solder, but if the content is less than 0.01%, the desired effect due to the above-mentioned effect can be obtained. However, if the Zn content exceeds 2.0%, the conductivity deteriorates. Therefore, the Zn content is 0.01 to 2.0%.
It was decided.

【００１５】ＴｉおよびＦｅ ＴｉおよびＦｅは、合金を時効処理した時に母相中にＴ
ｉとＦｅとの金属間化合物を形成し、その結果として合
金強度をさらに向上させる作用を発揮するため、必要に
応じて添加されるが、これらの含有量がそれぞれ０．０
５％未満では前記作用による所望の効果が得られない。
一方、Ｔｉ含有量が０．８％を超えたり、Ｆｅ含有量が
１．８％を超える場合には、導電率が低下する。このた
め、Ｆｅの含有量を０．０５〜１．８％、Ｔｉの含有量
を０．０５〜０．８％と定めた。 Ti and Fe Ti and Fe are T in the matrix when the alloy is aged.
It forms an intermetallic compound of i and Fe, and as a result, exerts an action of further improving the alloy strength, so that it is added as necessary, but the content of each of them is 0.0
If it is less than 5%, the desired effect due to the above action cannot be obtained.
On the other hand, when the Ti content exceeds 0.8% or the Fe content exceeds 1.8%, the conductivity decreases. Therefore, the Fe content is set to 0.05 to 1.8% and the Ti content is set to 0.05 to 0.8%.

【００１６】Ｎｉ，Ｓｎ，Ｉｎ，Ｍｎ，Ｐ，Ｍｇおよび
Ｓｉ これらの成分は、何れも合金の導電性を大きく低下させ
ずに主として固溶強化により強度を向上させる作用を有
しており、従って必要により１種または２種以上の添加
がなされるが、その含有量が総量で０．０１％未満であ
ると前記作用による所望の効果が得られず、一方、総量
で１．０％を超える含有量になると合金の導電性および
加工性を著しく劣化する。このため、単独添加或いは２
種以上の複合添加がなされるＮｉ，Ｓｎ，Ｉｎ，Ｍｎ，
Ｐ，ＭｇおよびＳｉの含有量は総量で０．０１〜１．０
％と定めた。 Ni, Sn, In, Mn, P, Mg and
Si Each of these components has the effect of mainly improving the strength by solid solution strengthening without significantly reducing the conductivity of the alloy, and therefore, if necessary, one kind or two or more kinds are added, If the total content is less than 0.01%, the desired effect due to the above-mentioned action cannot be obtained, while if the total content exceeds 1.0%, the conductivity and workability of the alloy are significantly deteriorated. . For this reason, single addition or 2
Ni, Sn, In, Mn, to which more than one kind of compound is added
The total content of P, Mg and Si is 0.01 to 1.0
%.

【００１７】本発明に係る金属基板に要求される強度
は、（イ）段落番号０００７で説明した耐変形性の他
に、（ロ）基板の薄肉化などを実現するための性能であ
り、引張強さの大小によりこれらを評価することができ
る。そして、好ましい引張強さは５５０Ｎ／ｍｍ2 以上
である。一方、熱伝導性の指標となる導電率は６０％Ｉ
ＡＣＳ以上であることが好ましい。次に、素材の調質状
態は時効処理状態である必要はあるが、最終仕上げ状態
は、時効処理仕上げ、冷間圧延仕上げ、歪取り焼鈍仕上
げの何れでもよい。以下、実施例により本発明をさらに
詳しく説明する。The strength required for the metal substrate according to the present invention is, in addition to the deformation resistance described in (a) Paragraph No. 0007, (b) the performance for realizing the thinning of the substrate and the like. These can be evaluated by the magnitude of strength. The preferred tensile strength is 550 N / mm 2 or more. On the other hand, the conductivity, which is an index of thermal conductivity, is 60% I.
It is preferably ACS or more. Next, the tempering state of the material needs to be an aging treatment state, but the final finishing state may be any of an aging treatment finish, a cold rolling finish, and a strain relief annealing finish. Hereinafter, the present invention will be described in more detail with reference to examples.

【００１８】[0018]

【実施例】高周波溶解炉にて図３、４（表１−１、２）
に示す各種成分組成の銅合金を溶製し、厚さ２０ｍｍの
インゴットに鋳造した。なお、溶解鋳造は真空中または
Ａｒ雰囲気中で実施した。次に、このインゴットを９５
０℃で１時間均質焼鈍してから熱間圧延、面削、冷間圧
延を行い、厚さが１．５ｍｍの板とした。その後、９０
０℃の温度で１０分間の加熱後水冷を行って結晶粒径を
約２０〜４０μｍに調整し、さらに冷間圧延で厚さ０．
３ｍｍの板した後、４００で４時間の時効を行った。そ
の後、さらに冷間圧延により厚さ０．２５ｍｍの板を得
た。[Examples] Figures 3 and 4 in a high-frequency melting furnace (Tables 1-1 and 2)
Copper alloys having various component compositions shown in Table 1 were melted and cast into an ingot having a thickness of 20 mm. The melt casting was performed in a vacuum or an Ar atmosphere. Next, this ingot 95
After homogeneous annealing at 0 ° C. for 1 hour, hot rolling, surface cutting and cold rolling were performed to obtain a plate having a thickness of 1.5 mm. Then 90
After heating at a temperature of 0 ° C. for 10 minutes, water cooling is performed to adjust the crystal grain size to about 20 to 40 μm, and further, the thickness is adjusted to 0.
After a plate of 3 mm, it was aged at 400 for 4 hours. Then, the plate having a thickness of 0.25 mm was obtained by further cold rolling.

【００１９】このようにして得られた各板材につき諸特
性の評価を行った。引張強さおよび伸びの測定には、Ｊ
ＩＳ１３号引張試験片を用いて圧延平行方向の引張試験
を行った。熱伝導性は導電率の値で評価することとし、
４端子法で固有抵抗を測定し、それを用いて導電率（％
ＩＡＣＳ）を求めた。参考までに求めためっき耐熱剥離
性は供試材に０．５〜０．８μｍの銅下地めっきを施し
た後、１〜１．５μｍの６０％Ｓｎ−４０％Ｐｂ半田を
電気めっきした後、リフロー処理したものについて幅１
０ｍｍ、長さ１００ｍｍに切断後１５０℃にて所定時間
（１００時間毎）加熱し、曲げ半径０．２５ｍｍ（＝板
厚）で片側の９０°曲げを往復１回行い、２０倍の視野
で表裏面の曲げ部近傍を観察しめっき剥がれの有無を確
認した。耐熱性の評価は、種々の温度で５分間の加熱を
行い、ビッカース硬さが加熱前の１／２になる温度を半
軟化温度として求めた。Various characteristics of each plate material thus obtained were evaluated. For the measurement of tensile strength and elongation, J
A tensile test in the rolling parallel direction was performed using IS13 tensile test pieces. Thermal conductivity is to be evaluated by the value of conductivity,
The specific resistance is measured by the 4-terminal method, and the conductivity (%
IACS) was determined. The heat-resistant peeling resistance obtained as a reference is obtained by subjecting the test material to copper undercoating of 0.5 to 0.8 μm, and then electroplating 1 to 1.5 μm of 60% Sn-40% Pb solder, Width 1 for reflowed products
After cutting it to 0 mm and 100 mm length, it is heated at 150 ° C for a predetermined time (every 100 hours), and 90 ° bending on one side is performed once with a bending radius of 0.25 mm (= plate thickness), and a 20-fold field of view is displayed. The vicinity of the bent portion on the back surface was observed to confirm the presence or absence of peeling of the plating. The heat resistance was evaluated by heating at various temperatures for 5 minutes, and the temperature at which the Vickers hardness became 1/2 that before heating was determined as the semi-softening temperature.

【００２０】表１−１、２からわかるように、本発明合
金は、強度、導電率および耐熱性にも優れていることが
分かる。一方、比較合金Ｎｏ．１はＣｒ含有量が低いた
めに強度が劣り、比較合金Ｎｏ．２はＺｒを含有してい
ないため耐熱性及び強度が劣る。比較合金Ｎｏ．３はＣ
ｒ含有量が、比較合金Ｎｏ．４はＺｒが、比較合金Ｎ
ｏ．５はＺｎが、それぞれ高いために導電率が劣る。比
較合金Ｎｏ．８は副成分の含有量の合計が本発明の範囲
を越えるため導電率が劣る。また比較合金Ｎｏ．６はＦ
ｅ含有量が、比較合金Ｎｏ．７はＴｉ含有量が高いため
に導電率が劣る。As can be seen from Tables 1-1 and 2, the alloy of the present invention is excellent in strength, conductivity and heat resistance. On the other hand, Comparative Alloy No. No. 1 was inferior in strength because the Cr content was low, and Comparative Alloy No. Since No. 2 does not contain Zr, it has poor heat resistance and strength. Comparative alloy No. 3 is C
The r content is comparative alloy No. No. 4 is Zr, comparative alloy N
o. In No. 5, since Zn is high, the conductivity is inferior. Comparative alloy No. In No. 8, since the total content of subcomponents exceeds the range of the present invention, the conductivity is poor. In addition, comparative alloy No. 6 is F
The content of e is comparative alloy No. No. 7 is inferior in conductivity because of high Ti content.

【００２１】[0021]

【発明の効果】以上説明したように本発明の銅合金は、
優れた熱伝導性と強度、さらには優れためっき耐熱剥離
性をも有し、樹脂封止パッケージング用金属基板材料と
して好適である。As described above, the copper alloy of the present invention is
It has excellent thermal conductivity and strength as well as excellent plating heat resistance peeling property, and is suitable as a metal substrate material for resin-sealed packaging.

【図面の簡単な説明】[Brief description of drawings]

【図１】プラスチック封止パッケージ断面の模式図であ
る。FIG. 1 is a schematic view of a cross section of a plastic sealed package.

【図２】プラスチック封止パッケージ断面の模式図であ
る。FIG. 2 is a schematic view of a cross section of a plastic sealed package.

【図３】本発明の合金組成及び特性を示す図表（表１−
１）である。FIG. 3 is a chart showing the alloy composition and properties of the present invention (Table 1-
1).

【図４】比較例の合金組成及び特性を示す図表（表１−
２）である。FIG. 4 is a chart showing the alloy composition and characteristics of a comparative example (Table 1-
2).

【符号の説明】[Explanation of symbols]

１ ヒートスプレッダ（金属基板） ２ 半導体チップ ３ 封止樹脂 ４ プリント基板 ５ ピン ６ 半田バンプ ７ ボンディングワイヤー 1 heat spreader (metal substrate) 2 semiconductor chip 3 sealing resin 4 printed circuit board 5 pins 6 solder bumps 7 bonding wire

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 金属基板上に接着された半導体チップを
熱硬化性樹脂により封止してなるプラスチックパッケー
ジの該金属基板の材料が、重量割合で、Ｃｒ：０．０５
〜１．０％，Ｚｒ：０．０３〜０．８％を含有し、残部
がＣｕおよびその不可避的不純物からなり、熱伝導性お
よび強度に優れた銅合金からなることを特徴とする半導
体パッケージング用金属基板材料。1. A material of the metal substrate of a plastic package obtained by sealing a semiconductor chip adhered on the metal substrate with a thermosetting resin is Cr: 0.05 in weight ratio.
To 1.0%, Zr: 0.03 to 0.8%, and the balance being Cu and its unavoidable impurities, and a copper alloy excellent in thermal conductivity and strength. Metal substrate material for welding. 【請求項２】 金属基板上に接着された半導体チップを
熱硬化性樹脂により封止してなるプラスチックパッケー
ジの該金属基板の材料が、重量割合で、Ｃｒ：０．０５
〜１．０％，Ｚｒ：０．０３〜０．８％を含有すると共
に、Ｔｉ，Ｎｉ，Ｓｎ，Ｆｅ，Ｉｎ，Ｍｎ，Ｐ，Ｍｇお
よびＳｉの１種以上：総量で０．０１〜１．０％をも含
有し、残部がＣｕおよびその不可避的不純物からなり、
熱伝導性および強度に優れた銅合金からなることを特徴
とする半導体パッケージング用金属基板材料。2. The material of the metal substrate of a plastic package obtained by sealing a semiconductor chip bonded on a metal substrate with a thermosetting resin is Cr: 0.05 in weight ratio.
.About.1.0%, Zr: 0.03 to 0.8% and at least one of Ti, Ni, Sn, Fe, In, Mn, P, Mg and Si: 0.01 to 1 in total amount 0.0%, the balance consisting of Cu and its unavoidable impurities,
A metal substrate material for semiconductor packaging, comprising a copper alloy having excellent thermal conductivity and strength. 【請求項３】 金属基板上に接着された半導体チップを
熱硬化性樹脂により封止してなるプラスチックパッケー
ジの該金属基板の材料が、重量割合で、Ｃｒ：０．０５
〜１．０％，Ｚｒ：０．０３〜０．８％，Ｚｎ：０．０
１〜２．０％を含有し、残部がＣｕおよびその不可避的
不純物からなり、熱伝導性および強度に優れた銅合金か
らなることを特徴とする半導体パッケージング用金属基
板材料。3. A material of the metal substrate of a plastic package obtained by sealing a semiconductor chip adhered on the metal substrate with a thermosetting resin is Cr: 0.05 in weight ratio.
~ 1.0%, Zr: 0.03 to 0.8%, Zn: 0.0
A metal substrate material for semiconductor packaging, containing 1 to 2.0%, the balance being Cu and unavoidable impurities thereof, and a copper alloy having excellent thermal conductivity and strength. 【請求項４】 金属基板上に接着された半導体チップを
熱硬化性樹脂により封止してなるプラスチックパッケー
ジにおいて、該金属基板の材料が、重量割合で、Ｃｒ：
０．０５〜１．０％，Ｚｒ：０．０３〜０．８％，Ｚ
ｎ：０．０１〜２．０％を含有すると共に、Ｔｉ，Ｎ
ｉ，Ｓｎ，Ｆｅ，Ｉｎ，Ｍｎ，Ｐ，ＭｇおよびＳｉの１
種以上：総量で０．０１〜１．０％をも含有し、残部が
Ｃｕおよびその不可避的不純物からなり、熱伝導性およ
び強度に優れた銅合金からなることを特徴とする半導体
パッケージング用金属基板材料。4. A plastic package obtained by encapsulating a semiconductor chip adhered on a metal substrate with a thermosetting resin, wherein the material of the metal substrate is Cr:
0.05-1.0%, Zr: 0.03-0.8%, Z
n: 0.01 to 2.0%, Ti, N
i, Sn, Fe, In, Mn, P, Mg and Si 1
Species or above: 0.01 to 1.0% in total, with the balance being Cu and its unavoidable impurities, and a copper alloy having excellent thermal conductivity and strength, for semiconductor packaging. Metal substrate material. 【請求項５】 金属基板上に接着された半導体チップを
熱硬化性樹脂により封止してなるプラスチックパッケー
ジにおいて、該金属基板の材料が、重量割合で、Ｃｒ：
０．０５〜１．０％，Ｚｒ：０．０３〜０．８％，Ｚ
ｎ：０．０１〜２．０％，Ｆｅ：０．０５〜１．８％，
Ｔｉ：０．０５〜０．８％を含有し、残部がＣｕおよび
その不可避的不純物からなり、熱伝導性および強度に優
れた銅合金からなることを特徴とする半導体パッケージ
ング用金属基板材料。5. A plastic package obtained by encapsulating a semiconductor chip adhered on a metal substrate with a thermosetting resin, wherein the material of the metal substrate is Cr:
0.05-1.0%, Zr: 0.03-0.8%, Z
n: 0.01 to 2.0%, Fe: 0.05 to 1.8%,
A metal substrate material for semiconductor packaging, characterized by containing Ti: 0.05 to 0.8%, the balance being Cu and inevitable impurities thereof, and a copper alloy having excellent thermal conductivity and strength. 【請求項６】 金属基板上に接着された半導体チップを
熱硬化性樹脂により封止してなるプラスチックパッケー
ジにおいて、該金属基板の材料が、重量割合で、Ｃｒ：
０．０５〜１．０％，Ｚｒ：０．０３〜０．８％，Ｚ
ｎ：０．０１〜２．０％，Ｆｅ：０．０５〜１．８％，
Ｔｉ：０．０５〜０．８％を含有するとともに、Ｎｉ，
Ｓｎ，Ｉｎ，Ｍｎ，Ｐ，ＭｇおよびＳｉの１種以上：総
量で０．０１〜１．０％をも含有し、残部がＣｕおよび
その不可避的不純物からなり、熱伝導性および強度に優
れた銅合金からなることを特徴とする半導体パッケージ
ング用金属基板材料。6. A plastic package obtained by encapsulating a semiconductor chip adhered on a metal substrate with a thermosetting resin, wherein the material of the metal substrate is Cr:
0.05-1.0%, Zr: 0.03-0.8%, Z
n: 0.01 to 2.0%, Fe: 0.05 to 1.8%,
Ti: contains 0.05 to 0.8%, and Ni,
One or more of Sn, In, Mn, P, Mg and Si: Contains 0.01 to 1.0% in total, the balance being Cu and its unavoidable impurities, and excellent in thermal conductivity and strength. A metal substrate material for semiconductor packaging, which is made of a copper alloy.
JP8108232A 1996-04-26 1996-04-26 Metallic substrate material for semiconductor packaging Pending JPH09291323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8108232A JPH09291323A (en) 1996-04-26 1996-04-26 Metallic substrate material for semiconductor packaging

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8108232A JPH09291323A (en) 1996-04-26 1996-04-26 Metallic substrate material for semiconductor packaging

Publications (1)

Publication Number Publication Date
JPH09291323A true JPH09291323A (en) 1997-11-11

Family

ID=14479421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8108232A Pending JPH09291323A (en) 1996-04-26 1996-04-26 Metallic substrate material for semiconductor packaging

Country Status (1)

Country Link
JP (1) JPH09291323A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6344171B1 (en) 1999-08-25 2002-02-05 Kobe Steel, Ltd. Copper alloy for electrical or electronic parts
CN113718128A (en) * 2021-08-30 2021-11-30 宁波金田铜业(集团)股份有限公司 Copper-chromium-zirconium alloy and preparation method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6344171B1 (en) 1999-08-25 2002-02-05 Kobe Steel, Ltd. Copper alloy for electrical or electronic parts
CN113718128A (en) * 2021-08-30 2021-11-30 宁波金田铜业(集团)股份有限公司 Copper-chromium-zirconium alloy and preparation method thereof
CN113718128B (en) * 2021-08-30 2022-06-28 宁波金田铜业(集团)股份有限公司 Copper-chromium-zirconium alloy and preparation method thereof

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