JPH09283589A - Method and apparatus for processing substrate - Google Patents
Method and apparatus for processing substrateInfo
- Publication number
- JPH09283589A JPH09283589A JP8085106A JP8510696A JPH09283589A JP H09283589 A JPH09283589 A JP H09283589A JP 8085106 A JP8085106 A JP 8085106A JP 8510696 A JP8510696 A JP 8510696A JP H09283589 A JPH09283589 A JP H09283589A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- substrate
- processing
- chamber
- wafers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/46—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
- C23C16/463—Cooling of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Materials Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Chemical Vapour Deposition (AREA)
- Drying Of Semiconductors (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体基板等の基
板を処理する方法及び処理装置に係り、特に枚葉処理方
式の基板処理方法及び処理装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a processing apparatus for processing a substrate such as a semiconductor substrate, and more particularly to a single wafer processing type substrate processing method and a processing apparatus.
【０００２】[0002]
【従来の技術】シリコンウエハなどの半導体基板を高温
（〜９００℃以上）に加熱しながら水分や酸素などの酸
化性ガスを供給し、表面反応により酸化膜を形成する熱
酸化プロセス、同様に高温度を加えながら熱処理して表
面の高濃度の不純物を内部に熱拡散する不純物拡散プロ
セス、さらに反応性ガスを供給しウエハ表面を気相化学
反応によりエッチするドライエッチングプロセス、ま
た、気相化学反応により薄膜をウエハ表面に堆積するＣ
ＶＤ（Chemical Vapor Deposition）プロセスなどは半
導体素子製造の重要なプロセスである。これまで前述の
プロセスは、大量の処理が可能でプロセスコストを小さ
くできると言う理由で、主として反応チャンバに多数の
ウエハを収納し処理する、所謂バッチ処理方式の半導体
処理装置で実施されている。2. Description of the Related Art A thermal oxidation process in which a semiconductor substrate such as a silicon wafer is heated to a high temperature (up to 900 ° C. or higher) and an oxidizing gas such as water or oxygen is supplied to form an oxide film by a surface reaction. Impurity diffusion process that thermally diffuses high concentration impurities on the surface by heat treatment while applying temperature, dry etching process that supplies reactive gas and etches the wafer surface by vapor phase chemical reaction, and vapor phase chemical reaction To deposit a thin film on the wafer surface by C
The VD (Chemical Vapor Deposition) process is an important process for manufacturing semiconductor devices. Up to now, the above-mentioned process has been mainly carried out in a so-called batch processing type semiconductor processing apparatus in which a large number of wafers are housed and processed in a reaction chamber because a large amount of processing can be performed and the process cost can be reduced.
【０００３】近年、益々大型化するウエハ径（８インチ
以上）への対応やウエハ・チャージ数の増大による生産
性の向上を目的とし、前述いずれのプロセスにおいても
処理室（反応室）の大型化が進められている。しかしな
がら、ウエハを水平に多段積載し大口径ウエハを大量に
チャージする方法では全てのウエハに対する均一処理が
非常に困難となり、また、ウエハを平面的に多数並べ処
理する方法では大型化の効果は小さくなってきている。In recent years, the size of the processing chamber (reaction chamber) has been increased in any of the above processes in order to cope with the ever-increasing wafer diameter (8 inches or more) and to improve the productivity by increasing the number of wafer charges. Is being promoted. However, it is very difficult to uniformly process all the wafers by the method of horizontally stacking the wafers in multiple stages and charging a large-diameter wafer in a large amount, and the method of arranging a large number of wafers in a plane has a small effect of increasing the size. It has become to.
【０００４】前述のプロセスに比べ比較的高温で処理
し、単結晶基板ウエハの上に基板と同じ方位をもつシリ
コン単結晶薄膜を気相化学反応で形成するシリコンエピ
タキシャル（epitaxial）成長技術も、半導体素子製造
における主要なプロセスである。従来、エピタキシャル
成長は石英製反応室内の回転する円盤状の加熱台（サセ
プタ）に基板ウエハを平面的に並べて高温（〜１０００
℃）に加熱し、原料のシリコン化合物ガスをサセプタ中
心の供給管から放射状に供給する方式（パンケーキ型エ
ピタキシャル炉）で行われている。また、加熱台を角錐
状とし、ウエハを平面的に並べてチャージ数を増やし
た、所謂バレル型と呼ばれるエピタキシャル成長炉も用
いられている。The silicon epitaxial growth technique, in which a silicon single crystal thin film having the same orientation as the substrate is formed on the single crystal substrate wafer by a vapor phase chemical reaction, which is processed at a relatively high temperature as compared with the above-mentioned process, is also a semiconductor. This is the main process in device manufacturing. Conventionally, the epitaxial growth is performed by arranging the substrate wafers on a rotating disk-shaped heating table (susceptor) in a quartz reaction chamber in a plane and at a high temperature (up to 1000).
(C)) and the raw material silicon compound gas is radially supplied from a supply pipe in the center of the susceptor (pancake type epitaxial furnace). Further, there is also used an epitaxial growth furnace of a so-called barrel type in which the heating table has a pyramid shape and the wafers are arranged in a plane to increase the number of charges.
【０００５】いずれの方式も加熱台上にウエハを平面的
に並べ処理する方式で、その大型化も限界に近く、さら
に、サセプタの大型化は熱容量の増大を招き昇降温のプ
ロセス時間も長くなり、この点からも生産性（単位時間
当たりのウエハ生産数：スループット）の向上効果を小
さくしている。さらに、大型サセプタの全ての領域に対
して原料ガスを均一供給することも困難となり、回転な
どの方法でこの不均一を補償しても、サセプタ全領域の
ウエハのエピタキシャル層膜厚や抵抗率を均一にするこ
とは非常に困難となっている。Each of the methods is a method in which wafers are arranged in a plane on a heating table, and the size increase is almost at the limit. Furthermore, the increase in the size of the susceptor causes an increase in heat capacity and a longer process time for raising and lowering temperature. Also from this point, the effect of improving productivity (the number of wafers produced per unit time: throughput) is reduced. Furthermore, it becomes difficult to supply the source gas uniformly to all areas of the large susceptor, and even if this non-uniformity is compensated by a method such as rotation, the epitaxial layer film thickness and resistivity of the wafer in all areas of the susceptor can be compensated. It is very difficult to make it uniform.
【０００６】近年、半導体プロセスの大口径化、高精度
化に伴う前述した問題点を解消する方策の一つとして、
特開平６−２９３５９５号公報又は特開平７−９４４１
９号公報などに記載された枚葉処理方式の半導体処理装
置が提案されている。この方法は、基板ウエハを１枚、
または２枚ずつ処理することから大口径ウエハの処理の
均一性確保は容易である。In recent years, as one of the measures to solve the above-mentioned problems associated with the increase in diameter and precision of semiconductor processes,
JP-A-6-293595 or JP-A-7-9441
A single-wafer processing type semiconductor processing apparatus described in Japanese Patent Publication No. 9 and the like has been proposed. This method uses one substrate wafer,
Alternatively, since the two wafers are processed at a time, it is easy to secure the processing uniformity of the large diameter wafer.
【０００７】しかしながら、枚葉処理方式は１バッチの
処理数が少なく原理的にスループットが小さい。このた
め、プロセス時間の短縮、ウエハ搬送などの操作の自動
化、加熱や膜厚の均一性確保が可能な２枚程度までのチ
ャージ・ウエハ数の増大、更に一つのウエハ搬送装置の
廻りに処理室チャンバを複数設置するマルチ化などの対
策によるスループットの増大が図られている。However, in the single-wafer processing method, the number of processings in one batch is small and the throughput is theoretically small. For this reason, the process time is shortened, the operations such as wafer transfer are automated, the number of charged wafers is increased up to about 2 which can ensure the uniformity of heating and film thickness, and the processing chambers around one wafer transfer device are increased. Throughput is being increased by taking measures such as multi-setting in which a plurality of chambers are installed.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、上記従
来技術では、チャンバのマルチ化によってもスループッ
トの大幅な増大を達成できないという難点がある。図８
は、熱酸化をチャンバを３室にマルチ化した枚葉処理方
式熱処理装置により実施する場合のプロセス・シーケン
スの一例の説明図である。図中の横軸は時間軸である。However, the above-mentioned conventional technique has a drawback in that a large increase in throughput cannot be achieved even by using multiple chambers. FIG.
FIG. 4 is an explanatory diagram of an example of a process sequence in the case where thermal oxidation is performed by a single-wafer processing heat treatment apparatus having multiple chambers. The horizontal axis in the figure is the time axis.
【０００９】プロセスは、ウエハを処理室に挿入し、酸
化性の雰囲気中で熱処理する工程、及び樹脂製のウエハ
カセットの変形を防ぐため熱処理を終えた高温のウエハ
を冷却する冷却工程で構成されている。一つのウエハ搬
送装置（ロボット）の稼働（図中の太い矢印）を有効に
利用して３つのチャンバのプロセスを完了することで高
いスループットが得られる。このプロセスにおいてスル
ープットを更に増大するには、熱処理工程や冷却工程時
間を短縮し、全体のプロセス時間を短縮することが重要
である。しかしながら、ウエハ冷却が１つのチャンバで
実施されることから、ウエハ搬送装置（ロボット）の稼
働以外にも、冷却工程がそれぞれのチャンバの工程の自
由度を制約し、結局装置全体のプロセス時間の短縮を困
難とし、スループット増大の目的を達成できない。熱酸
化チャンバそれぞれに対応した冷却チャンバ（冷却室）
を設ける方法で冷却工程の制約を解消する方策は、装置
の大型化と高額化を招き得策とは言えない。The process comprises a step of inserting a wafer into a processing chamber and heat-treating it in an oxidizing atmosphere, and a cooling step of cooling a high-temperature wafer that has been heat-treated to prevent deformation of a resin wafer cassette. ing. High throughput can be obtained by effectively utilizing the operation of one wafer transfer device (robot) (thick arrow in the figure) to complete the process of three chambers. In order to further increase the throughput in this process, it is important to shorten the heat treatment process and the cooling process time and shorten the overall process time. However, since the wafer is cooled in one chamber, the cooling process restricts the process flexibility of each chamber in addition to the operation of the wafer transfer device (robot), and eventually the process time of the entire device is shortened. It is difficult to achieve the objective of increasing throughput. Cooling chamber (cooling chamber) corresponding to each thermal oxidation chamber
The method of eliminating the restriction of the cooling process by the method of providing the above method cannot be said to be a promising measure because it causes an increase in the size and cost of the device.
【００１０】図９は、成長チャンバを３室にマルチ化し
た枚葉処理方式エピタキシャル成長装置のプロセス・シ
ーケンスの一例の説明図である。エピタキシャル成長の
場合、プロセスは、基板ウエハを反応室に挿入してエピ
タキシャル層を形成する成長工程とウエハの冷却工程の
外、成長後反応室に析出した不要のシリコンを気相エッ
チングにより除去して清浄化するクリーニング工程が増
える。一般に、シリコンエピタキシャル成長のような１
０００℃以上の高温度の反応ではウエハ冷却の工程時間
が長く、装置全体のプロセス時間に対する冷却工程の影
響はより大きい。本発明は前述した問題点を解消し、ス
ループットの大きな枚葉処理方式の半導体処理方法及び
処理装置を提供することを目的とする。FIG. 9 is an explanatory view of an example of a process sequence of a single wafer processing type epitaxial growth apparatus in which the growth chamber is multi-chambered. In the case of epitaxial growth, the process is a clean process by removing unnecessary silicon deposited in the reaction chamber after growth by vapor phase etching, in addition to the growth process of inserting the substrate wafer into the reaction chamber and forming the epitaxial layer and the cooling process of the wafer. The number of cleaning steps to be changed increases. Generally, one such as silicon epitaxial growth
In the case of a reaction at a high temperature of 000 ° C. or higher, the process time for cooling the wafer is long, and the influence of the cooling process on the process time of the entire apparatus is greater. An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor processing method and a processing apparatus of a single-wafer processing system having a large throughput.
【００１１】[0011]
【課題を解決するための手段】本発明は、単一の搬送手
段を備える基板搬送室に、各々ｎ（ｎ≧１）枚の基板を
収納して高温処理できるｍ（ｍ≧２）個の処理室と１個
の冷却室とが連結されている基板処理装置を用いて、搬
送手段によりカセットに収納された基板を処理室に順次
挿入して処理する工程と、処理後の高温の基板を搬送手
段により冷却室に収納して冷却する工程とを含む基板の
処理方法において、冷却室に高温の基板をｎ×ｍ枚以上
収納して冷却することを特徴とするものである。According to the present invention, n (n ≧ 1) substrates can be housed in a substrate transfer chamber provided with a single transfer means and m (m ≧ 2) substrates can be processed at high temperature. Using the substrate processing apparatus in which the processing chamber and one cooling chamber are connected, a step of sequentially inserting the substrates housed in the cassette by the transfer means into the processing chamber for processing, and the high temperature substrate after processing In a method of processing a substrate, including a step of storing the substrate in a cooling chamber by a transfer means and cooling the substrate, n × m or more high-temperature substrates are stored in the cooling chamber and cooled.
【００１２】処理室は、シリコン基板等の基板を加熱処
理して酸化膜や不純物拡散層を形成する加熱処理室とす
ることができる。また、処理室は、シリコン基板等の基
板を加熱し、原料ガスを供給してシリコンのエピタキシ
ャル成長層、例えばＣＶＤ膜を形成する反応室であって
もよい。The treatment chamber may be a heat treatment chamber in which a substrate such as a silicon substrate is heat-treated to form an oxide film and an impurity diffusion layer. Further, the processing chamber may be a reaction chamber in which a substrate such as a silicon substrate is heated and a source gas is supplied to form a silicon epitaxial growth layer, for example, a CVD film.
【００１３】また、本発明は、単一の搬送手段を備える
基板搬送室に、各々ｎ（ｎ≧１）枚の基板を収納して高
温処理できるｍ（ｍ≧２）個の処理室と１個の冷却室と
を連結した基板の処理装置において、冷却室はｎ×ｍ枚
以上の基板を収納できることを特徴とするものである。
処理室は、基板に酸化膜又は不純物拡散層を形成する熱
処理を行う処理室、あるいは、基板を加熱し、原料ガス
を供給して基板にエピタキシャル成長層、例えばＣＶＤ
膜を形成する反応室とすることができる。Further, according to the present invention, m (m ≧ 2) processing chambers capable of high temperature processing by accommodating n (n ≧ 1) substrates each in a substrate transfer chamber provided with a single transfer means and 1 In the substrate processing apparatus connected to the individual cooling chambers, the cooling chamber can store n × m or more substrates.
The processing chamber is a processing chamber for performing a heat treatment for forming an oxide film or an impurity diffusion layer on the substrate, or heating the substrate and supplying a source gas to form an epitaxial growth layer on the substrate, for example, CVD.
It can be a reaction chamber for forming a film.
【００１４】冷却室は、すでに冷却室に収納されて冷却
中の基板に対して後から収納された高温の基板が与える
影響を軽減するために、収納する基板を少なくともｎ枚
ずつ仕切る仕切板を設けてもよい。本発明によれば、処
理室から搬送装置により順次取り出される処理を完了し
た高温状態のウエハ全てを一つの冷却室において冷却す
ることが可能となり、装置全体のプロセス時間に対する
冷却工程の影響を小さくできる。The cooling chamber is provided with a partition plate for partitioning at least n substrates to be stored in order to reduce the influence of a high temperature substrate which has been already stored in the cooling chamber and is being cooled. It may be provided. According to the present invention, it becomes possible to cool all the wafers in the high temperature state, which have undergone the processing sequentially taken out from the processing chamber by the transfer device, in one cooling chamber, and reduce the influence of the cooling step on the process time of the entire apparatus. .
【００１５】[0015]
【発明の実施の形態】以下、本発明の実施の形態を図面
を参照して詳細に説明する。図１は、本発明の枚葉処理
方式の熱酸化装置の一例を説明する平面略図である。装
置の中央部にウエハ搬送装置４を備えた六角形状の搬送
室３が設けられている。そして搬送室３の廻りには、処
理前のウエハ（基板ウエハ）２を加熱しながら酸化性ガ
スを供給して酸化膜を形成する３室の処理室１、酸化膜
の形成を終え反応室から取り出された高温の酸化膜形成
ウエハ２１を収納して冷却するウエハ冷却室５、基板ウ
エハ２及び酸化膜形成ウエハ２１をそれぞれのカセット
７に収納する２室のカセット室６が機能的に配置されて
いる。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic plan view illustrating an example of a single-wafer processing thermal oxidation device of the present invention. A hexagonal transfer chamber 3 having a wafer transfer device 4 is provided at the center of the apparatus. Around the transfer chamber 3, three processing chambers 1 for forming an oxide film by supplying an oxidizing gas while heating the unprocessed wafer (substrate wafer) 2 are formed. A wafer cooling chamber 5 for storing and cooling the taken-out high temperature oxide film forming wafer 21 and two cassette chambers 6 for storing the substrate wafer 2 and the oxide film forming wafer 21 in their respective cassettes 7 are functionally arranged. ing.
【００１６】図２は、図１に示す熱酸化装置において、
一つの処理室１と、ウエハ搬送室３及びウエハ冷却室５
のそれぞれの中心部を結ぶ直線Ａ、Ｂ間における装置の
断面説明図である。処理室１、ウエハ搬送室３の断面構
造と機能は従来とほぼ同等である。しかしながら、冷却
室５はウエハ受取部５１が多段構造であり、３つの処理
室１において１回の工程で処理されるウエハ２１の全て
を収納（１処理室で１枚処理の場合には３枚以上、１処
理室で２枚処理の場合には６枚以上収納）して冷却でき
る機能を有し、この構造と機能が従来装置と異なる。FIG. 2 shows the thermal oxidizer shown in FIG.
One processing chamber 1, wafer transfer chamber 3 and wafer cooling chamber 5
FIG. 4 is a cross-sectional explanatory view of the device between straight lines A and B connecting the respective central portions of FIG. The sectional structures and functions of the processing chamber 1 and the wafer transfer chamber 3 are almost the same as those of the conventional one. However, in the cooling chamber 5, the wafer receiving portion 51 has a multi-stage structure, and all of the wafers 21 processed in one process in the three processing chambers 1 are accommodated (three wafers are processed in one processing chamber). As described above, in the case of processing two wafers in one processing chamber, six or more wafers can be stored and cooled. This structure and function are different from the conventional apparatus.
【００１７】この熱酸化装置において、搬送室３の搬送
装置４によりウエハ・カセット７から処理前の基板ウエ
ハ２が取り出され、第１から第３のそれぞれの処理室１
に順次搬送され、処理室１の所定位置にセットされる。
基板ウエハ２は加熱装置により予め高温に保持された処
理室１内で所定温度に昇温されると共に、処理室１内部
はゲートバルブ１１を閉じて処理雰囲気ガスに置換さ
れ、酸化性ガスを所定時間供給して所望の厚みの酸化膜
が形成される。酸化膜の形成を終えたウエハ２１は、ゲ
ートバルブ１１を開けて処理室１から順次搬送装置４に
より取り出され、冷却室５に搬送される。ウエハが取り
出された処理室１には、１回目と同様に、第１から第３
の処理室１それぞれに基板ウエハ２が順次搬送される。
冷却室５に順次搬入された酸化膜を形成した高温のウエ
ハ２１は、冷却室５内で所定時間冷却された後、搬送装
置４の空き時間を利用してウエハ・カセット７へ搬送さ
れる。In this thermal oxidizer, the unprocessed substrate wafer 2 is taken out from the wafer cassette 7 by the transfer device 4 of the transfer chamber 3, and the first to third processing chambers 1 are processed.
Are sequentially transported to and set at a predetermined position in the processing chamber 1.
The substrate wafer 2 is heated to a predetermined temperature in the processing chamber 1 that has been kept at a high temperature by a heating device, and the inside of the processing chamber 1 is replaced with a processing atmosphere gas by closing the gate valve 11 so that the oxidizing gas is controlled to a predetermined temperature. By supplying for a time, an oxide film having a desired thickness is formed. The wafer 21 on which the oxide film has been formed is sequentially taken out from the processing chamber 1 by the transfer device 4 by opening the gate valve 11 and transferred to the cooling chamber 5. In the processing chamber 1 from which the wafer is taken out, the first to the third
The substrate wafers 2 are sequentially transferred to the respective processing chambers 1.
The high-temperature wafer 21 having the oxide film formed thereon, which is sequentially loaded into the cooling chamber 5, is cooled in the cooling chamber 5 for a predetermined time and then transferred to the wafer cassette 7 by utilizing the idle time of the transfer device 4.
【００１８】以上に説明した装置により、酸化膜形成を
完了した高温状態のウエハ２１が処理室１から搬送装置
４により順次取り出された場合にも、一つの冷却室５に
おいて全てのウエハ２１の冷却が可能であり、それぞれ
の処理室１はウエハ冷却工程の制約なしに次の酸化ウエ
ハ２１を製造できる。したがって、装置全体のプロセス
時間を大幅に短縮でき、枚葉式処理装置の生産性を大幅
に向上することができる。By the apparatus described above, even when the wafers 21 in the high temperature state where the oxide film formation is completed are sequentially taken out from the processing chamber 1 by the transfer device 4, all the wafers 21 are cooled in one cooling chamber 5. In each processing chamber 1, the next oxidized wafer 21 can be manufactured without restriction of the wafer cooling process. Therefore, the process time of the entire apparatus can be significantly reduced, and the productivity of the single-wafer processing apparatus can be significantly improved.
【００１９】次に、図３も参照して本発明による処理方
法の例について説明する。図３は、図１に示す本発明の
枚葉式処理装置により酸化膜形成ウエハを作製する場合
の工程ダイアグラムの説明図である。最初に、搬送室３
の搬送装置４によりウエハ・カセット７から直径２００
ｍｍの基板ウエハ２が取り出される。その基板ウエハ２
は、第１処理室１のゲートバルブ１１を開いて第１処理
室１内に挿入され、その石英製のウエハ載置台１２にセ
ットされる。次に、ゲートバルブ１１を閉じ、キャリア
ガスのＮ2 を５ｌ／ｍｉｎ導入し、処理室１内部をガス
置換する。この時、基板ウエハ２は加熱装置により予め
高温に保持された処理室１内で昇温される。基板ウエハ
２が１０５０℃の所定温度に達すると同時に、Ｈ2 を２
ｌ／ｍｉｎ、Ｏ2 を１ｌ／ｍｉｎの混合ガスを燃焼して
水蒸気を作ってキャリアガスのＮ2 中に３分間混入し、
基板ウエハ表面に厚みおよそ０．１μｍの酸化膜を形成
する。酸化膜形成後、Ｈ2 とＯ2の供給を止め、Ｎ2 キ
ャリアガスで反応室１を１分間置換する。続いて、ゲー
トバルブ１１を開け、搬送装置４で処理室１の酸化膜形
成ウエハ２１を取り出して冷却室５に搬送する。ウエハ
を取り出した処理室は、搬送装置４により新たな基板ウ
エハ２が再び挿入され、次の酸化膜形成の工程が繰り返
される。Next, an example of the processing method according to the present invention will be described with reference to FIG. FIG. 3 is an explanatory view of a process diagram in the case of producing an oxide film forming wafer by the single-wafer processing apparatus of the present invention shown in FIG. First, the transfer chamber 3
From the wafer cassette 7 by the transfer device 4 of
The mm substrate wafer 2 is taken out. The substrate wafer 2
Is inserted into the first processing chamber 1 by opening the gate valve 11 of the first processing chamber 1 and set on the quartz wafer mounting table 12. Next, the gate valve 11 is closed, N 2 of the carrier gas is introduced at 5 l / min, and the inside of the processing chamber 1 is replaced with gas. At this time, the temperature of the substrate wafer 2 is raised in the processing chamber 1 which is previously kept at a high temperature by the heating device. At the same time the substrate wafer 2 reaches a predetermined temperature of 1050 ° C., H 2 2
1 / min, O 2 was burned with a mixed gas of 1 l / min to produce water vapor, which was mixed with N 2 as a carrier gas for 3 minutes,
An oxide film having a thickness of about 0.1 μm is formed on the surface of the substrate wafer. After the oxide film is formed, the supply of H 2 and O 2 is stopped, and the reaction chamber 1 is replaced with N 2 carrier gas for 1 minute. Subsequently, the gate valve 11 is opened, the transfer device 4 takes out the oxide film-formed wafer 21 in the processing chamber 1 and transfers it to the cooling chamber 5. In the processing chamber from which the wafer has been taken out, a new substrate wafer 2 is inserted again by the transfer device 4, and the subsequent oxide film forming process is repeated.
【００２０】以上の操作は、ウエハ搬送装置４の稼働が
可能な範囲で第２及び第３の処理室１において順次実施
される。一方、ゲートバルブ１１開けて搬送装置４で処
理室１から取り出された、酸化膜形成を終えたウエハ２
１は高温である。このため、ウエハはカセット７に収納
可能な１５０℃以下の温度になるまでの所定時間、冷却
室５内で放冷され、更に搬送装置４が基板ウエハ２の搬
送を終えるまで冷却室５で待機（図中破線矢印）した
後、ウエハ・カセット７へ搬送される。The above-mentioned operations are sequentially carried out in the second and third processing chambers 1 within a range where the wafer transfer device 4 can be operated. On the other hand, the gate valve 11 is opened and the wafer 2 that has been taken out of the processing chamber 1 by the transfer device 4 and has completed the oxide film formation
1 is high temperature. For this reason, the wafer is allowed to cool in the cooling chamber 5 for a predetermined time until it reaches a temperature of 150 ° C. or less that can be stored in the cassette 7, and then waits in the cooling chamber 5 until the transfer device 4 finishes transferring the substrate wafer 2. After (shown by the broken line arrow in the figure), the wafer is transferred to the wafer cassette 7.
【００２１】図４は冷却室５の一例の詳細を示す図で、
（ａ）は縦断面図、（ｂ）はそのＡ−Ｂ断面図である。
冷却室５のウエハ受取部５１は多段状で多数のウエハ２
１の収納、放冷が可能で、第２、第３の処理室から順次
搬送されるウエハ２１はこの一つの冷却室５で冷却され
る。多段状のウエハ受取部５１は、昇降部材５２によっ
て一体的に上下動することができ、搬送装置４により所
望の場所にウエハ２１を出し入れすることができる。多
段状のウエハ受取部５１は、中間に断熱仕切板８を設け
てもよい。FIG. 4 is a diagram showing details of an example of the cooling chamber 5,
(A) is a longitudinal sectional view and (b) is an AB sectional view thereof.
The wafer receiving portion 51 of the cooling chamber 5 has a multi-stage structure and has a large number of wafers 2.
The wafer 21 that can store and cool 1 and is sequentially transferred from the second and third processing chambers is cooled in the single cooling chamber 5. The multistage wafer receiving portion 51 can be integrally moved up and down by the elevating member 52, and the wafer 21 can be taken in and out at a desired place by the transfer device 4. The multistage wafer receiving portion 51 may be provided with the heat insulating partition plate 8 in the middle.
【００２２】多数のウエハを収納できる冷却室を用いる
ことにより、直径２００ｍｍのウエハを２枚ずつ処理す
る処理室を３室配置した場合、１時間当たりおよそ５４
枚の酸化膜形成ウエハの生産が可能となり、従来構造の
冷却室を有する枚葉方式の処理装置に比べ、スループッ
トを１．５倍に向上することができた。By using a cooling chamber capable of accommodating a large number of wafers, when three processing chambers for processing two wafers each having a diameter of 200 mm are arranged, approximately 54 per hour can be obtained.
It has become possible to produce a single oxide film-formed wafer, and the throughput can be improved by a factor of 1.5 as compared with a single-wafer processing apparatus having a conventional cooling chamber.
【００２３】次に、本発明の枚葉処理方式装置をエピタ
キシャル成長装置に適用した場合の例を説明する。エピ
タキシャル成長装置の場合、中央部のウエハ搬送室３、
ウエハ冷却室５、カセット室６などの主な装置構成は図
１及び図２に示した酸化炉と同一である。エピタキシャ
ル成長は、基板ウエハを並べて高温（〜１０００℃）に
加熱し、原料のシリコン化合物ガスを供給して気相化学
反応によりエピタキシャル層を形成することから、図１
の処理室は反応室となる。したがって、反応室１はエピ
タキシャル成長時に反応生成物により汚染され、この点
が酸化炉の場合と異なる。Next, an example in which the single-wafer processing apparatus of the present invention is applied to an epitaxial growth apparatus will be described. In the case of an epitaxial growth apparatus, the wafer transfer chamber 3 at the center,
The main apparatus configurations such as the wafer cooling chamber 5 and the cassette chamber 6 are the same as those of the oxidation furnace shown in FIGS. In the epitaxial growth, the substrate wafers are arranged and heated to a high temperature (up to 1000 ° C.), and a silicon compound gas as a raw material is supplied to form an epitaxial layer by a vapor phase chemical reaction.
The processing chamber becomes the reaction chamber. Therefore, the reaction chamber 1 is contaminated by reaction products during the epitaxial growth, which is different from the case of the oxidation furnace.
【００２４】図５は、本発明のエピタキシャル成長装置
によりエピタキシャル・ウエハを作製する場合の工程ダ
イアグラムである。最初に、搬送室３の搬送装置４によ
りウエハ・カセット７から直径２００ｍｍの基板ウエハ
２が取り出されて、ゲートバルブ１１を開いた第１反応
室１の石英製のウエハ載置台１２にセットされる。次
に、ゲートバルブ１１を閉じてガス置換すると共に反応
室１内部を成長のキャリアガスのＨ2 を２０ｌ／ｍｉ
ｎ、５０Ｔｏｒｒ導入すると同時に加熱してウエハを１
０００℃の所定温度に昇温する。次いで、シリコン原料
ガスのモノシラン（ＳｉＨ4 ）を１ｌ／ｍｉｎ、ｎ型の
ドーピングガスのフォスフィン（ＰＨ3 ）を１００ｃｃ
／ｍｉｎ、３分間供給して、厚みおよそ５μｍで所望の
抵抗率を持ったｎ型エピタキシャル層を形成する。次
に、モノシランとフォスフィンの供給を止め、Ｈ2 キャ
リアガスで反応室を１分間置換すると同時に加熱装置の
出力を下げ、およそ８００℃までウエハを降温する。FIG. 5 is a process diagram for producing an epitaxial wafer by the epitaxial growth apparatus of the present invention. First, the substrate wafer 2 having a diameter of 200 mm is taken out from the wafer cassette 7 by the transfer device 4 of the transfer chamber 3 and set on the quartz wafer mounting table 12 of the first reaction chamber 1 in which the gate valve 11 is opened. . Next, the gate valve 11 is closed to replace the gas, and the inside of the reaction chamber 1 is filled with H 2 of a carrier gas of 20 l / mi.
n and 50 Torr are introduced and heated at the same time to heat the wafer 1
The temperature is raised to a predetermined temperature of 000 ° C. Next, monosilane (SiH 4 ) as a silicon source gas is added at 1 l / min, and phosphine (PH 3 ) as an n-type doping gas is added at 100 cc.
/ Min for 3 minutes to form an n-type epitaxial layer having a desired resistivity with a thickness of about 5 μm. Next, the supply of monosilane and phosphine is stopped, the reaction chamber is replaced with H 2 carrier gas for 1 minute, and at the same time, the output of the heating device is lowered to lower the temperature of the wafer to about 800 ° C.
【００２５】その後、ゲートバルブ１１を開け、搬送装
置４で反応室１のエピウエハ２１を取り出して冷却室５
に搬送する。ウエハを取り出した反応室１を再び１００
０℃以上の所定温度に昇温し、Ｈ2 キャリアガス２０ｌ
／ｍｉｎとエッチングガスの塩化水素（ＨＣｌ）２ｌ／
ｍｉｎを２ｍｉｎ間導入して、内壁やウエハ載置台１２
に析出したシリコンをエッチ除去した後、降温する。ク
リーニングにより清浄した反応室１にウエハカセット７
から新たな基板ウエハ２を再び搬送し、次のエピタキシ
ャル成長を実施する。After that, the gate valve 11 is opened, the epiwafer 21 in the reaction chamber 1 is taken out by the transfer device 4, and the cooling chamber 5 is opened.
Transport to The reaction chamber 1 from which the wafer was taken out
The temperature is raised to a predetermined temperature of 0 ° C. or higher, and 20 L of H 2 carrier gas is used.
/ Min and etching gas hydrogen chloride (HCl) 2 l /
Introducing min for 2 minutes, the inner wall and the wafer mounting table 12
After the silicon deposited on the substrate is removed by etching, the temperature is lowered. Wafer cassette 7 in reaction chamber 1 cleaned by cleaning
Then, a new substrate wafer 2 is transferred again and the next epitaxial growth is performed.
【００２６】以上の操作は、ウエハ搬送装置４の稼働が
可能な範囲で第２、第３の反応室１において順次実施さ
れる。一方、ゲートバルブ１１開けて搬送装置４で反応
室１から取り出されたエピウエハ２１は、エピタキシャ
ル装置のスループットを高めるために反応室１の降温時
間が短く比較的高温である。このため、ウエハはカセッ
ト７に収納可能な１５０℃以下の温度になるまで冷却室
５内で放冷された後、搬送装置４の空き時間を利用して
ウエハ・カセット７に搬送される。この場合、冷却室５
のウエハ受取部５１は、図４に示したように多段状で多
数のエピウエハ２１の収納、放冷が可能であり、第２、
第３の反応室から順次搬送されるエピウエハ２１は一つ
の冷却室５で冷却される。The above operations are sequentially carried out in the second and third reaction chambers 1 within a range where the wafer transfer device 4 can be operated. On the other hand, the epi-wafer 21, which is opened from the gate valve 11 and taken out of the reaction chamber 1 by the transfer device 4, has a relatively short temperature falling time in the reaction chamber 1 in order to increase the throughput of the epitaxial device. Therefore, the wafer is allowed to cool in the cooling chamber 5 to a temperature of 150 ° C. or lower that can be stored in the cassette 7, and then is transferred to the wafer cassette 7 by utilizing the idle time of the transfer device 4. In this case, the cooling chamber 5
The wafer receiving section 51 of the multi-stage wafer receiving section 51 is capable of accommodating and cooling a large number of epi-wafers 21 as shown in FIG.
The epi-wafers 21 sequentially transferred from the third reaction chamber are cooled in one cooling chamber 5.
【００２７】このように多数のウエハを収納できる冷却
室を用いることにより、直径２００ｍｍのウエハ２枚ず
つ処理する反応室を３室配置した場合、１時間当たりお
よそ４３枚のエピウエハの生産が可能となり、従来構造
の冷却室を有する枚葉方式エピタキシャル成長装置に比
べスループットを１．５倍に向上することができた。ま
た、反応室に供給する反応ガスの種類や基板温度を変更
することで、周知の方法により基板上にポリシリコン
膜、ＳｉＯ2 膜、Ｓｉ3Ｎ4 膜などのＣＶＤ膜を形成す
ることができる。By using a cooling chamber capable of accommodating a large number of wafers in this way, when three reaction chambers for processing two wafers each having a diameter of 200 mm are arranged, approximately 43 epiwafers can be produced per hour. The throughput can be improved by 1.5 times as compared with the single-wafer type epitaxial growth apparatus having the conventional cooling chamber. Further, by changing the type of reaction gas supplied to the reaction chamber and the substrate temperature, a CVD film such as a polysilicon film, a SiO 2 film and a Si 3 N 4 film can be formed on the substrate by a known method. .
【００２８】図６は、２枚ずつ３回にわたりウエハを等
時間間隔で冷却室５に搬送した場合のウエハの冷却特性
を示す。ウエハは、冷却室の多段のウエハ受取部の上部
から順に収納した。後で搬送された高温のウエハの影響
を受け、最初に搬送した２枚のウエハのうち下側のウエ
ハの温度が上がり、目標温度までの冷却時間が長くなる
ことが分かる。スループットを大きくするためにプロセ
ス時間を短縮する場合、前述ウエハ冷却時間に対する高
温のウエハの影響は大きくなる。FIG. 6 shows the cooling characteristics of the wafers when the wafers are transferred to the cooling chamber 5 at equal time intervals two by three times. The wafers were stored in order from the top of the multi-stage wafer receiving section in the cooling chamber. It can be seen that the temperature of the lower wafer of the two initially transported wafers rises due to the influence of the hot wafers transported later, and the cooling time to the target temperature becomes longer. When the process time is shortened to increase the throughput, the influence of the high temperature wafer on the wafer cooling time becomes large.
【００２９】図７は、このような問題点を解消するた
め、１回に搬送されるウエハ毎に仕切板８を設けて、後
で搬送される高温ウエハの影響を小さくした冷却室５を
示す。このような構造の冷却室を採用することにより、
短時間に多数のウエハが搬送される場合にも、目標温度
までの冷却時間が長くなる問題を解消することができ
る。仕切板８をガスや水により冷却する方法は効果をよ
り有効にする方策である。ここではシリコン基板ウエハ
を例にとって説明したが、本発明は炭化珪素（ＳｉＣ）
など他の半導体基板や液晶用のガラス基板に対しても適
用可能である。FIG. 7 shows a cooling chamber 5 in which a partition plate 8 is provided for each wafer transferred at one time to reduce the influence of high-temperature wafers transferred later in order to solve such a problem. . By adopting a cooling chamber with such a structure,
Even when a large number of wafers are transferred in a short time, it is possible to solve the problem that the cooling time to the target temperature is long. A method of cooling the partition plate 8 with gas or water is a measure for making the effect more effective. Although a silicon substrate wafer has been described here as an example, the present invention is not limited to silicon carbide (SiC).
It is also applicable to other semiconductor substrates and glass substrates for liquid crystals.
【００３０】[0030]
【発明の効果】本発明によれば、枚葉方式の基板処理装
置におけるスループットを向上し、高い生産性で処理す
ることが可能となる。According to the present invention, it is possible to improve throughput in a single-wafer type substrate processing apparatus and process with high productivity.
【図１】本発明による枚葉方式基板処理装置の一例の構
成を示す概略平面図。FIG. 1 is a schematic plan view showing the configuration of an example of a single-wafer type substrate processing apparatus according to the present invention.
【図２】図１のＡ−Ｂ断面図。FIG. 2 is a sectional view taken along the line AB of FIG.
【図３】本発明による枚葉方式基板処理のプロセスダイ
ヤグラムの一例を示す図。FIG. 3 is a diagram showing an example of a process diagram of single-wafer type substrate processing according to the present invention.
【図４】冷却室の詳細説明図。FIG. 4 is a detailed explanatory view of a cooling chamber.
【図５】本発明による枚葉処理方式エピタキシャル成長
のプロセスダイヤグラムの一例を示す図。FIG. 5 is a diagram showing an example of a process diagram of single-wafer processing type epitaxial growth according to the present invention.
【図６】冷却室に搬送されたウエハの冷却特性を説明す
る図。FIG. 6 is a diagram illustrating cooling characteristics of a wafer transferred to a cooling chamber.
【図７】仕切板を設けた冷却室を備える装置の断面説明
図。FIG. 7 is an explanatory cross-sectional view of an apparatus including a cooling chamber provided with a partition plate.
【図８】従来の枚葉方式基板処理のプロセスダイヤグラ
ムを示す図。FIG. 8 is a diagram showing a process diagram of conventional single-wafer processing substrate processing.
【図９】従来の枚葉処理方式エピタキシャル成長のプロ
セスダイヤグラムを示す図。FIG. 9 is a diagram showing a process diagram of conventional single-wafer processing epitaxial growth.
１…処理室、２…基板ウエハ、３…ウエハ搬送室、４…
ウエハ搬送装置、５…ウエハ冷却室、６…カセット室、
７…ウエハ・カセット、８…仕切板、２１…処理（エピ
タキシャル成長）完了ウエハ、５１…ウエハ受取部、５
２…昇降部材1 ... Processing chamber, 2 ... Substrate wafer, 3 ... Wafer transfer chamber, 4 ...
Wafer transfer device, 5 ... Wafer cooling chamber, 6 ... Cassette chamber,
7 ... Wafer cassette, 8 ... Partition plate, 21 ... Processing (epitaxial growth) completed wafer, 51 ... Wafer receiving section, 5
2 ... Lifting member
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/3065 Ｈ０１Ｌ 21/31 Ｃ 21/31 21/302 Ｂ (72)発明者 渡辺 智司 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 三瀬 信行 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 内野 敏幸 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 桜井 義彦 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 内藤 孝男 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 池田 文秀 東京都中野区東中野三丁目14番20号 国際 電気株式会社内 (72)発明者 井ノ口 泰啓 東京都中野区東中野三丁目14番20号 国際 電気株式会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication location H01L 21/3065 H01L 21/31 C 21/31 21/302 B (72) Inventor Tomoji Watanabe Ibaraki Prefecture No. 502, Jinritsu Machinery Co., Ltd., Tsuchiura-shi (72) Inventor Nobuyuki Mise No. 502, Kintate-cho, Tsuchiura-shi, Ibaraki Prefecture, In Machinery Research Lab, Hiritsu, Ltd. (72) Toshiyuki Uchino, Jodai, Kodaira-shi, Tokyo 5-20-1 Honcho, Ltd. Semiconductor Business Division, Hitachi, Ltd. (72) Inventor Yoshihiko Sakurai 5-20-1, Kamisuihonmachi, Kodaira-shi, Tokyo Incorporation Company Hitachi Ltd. Semiconductor Division (72) Takao Naito 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division (72) Inventor Fumihide Ikeda 3-14 Higashi-Nakano, Nakano-ku, Tokyo No. 20 Kokusai Electric Co., Ltd. (72) Inventor Yasuhiro Inoguchi 3-14-20 Higashi-Nakano, Nakano-ku, Tokyo Kokusai Electric Co., Ltd.
Claims (9)
各々ｎ（ｎ≧１）枚の基板を収納して高温処理できるｍ
（ｍ≧２）個の処理室と１個の冷却室とが連結されてい
る基板処理装置を用いて、前記搬送手段によりカセット
に収納された基板を前記処理室に順次挿入して処理する
工程と、処理後の高温の基板を前記搬送手段により前記
冷却室に収納して冷却する工程とを含む基板の処理方法
において、 前記冷却室に前記高温の基板をｎ×ｍ枚以上収納して冷
却することを特徴とする基板の処理方法。1. A substrate transfer chamber provided with a single transfer means,
Each of n (n ≧ 1) substrates can be stored and processed at high temperature.
Using a substrate processing apparatus in which (m ≧ 2) processing chambers and one cooling chamber are connected, the substrates stored in the cassette by the transfer means are sequentially inserted into the processing chambers for processing. And a step of storing the treated high temperature substrate in the cooling chamber by the transfer means and cooling the substrate, wherein the cooling chamber stores and cools n × m or more of the high temperature substrate. A method for treating a substrate, comprising:
化膜又は不純物拡散層を形成することを特徴とする請求
項１記載の基板の処理方法。2. The substrate processing method according to claim 1, wherein the substrate is heat-treated in the processing chamber to form an oxide film or an impurity diffusion layer.
スを供給してシリコンのエピタキシャル成長層を形成す
ることを特徴とする請求項１記載の基板の処理方法。3. The method for processing a substrate according to claim 1, wherein the substrate is heated in the processing chamber and a source gas is supplied to form an epitaxial growth layer of silicon.
を特徴とする請求項３記載の基板の処理方法。4. The method for treating a substrate according to claim 3, wherein a CVD film is formed on the silicon substrate.
各々ｎ（ｎ≧１）枚の基板を収納して高温処理できるｍ
（ｍ≧２）個の処理室と１個の冷却室とを連結した基板
の処理装置において、 前記冷却室はｎ×ｍ枚以上の基板を収納できることを特
徴とする基板の処理装置。5. A substrate transfer chamber provided with a single transfer means,
Each of n (n ≧ 1) substrates can be stored and processed at high temperature.
A substrate processing apparatus in which (m ≧ 2) processing chambers and one cooling chamber are connected to each other, wherein the cooling chamber can store n × m or more substrates.
純物拡散層を形成する熱処理を行う処理室であることを
特徴とする請求項５記載の基板の処理装置。6. The substrate processing apparatus according to claim 5, wherein the processing chamber is a processing chamber for performing a heat treatment for forming an oxide film or an impurity diffusion layer on the substrate.
ガスを供給して前記基板にエピタキシャル成長層を形成
する反応室であることを特徴とする請求項５記載の基板
の処理装置。7. The apparatus for processing a substrate according to claim 5, wherein the processing chamber is a reaction chamber for heating the substrate and supplying a source gas to form an epitaxial growth layer on the substrate.
する反応室であることを特徴とする請求項７記載の基板
の処理装置。8. The substrate processing apparatus according to claim 7, wherein the processing chamber is a reaction chamber for forming a CVD film on the substrate.
もｎ枚ずつ仕切る仕切板を備えることを特徴とする請求
項５〜８の何れか１項記載の基板の処理装置。9. The substrate processing apparatus according to claim 5, wherein the cooling chamber includes a partition plate that partitions at least n substrates to be stored.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08510696A JP3274602B2 (en) | 1996-04-08 | 1996-04-08 | Semiconductor element manufacturing method and substrate processing apparatus |
| KR1019970012599A KR970072120A (en) | 1996-04-08 | 1997-04-04 | Substrate Processing Method and Processing Equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08510696A JP3274602B2 (en) | 1996-04-08 | 1996-04-08 | Semiconductor element manufacturing method and substrate processing apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09283589A true JPH09283589A (en) | 1997-10-31 |
| JP3274602B2 JP3274602B2 (en) | 2002-04-15 |
Family
ID=13849374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP08510696A Expired - Fee Related JP3274602B2 (en) | 1996-04-08 | 1996-04-08 | Semiconductor element manufacturing method and substrate processing apparatus |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3274602B2 (en) |
| KR (1) | KR970072120A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100315459B1 (en) * | 1999-12-31 | 2001-11-28 | 황인길 | Cooling chamber of rapid thermal processing apparatus with dual process chamber |
| JP2003077978A (en) * | 2001-09-05 | 2003-03-14 | Tokyo Electron Ltd | Processing system and processing method |
| KR20040104004A (en) * | 2003-06-02 | 2004-12-10 | 주성엔지니어링(주) | Cluster Apparatus for Liquid Crystal Display Apparatus |
| KR100462237B1 (en) * | 2000-02-28 | 2004-12-17 | 주성엔지니어링(주) | Cluster tool for semiconductor device fabrication having a substrate cooling apparatus |
| US10002805B2 (en) * | 2010-02-24 | 2018-06-19 | Veeco Instruments Inc. | Processing methods and apparatus with temperature distribution control |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100385391B1 (en) * | 2001-01-04 | 2003-05-27 | 주식회사 아토 | A thin-film evaporation methode for wafer |
-
1996
- 1996-04-08 JP JP08510696A patent/JP3274602B2/en not_active Expired - Fee Related
-
1997
- 1997-04-04 KR KR1019970012599A patent/KR970072120A/en not_active Application Discontinuation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100315459B1 (en) * | 1999-12-31 | 2001-11-28 | 황인길 | Cooling chamber of rapid thermal processing apparatus with dual process chamber |
| KR100462237B1 (en) * | 2000-02-28 | 2004-12-17 | 주성엔지니어링(주) | Cluster tool for semiconductor device fabrication having a substrate cooling apparatus |
| JP2003077978A (en) * | 2001-09-05 | 2003-03-14 | Tokyo Electron Ltd | Processing system and processing method |
| JP4657528B2 (en) * | 2001-09-05 | 2011-03-23 | 東京エレクトロン株式会社 | Processing system and processing method |
| KR20040104004A (en) * | 2003-06-02 | 2004-12-10 | 주성엔지니어링(주) | Cluster Apparatus for Liquid Crystal Display Apparatus |
| US10002805B2 (en) * | 2010-02-24 | 2018-06-19 | Veeco Instruments Inc. | Processing methods and apparatus with temperature distribution control |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970072120A (en) | 1997-11-07 |
| JP3274602B2 (en) | 2002-04-15 |
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