JPH09275212A - Voltage-driven semiconductor device - Google Patents
Voltage-driven semiconductor deviceInfo
- Publication number
- JPH09275212A JPH09275212A JP8082331A JP8233196A JPH09275212A JP H09275212 A JPH09275212 A JP H09275212A JP 8082331 A JP8082331 A JP 8082331A JP 8233196 A JP8233196 A JP 8233196A JP H09275212 A JPH09275212 A JP H09275212A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- semiconductor region
- semiconductor
- region
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 239000012535 impurity Substances 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 15
- 239000000758 substrate Substances 0.000 description 12
- 239000000969 carrier Substances 0.000 description 11
- 230000002093 peripheral effect Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 230000007423 decrease Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 239000012141 concentrate Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010943 off-gassing Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はトレンチ型の絶縁ゲ
ートを有する半導体装置に係り、特にパワーMOSFETやＩ
ＧＢＴなどに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a trench type insulated gate, and more particularly to a power MOSFET and an I / O device.
It relates to GBT.
【０００２】[0002]
【従来の技術】図８（ａ),（ｂ）に従来のトレンチ型の
絶縁ゲートを有するＩＧＢＴ(Insulated Gate Bipolar
Transistor）の断面模式図及び平面模式図を示す（以
下、この素子をトレンチＩＧＢＴと呼ぶ）。なお、断面
模式図（ａ）は平面模式図（ｂ）のＸ−Ｙに対応してい
る。トレンチＩＧＢＴはｐ+ 基板１上にｎ+ バッファ層
２０が形成され、さらにその上にｎ- ドリフト層２が形
成される。ｎ- ドリフト層２の表面にｐベース層３が形
成され、さらに、ｐベース層３を貫通して、選択的にか
つ連続的にトレンチが形成され、トレンチ表面には、ゲ
ート絶縁膜９及びゲート電極１０が形成される。ゲート
絶縁膜９及びゲート電極１０に隣接するｐベース層３の
表面に選択的にｎ+ エミッタ層４が形成される。さら
に、ｐ+ 基板１の裏面上にコレクタ電極１１が形成さ
れ、ｎ- ドリフト層２上に選択的にエミッタ電極１２が
形成される。2. Description of the Related Art An IGBT (Insulated Gate Bipolar) having a conventional trench type insulated gate is shown in FIGS.
Transistor) shows a schematic sectional view and a schematic plan view (hereinafter, this element is referred to as a trench IGBT). The schematic sectional view (a) corresponds to XY in the schematic plan view (b). In trench IGBT, n @ + buffer layer 20 is formed on p @ + substrate 1, and n @-drift layer 2 is further formed thereon. A p base layer 3 is formed on the surface of the n − drift layer 2, and a trench is selectively and continuously formed through the p base layer 3, and a gate insulating film 9 and a gate are formed on the trench surface. The electrode 10 is formed. An n + emitter layer 4 is selectively formed on the surface of the p base layer 3 adjacent to the gate insulating film 9 and the gate electrode 10. Further, collector electrode 11 is formed on the back surface of p @ + substrate 1, and emitter electrode 12 is selectively formed on n @-drift layer 2.
【０００３】動作原理は以下の通りである。まず、エミ
ッタ電極１２を接地し、コレクタ電極１１にある一定の
正電圧を印加する。この状態で、ゲート電極１０にしき
い値電圧以上の電圧を加えることにより、ゲート電極１
０に沿って、縦方向にチャネルが形成され、コレクタ電
極１１，エミッタ電極１２間に電流が流れ、トレンチＩ
ＧＢＴはオン状態となる。The operating principle is as follows. First, the emitter electrode 12 is grounded and a certain positive voltage is applied to the collector electrode 11. In this state, by applying a voltage higher than the threshold voltage to the gate electrode 10, the gate electrode 1
A channel is formed in the vertical direction along 0, a current flows between the collector electrode 11 and the emitter electrode 12, and the trench I
The GBT is turned on.
【０００４】プレーナ型のＩＧＢＴに比べ、ＪＦＥＴ効
果による抵抗成分が存在せず、さらに、微細化が可能で
あることから、オン電圧が低減できることが特徴であ
る。Compared with the planar type IGBT, there is no resistance component due to the JFET effect, and further, miniaturization is possible, and therefore, the on-voltage can be reduced.
【０００５】また、図９（ａ),（ｂ）に従来のトレンチ
型の絶縁ゲートを有するパワーMOSFET(Metal-Oxide-Sem
iconductor Feild Effect Transistor）の断面模式図及
び平面模式図を示す（以下、この素子をトレンチＭＯＳ
と呼ぶ）。トレンチIGBTと異なるのは、ｐ+ 基板１の代
わりにｎ+ 基板１ａが使用される点である。Further, a power MOSFET (Metal-Oxide-Sem) having a conventional trench type insulated gate is shown in FIGS. 9 (a) and 9 (b).
A schematic cross-sectional view and a schematic plan view of an insulator Feild Effect Transistor are shown below (hereinafter, this element will be referred to as a trench MOS
). The difference from the trench IGBT is that an n + substrate 1a is used instead of the p + substrate 1.
【０００６】[0006]
【発明が解決しようとする課題】トレンチ型の絶縁ゲー
トを有する半導体装置はその特徴であるゲート電極を形
成するために、一般的に、ドライエッチング技術を利用
して、シリコン基板にトレンチを形成する。この時、ト
レンチの形状や表面状態等は、チップ内エッチング領域
の外周部が最も不安定となる。これはエッチング領域の
疎密によりサイドエッチ量が異なるためである。チップ
の内側は導通領域を形成するために、トレンチ領域が密
に形成されている。それに対し、チップの外側は耐圧を
確保する領域（ターミネーション領域）であり、トレン
チは形成しない。このため、チップの内側と外側でエッ
チング領域に疎密が生じる。エッチング領域が疎な領域
では脱ガスが少なく、従って側壁保護のポリマーが薄
く、このため、サイドエッチが入り易くなり、密な領域
とは形状や表面状態等が異なってしまう。In order to form a gate electrode, which is a characteristic of a semiconductor device having a trench type insulated gate, a dry etching technique is generally used to form a trench in a silicon substrate. . At this time, the shape and surface condition of the trench are the most unstable in the outer peripheral portion of the in-chip etching region. This is because the side etch amount differs depending on the density of the etching region. Trench regions are densely formed inside the chip to form a conductive region. On the other hand, the outside of the chip is a region (termination region) where the breakdown voltage is secured, and the trench is not formed. Therefore, sparseness and denseness occur in the etching region inside and outside the chip. In a region where the etching region is sparse, outgassing is small, and therefore, the polymer for protecting the side wall is thin, so that side etching is likely to occur, and the shape and surface state are different from those in the dense region.
【０００７】したがって、ゲート電圧印加時に、チップ
内エッチング領域の外周部、即ち、ゲート電極の外周部
において、ゲート形状の変化によるしきい値電圧の不均
一が生じ、素子の均一動作が妨げられる。なお、外周部
のしきい値電圧が高い場合は、素子のオン電圧低減効果
が低下し、低い場合は、電流集中による素子破壊が生じ
やすくなる。Therefore, when the gate voltage is applied, the threshold voltage becomes non-uniform due to the change of the gate shape in the outer peripheral portion of the in-chip etching region, that is, the outer peripheral portion of the gate electrode, and the uniform operation of the element is hindered. When the threshold voltage of the outer peripheral portion is high, the effect of reducing the on-voltage of the element is lowered, and when it is low, element breakdown due to current concentration tends to occur.
【０００８】本発明の目的は、トレンチ型の絶縁ゲート
を有する半導体装置において、前記従来技術の問題点を
解決することにある。すなわち、ゲート電圧印加時にチ
ップ内で均一動作を確実にすることにより、トレンチ外
周部でのしきい値電圧の上昇によるオン電圧の上昇、あ
るいは、しきい値電圧の低下によるトレンチ外周部での
電流集中による破壊の生じにくい素子を提供することで
ある。An object of the present invention is to solve the above-mentioned problems of the prior art in a semiconductor device having a trench type insulated gate. That is, by ensuring uniform operation within the chip when the gate voltage is applied, the on-voltage rises due to the rise of the threshold voltage in the trench outer periphery, or the current in the trench periphery rises due to the decrease of the threshold voltage. An object is to provide an element that is less likely to be destroyed by concentration.
【０００９】[0009]
【課題を解決するための手段】前記目的は、ゲート電圧
印加時に、チップ内のターミネーション領域に隣接する
トレンチがＭＯＳ動作しない構造にする。即ち、このト
レンチをダミーゲートとして使うことによって達成され
る。The object is to provide a structure in which a trench adjacent to a termination region in a chip does not operate as a MOS when a gate voltage is applied. That is, it is achieved by using this trench as a dummy gate.
【００１０】具体的には、ターミネーション領域に隣接
するトレンチをエミッタ電極に電気的に接続する、ある
いは、零電位になる構造にする。また、ターミネーショ
ン領域に隣接するトレンチに隣接するｎ+ エミッタ層を
形成しない構造にする。Specifically, the trench adjacent to the termination region is electrically connected to the emitter electrode or has a structure in which the potential is zero. Further, the n + emitter layer adjacent to the trench adjacent to the termination region is not formed.
【００１１】あるいは、ターミネーション領域に隣接す
るトレンチのチャネル領域にｐウェル層よりも不純物濃
度の高いｐ層が接触する構造にする。Alternatively, the p-layer having a higher impurity concentration than the p-well layer contacts the channel region of the trench adjacent to the termination region.
【００１２】[0012]
【発明の実施の形態】以下、本発明の実施例を図面を用
いて説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【００１３】図１は本発明の一実施例であるＩＧＢＴを
示す図であり、（ａ）は断面模式図、（ｂ）は平面模式
図である。1A and 1B are views showing an IGBT according to an embodiment of the present invention. FIG. 1A is a schematic sectional view and FIG. 1B is a schematic plan view.
【００１４】ｐ+ 基板１上にｎ- ドリフト層２が形成さ
れる。そして、ｎ- ドリフト層２の表面にｐベース層３
が形成され、さらに、ドライエッチング技術を使って、
ｐベース層３を貫通して、選択的にかつ連続的にトレン
チが形成され、トレンチ表面にゲート絶縁膜９及びゲー
ト電極１０が形成される。そして、ゲート絶縁膜９及び
ゲート電極１０に隣接するｐベース層３の表面に選択的
にｎ+ エミッタ層４が形成される。そして、ｐ+ 基板１
の裏面上にコレクタ電極１１が形成され、ｎ-ドリフト
層２上にｐベース層３及びｎ+ エミッタ層４に接するよ
うに選択的にエミッタ電極１２が形成される。An n @-drift layer 2 is formed on p @ + substrate 1. Then, the p base layer 3 is formed on the surface of the n − drift layer 2.
Is formed, and using dry etching technology,
A trench is selectively and continuously formed penetrating the p base layer 3, and a gate insulating film 9 and a gate electrode 10 are formed on the trench surface. Then, the n @ + emitter layer 4 is selectively formed on the surface of the p base layer 3 adjacent to the gate insulating film 9 and the gate electrode 10. And p + substrate 1
A collector electrode 11 is formed on the back surface of the n-drift layer 2, and an emitter electrode 12 is selectively formed on the n − drift layer 2 so as to be in contact with the p base layer 3 and the n + emitter layer 4.
【００１５】最外周のゲート絶縁膜９Ａ及びゲート電極
１０Ａ（以下、これらをまとめて最外トレンチと呼ぶ）
のみが、エミッタ電極１２と電気的に接続されている。
ゲート電極１０Ａは他のゲート電極と電気的に分離され
ている。Outermost gate insulating film 9A and gate electrode 10A (hereinafter collectively referred to as outermost trench)
Only the emitter electrode 12 is electrically connected.
The gate electrode 10A is electrically separated from other gate electrodes.
【００１６】動作原理は以下の通りである。まず、エミ
ッタ電極１２を接地し、コレクタ電極１１にある一定の
正電圧を印加する。この状態で、ゲート電極１０にしき
い値電圧以上の電圧を加えることにより、ゲート電極１
０に沿って、縦方向にチャネルが形成され、コレクタ電
極１１，エミッタ電極１２間に電流が流れ、素子はオン
状態となる。この際、トレンチの形状や表面状態等が最
も不安定となる最外トレンチ内のゲート電極は他のゲー
ト電極と電気的に分離されているため、ＭＯＳ動作せ
ず、素子のスイッチングには関与しない。従って、素子
の均一動作が確実となり、トレンチ外周部におけるしき
い値電圧の上昇による素子のオン電圧の上昇、あるい
は、しきい値電圧の低下によるトレンチ外周部での電流
集中による素子の破壊が生じにくくなる。The operating principle is as follows. First, the emitter electrode 12 is grounded and a certain positive voltage is applied to the collector electrode 11. In this state, by applying a voltage higher than the threshold voltage to the gate electrode 10, the gate electrode 1
A channel is formed in the vertical direction along 0, a current flows between the collector electrode 11 and the emitter electrode 12, and the element is turned on. At this time, since the gate electrode in the outermost trench where the shape and surface state of the trench are most unstable is electrically separated from other gate electrodes, MOS operation does not occur and it does not participate in element switching. . Therefore, the uniform operation of the element is ensured, and the on-voltage of the element is increased due to the increase of the threshold voltage in the outer periphery of the trench, or the element is broken due to the current concentration in the outer periphery of the trench due to the decrease of the threshold voltage. It gets harder.
【００１７】また、最外トレンチを零電位にした場合
も、同様の効果が得られる。しかし、エミッタ電極１２
と電気的に接続した方が、ゲート電極の電位が固定され
るため、安定したスイッチング動作が得られる。The same effect can be obtained when the outermost trench is set to zero potential. However, the emitter electrode 12
Since the potential of the gate electrode is fixed when electrically connected to, stable switching operation can be obtained.
【００１８】図２は本発明の一実施例を示す図であり、
（ａ）は断面模式図、（ｂ）は平面模式図である。図１
に示した実施例と異なる点は、最外トレンチがゲート電
極１０に電気的に接続され、さらに、最外トレンチに隣
接するｎ+ エミッタ層４が形成されていないことにあ
る。すなわち、最外トレンチの側面にはｐベース層３の
みが接している。FIG. 2 shows an embodiment of the present invention.
(A) is a schematic cross-sectional view, and (b) is a schematic plan view. FIG.
The embodiment is different from the embodiment shown in FIG. 1 in that the outermost trench is electrically connected to the gate electrode 10 and that the n + emitter layer 4 adjacent to the outermost trench is not formed. That is, only the p base layer 3 is in contact with the side surface of the outermost trench.
【００１９】これにより、素子がオン状態では、トレン
チの形状や表面状態等が最も不安定な最外トレンチはｎ
+ エミッタ層４が形成されていないため、チャネルは形
成されず、電流は流れない。従って、素子の均一動作が
確実となり、トレンチ外周部におけるしきい値電圧の上
昇による素子のオン電圧の上昇、あるいは、しきい値電
圧の低下によるトレンチ外周部での電流集中による素子
の破壊が生じにくくなる。As a result, when the element is in the ON state, the outermost trench whose trench shape and surface state are the most unstable is n.
Since the + emitter layer 4 is not formed, no channel is formed and no current flows. Therefore, the uniform operation of the element is ensured, and the on-voltage of the element is increased due to the increase of the threshold voltage in the outer periphery of the trench, or the element is broken due to the current concentration in the outer periphery of the trench due to the decrease of the threshold voltage. It gets harder.
【００２０】さらに、素子がオン状態からオフ状態に移
行する際には、キャリア（この場合は正孔）が最も集中
しやすいゲート電極の外周部にｎ+ エミッタ層４が存在
しないため、従来構造よりもキャリア（この場合は正
孔）の出口が広くなり、高速かつ破壊耐量の大きな素子
を得ることができる。Further, when the device shifts from the ON state to the OFF state, the n + emitter layer 4 does not exist on the outer peripheral portion of the gate electrode where carriers (holes in this case) are most likely to concentrate, so that the conventional structure is used. The exit of carriers (holes in this case) is wider than that, and a device having a high speed and a large breakdown resistance can be obtained.
【００２１】図３は本発明の一実施例を示す図であり、
（ａ）は断面模式図、（ｂ）は平面模式図である。図１
に示した実施例と異なる点は、最外トレンチがゲート電
極１０に電気的に接続され、さらに、少なくとも最外ト
レンチに接し、しかも、所定のゲート電圧（例えば１５
Ｖ程度）を印加しても電流が流れないように、ｐベース
層３よりも不純物濃度の高いｐウェル層６が形成されて
いることにある。最外トレンチの側面に接するｎ+ エミ
ッタ層はｐウェル層６に包囲されるように同ウェル層内
に設けられる。FIG. 3 is a diagram showing an embodiment of the present invention.
(A) is a schematic cross-sectional view, and (b) is a schematic plan view. FIG.
The embodiment is different from the embodiment shown in FIG. 1 in that the outermost trench is electrically connected to the gate electrode 10 and is in contact with at least the outermost trench and has a predetermined gate voltage (eg, 15
The p well layer 6 having a higher impurity concentration than the p base layer 3 is formed so that the current does not flow even when a voltage of about V) is applied. The n + emitter layer in contact with the side surface of the outermost trench is provided in the well layer so as to be surrounded by the p well layer 6.
【００２２】これにより、素子がオン状態では、トレン
チの形状や表面状態等が最も不安定となる最外トレンチ
は、ＭＯＳ動作せず、素子のスイッチングには関与しな
い。従って、素子の均一動作が確実となり、トレンチ外
周部におけるしきい値電圧の上昇による素子のオン電圧
の上昇、あるいは、しきい値電圧の低下によるトレンチ
外周部での電流集中による素子の破壊が生じにくくな
る。As a result, when the element is in the ON state, the outermost trench where the shape and surface state of the trench are the most unstable does not operate as a MOS and does not participate in the switching of the element. Therefore, the uniform operation of the element is ensured, and the on-voltage of the element is increased due to the increase of the threshold voltage in the outer periphery of the trench, or the element is broken due to the current concentration in the outer periphery of the trench due to the decrease of the threshold voltage. It gets harder.
【００２３】また、素子がオン状態からオフ状態に移行
する際には、キャリア（この場合は正孔）が最も集中し
やすいゲート電極外周部のｐウェル層６の不純物濃度が
高いため、従来構造よりもキャリア（この場合は正孔）
をスムーズに引き抜くことができるので、高速かつ短絡
耐量の大きな素子を得ることができる。さらに、ｐウェ
ル層６の接合深さを深くすることで、キャリアをよりス
ムーズに引き抜くことができるので、その効果は大きく
なる。Further, when the device shifts from the on state to the off state, the impurity concentration of the p well layer 6 in the peripheral portion of the gate electrode where the carriers (holes in this case) are most likely to concentrate is high, so that the conventional structure is used. Than carriers (holes in this case)
Can be pulled out smoothly, so that it is possible to obtain an element having a high speed and a large short circuit resistance. Further, by making the junction depth of the p-well layer 6 deeper, the carriers can be extracted more smoothly, so that the effect is enhanced.
【００２４】図４は本発明の一実施例を示す図であり、
（ａ）は断面模式図、（ｂ）は平面模式図である。図１
に示した実施例と異なる点は、最外トレンチを囲んでｐ
ベース層３よりも不純物濃度の高いｐウェル層７がｐベ
ース層３よりも深く形成され、しかも、最外トレンチに
隣接するｎ+ エミッタ層４が形成されていないことにあ
る。FIG. 4 is a diagram showing an embodiment of the present invention.
(A) is a schematic cross-sectional view, and (b) is a schematic plan view. FIG.
The difference from the embodiment shown in FIG.
This is because the p well layer 7 having an impurity concentration higher than that of the base layer 3 is formed deeper than the p base layer 3 and the n + emitter layer 4 adjacent to the outermost trench is not formed.
【００２５】これにより、素子がオン状態では、トレン
チの形状や表面状態等が最も不安定となる最外トレンチ
はｐウェル層７で囲まれているため、ＭＯＳ動作せず、
素子のスイッチングには関与しない。従って、素子の均
一動作が確実となり、トレンチ外周部におけるしきい値
電圧の上昇による素子のオン電圧の上昇、あるいは、し
きい値電圧の低下によるトレンチ外周部での電流集中に
よる素子の破壊が生じにくくなる。As a result, when the element is in the ON state, the outermost trench, in which the shape and surface state of the trench are most unstable, is surrounded by the p-well layer 7, so that MOS operation does not occur,
It does not participate in device switching. Therefore, the uniform operation of the element is ensured, and the on-voltage of the element is increased due to the increase of the threshold voltage in the outer periphery of the trench, or the element is broken due to the current concentration in the outer periphery of the trench due to the decrease of the threshold voltage. It gets harder.
【００２６】さらに、素子がオン状態からオフ状態に移
行する際には、キャリア（この場合は正孔）が最も集中
しやすいゲート電極の外周部にｎ+ エミッタ層４が存在
しないため、従来構造よりもキャリア（この場合は正
孔）の出口が広くなり、高速かつ破壊耐量の大きな素子
を得ることができる。しかも、図２の実施例に比べ、接
合深さが深く、かつ、不純物濃度の高いｐウェル層７を
形成しているため、チップ周辺のキャリア（この場合は
正孔）をよりスムーズに引き抜くことができるので、さ
らに、高速かつ破壊耐量の大きな素子を得ることができ
る。そして、オフ状態においては、最も電界の集中しや
すい最外トレンチの底部がｐウェル層７で囲まれている
ため、電界が緩和され、従来構造に比べ、素子耐圧も向
上する。Further, when the device shifts from the ON state to the OFF state, the n + emitter layer 4 does not exist on the outer peripheral portion of the gate electrode where carriers (holes in this case) are most likely to concentrate, so that the conventional structure is used. The exit of carriers (holes in this case) is wider than that, and a device having a high speed and a large breakdown resistance can be obtained. Moreover, since the p-well layer 7 having a deeper junction depth and a higher impurity concentration is formed as compared with the embodiment of FIG. 2, carriers (holes in this case) around the chip can be extracted more smoothly. Therefore, it is possible to obtain an element having a high speed and a large breakdown resistance. In the off state, the bottom of the outermost trench where the electric field is most likely to be concentrated is surrounded by the p-well layer 7, so that the electric field is relaxed and the breakdown voltage of the device is improved as compared with the conventional structure.
【００２７】なお、図５は、このようなＭＯＳ動作をし
ないダミーゲートを２個形成した場合の模式図である。
（ａ）は断面模式図、（ｂ）は平面模式図である。この
ように、ダミーゲートを２個（１０Ａ，１０Ｂ）、ある
いは３個，４個などと複数個形成することにより、上記
の効果はさらに大きくなる。しかしながら、その数をあ
まり多くしすぎると、アクティブ領域が狭くなり、オン
電圧低減効果が低減してしまうので、注意が必要であ
る。FIG. 5 is a schematic view of a case in which two dummy gates which do not operate as described above are formed.
(A) is a schematic cross-sectional view, and (b) is a schematic plan view. As described above, by forming a plurality of dummy gates such as two (10A, 10B) or three or four dummy gates, the above effect is further enhanced. However, if the number is too large, the active area becomes narrow and the effect of reducing the on-voltage decreases, so caution is required.
【００２８】図６は図４を用いて説明した実施例の異な
る断面における一実施例であり、（ａ），（ｂ）は断面
模式図、（ｃ）は平面模式図である。ｐ+ 基板１上にｎ
-ドリフト層２が形成される。そして、ｎ- ドリフト層
２の表面にｐベース層３が形成され、さらに、ドライエ
ッチング技術を使って、ｐベース層３を貫通して、トレ
ンチが形成され、トレンチ表面にゲート絶縁膜９及びゲ
ート電極１０が形成される。さらに、トレンチに隣接
し、トレンチ端部よりも内側にｎ+ エミッタ層４が形成
される。さらに、トレンチ端部を囲み、トレンチよりも
形成深さの深いｐウェル層５が形成される。そして、ｐ
+ 基板１の裏面上にコレクタ電極１１が形成され、ｎ-
ドリフト層２上にｐベース層３及びｎ+ エミッタ層４に
接するようにエミッタ電極１２が形成される。FIG. 6 shows an embodiment in a different cross section of the embodiment described with reference to FIG. 4, where (a) and (b) are schematic sectional views and (c) are schematic plan views. n on p + substrate 1
-Drift layer 2 is formed. Then, a p base layer 3 is formed on the surface of the n − drift layer 2, and a trench is formed through the p base layer 3 by using a dry etching technique, and a gate insulating film 9 and a gate are formed on the trench surface. The electrode 10 is formed. Further, an n + emitter layer 4 is formed adjacent to the trench and inside the end of the trench. Further, a p-well layer 5 that surrounds the trench end and is deeper than the trench is formed. And p
+ The collector electrode 11 is formed on the back surface of the substrate 1, and n−
An emitter electrode 12 is formed on drift layer 2 so as to contact p base layer 3 and n + emitter layer 4.
【００２９】トレンチの形状や表面状態等が最も不安定
なトレンチ端部にはｎ+ エミッタ層４が形成されていな
いため、チャネルは形成されず、電流は流れない。さら
に、トレンチ端部は深いｐウェル層で覆われているた
め、素子の均一動作がより確実となり、トレンチ外周部
におけるしきい値電圧の上昇による素子のオン電圧の上
昇、あるいは、しきい値電圧の低下によるトレンチ外周
部での電流集中による素子の破壊が生じにくくなる。Since the n + emitter layer 4 is not formed at the end of the trench where the shape and surface condition of the trench are the most unstable, no channel is formed and no current flows. Further, since the trench end is covered with the deep p-well layer, uniform operation of the device is more reliable, and the on-voltage of the device is increased due to the increase of the threshold voltage in the outer periphery of the trench, or the threshold voltage is increased. The breakdown of the element due to the current concentration in the outer peripheral portion of the trench due to the decrease of the resistance is less likely to occur.
【００３０】さらに、素子がオン状態からオフ状態に移
行する際には、キャリア（この場合は正孔）が最も集中
しやすいゲート電極の外周部にｎ+ エミッタ層４が存在
しないため、従来構造よりもキャリア（この場合は正
孔）の出口が広くなり、高速かつ破壊耐量の大きな素子
を得ることができる。しかも、接合深さの深いｐウェル
層５を形成しているため、チップ周辺のキャリア（この
場合は正孔）をよりスムーズに引き抜くことができるの
で、さらに、高速かつ破壊耐量の大きな素子を得ること
ができる。また、ｐウェル層５の不純物濃度を高くする
ことにより、この効果はより顕著となる。そして、オフ
状態においては、最も電界の集中しやすいトレンチ端部
がｐウェル層５で囲まれているため、電界が緩和され、
従来構造に比べ、素子耐圧も向上する。Further, when the device shifts from the ON state to the OFF state, the n + emitter layer 4 does not exist on the outer peripheral portion of the gate electrode where carriers (holes in this case) are most likely to be concentrated. The exit of carriers (holes in this case) is wider than that, and a device having a high speed and a large breakdown resistance can be obtained. Moreover, since the p-well layer 5 having a deep junction depth is formed, carriers (holes in this case) around the chip can be extracted more smoothly, and thus an element having a high speed and a large breakdown resistance can be obtained. be able to. Further, this effect becomes more remarkable by increasing the impurity concentration of the p well layer 5. In the off state, the trench well where the electric field is most likely to be concentrated is surrounded by the p-well layer 5, so that the electric field is relaxed.
The breakdown voltage of the device is also improved as compared with the conventional structure.
【００３１】図７は本発明のトレンチＩＧＢＴを使って
構成したモータ駆動用インバータ回路の例である。トレ
ンチIGBT100 には逆並列にダイオード１０１が接続され
ており、トレンチＩＧＢＴが２個直列に接続され、１相
が形成されている。トレンチＩＧＢＴが接続された中点
から出力され、モータ１０６と接続されている。上アー
ム側のトレンチIGBT100a，b，cのコレクタは共通であ
り、整流回路の高電位側と接続されている。また、下ア
ーム側のトレンチIGBT100d，e，fのエミッタは共通であ
り、整流回路のアース側と接続されている。整流回路１
０３は、交流電源１０２を直流に変換する。トレンチIG
BT100 は、この直流を受電し、再度交流に変換してモー
タを駆動する。上下の駆動回路１０４，１０５は、トレ
ンチIGBTのゲートに駆動信号を伝え、所定の周期でトレ
ンチＩＧＢＴをオン・オフさせる。本実施例では、トレ
ンチＩＧＢＴにダミーゲートを使用することにより、オ
ン電圧が低下し、さらに、破壊耐量及び素子耐圧が向上
するため、従来のトレンチＩＧＢＴを使用した場合より
も、低損失で、信頼性の高いインバータを提供できる。FIG. 7 shows an example of a motor driving inverter circuit constructed by using the trench IGBT of the present invention. A diode 101 is connected to the trench IGBT 100 in anti-parallel, and two trench IGBTs are connected in series to form one phase. The signal is output from the middle point where the trench IGBT is connected, and is connected to the motor 106. The collectors of the trench IGBTs 100a, b, c on the upper arm side are common and are connected to the high potential side of the rectifier circuit. In addition, the emitters of the trench IGBTs 100d, e, f on the lower arm side are common and are connected to the ground side of the rectifier circuit. Rectifier circuit 1
03 converts the AC power supply 102 into DC. Trench IG
The BT100 receives this direct current, converts it to alternating current, and drives the motor. The upper and lower drive circuits 104 and 105 transmit a drive signal to the gate of the trench IGBT to turn on / off the trench IGBT at a predetermined cycle. In the present embodiment, the use of the dummy gate in the trench IGBT lowers the on-voltage, and further improves the breakdown resistance and the device breakdown voltage. A highly reliable inverter can be provided.
【００３２】なお、実施例では、半導体素子の例として
ＩＧＢＴのみについて述べたが、絶縁ゲートを持つ他の
素子、例えば、トレンチ型のパワーMOSFET及びＭＯＳサ
イリスタなどでも同様の効果があるのは明らかである。
パワーMOSFETの場合、上記実施例のｐ+ 基板１がｎ+ 基
板に置き替わる。また従来のＩＧＢＴと同様に図８にお
けるｎ+ バッファ層２０を形成してもよい。In the embodiment, only the IGBT is described as an example of the semiconductor element, but it is obvious that other elements having an insulated gate, such as a trench type power MOSFET and a MOS thyristor, have the same effect. is there.
In the case of a power MOSFET, the p + substrate 1 in the above embodiment is replaced with an n + substrate. Further, n + buffer layer 20 in FIG. 8 may be formed similarly to the conventional IGBT.
【００３３】[0033]
【発明の効果】以上説明したように、本発明によるトレ
ンチ型の絶縁ゲートを有する半導体装置の場合、少なく
とも最外周のトレンチをダミーゲートとすることによ
り、トレンチ外周部におけるしきい値電圧の上昇による
素子のオン電圧の上昇、あるいは、しきい値電圧の低下
によるトレンチ外周部での電流集中による素子の破壊が
生じにくくなる。As described above, in the case of the semiconductor device having the trench type insulated gate according to the present invention, at least the outermost trench is used as the dummy gate, so that the threshold voltage in the outer periphery of the trench increases. The breakdown of the device due to current concentration in the outer peripheral portion of the trench due to increase in the on-voltage of the device or decrease in the threshold voltage is less likely to occur.
【図１】本発明による一実施例を説明する断面模式図及
び平面模式図である。FIG. 1 is a schematic sectional view and a schematic plan view illustrating an embodiment according to the present invention.
【図２】本発明による一実施例を説明する断面模式図及
び平面模式図である。2A and 2B are a schematic sectional view and a schematic plan view for explaining an embodiment according to the present invention.
【図３】本発明による一実施例を説明する断面模式図及
び平面模式図である。FIG. 3 is a schematic sectional view and a schematic plan view for explaining an embodiment according to the present invention.
【図４】本発明による一実施例を説明する断面模式図及
び平面模式図である。FIG. 4 is a schematic sectional view and a schematic plan view for explaining an embodiment according to the present invention.
【図５】本発明による一実施例を説明する断面模式図及
び平面模式図である。5A and 5B are a schematic sectional view and a schematic plan view illustrating an embodiment according to the present invention.
【図６】本発明による一実施例を説明する断面模式図及
び平面模式図である。6A and 6B are a schematic sectional view and a schematic plan view illustrating an embodiment according to the present invention.
【図７】本発明の電圧駆動型半導体装置を使用したイン
バータ装置の一実施例を説明する回路図である。FIG. 7 is a circuit diagram illustrating an embodiment of an inverter device using the voltage-driven semiconductor device of the present invention.
【図８】従来のトレンチ型の絶縁ゲートを有するＩＧＢ
Ｔの断面模式図及び平面模式図である。FIG. 8 shows a conventional IGB having a trench-type insulated gate.
It is a cross-sectional schematic diagram and plane schematic diagram of T.
【図９】従来のトレンチ型の絶縁ゲートを有するMOSFET
の断面模式図及び平面模式図である。FIG. 9 is a conventional MOSFET having a trench type insulated gate.
FIG. 3 is a schematic sectional view and a schematic plan view of FIG.
１…ｐ+ 基板、２…ｎ- ドリフト層、３…ｐベース層、
４…ｎ+ エミッタ層、５，６，７…ｐウェル層、９…ゲ
ート絶縁膜、１０…ゲート電極、１１…コレクタ電極、
１２…エミッタ電極、２０…ｎ+ バッファ層、１００…
トレンチIGBT、１０１…ダイオード、１０２…交流電
源、１０３…整流回路、１０４…上アーム駆動回路、１
０５…下ア−ム駆動回路、１０６…モータ。1 ... p + substrate, 2 ... n- drift layer, 3 ... p base layer,
4 ... n + emitter layer, 5,6,7 ... p well layer, 9 ... gate insulating film, 10 ... gate electrode, 11 ... collector electrode,
12 ... Emitter electrode, 20 ... N + buffer layer, 100 ...
Trench IGBT, 101 ... Diode, 102 ... AC power supply, 103 ... Rectifier circuit, 104 ... Upper arm drive circuit, 1
05 ... lower arm drive circuit, 106 ... motor.
Claims (6)
と、 第２半導体領域に隣接する第２導電型の第３半導体領域
と、 第３半導体領域内に設けられる第１導電型の第４半導体
領域と、を有する半導体チップを備え、 第１半導体領域に接触する第１主電極と、 第４半導体領域に接触する第２主電極と、 第３半導体領域を貫通する複数のトレンチ内に設けられ
る絶縁ゲート電極と、を具備し、 半導体チップのターミネーション部に隣接するトレンチ
内に設けられる絶縁ゲート電極が第２主電極に接続され
ることを特徴とする電圧駆動型半導体装置。1. A first semiconductor region, a second semiconductor region of a first conductivity type adjacent to the first semiconductor region, a third semiconductor region of a second conductivity type adjacent to the second semiconductor region, and a third semiconductor. A semiconductor chip having a fourth semiconductor region of a first conductivity type provided in the region, a first main electrode in contact with the first semiconductor region, a second main electrode in contact with the fourth semiconductor region, And an insulated gate electrode provided in a plurality of trenches penetrating the semiconductor region, wherein the insulated gate electrode provided in the trench adjacent to the termination portion of the semiconductor chip is connected to the second main electrode. Voltage drive type semiconductor device.
と、 第２半導体領域に隣接する第２導電型の第３半導体領域
と、 第３半導体領域内に設けられる第１導電型の第４半導体
領域と、を有する半導体チップを備え、 第１半導体領域に接触する第１主電極と、 第４半導体領域に接触する第２主電極と、 第３半導体領域を貫通する複数のトレンチ内に設けられ
る絶縁ゲート電極と、を具備し、 半導体チップのターミネーション部に隣接するトレンチ
の側面には第３半導体領域のみが接することを特徴とす
る電圧駆動型半導体装置。2. A first semiconductor region, a second semiconductor region of the first conductivity type adjacent to the first semiconductor region, a third semiconductor region of the second conductivity type adjacent to the second semiconductor region, and a third semiconductor. A semiconductor chip having a fourth semiconductor region of a first conductivity type provided in the region, a first main electrode in contact with the first semiconductor region, a second main electrode in contact with the fourth semiconductor region, And a insulated gate electrode provided in a plurality of trenches penetrating the three semiconductor regions, wherein only the third semiconductor region is in contact with the side surface of the trench adjacent to the termination portion of the semiconductor chip. Semiconductor device.
と、 第２半導体領域に隣接する第２導電型の第３半導体領域
と、 第３半導体領域内に設けられる第１導電型の第４半導体
領域と、を有する半導体チップを備え、 第１半導体領域に接触する第１主電極と、 第４半導体領域に接触する第２主電極と、 第３半導体領域を貫通する複数のトレンチ内に設けられ
る絶縁ゲート電極と、を具備し、 半導体チップのターミネーション部に隣接するトレンチ
側面に接する第４半導体領域を包囲するように、第３半
導体領域よりも不純物濃度が高い第２導電型の第５半導
体領域が設けられることを特徴とする電圧駆動型半導体
装置。3. A first semiconductor region, a second semiconductor region of a first conductivity type adjacent to the first semiconductor region, a third semiconductor region of a second conductivity type adjacent to the second semiconductor region, and a third semiconductor. A semiconductor chip having a fourth semiconductor region of a first conductivity type provided in the region, a first main electrode in contact with the first semiconductor region, a second main electrode in contact with the fourth semiconductor region, An insulated gate electrode provided in a plurality of trenches penetrating the third semiconductor region, and surrounding the fourth semiconductor region in contact with the side surface of the trench adjacent to the termination portion of the semiconductor chip. A voltage-driven semiconductor device comprising a fifth semiconductor region of the second conductivity type having a high impurity concentration.
と、 第２半導体領域に隣接する第２導電型の第３半導体領域
と、 第３半導体領域内に設けられる第１導電型の第４半導体
領域と、を有する半導体チップを備え、 第１半導体領域に接触する第１主電極と、 第４半導体領域に接触する第２主電極と、 第３半導体領域を貫通する複数のトレンチ内に設けられ
る絶縁ゲート電極と、を具備し、 半導体チップのターミネーション部に隣接するトレンチ
を包囲するように、第３半導体領域よりも深い第２導電
型の第５半導体領域が設けられることを特徴とする電圧
駆動型半導体装置。4. A first semiconductor region, a second semiconductor region of the first conductivity type adjacent to the first semiconductor region, a third semiconductor region of the second conductivity type adjacent to the second semiconductor region, and a third semiconductor. A semiconductor chip having a fourth semiconductor region of a first conductivity type provided in the region, a first main electrode in contact with the first semiconductor region, a second main electrode in contact with the fourth semiconductor region, An insulated gate electrode provided in a plurality of trenches penetrating the third semiconductor region, and a second conductivity type deeper than the third semiconductor region so as to surround the trench adjacent to the termination portion of the semiconductor chip. 5. A voltage drive type semiconductor device, wherein 5 semiconductor regions are provided.
電圧駆動型半導体装置において、第１半導体領域が第１
導電型であることを特徴とする電圧駆動型半導体装置。5. The voltage-driven semiconductor device according to claim 1, wherein the first semiconductor region is the first semiconductor region.
A voltage-driven semiconductor device, which is of a conductive type.
電圧駆動型半導体装置において、第１半導体領域が第２
導電型であることを特徴とする電圧駆動型半導体装置。6. The voltage-driven semiconductor device according to claim 1, wherein the first semiconductor region is a second semiconductor region.
A voltage-driven semiconductor device, which is of a conductive type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08233196A JP3257394B2 (en) | 1996-04-04 | 1996-04-04 | Voltage driven semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08233196A JP3257394B2 (en) | 1996-04-04 | 1996-04-04 | Voltage driven semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09275212A true JPH09275212A (en) | 1997-10-21 |
| JP3257394B2 JP3257394B2 (en) | 2002-02-18 |
Family
ID=13771586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP08233196A Expired - Lifetime JP3257394B2 (en) | 1996-04-04 | 1996-04-04 | Voltage driven semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3257394B2 (en) |
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