JPH09260522A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH09260522A JPH09260522A JP8064115A JP6411596A JPH09260522A JP H09260522 A JPH09260522 A JP H09260522A JP 8064115 A JP8064115 A JP 8064115A JP 6411596 A JP6411596 A JP 6411596A JP H09260522 A JPH09260522 A JP H09260522A
- Authority
- JP
- Japan
- Prior art keywords
- noise
- envelope
- power supply
- filter
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は外囲器を備える半導
体装置に関わり、特にグランド即ちＧＮＤのノイズ対策
に好適する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an envelope, and is particularly suitable as a countermeasure against ground noise, that is, GND noise.
【０００２】[0002]
【従来の技術】半導体素子とりわけ多ピン素子の例えば
ＣＰＵなどが利用する外囲器には、図９に示すようにい
わゆるＰＧＡ（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）型が頻
繁に利用されている。即ちセラミック板２０に環状のセ
ラミック２１を多段に取付け、セラミック板２０に固定
した集積回路２２は、セラミック２１に配置される配線
層２４と電気的に固定し、これは露出された環状のセラ
ミック２１に設置するリード端子２５と接続する構造が
採られている。2. Description of the Related Art As shown in FIG. 9, a so-called PGA (Pin Grid Array) type is frequently used for an envelope used by a semiconductor device, especially a multi-pin device such as a CPU. That is, the annular ceramics 21 are attached to the ceramic plate 20 in multiple stages, and the integrated circuit 22 fixed to the ceramic plate 20 is electrically fixed to the wiring layer 24 arranged on the ceramic 21. This is the exposed annular ceramic 21. The structure is such that it is connected to the lead terminal 25 installed at.
【０００３】又集積回路２２を覆う例えば金属製の蓋２
３を環状のセラミック２１の開口面を覆って固着して外
部雰囲気から保護する。配線層２４は、例えばスクリー
ン印刷法により環状のセラミック２１に形成され、環状
のセラミック２１の露出面又はスルーホールを通って
（図示せず）環状のセラミック２１外に導出し、ここに
配置するリード端子２５と電気的に接続する。A lid 2 made of, for example, a metal, which covers the integrated circuit 22,
3 is fixed by covering the opening surface of the annular ceramic 21 to protect it from the external atmosphere. The wiring layer 24 is formed on the ring-shaped ceramic 21 by, for example, a screen printing method, and is led out to the outside of the ring-shaped ceramic 21 through the exposed surface of the ring-shaped ceramic 21 or a through hole (not shown), and is placed there. It is electrically connected to the terminal 25.
【０００４】集積回路２２と配線層２４間には，金属細
線２６を例えばボンディング法により架橋して電気的に
接続する。この結果例えばコバール製の蓋２３の周りに
は、多数例えば３００ピンのリード端子２５が林立する
状態になる。A thin metal wire 26 is electrically connected between the integrated circuit 22 and the wiring layer 24 by bridging, for example, a bonding method. As a result, a large number of lead terminals 25 of, for example, 300 pins stand around the Kovar lid 23.
【０００５】又このような外囲器にマウントした集積回
路２２に電気的に接続するリード端子２５は、電子回路
を設けたボードｃ（図１０参照）に挿入半田付けする。
このような構造の等価回路図が図１０に示されており、
点線で区切られたａが集積回路、ｂがＰＧＡ外囲器であ
る。The lead terminal 25 electrically connected to the integrated circuit 22 mounted on such an envelope is inserted and soldered into a board c (see FIG. 10) provided with an electronic circuit.
An equivalent circuit diagram of such a structure is shown in FIG.
An a is an integrated circuit and a b is a PGA envelope which is separated by a dotted line.
【０００６】この図１０においては、外囲器ｂに寄生又
は取付けられるインダクタンスと抵抗をＬ及びＲと記載
した。入力バッファ２８と出力バッファ２７はそれぞれ
ＰＧＡ外囲器ｂに入力して、ここに寄生するインダクタ
ンスＬと抵抗Ｒを経て、ボードｃにも寄生するインダク
タンスＬと抵抗Ｒを介して出力系電源用ＶD D 端子２９
に電気的に接続され、又出力端子ｄ、ＧＮＤ端子ｅに接
続する。従って出力バッファ２７のスイッチングにより
生ずる電源ノイズは、ＰＧＡ外囲器ｂとボードｃに寄生
するインダクタンスＬと抵抗Ｒを介して入力系電源用配
線ｆを経由して入力バッファ２８にも伝搬する。In FIG. 10, the inductance and resistance parasitic or attached to the envelope b are described as L and R. The input buffer 28 and the output buffer 27 are input to the PGA envelope b, respectively, through the inductance L and the resistance R parasitic there, and via the inductance L and the resistance R parasitic on the board c as well. DD terminal 29
To the output terminal d and the GND terminal e. Therefore, the power supply noise generated by the switching of the output buffer 27 is also propagated to the input buffer 28 via the input system power supply wiring f via the inductance L and the resistance R parasitic on the PGA envelope b and the board c.
【０００７】このように多ピン化した集積回路２２の高
速化に伴い、出力バッファがスイッチングすると電源が
揺れる同時スイッチング・ノイズなどが問題化してい
る。このノイズが入力バッファの電源に伝搬して回路の
誤動作を防止するために、外囲器における入出力電源を
分離する方策が採られている。With the increase in speed of the integrated circuit 22 having a large number of pins as described above, there is a problem such as simultaneous switching noise in which the power supply fluctuates when the output buffer switches. In order to prevent this noise from propagating to the power supply of the input buffer and malfunctioning of the circuit, a measure is taken to separate the input and output power supplies in the envelope.
【０００８】[0008]
【発明が解決しようとする課題】このような電源を分離
するなどの対策は、多少の効果はあるものの、分離した
電源が容量などにより電気的に結合しているために、ノ
イズの伝搬を効果的に防止する決定的な手段と言えな
い。Although the measures such as separating the power source have some effect, the separated power sources are electrically coupled by the capacity or the like, so that noise propagation is effective. It cannot be said to be a decisive means to prevent it.
【０００９】本発明はこのような事情により成されたも
ので、特に集積回路などを搭載する外囲器やボードなど
の電源ノイズ対策を効果的にする。The present invention has been made in view of the above circumstances, and in particular makes effective measures against power supply noise in an enclosure or board on which an integrated circuit or the like is mounted.
【００１０】[0010]
【課題を解決するための手段】本発明に係る半導体装置
における第１の発明は、半導体素子を搭載する外囲器及
びボード用電源に４０ｍｍ以上の帯域フィルタを取付け
た点に特徴がある。A first aspect of the semiconductor device according to the present invention is characterized in that a band filter having a length of 40 mm or more is attached to a power supply for an envelope and a board on which a semiconductor element is mounted.
【００１１】第２の発明は、半導体素子を搭載する外囲
器及びボード用入力電源に４０ｍｍ以上の帯域フィルタ
を取付けた点に特徴があり、第３の発明は、半導体素子
を搭載する外囲器及びボード用出力電源に４０ｍｍ以上
の帯域フィルタを取付けた点に特徴がある。A second aspect of the present invention is characterized in that a band filter having a length of 40 mm or more is attached to an enclosure for mounting a semiconductor element and a board input power source, and a third aspect of the invention is for an enclosure on which a semiconductor element is mounted. The feature is that a band-pass filter of 40 mm or more is attached to the output power source for the container and the board.
【００１２】半導体素子をマウントした絶縁物から成る
外囲器及びボードに固着する際の等価回路の一例を図２
に明らかにした。この図では従来の技術欄と同様に集積
回路ａ、ＰＧＡ外囲器がｂ、ボードがｃとして表わして
いる。例えばＰＧＡ外囲器ｂならびにボードｃには、寄
生的にインダクタンスＬ1 Ｌ2 や抵抗などが生じ、更に
集積回路ａ内には入力バッファ２及び出力バッファ３が
形成され、前者は集積回路ａ内に形成するパッド４に電
気的に接続する。更にボードｃには、ＶD D 端子５、Ｖ
S S 端子６及び５Ｖの電源７を設けると共に、ＰＧＡ外
囲器に設置する帯域フィルタ８をＶD D 端子５に電気的
に接続する。FIG. 2 shows an example of an equivalent circuit when the semiconductor element is mounted on an enclosure made of an insulating material and a board.
Revealed to. In this figure, the integrated circuit a, the PGA envelope are shown as b, and the board is shown as c, as in the prior art section. For example, in the PGA envelope b and the board c, inductances L 1 L 2 and resistance are parasitically generated, and the input buffer 2 and the output buffer 3 are further formed in the integrated circuit a. It is electrically connected to the pad 4 formed in. Furthermore, on board c, V DD terminal 5, V
The SS terminal 6 and the 5V power supply 7 are provided, and the bandpass filter 8 installed in the PGA envelope is electrically connected to the V DD terminal 5.
【００１３】このような回路においては、ＶD D 端子５
側では、出力バッファ３によるＣーＢーＡ点を流れる電
流と、Ｌ1 とＬ2 を経る電流ノイズがＢーＤを経て入力
バッファ２に伝搬されるのが、出力バッファ３によりＢ
ーＤ間には流れない。これはＢーＤ間のパルスの伝搬と
想定でき、従って本願では、ノイズの主成分の周波数を
帯域フィルタ８によりカットして、Ｄ点におけるノイズ
が減少される。In such a circuit, the V DD terminal 5
On the side, the current flowing through the point C-B-A due to the output buffer 3 and the current noise passing through L 1 and L 2 are propagated to the input buffer 2 via B-D.
It does not flow between -D. This can be assumed to be pulse propagation between B and D. Therefore, in the present application, the frequency of the main component of noise is cut by the bandpass filter 8 to reduce the noise at point D.
【００１４】帯域フィルタ８をＢーＤ間に設置する例を
図４により説明すると、帯域フィルタ８により分岐線ｌ
1 とｌ2 を設置することにより（１＋２ｍ）／４×λ
（ｍ＝０、１、２…整数）の周波数をカットすることに
なる。なおλは波長を示す。An example of installing the bandpass filter 8 between BD will be described with reference to FIG.
(1 + 2m) / 4 × λ by installing 1 and l 2
The frequencies of (m = 0, 1, 2, ... Integer) will be cut. Note that λ indicates the wavelength.
【００１５】以上のように入出力電源間に４０ｍｍの帯
域フィルタ８を配置することにより、ノイズの主成分の
周波数だけを遮断してノイズの伝搬が防止される。By disposing the bandpass filter 8 of 40 mm between the input and output power sources as described above, only the frequency of the main component of noise is cut off and the propagation of noise is prevented.
【００１６】一般的なノイズの周波数成分は、集積回路
の性能にもよるが５０Ｍ〜５００ＭＨｚが多く、この帯
域をカットする帯域フィルタ８は、絶縁物例えばセラミ
ック表面で４０〜５００ｍｍの長さが必要である。現在
の外囲器ｂにあっては、メッキを行う型例えばＰＧＡな
どの岐線の長さが２０ｍｍ以下が殆どであり、これでは
１ＧＨｚ以上にしか効果がなくノイズフイルタとして機
能しない。The frequency component of general noise is often 50 M to 500 MHz depending on the performance of the integrated circuit, and the band filter 8 that cuts this band needs to have a length of 40 to 500 mm on an insulating material such as a ceramic surface. Is. In the current envelope b, the length of the line for plating, such as PGA, is 20 mm or less in most cases, and this is effective only at 1 GHz or more and does not function as a noise filter.
【００１７】なお帯域フィルタ８の長さが必要な場合に
は図５及び図６に示すように直線状でなく、入り組んだ
パターンとすることもできる。When the band-pass filter 8 needs to have a length, it may have a complicated pattern instead of the straight line as shown in FIGS.
【００１８】外囲器ｂから後述する配線２４と２４′
（図２、３参照）や容量を介して、入力系電源に伝搬
し、半導体チップａに形成される入力バッファ（図２な
ど参照）に伝わる。そして後述するオープンスタブ８の
ようなフィルター効果のある構造は入力系電源でノイズ
が伝搬するのを防止する。Wirings 24 and 24 'which will be described later from the envelope b.
(See FIGS. 2 and 3) and a capacitor, and propagates to the input power supply and is transmitted to the input buffer (see FIG. 2 and the like) formed in the semiconductor chip a. A structure having a filter effect, such as an open stub 8 described later, prevents noise from propagating in the input power supply.
【００１９】又図８のように出力系電源にも同様なフィ
ルター効果のある構造を取入れることにより、電流変化
率を変化させると共にノイズの反射を利用して、出力系
ノイズを分散低減することができる。Further, as shown in FIG. 8, by incorporating a structure having a similar filter effect in the output system power source, the output system noise is dispersed and reduced by changing the current change rate and utilizing the noise reflection. You can
【００２０】[0020]
【発明の実施の形態】本発明に係る実施の形態を図１乃
至図８を参照して説明する。図２及び図８において点線
で区切られたａ、ｂ、ｃは、従来の技術と同様に半導体
チップａ、外囲器ｂそしてボードｃを表す。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIGS. 2 and 8, a, b, and c separated by a dotted line represent the semiconductor chip a, the envelope b, and the board c, as in the conventional technique.
【００２１】帯域フィルタ８を入力系電源２に接続した
第１の実施の形態における半導体装置の構造を図１の断
面図により説明するが、この後の実施例で説明するＰＧ
Ａ外囲器ｂの構造は従来の技術と全く同じなので説明を
省略し番号も同じにする。The structure of the semiconductor device according to the first embodiment in which the band-pass filter 8 is connected to the input system power supply 2 will be described with reference to the sectional view of FIG. 1. The PG described in the subsequent examples.
Since the structure of the A envelope b is exactly the same as that of the conventional technique, its description is omitted and the numbers are the same.
【００２２】ＰＧＡ外囲器ｂの周りには例えば３００ピ
ンのリード端子２５が林立する状態になるが、これには
他の配線２４′を利用する。即ち板状のセラミック２０
には多段の環状のセラミック２１を固着することにより
表面部分を露出させ、ここに半導体チップａをマウント
する。一方多段の環状のセラミック２１にも形成される
環状の露出表面には配線２４を設置し、多段の環状のセ
ラミック２１間に形成する図示しない例えばスルーホー
ルを利用して他の配線２４′を設け、これにより配線２
４と電気的に接続する。半導体チップａには入力バッフ
ァ２ならびに出力バッファ３などから成る集積回路が形
成され、環状のセラミック２１の露出表面に形成する配
線２４とこの集積回路の所定の電極間を電気的に結ぶ金
属細線２６により接続する。このように配線２４と２
４′により帯域フィルタ８はリード端子２５に電気的に
接続される。又ＶD D 端子５、ＶS S 端子６及び５Ｖの
電源７に帯域フィルタ８が電気的に接続される。A lead terminal 25 of, for example, 300 pins stands around the PGA envelope b, and another wiring 24 'is used for this. That is, the plate-shaped ceramic 20
A multi-stage annular ceramic 21 is fixedly attached to expose the surface portion, and the semiconductor chip a is mounted thereon. On the other hand, the wiring 24 is installed on the annular exposed surface that is also formed on the multistage annular ceramic 21, and another wiring 24 'is provided by using, for example, a through hole (not shown) formed between the multistage annular ceramics 21. , By this, wiring 2
4 and electrically connected. An integrated circuit including an input buffer 2 and an output buffer 3 is formed on the semiconductor chip a, and a metal wire 26 that electrically connects a wiring 24 formed on the exposed surface of the annular ceramic 21 and a predetermined electrode of this integrated circuit. To connect. In this way wiring 24 and 2
The band filter 8 is electrically connected to the lead terminal 25 by 4 '. A bandpass filter 8 is electrically connected to the V DD terminal 5, the V SS terminal 6 and the 5 V power source 7.
【００２３】図３には図１と相違する例を示した。すな
わち帯域フィルタ８より他の配線２４′を設置して配線
２４と電気的に接続しているのは前記の通りである。FIG. 3 shows an example different from FIG. That is, as described above, the other wire 24 ′ is installed from the bandpass filter 8 and is electrically connected to the wire 24.
【００２４】次に第２の実施の形態としてＰＧＡ外囲器
ｂの出力系電源に帯域フィルタ８を電気的に接続する例
を図７に示すが、ほぼ図１の断面図と同様な形状にな
る。帯域フィルタ８は直線状の外にノイズ周波数の主成
分が低い時には、図５と図６に明らかにしたように直線
を折曲げる形状や、箱状の形状にして長さをかせぐこと
もできる。Next, as a second embodiment, an example of electrically connecting the bandpass filter 8 to the output system power source of the PGA envelope b is shown in FIG. 7, which has a shape similar to that of the sectional view of FIG. Become. When the main component of the noise frequency is low in addition to the linear shape, the band-pass filter 8 may be formed by bending a straight line as shown in FIGS. 5 and 6, or may be formed in a box shape to gain the length.
【００２５】更にＰＧＡ外囲器ｂの出力系電源に帯域フ
ィルタ８を取付ける例として第３の実施の形態を図８の
等価回路図により説明する。A third embodiment will be described with reference to the equivalent circuit diagram of FIG. 8 as an example in which the bandpass filter 8 is attached to the output power supply of the PGA envelope b.
【００２６】この実施の形態は、第２の実施の形態と同
様にＰＧＡタイプの外囲器ｂにフィルター効果を取入れ
た実施例であるが、出力系電源のＶD D ３０とフィルタ
ー構造のＧＮＤ３１を組合せ、更に出力系電源のＧＮＤ
３２とフィルター構造のＶD D ３３を組合せた構造であ
る。フィルター構造のＧＮＤ３１とフィルター構造のＶ
D D ３３にはフィルター８ー１と８ー２を設置した。This embodiment is an embodiment in which the filter effect is incorporated in the PGA type envelope b as in the second embodiment, but V DD 30 of the output system power supply and GND 31 of the filter structure are used. Combination, and output system power supply GND
32 and a filter structure V D D 33 are combined. Filter structure GND31 and filter structure V
Filters 8-1 and 8-2 were installed on DD 33.
【００２７】これにより出力系系電源ＶD D 端子５に流
れる電流がフィルター構造のＧＮＤ３１に、出力系電源
３０のＧＮＤを流れる電流をフィルター構造のＶD D ３
３Ｇに逃がすことができる。これにより、出力系の電源
に生ずるインダクタンス３４にながれるスイッチング電
流が低減されると共に電流をＧＮＤとＶD D に振分ける
ことができる。As a result, the current flowing through the output system power supply V DD terminal 5 flows into the GND 31 of the filter structure, and the current flowing through the GND of the output system power supply 30 flows into the V DD 3 of the filter structure.
You can escape to 3G. As a result, the switching current flowing to the inductance 34 generated in the power supply of the output system is reduced and the current can be distributed between GND and V DD .
【００２８】[0028]
【発明の効果】以上のように、電源系のノイズが抑えら
れるので、集積回路を搭載するシステムを安定した状態
で高速動作させることが可能になり、構造的にも従来の
外囲器や配線基板に帯域フィルタ８を設置するだけなの
で、スペースとコストも変えずに実現できる。As described above, since the noise of the power supply system is suppressed, it becomes possible to operate the system in which the integrated circuit is mounted at a high speed in a stable state, and structurally the conventional enclosure and wiring. Since only the bandpass filter 8 is installed on the substrate, it can be realized without changing the space and cost.
【図１】本発明に関わる半導体装置の実施の形態を示す
断面図である。FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention.
【図２】図１の半導体装置の等価回路図である。FIG. 2 is an equivalent circuit diagram of the semiconductor device of FIG.
【図３】本発明に関わる半導体装置の他の実施の形態を
示す断面図である。FIG. 3 is a sectional view showing another embodiment of the semiconductor device according to the present invention.
【図４】図１の半導体装置に設置する帯域フィルタの分
割状態を示す図である。FIG. 4 is a diagram showing a division state of a bandpass filter installed in the semiconductor device of FIG.
【図５】図１の半導体装置に設置する帯域フィルタの形
状を示す図である。5 is a diagram showing a shape of a bandpass filter installed in the semiconductor device of FIG.
【図６】図１の半導体装置に設置する帯域フィルタの他
の形状を示す図である。6 is a diagram showing another shape of the bandpass filter installed in the semiconductor device of FIG.
【図７】本発明に関わる半導体装置の更に他の実施の形
態を示す断面図である。FIG. 7 is a sectional view showing still another embodiment of a semiconductor device according to the present invention.
【図８】図８の等価回路図である。FIG. 8 is an equivalent circuit diagram of FIG.
【図９】従来の帯域フィルタを備えた半導体素子の断面
図である。FIG. 9 is a cross-sectional view of a semiconductor device including a conventional bandpass filter.
【図１０】図９の等価回路図である。FIG. 10 is an equivalent circuit diagram of FIG.
１、２２：集積回路、 ２、２８：入力バッファ、 ３、２７：出力バッファ、 ４：パッド、 ５：ＶD D 端子、 ６：ＶS S 端子、 ７：電源、 ８、３０：帯域フィルタ、 ２６：金属細線、 ２９：出力電源端子、 ２０：セラミック板、 ２１：環状のセラミック、 ２３：蓋、 ２４、２４′：配線、 ２５：リード端子。1, 22: Integrated circuit, 2, 28: Input buffer, 3, 27: Output buffer, 4: Pad, 5: V DD terminal, 6: V SS terminal, 7: Power supply, 8, 30: Bandpass filter, 26: Thin metal wire, 29: output power supply terminal, 20: ceramic plate, 21: annular ceramic, 23: lid, 24, 24 ′: wiring, 25: lead terminal.
Claims (3)
用電源に４０ｍｍ以上の帯域フィルタを取付けたことを
特徴とする半導体装置。1. A semiconductor device in which a bandpass filter having a length of 40 mm or more is attached to an enclosure for mounting a semiconductor element and a power supply for a board.
用入力電源に４０ｍｍ以上の帯域フィルタを取付けたこ
とを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a band-pass filter having a length of 40 mm or more is attached to the enclosure for mounting the semiconductor element and the input power supply for the board.
用出力電源に４０ｍｍ以上の帯域フィルタを取付けたこ
とを特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein a bandpass filter having a length of 40 mm or more is attached to the envelope mounting the semiconductor element and the output power supply for the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8064115A JPH09260522A (en) | 1996-03-21 | 1996-03-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8064115A JPH09260522A (en) | 1996-03-21 | 1996-03-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09260522A true JPH09260522A (en) | 1997-10-03 |
Family
ID=13248757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8064115A Pending JPH09260522A (en) | 1996-03-21 | 1996-03-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09260522A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004140210A (en) * | 2002-10-18 | 2004-05-13 | Renesas Technology Corp | System |
| JP2006185936A (en) * | 2004-12-24 | 2006-07-13 | Fujitsu Ltd | Semiconductor device and its regulation method |
| JP2008124490A (en) * | 2008-01-07 | 2008-05-29 | Renesas Technology Corp | System |
| JP2011160428A (en) * | 2011-02-04 | 2011-08-18 | Renesas Electronics Corp | System |
| JP2013153213A (en) * | 2013-04-11 | 2013-08-08 | Japan Oclaro Inc | Printed circuit board and optical transmitting apparatus |
-
1996
- 1996-03-21 JP JP8064115A patent/JPH09260522A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004140210A (en) * | 2002-10-18 | 2004-05-13 | Renesas Technology Corp | System |
| JP2006185936A (en) * | 2004-12-24 | 2006-07-13 | Fujitsu Ltd | Semiconductor device and its regulation method |
| US7408423B2 (en) | 2004-12-24 | 2008-08-05 | Fujitsu Limited | Semiconductor device and adjusting method for semiconductor device |
| US7619490B2 (en) | 2004-12-24 | 2009-11-17 | Fujitsu Microelectronics Limited | Semiconductor device and adjusting method for semiconductor device |
| JP4633455B2 (en) * | 2004-12-24 | 2011-02-16 | 富士通セミコンダクター株式会社 | Semiconductor device |
| JP2008124490A (en) * | 2008-01-07 | 2008-05-29 | Renesas Technology Corp | System |
| JP2011160428A (en) * | 2011-02-04 | 2011-08-18 | Renesas Electronics Corp | System |
| JP2013153213A (en) * | 2013-04-11 | 2013-08-08 | Japan Oclaro Inc | Printed circuit board and optical transmitting apparatus |
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