JPH09232547A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH09232547A JPH09232547A JP4114696A JP4114696A JPH09232547A JP H09232547 A JPH09232547 A JP H09232547A JP 4114696 A JP4114696 A JP 4114696A JP 4114696 A JP4114696 A JP 4114696A JP H09232547 A JPH09232547 A JP H09232547A
- Authority
- JP
- Japan
- Prior art keywords
- macro
- noise
- logic
- semiconductor integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体集積回路に関
し、特に雑音の影響を受け易いアナログ回路などのマク
ロを含むゲートアレイ等の半導体集積回路に関する。The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit such as a gate array including a macro such as an analog circuit which is easily affected by noise.
【0002】[0002]
【従来の技術】一般的なこの種のゲートアレイのチップ
構成においては、入出力回路であるI/Oバッファが内
部の各機能回路ブロックより高い駆動能力を必要とする
ため、内部機能回路とI/Oバッファとのセル構成が異
なり、前者は内部領域に後者は外側のI/O領域にそれ
ぞれ分離配置されている。当然機能回路ブロックである
マクロは内部領域に配置されるが、アナログ回路など雑
音の影響を受け易いマクロすなわち雑音感受性マクロが
あった場合は、その雑音感受性マクロは他の論理回路等
のマクロやI/Oバッファ等からの雑音の影響を受け雑
音発生や誤動作をすることがあった。2. Description of the Related Art In a general chip configuration of a gate array of this kind, an I / O buffer as an input / output circuit requires a higher driving capability than each internal functional circuit block. The cell configuration is different from that of the I / O buffer, and the former is separately disposed in the inner region and the latter is disposed in the outer I / O region. Naturally, the macro which is a functional circuit block is arranged in the internal area. However, if there is a macro that is easily affected by noise such as an analog circuit, that is, a noise-sensitive macro, the noise-sensitive macro is a macro such as another logic circuit or the like. In some cases, noise was generated or a malfunction occurred due to the influence of noise from the / O buffer or the like.
【0003】特開平4−30470号公報記載の従来の
この種の半導体集積回路では、上記雑音防止策として雑
音感受性マクロの周囲を電源ラインや接地ライン等のシ
ールドブロックで囲み、雑音源となる他のマクロから電
気的に分離していた。In this type of conventional semiconductor integrated circuit described in Japanese Patent Application Laid-Open No. Hei 4-30470, as a noise prevention measure, a noise susceptible macro is surrounded by a shield block such as a power supply line or a ground line to be a noise source. Was electrically isolated from the macro.
【0004】従来の半導体集積回路を模式平面図で示す
図3を参照すると、この従来の半導体集積回路は、基板
1の周辺部分に外部との接続用のパッド7を配置するパ
ッド領域8と、その内側のI/Oバッファ5を配置する
I/O領域6と、雑音感受性マクロ3およびその他の論
理回路等の論理マクロ4を配置する内部領域2とを有
し、雑音感受性マクロ3の周囲に配置したシールド用の
電源ラインや接地ライン等から成るシールドブロック1
0を備える。Referring to FIG. 3, which is a schematic plan view of a conventional semiconductor integrated circuit, the conventional semiconductor integrated circuit has a pad area 8 in which a pad 7 for connection to the outside is arranged on a peripheral portion of a substrate 1. It has an I / O area 6 in which an I / O buffer 5 is arranged and an internal area 2 in which a noise-sensitive macro 3 and a logic macro 4 such as other logic circuits are arranged. Shield block 1 consisting of a shielded power supply line, ground line, etc.
0 is provided.
【0005】このように、雑音感受性マクロ3の周囲を
囲むシールドブロック10は相当の面積を占めるため、
この雑音感受性マクロ3の周辺では多くの論理セルが使
用不能となる。この面積は、集積度の向上およびチップ
サイズの縮小を考慮すると無視できない。As described above, since the shield block 10 surrounding the noise-sensitive macro 3 occupies a considerable area,
Many logic cells become unusable around the noise sensitive macro 3. This area cannot be ignored in consideration of the improvement in the degree of integration and the reduction in chip size.
【0006】[0006]
【発明が解決しようとする課題】上述した従来の半導体
集積回路は、マクロを配置する内部領域とI/Oバッフ
ァを配置するI/O領域とが分離されているため、論理
マクロの雑音をシールドするため雑音感受性マクロの周
囲をシールドブロックで囲む必要があるが、このシール
ドブロックの占有面積は集積度の向上およびチップ面積
の縮小の動向を考慮すると無視できない大きさとなると
いう欠点があった。In the above-described conventional semiconductor integrated circuit, since the internal area in which the macro is arranged and the I / O area in which the I / O buffer is arranged are separated, the noise of the logic macro is shielded. Therefore, it is necessary to surround the noise-sensitive macro with a shield block, but there is a disadvantage that the occupied area of the shield block is not negligible in view of the trend of improvement in integration and reduction in chip area.
【0007】[0007]
【課題を解決するための手段】本発明の半導体集積回路
は、半導体基板の一主面に複数個の同一の論理セルを規
則正しく配置し雑音の影響を受け易い機能回路ブロック
である雑音感受性マクロを含むゲートアレイ方式の半導
体集積回路において、前記一主面の入出力バッファ領域
を含む全面に前記論理セルを配置しコーナ部に前記雑音
感受性マクロを配置した全面論理ゲート構成の内部領域
と、前記雑音感受性マクロの内部領域側の2辺を囲むよ
うに配置したシールド配線とを備え、前記論理セルから
成る論理回路の所定数の並列接続で入出力バッフアを構
成することを特徴とするものである。SUMMARY OF THE INVENTION A semiconductor integrated circuit according to the present invention includes a noise sensitive macro which is a functional circuit block in which a plurality of identical logic cells are regularly arranged on one main surface of a semiconductor substrate and which is easily affected by noise. In a gate array type semiconductor integrated circuit including: the internal area of the entire logic gate structure in which the logic cell is arranged on the entire surface including the input / output buffer area of the one main surface and the noise sensitive macro is arranged at a corner portion; And a shield wiring arranged so as to surround two sides on the inner area side of the sensitive macro, and the input / output buffer is constituted by a predetermined number of parallel connections of logic circuits each including the logic cell.
【0008】[0008]
【発明の実施の形態】次に、本発明の実施の形態を図3
と共通の構成要素には共通の参照文字/数字を付して同
様に模式平面図で示す図1を参照すると、この図に示す
本実施の形態の半導体集積回路は、従来と共通の基板1
の周辺部分に外部との接続用のパッド7を配置するパッ
ド領域8と、従来のI/O領域を含めて論理セルで敷き
詰めた完全なSOG(Sea Of Gates)チッ
プのコーナ部11に雑音感受性マクロ3を配置しその他
の部分に論理マクロ4を配置した内部領域2Aとを備え
る。FIG. 3 shows an embodiment of the present invention.
Referring to FIG. 1 also shown in a schematic plan view with common reference characters / numerals attached to common components, the semiconductor integrated circuit of this embodiment shown in FIG.
And a pad area 8 in which a pad 7 for connection to the outside is arranged in a peripheral portion of the semiconductor device, and a corner portion 11 of a complete SOG (Sea Of Gates) chip including a conventional I / O area spread by logic cells. And an internal area 2A in which the macro 3 is arranged and the logic macro 4 is arranged in other parts.
【0009】雑音感受性マクロ3の内部領域側の2辺の
周囲には端末がパッド領域8のパッド71,73に接続
した電源ライン10Aとパッド72,74に接続した接
地ライン10Bとを配置しシールドブロックとして動作
させる。A terminal is provided with a power supply line 10A connected to the pads 71 and 73 of the pad area 8 and a ground line 10B connected to the pads 72 and 74, and shielded around the two sides on the inner area side of the noise sensitive macro 3. Operate as a block.
【0010】これら電源ライン10A,接地ライン10
Bは広幅のアルミ配線で構成してもよい。These power supply line 10A and ground line 10
B may be composed of a wide aluminum wiring.
【0011】このように、内部領域およびI/Oバッフ
ァ領域を含め論理セルをチップ全面に配置した完全なS
OG構成とすることにより、雑音感受性マクロ等を従来
のI/Oバッファ領域であるコーナ部11に配置可能と
なる。したがって、本実施の形態の半導体集積回路は、
他の2辺を電源ライン10Aや接地ライン10Bで囲う
ことにより、雑音感受性マクロ3を雑音発生限である論
理マクロ4から電気的に十分分離でき、これらマクロ4
で発生した雑音は電源ライン10A,接地ライン10B
でシールドされるので、雑音感受性マクロ3に対する影
響を殆ど除去できる。As described above, the complete S in which the logic cells including the internal area and the I / O buffer area are arranged on the entire surface of the chip is provided.
With the OG configuration, noise-sensitive macros and the like can be arranged in the corner section 11 which is a conventional I / O buffer area. Therefore, the semiconductor integrated circuit of the present embodiment
By surrounding the other two sides with the power supply line 10A and the ground line 10B, the noise-sensitive macro 3 can be electrically separated sufficiently from the logic macro 4 which is a noise generation limit.
Generated by the power line 10A and the ground line 10B
, The effect on the noise sensitive macro 3 can be almost eliminated.
【0012】また、完全なSOG構成とすることによ
り、I/Oバッファ領域がなくなるため、I/Oバッフ
ァをSOGを構成している論理セルで構成する必要があ
る。この場合、従来の技術で説明したように、I/Oバ
ッファは内部の論理マクロの論理回路より高い駆動能力
が要求される。このため、本実施の形態では上記論理セ
ルの並列接続により所要のI/Oバッフア機能を実現し
ている。In addition, since a complete SOG configuration eliminates an I / O buffer area, it is necessary to configure an I / O buffer with logic cells constituting the SOG. In this case, as described in the related art, the I / O buffer requires a higher driving capability than the logic circuit of the internal logic macro. Therefore, in this embodiment, a required I / O buffer function is realized by connecting the logic cells in parallel.
【0013】本実施の形態のI/Oバッフアの構成を回
路図で示す図2を参照すると、このI/Oバッファは、
電源VDDと接地GND間に直列接続したPチャネルM
OSトランジスタPi(iは1〜n)とNチャネルMO
SトランジスタNiとから成るCMOSゲート回路Gi
を所要駆動能力対応のn個の並列接続により構成され
る。FIG. 2 is a circuit diagram showing the configuration of the I / O buffer according to the present embodiment.
P channel M connected in series between power supply VDD and ground GND
OS transistor Pi (i is 1 to n) and N-channel MO
CMOS gate circuit Gi comprising S transistor Ni
Are constituted by n parallel connections corresponding to the required driving capability.
【0014】動作について説明すると、CMOSゲート
回路Giの各々は、正補の入力信号H1,H2のトラン
ジスタPi,Niのゲートへの供給に応答して対応する
出力信号Oをパッド7に出力する。In operation, each of the CMOS gate circuits Gi outputs a corresponding output signal O to the pad 7 in response to the supply of the complementary input signals H1 and H2 to the gates of the transistors Pi and Ni.
【0015】このような構成とすることにより、本実施
の形態の半導体集積回路は、雑音感受性マクロ3に対し
て論理マクロ4を十分分離するとともに、回路面積を縮
小し、集積度を向上することができる。With such a configuration, the semiconductor integrated circuit of the present embodiment can sufficiently separate the logic macro 4 from the noise-sensitive macro 3, reduce the circuit area, and improve the degree of integration. Can be.
【0016】[0016]
【発明の効果】以上説明したように、本発明の半導体集
積回路は、入出力バッファ領域を含む全面に論理セルを
配置した完全SOG構成の内部領域のコーナ部に雑音感
受性マクロを配置し、この雑音感受性マクロの内側の2
辺を囲むように配置したシールド配線とを備え、論理セ
ルから成る論理回路の所定数の並列接続で入出力バッフ
アを構成することにより、上記雑音感受性マクロに対す
る論理マクロとの間の十分なシールド効果を得るととも
に、回路面積を縮小し、集積度を向上することができる
という効果がある。As described above, in the semiconductor integrated circuit of the present invention, a noise-sensitive macro is arranged at a corner of an internal area of a complete SOG structure in which logic cells are arranged on the entire surface including an input / output buffer area. 2 inside noise sensitive macro
A shield wiring arranged so as to surround the sides, and by forming an input / output buffer with a predetermined number of parallel connections of a logic circuit composed of logic cells, a sufficient shielding effect between the noise-sensitive macro and the logic macro is provided. And the circuit area can be reduced, and the degree of integration can be improved.
【図1】本発明の半導体集積回路の一実施の形態を示す
模式平面図である。FIG. 1 is a schematic plan view showing one embodiment of a semiconductor integrated circuit of the present invention.
【図2】本実施の形態の半導体集積回路のI/Oバッフ
ァの構成を示す回路図である。FIG. 2 is a circuit diagram showing a configuration of an I / O buffer of the semiconductor integrated circuit according to the present embodiment.
【図3】従来の半導体集積回路の一例を示す模式平面図
である。FIG. 3 is a schematic plan view showing an example of a conventional semiconductor integrated circuit.
1 基板 2,2A 内部領域 3 雑音感受性マクロ 4 論理マクロ 5 I/Oバッファ 6 I/O領域 7 パッド 8 パッド領域 10 シールドブロック 10A 電源ライン 10B 接地ライン 11 コーナ部 G1〜Gn CMOSゲート回路 N1〜Nn,P1〜Pn トランジスタ DESCRIPTION OF SYMBOLS 1 Substrate 2, 2A Internal area 3 Noise sensitive macro 4 Logic macro 5 I / O buffer 6 I / O area 7 Pad 8 Pad area 10 Shield block 10A Power supply line 10B Ground line 11 Corner part G1-Gn CMOS gate circuits N1-Nn , P1 to Pn transistors
Claims (3)
理セルを規則正しく配置し雑音の影響を受け易い機能回
路ブロックである雑音感受性マクロを含むゲートアレイ
方式の半導体集積回路において、 前記一主面の入出力バッファ領域を含む全面に前記論理
セルを配置しコーナ部に前記雑音感受性マクロを配置し
た全面論理ゲート構成の内部領域と、 前記雑音感受性マクロの内部領域側の2辺を囲むように
配置したシールド配線とを備え、 前記論理セルから成る論理回路の所定数の並列接続で入
出力バッフアを構成することを特徴とする半導体集積回
路。1. A gate array semiconductor integrated circuit including a noise sensitive macro which is a functional circuit block in which a plurality of identical logic cells are regularly arranged on one main surface of a semiconductor substrate and which is easily affected by noise. The logic cell is arranged on the entire surface including the input / output buffer area of the main surface, and the inner area of the whole logic gate structure in which the noise sensitive macro is arranged at the corner portion and the two sides on the inner area side of the noise sensitive macro are surrounded. And a shield wiring disposed on the input / output buffer.
接続した第1,第2の導電型のMOSトランジスタから
成ることを特徴とする請求項1記載の半導体集積回路。2. The semiconductor integrated circuit according to claim 1, wherein the logic cell comprises first and second conductivity type MOS transistors connected in series between a power supply and ground.
/または接地ラインであることを特徴とする請求項1記
載の半導体集積回路。3. The semiconductor integrated circuit according to claim 1, wherein the shield wiring is a power supply line and / or a ground line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4114696A JP2833568B2 (en) | 1996-02-28 | 1996-02-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4114696A JP2833568B2 (en) | 1996-02-28 | 1996-02-28 | Semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09232547A true JPH09232547A (en) | 1997-09-05 |
JP2833568B2 JP2833568B2 (en) | 1998-12-09 |
Family
ID=12600287
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4114696A Expired - Fee Related JP2833568B2 (en) | 1996-02-28 | 1996-02-28 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2833568B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7051311B2 (en) * | 2002-06-21 | 2006-05-23 | Fujitsu Limited | Semiconductor circuit designing method, semiconductor circuit designing apparatus, program, and semiconductor device |
US7411277B2 (en) | 2002-03-19 | 2008-08-12 | Fujitsu Limited | Semiconductor integrated circuit having shield wiring |
JP2011003570A (en) * | 2009-06-16 | 2011-01-06 | Renesas Electronics Corp | Semiconductor device |
US7977974B2 (en) | 2007-02-20 | 2011-07-12 | Seiko Epson Corporation | Integrated circuit device and electronic instrument |
-
1996
- 1996-02-28 JP JP4114696A patent/JP2833568B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7411277B2 (en) | 2002-03-19 | 2008-08-12 | Fujitsu Limited | Semiconductor integrated circuit having shield wiring |
US7051311B2 (en) * | 2002-06-21 | 2006-05-23 | Fujitsu Limited | Semiconductor circuit designing method, semiconductor circuit designing apparatus, program, and semiconductor device |
US7977974B2 (en) | 2007-02-20 | 2011-07-12 | Seiko Epson Corporation | Integrated circuit device and electronic instrument |
JP2011003570A (en) * | 2009-06-16 | 2011-01-06 | Renesas Electronics Corp | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2833568B2 (en) | 1998-12-09 |
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Legal Events
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A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980901 |
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LAPS | Cancellation because of no payment of annual fees |