JPH09232506A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JPH09232506A
JPH09232506A JP8031790A JP3179096A JPH09232506A JP H09232506 A JPH09232506 A JP H09232506A JP 8031790 A JP8031790 A JP 8031790A JP 3179096 A JP3179096 A JP 3179096A JP H09232506 A JPH09232506 A JP H09232506A
Authority
JP
Japan
Prior art keywords
semiconductor chip
electrodes
electrode
protruding
element region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8031790A
Other languages
Japanese (ja)
Other versions
JP3279470B2 (en
Inventor
Takashi Otsuka
隆 大塚
Hiroaki Fujimoto
博昭 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP03179096A priority Critical patent/JP3279470B2/en
Publication of JPH09232506A publication Critical patent/JPH09232506A/en
Application granted granted Critical
Publication of JP3279470B2 publication Critical patent/JP3279470B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To enable the mounting of LSIs one above the other or on an interconnection board, without damaging semiconductor elements. SOLUTION: A first and second semiconductor chips 1 and 2 are adhered mutually surface to surface through an insulative region 5 and the area occupied by electrodes 3a formed on element regions 6 of both chips is less than that occupied by electrodes 3b formed on other than regions 6. This makes the height of bump electrodes 4a formed on the electrodes 3a of the regions 6 less than that of bump electrodes 4b formed on the electrodes 3b on other regions, resulting in such a structure that at bonding of the electrodes 4a, 4b, the stress is concentrated on the electrodes 4b on other reactors while no stress is concentrated on the electrodes 4a on the regions 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】この発明は、電子機器に利用
される高機能ＬＳＩとその実装技術に関し、半導体素子
の電極上に形成した突起電極を用いて接続した半導体装
置およびその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-performance LSI used in electronic equipment and its mounting technology, and more particularly to a semiconductor device connected by using a protruding electrode formed on an electrode of a semiconductor element and a manufacturing method thereof. is there.

【０００２】[0002]

【従来の技術】近年、電子機器が高機能化されるに従
い、ＬＳＩが多く使用され、サイズを小さくするため
に、多数のチップを１チップ化していく手法がよくとら
れる。しかしながら、回路規模が大きくなってくると、
ＬＳＩの開発期間の長期化や、チップサイズの増大によ
るコスト上昇という課題を有している。2. Description of the Related Art In recent years, as electronic devices have become more sophisticated, LSIs are often used, and in order to reduce the size, it is often the case that many chips are integrated into one chip. However, as the circuit scale becomes larger,
There are problems that the development period of the LSI is extended and the cost is increased due to the increase of the chip size.

【０００３】その一つの解決策として、半導体チップの
外周部に設けられていた電極を素子領域上にも配置し、
チップ面積を小さくすることにより低コスト化を図る方
法と、異なるチップを積層する技術があるこの２つの方
法は、どちらか一方用いられることもあるが、両方法を
合わせて用いることにより、大きな低コスト化が図られ
る。As one of the solutions, the electrodes provided on the outer peripheral portion of the semiconductor chip are arranged also on the element region,
Either one of these two methods, which has a technique of reducing the cost by reducing the chip area and a technique of stacking different chips, may be used. Cost reduction is achieved.

【０００４】しかし、半導体チップ上の電極を素子領域
上に形成した場合、配線、コンタクト、トランジスタの
いずれかが、電極下に存在することになり、突起電極を
用いて張り合わせるときに、機械的なストレスが加わ
り、素子を破壊したり、特性を変動させ、半導体チップ
の信頼性にも影響を与えるため、素子にダメージを与え
ない圧力での電気的な接続が必要となっている。However, when the electrode on the semiconductor chip is formed on the element region, any one of the wiring, the contact, and the transistor exists under the electrode, and when the protruding electrode is used for bonding, mechanical contact is required. Since various stresses are applied to break the element or change the characteristics and affect the reliability of the semiconductor chip, it is necessary to make electrical connection under a pressure that does not damage the element.

【０００５】また、異なるチップを積層するために通常
半導体チップの電極上に設ける突起電極は、電解めっき
による方法、蒸着による方法、別基板に形成された突起
電極を熱転写する方法がある。しかしいずれの方法も多
くの複雑なプロセスを必要とするために、コスト上昇を
招いてしまい、積層化のコスト増大につながる。そこ
で、この課題を解決するために、無電解めっき法による
電極上への突起電極の形成技術が開発されつつある。こ
の技術では、通常Ｎｉの無電解めっきが使用される。こ
の方法は、まずＡｌ上の酸化膜を除去するために、水酸
化ナトリウムや燐酸を用いてライトエッチングを行う。
つぎにＡｌ電極上が再酸化されるのを防ぐ目的で表面を
Ｚｎで置換処理する。この後無電解Ｎｉめっきを行い所
定の高さまで析出させることにより突起電極は完成す
る。Ｎｉ表面の酸化を防ぐ目的で、Ｎｉめっき後に置換
Ａｕめっきを行うこともしばしば行われる。Further, the bump electrodes usually provided on the electrodes of the semiconductor chip for stacking different chips may be electrolytic plating method, vapor deposition method, or thermal transfer method of bump electrodes formed on another substrate. However, any of these methods requires many complicated processes, which leads to an increase in cost and an increase in the cost of lamination. Therefore, in order to solve this problem, a technique for forming a protruding electrode on the electrode by an electroless plating method is being developed. This technique typically uses Ni electroless plating. In this method, first, light etching is performed using sodium hydroxide or phosphoric acid in order to remove the oxide film on Al.
Next, the surface is replaced with Zn for the purpose of preventing re-oxidation on the Al electrode. After this, electroless Ni plating is performed to deposit to a predetermined height to complete the protruding electrode. Substitution Au plating is often performed after Ni plating for the purpose of preventing oxidation of the Ni surface.

【０００６】この方法では、無電解めっき液に浸漬させ
るだけで、半導体チップのＡｌ電極上に突起電極を形成
できるため、低コスト化が可能となる。According to this method, the protruding electrode can be formed on the Al electrode of the semiconductor chip only by immersing it in the electroless plating solution, so that the cost can be reduced.

【０００７】[0007]

【発明が解決しようとする課題】しかしながらＮｉの無
電解めっき法を行う場合には、電極の面積や表面状態や
電気的な状態、めっき液の状態により高さばらつきが生
じ、張り合わせ時に高さの高い突起電極に応力集中が生
じる、この応力集中は、Ｎｉの様な変形し難い材料の場
合特に顕著であり、電極下の素子にダメージを与えてし
まうため、高さばらつきを吸収するために低硬度の材料
やはんだ等の拡散によりぬれ広がり、突起電極の高さば
らつきを吸収する導電材料を形成する必要があった。However, when the electroless plating method of Ni is carried out, height variations occur depending on the area of the electrodes, the surface condition, the electrical condition, and the condition of the plating solution, and the height of the electrodes during the bonding is increased. Stress concentration occurs on the high bump electrode. This stress concentration is particularly remarkable in the case of a material such as Ni that is difficult to deform, and damages the element under the electrode. It has been necessary to form a conductive material that absorbs and spreads the height variation of the protruding electrodes by spreading by wetting due to the diffusion of hardness material or solder.

【０００８】しかしこのような高さばらつきを吸収する
材料を形成した場合においても、Ｎｉの突起電極が相対
する突起電極に直接接して接続されると、張り合わせ時
や張り合わせ後の外力により容易に応力集中が生じてし
まい素子にダメージを与えるという問題点を有してい
た。この問題点は、ＮｉだけでなくＣｕ，Ａｕ等の導電
材料においても同様である。However, even when a material that absorbs such height variations is formed, if the Ni protruding electrodes are directly contacted and connected to the opposing protruding electrodes, stress is easily applied by the external force after the bonding or after the bonding. There is a problem that concentration occurs and the element is damaged. This problem is the same not only in Ni but also in conductive materials such as Cu and Au.

【０００９】したがって、この発明の目的は、上記問題
点に鑑み、半導体素子へのダメージを与えずにＬＳＩ同
士あるいは配線基板へ実装することを可能とする半導体
装置およびその製造方法を提供するものである。Therefore, in view of the above problems, an object of the present invention is to provide a semiconductor device which can be mounted on LSIs or on a wiring board without damaging the semiconductor element and a manufacturing method thereof. is there.

【００１０】[0010]

【課題を解決するための手段】請求項１記載の半導体装
置は、第１の半導体チップと第２の半導体チップの表面
同士が絶縁性樹脂を介して互いに張り合わされ、第１の
半導体チップの表面上に位置する電極上に形成された突
起電極と、第２の半導体チップの表面上に位置し第１の
半導体チップの電極に対応する電極上に形成された突起
電極とが電気的に接続された半導体装置であって、第１
の半導体チップおよび第２の半導体チップの素子領域上
に形成された電極の面積が素子領域上以外に形成された
電極の面積よりも小さいことを特徴とするものである。According to another aspect of the present invention, there is provided a semiconductor device, wherein the surfaces of a first semiconductor chip and a second semiconductor chip are adhered to each other via an insulating resin, and the surface of the first semiconductor chip is affixed to each other. The protruding electrode formed on the upper electrode is electrically connected to the protruding electrode formed on the surface of the second semiconductor chip and corresponding to the electrode of the first semiconductor chip. First semiconductor device,
The area of the electrodes formed on the element regions of the semiconductor chip and the second semiconductor chip is smaller than the area of the electrodes formed on other than the element region.

【００１１】このように、第１の半導体チップおよび第
２の半導体チップの素子領域上に形成された電極の面積
を素子領域上以外に形成された電極の面積よりも小さく
したので、素子領域上の電極上に形成された突起電極の
高さが素子領域上以外の電極上に形成された突起電極の
高さよりも低くなり、それゆえ突起電極の接合時に、素
子領域上以外の突起電極に応力集中が生じ、素子領域上
の突起電極に応力集中が生じない構造となる。このた
め、素子領域上に電極を形成したＬＳＩの実装におい
て、素子へのダメージを与えることなく実装できるた
め、信頼性の高い積層型ＬＳＩや配線基板への実装が実
現できる。As described above, the area of the electrodes formed on the element regions of the first semiconductor chip and the second semiconductor chip is made smaller than the area of the electrodes formed other than on the element region, and thus on the element region. The height of the bump electrodes formed on the electrodes of the electrodes is lower than the height of the bump electrodes formed on the electrodes other than the element region, and therefore, when the bump electrodes are joined, stress is applied to the bump electrodes other than the element region. Concentration occurs, and the stress is not concentrated on the protruding electrodes on the element region. Therefore, when mounting an LSI in which electrodes are formed on the element region, the element can be mounted without damaging the element, and thus mounting on a highly reliable laminated LSI or wiring board can be realized.

【００１２】請求項２記載の半導体装置は、第１の半導
体チップと第２の半導体チップの表面同士が絶縁性樹脂
を介して互いに張り合わされ、第１の半導体チップの表
面上に位置する電極上に形成された突起電極と、第２の
半導体チップの表面上に位置し第１の半導体チップの電
極に対応する電極上に形成された突起電極とが電気的に
接続された半導体装置であって、第１の半導体チップお
よび第２の半導体チップの素子領域上に形成された電極
が絶縁膜により少なくとも２つ以上に分割された領域か
らなり分割された領域が素子領域上以外に形成された電
極よりも面積が小さいことを特徴とするものである。According to another aspect of the semiconductor device of the present invention, the surfaces of the first semiconductor chip and the second semiconductor chip are adhered to each other via an insulating resin, and the electrodes are located on the surface of the first semiconductor chip. A semiconductor device in which the protruding electrode formed on the second semiconductor chip and the protruding electrode formed on the surface of the second semiconductor chip and corresponding to the electrode of the first semiconductor chip are electrically connected to each other. An electrode formed on the element regions of the first semiconductor chip and the second semiconductor chip is divided into at least two or more regions by an insulating film, and the divided regions are formed on regions other than the element region. It is characterized by having a smaller area.

【００１３】このように、第１の半導体チップおよび第
２の半導体チップの素子領域上に形成された電極を絶縁
膜により少なくとも２つ以上に分割することにより、こ
の分割された領域を素子領域上以外に形成された電極よ
りも面積よりも小さくしたので、素子領域上の電極上に
形成された突起電極の高さが素子領域上以外の電極上に
形成された突起電極の高さよりも低くなり、それゆえ突
起電極の接合時に、素子領域上以外の突起電極に応力集
中が生じ、素子領域上の突起電極に応力集中が生じない
構造となり、請求項１と同様の効果が得られる。Thus, the electrodes formed on the element regions of the first semiconductor chip and the second semiconductor chip are divided into at least two or more parts by the insulating film, and the divided regions are formed on the element regions. Since it is smaller than the area of the electrodes formed in other areas, the height of the protruding electrodes formed on the electrodes on the element area is lower than the height of the protruding electrodes formed on electrodes other than the element area. Therefore, at the time of joining the projecting electrodes, stress concentration occurs on the projecting electrodes other than on the element region, and stress concentration does not occur on the projecting electrodes on the element region, and the same effect as in claim 1 can be obtained.

【００１４】請求項３記載の半導体装置は、請求項１ま
たは２において、第１の半導体チップおよび第２の半導
体チップの突起電極の少なくとも一方が無電解めっき法
にて形成されたものである。このように、第１の半導体
チップおよび第２の半導体チップの突起電極の少なくと
も一方が無電解めっき法にて形成されているので、半導
体チップを無電解めっき液に浸漬するだけで突起電極を
形成でき、低コストで製造できる。また、請求項１およ
び２に記載のように、素子領域上の電極上に形成された
突起電極の高さが素子領域上以外の電極上に形成された
突起電極の高さよりも低くなるため、電極およびめっき
液の状態による突起電極の高さばらつきにより素子にダ
メージを与えることはない。A third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein at least one of the protruding electrodes of the first semiconductor chip and the second semiconductor chip is formed by electroless plating. Thus, since at least one of the protruding electrodes of the first semiconductor chip and the second semiconductor chip is formed by the electroless plating method, the protruding electrodes can be formed simply by immersing the semiconductor chip in the electroless plating solution. It can be manufactured at low cost. Further, as described in claims 1 and 2, since the height of the protruding electrode formed on the electrode on the element region is lower than the height of the protruding electrode formed on the electrode other than the element region, There is no damage to the element due to height variations of the protruding electrodes due to the state of the electrodes and the plating solution.

【００１５】請求項４記載の半導体装置は、請求項１ま
たは２において、第１の半導体チップおよび第２の半導
体チップの少なくとも一方が配線基板であるものであ
る。このように、第１の半導体チップおよび第２の半導
体チップの少なくとも一方が配線基板であるので、配線
基板への実装が実現できる。請求項５記載の半導体装置
は、請求項１または２において、第１の半導体チップお
よび第２の半導体チップの突起電極の少なくとも一方が
無電解めっき法にて形成され、その上部に、無電解めっ
き法にて形成された突起電極より硬度が低い導電材料層
を形成したものである。A semiconductor device according to a fourth aspect is the semiconductor device according to the first or second aspect, wherein at least one of the first semiconductor chip and the second semiconductor chip is a wiring board. Thus, since at least one of the first semiconductor chip and the second semiconductor chip is the wiring board, mounting on the wiring board can be realized. According to a fifth aspect of the present invention, in the semiconductor device according to the first or second aspect, at least one of the protruding electrodes of the first semiconductor chip and the second semiconductor chip is formed by an electroless plating method, and an electroless plating is formed on an upper portion thereof. A conductive material layer having a hardness lower than that of the bump electrode formed by the method is formed.

【００１６】このように、無電解めっき法にて形成され
た突起電極の上部に、この突起電極より硬度が低い導電
材料層を形成したので、素子にダメージを与えない荷重
で接合することができる。すなわち、接続時に導電材料
層が素子にダメージを与えない荷重以内で塑性変形する
ことにより、突起電極の高さばらつきや半導体チップの
持つ反りを吸収し、素子領域上の電極に加わる圧力が素
子領域上以外の電極に加わる圧力よりも小さくなって素
子にダメージを与えることはない。As described above, since the conductive material layer having a hardness lower than that of the bump electrode is formed on the bump electrode formed by the electroless plating method, the element can be bonded with a load that does not damage the element. . That is, when the conductive material layer is plastically deformed during connection within a load that does not damage the element, variations in height of the protruding electrodes and warpage of the semiconductor chip are absorbed, and the pressure applied to the electrodes on the element region is The pressure is smaller than the pressure applied to the electrodes other than the above and does not damage the device.

【００１７】請求項６記載の半導体装置は、請求項５に
おいて、導電材料層がＩｎあるいはＩｎにＳｎ，Ｐｂ，
Ｂｉ，Ａｇ，Ｚｎのうち少なくとも１つ以上を含む金属
からなるものである。このように、導電材料層としてＩ
ｎあるいはＩｎにＳｎ，Ｐｂ，Ｂｉ，Ａｇ，Ｚｎのうち
少なくとも１つ以上を含む金属を用いることにより、接
続時に導電材料層が素子にダメージを与えない荷重以内
で塑性変形し、突起電極の高さばらつきや半導体チップ
の持つ反りを吸収することができる。According to a sixth aspect of the present invention, in the semiconductor device according to the fifth aspect, the conductive material layer is In or In containing Sn, Pb,
It is made of a metal containing at least one of Bi, Ag and Zn. Thus, the conductive material layer I
By using a metal containing at least one of Sn, Pb, Bi, Ag, and Zn for n or In, the conductive material layer is plastically deformed within a load that does not damage the element at the time of connection, and the height of the protruding electrode is increased. It is possible to absorb variations in thickness and warp of the semiconductor chip.

【００１８】請求項７記載の半導体装置は、請求項５に
おいて、導電材料層が樹脂と金属からなる導電性ペース
トであるものである。このように、導電材料層を樹脂と
金属からなる導電性ペーストとすることにより、接続時
に導電材料層が素子にダメージを与えない荷重以内で塑
性変形し、突起電極の高さばらつきや半導体チップの持
つ反りを吸収することができる。According to a seventh aspect of the present invention, in the fifth aspect, the conductive material layer is a conductive paste made of resin and metal. As described above, by using the conductive material layer as the conductive paste made of resin and metal, the conductive material layer is plastically deformed within a load that does not damage the element at the time of connection, and the height variation of the protruding electrode or the semiconductor chip It can absorb the warp it has.

【００１９】請求項８記載の半導体装置製造方法は、素
子領域上が素子領域上以外よりも面積が小さくなるよう
に第１の半導体チップおよび第２の半導体チップの表面
上の対応する位置に電極を形成する工程と、第１の半導
体チップおよび第２の半導体チップの電極上に無電解め
っき処理により突起電極を形成する工程と、第１の半導
体チップあるいは第２の半導体チップの表面上に絶縁性
樹脂を塗布する工程と、第１の半導体チップおよび第２
の半導体チップの突起電極を位置合わせする工程と、第
１の半導体チップあるいは第２の半導体チップの裏面を
加圧し、絶縁性樹脂を硬化させることにより第１の半導
体チップと第２の半導体チップの電極を電気的に接続す
る工程とからなるものである。According to another aspect of the semiconductor device manufacturing method of the present invention, electrodes are provided at corresponding positions on the surfaces of the first semiconductor chip and the second semiconductor chip so that the area on the element region is smaller than the area on the element region. Forming a protruding electrode on the electrodes of the first semiconductor chip and the second semiconductor chip by electroless plating, and insulating on the surface of the first semiconductor chip or the second semiconductor chip. Of applying a conductive resin, the first semiconductor chip and the second semiconductor chip
Of aligning the protruding electrodes of the semiconductor chip, and pressing the back surface of the first semiconductor chip or the second semiconductor chip to cure the insulating resin so that the first semiconductor chip and the second semiconductor chip And the step of electrically connecting the electrodes.

【００２０】このように、素子領域上が素子領域上以外
よりも面積が小さくなるように第１の半導体チップおよ
び第２の半導体チップの表面上の対応する位置に電極を
形成するので、素子領域上の電極上に形成された突起電
極が素子領域上以外の電極上に形成された突起電極より
も高さが低くなる。このため、第１の半導体チップある
いは第２の半導体チップの裏面を加圧して突起電極の接
合する時に、素子領域上以外の突起電極に応力集中が生
じ、素子領域上の突起電極に応力集中が生じない構造と
なる。また、突起電極が無電解めっき処理にて形成され
ているので、半導体チップを無電解めっき液に浸漬する
だけで突起電極を形成でき、低コストで製造できる。As described above, the electrodes are formed at the corresponding positions on the surfaces of the first semiconductor chip and the second semiconductor chip so that the area of the element region is smaller than that of the area other than the element region. The height of the protruding electrode formed on the upper electrode is lower than that of the protruding electrode formed on the electrodes other than the element region. Therefore, when pressure is applied to the back surface of the first semiconductor chip or the second semiconductor chip to join the protruding electrodes, stress concentration occurs on the protruding electrodes other than on the element region, and stress concentration on the protruding electrodes on the element region. The structure does not occur. Further, since the protruding electrodes are formed by the electroless plating treatment, the protruding electrodes can be formed only by immersing the semiconductor chip in the electroless plating solution, and the manufacturing cost can be reduced.

【００２１】請求項９記載の半導体装置の製造方法は、
請求項８において、第１の半導体チップと第２の半導体
チップの電極を電気的に接続する工程において、素子領
域上の電極に加わる圧力が０．０２ｇ／μｍ2 以下であ
るものである。このように、素子領域上の電極に加わる
圧力が０．０２ｇ／μｍ2 以下であるので、素子にダメ
ージを与えることはない。A method of manufacturing a semiconductor device according to a ninth aspect is
In the eighth aspect, the pressure applied to the electrode on the element region in the step of electrically connecting the electrodes of the first semiconductor chip and the second semiconductor chip is 0.02 g / μm 2 or less. As described above, the pressure applied to the electrode on the element region is 0.02 g / μm 2 or less, so that the element is not damaged.

【００２２】請求項１０記載の半導体装置の製造方法
は、請求項８において、第１の半導体チップと第２の半
導体チップの電極上に突起電極を形成する工程におい
て、導電材料層を構成する金属の融液に第１の半導体チ
ップあるいは第２の半導体チップの少なくとも一方を浸
漬させることにより、突起電極の上部にこの突起電極よ
りも硬度が低い導電材料層を形成するものである。According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eighth aspect, the metal forming the conductive material layer is formed in the step of forming the protruding electrodes on the electrodes of the first semiconductor chip and the second semiconductor chip. By dipping at least one of the first semiconductor chip and the second semiconductor chip in the melt, a conductive material layer having a hardness lower than that of the protruding electrode is formed on the protruding electrode.

【００２３】このように、導電材料層を構成する金属の
融液に第１の半導体チップあるいは第２の半導体チップ
の少なくとも一方を浸漬させることにより、突起電極の
上部にこの突起電極よりも硬度が低い導電材料層を形成
するので、素子にダメージを与えない荷重で接合するこ
とができる。すなわち、接続時に導電材料層が素子にダ
メージを与えない荷重以内で塑性変形することにより、
突起電極の高さばらつきや半導体チップの持つ反りを吸
収し、素子領域上の電極に加わる圧力が素子領域上以外
の電極に加わる圧力よりも小さくなって素子にダメージ
を与えることはない。また、上記のように導電材料の融
液中に浸漬することにより導電材料層を形成したので、
コスト的に有利である。As described above, by immersing at least one of the first semiconductor chip and the second semiconductor chip in the melt of the metal forming the conductive material layer, the hardness above the protruding electrode is higher than that of the protruding electrode. Since the low conductive material layer is formed, the elements can be bonded with a load that does not damage the element. That is, when the conductive material layer is plastically deformed within a load that does not damage the element during connection,
The height variations of the protruding electrodes and the warp of the semiconductor chip are absorbed, and the pressure applied to the electrodes on the element region is smaller than the pressure applied to the electrodes other than on the element region, so that the elements are not damaged. Since the conductive material layer was formed by immersing in the melt of the conductive material as described above,
It is cost effective.

【００２４】[0024]

【発明の実施の形態】この発明の第１の実施の形態の半
導体装置およびその製造方法を図１および図２に基づい
て説明する。図１において、１，２は第１および第２の
半導体チップ、３ａ，３ｂはＡｌ電極、４ａ，４ｂは突
起電極、５は絶縁性樹脂、６は素子領域、７は保護膜、
８は導電材料層である。また、３ａ，４ａは素子領域６
上に形成されたＡｌ電極およこれに対応する突起電極で
あり、３ｂ，４ｂは素子領域６上以外に形成されたＡｌ
電極およびこれに対応する突起電極である。DETAILED DESCRIPTION OF THE INVENTION A semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention will be described with reference to FIGS. In FIG. 1, 1 and 2 are first and second semiconductor chips, 3a and 3b are Al electrodes, 4a and 4b are protruding electrodes, 5 is an insulating resin, 6 is an element region, 7 is a protective film,
Reference numeral 8 is a conductive material layer. Further, 3a and 4a are element regions 6
3b and 4b are Al electrodes formed on the upper surface and corresponding protruding electrodes, and 3b and 4b are Al formed on areas other than the element region 6.
An electrode and a corresponding bump electrode.

【００２５】素子領域６上に形成されたＡｌ電極３ａの
面積は素子領域６上以外に形成されたＡｌ電極３ｂの面
積よりも小さい構造となっている。この場合、第１およ
び第２の半導体チップ１，２の表面を被覆する保護膜７
により露出するＡｌ電極３ａ，３ｂの面積が異なる。こ
れらのＡｌ電極３ａ，３ｂ上に無電解めっき法により突
起電極４ａ，４ｂが形成されている。そして、上記のよ
うにＡｌ電極３ａ，３ｂの面積が異なるため、素子領域
６上のＡｌ電極３ａ上に形成された突起電極４ａが素子
領域６上以外のＡｌ電極３ｂ上に形成された突起電極４
ｂよりも高さが低くなっている。また、この第１の半導
体チップ１と第２の半導体チップ２が絶縁性樹脂５を介
して互いに張り合わされ、相対する位置のＡｌ電極３
ａ，３ｂが、突起電極４ａ，４ｂを介して電気的に接続
された構成となっている。The area of the Al electrode 3a formed on the element region 6 is smaller than the area of the Al electrode 3b formed on other than the element region 6. In this case, the protective film 7 that covers the surfaces of the first and second semiconductor chips 1 and 2
The exposed areas of the Al electrodes 3a and 3b are different. Protrusion electrodes 4a and 4b are formed on these Al electrodes 3a and 3b by electroless plating. Since the Al electrodes 3a and 3b have different areas as described above, the protruding electrode 4a formed on the Al electrode 3a on the element region 6 is the protruding electrode formed on the Al electrode 3b other than on the element region 6. Four
Height is lower than b. In addition, the first semiconductor chip 1 and the second semiconductor chip 2 are attached to each other with the insulating resin 5 interposed therebetween, and the Al electrodes 3 at opposite positions are attached to each other.
a and 3b are electrically connected via the protruding electrodes 4a and 4b.

【００２６】つぎに、この半導体装置の製造方法につい
て説明する。Ａｌ電極３ａ，３ｂ上に無電解Ｎｉめっき
により突起電極４ａ，４ｂを形成する。この場合、半導
体チップ１，２上のＡｌ電極３ａ，３ｂはスパッタ法で
形成されており、厚みは１μｍ、材料は、Ａｌ−１％Ｓ
ｉ−０．５％Ｃｕを用いた。例えば、Ａｌ電極３ａサイ
ズを１５μｍ角、Ａｌ電極３ｂのサイズを１００μｍ角
とする。また半導体チップ１，２のサイズはそれぞれ６
ｍｍ、８ｍｍとし、保護膜７は、Ｓｉ3 Ｎ4 膜である。Next, a method of manufacturing this semiconductor device will be described. The protruding electrodes 4a and 4b are formed on the Al electrodes 3a and 3b by electroless Ni plating. In this case, the Al electrodes 3a and 3b on the semiconductor chips 1 and 2 are formed by the sputtering method, the thickness is 1 μm, and the material is Al-1% S.
i-0.5% Cu was used. For example, the size of the Al electrode 3a is 15 μm square and the size of the Al electrode 3b is 100 μm square. The size of each of the semiconductor chips 1 and 2 is 6
mm and 8 mm, and the protective film 7 is a Si 3 N 4 film.

【００２７】無電解Ｎｉめっきによる突起電極４ａ，４
ｂの形成は、通常のＡｌに対するＮｉの無電解めっきプ
ロセスと同様で、例えば、ライトエッチング、Ｚｎ置換
処理、無電解Ｎｉめっきを３μｍ行い最後にＮｉ表面の
酸化防止の目的で無電解Ａｕめっきを０．２μｍ施す。
用いたＮｉめっき液は、硫酸ニッケルを主成分とする無
電解Ｎｉめっき液を用いる。このとき、Ｎｉ突起電極４
ａ，４ｂはＡｌ電極３ａ，３ｂの面積が異なると、突起
電極４ａ，４ｂの高さも異なり、面積が大きい方が高く
なる。これは電極サイズか小さくなると、液の表面張力
と液の循環性から高さが異なって成長するためである。
この場合、突起電極４ａよりも突起電極４ｂが高くな
る。Protruding electrodes 4a, 4 formed by electroless Ni plating
The formation of b is similar to the ordinary electroless plating process of Ni on Al. For example, light etching, Zn substitution treatment, electroless Ni plating is performed to 3 μm, and finally electroless Au plating is performed for the purpose of preventing oxidation of the Ni surface. 0.2 μm is applied.
The Ni plating solution used is an electroless Ni plating solution containing nickel sulfate as a main component. At this time, the Ni protrusion electrode 4
When the areas of the Al electrodes 3a and 3b of a and 4b are different, the heights of the protruding electrodes 4a and 4b are also different, and the larger the area, the higher. This is because when the electrode size becomes smaller, the height grows differently due to the surface tension of the liquid and the circulating property of the liquid.
In this case, the protruding electrode 4b is higher than the protruding electrode 4a.

【００２８】したがって、接続時にＮｉの突起電極４
ａ，４ｂのうち直接接触することにより、応力集中をお
こす突起電極４ｂは素子領域６上以外の電極３ｂに形成
されることとなり、荷重に対してダメージを受けやすい
素子領域６上の電極３ａに形成された突起電極４ａには
接続時の応力集中が生じない構造となる。突起電極４
ａ，４ｂの作製プロセスは基本的には以上で完了し、相
対する突起電極４ａ，４ｂを電気的な接続が得られるよ
うに接続する。Therefore, at the time of connection, the Ni protruding electrode 4 is connected.
The protruding electrode 4b that causes stress concentration due to direct contact between a and 4b is formed on the electrode 3b other than on the element region 6, and thus on the electrode 3a on the element region 6 which is easily damaged by a load. The formed protruding electrode 4a has a structure in which stress concentration does not occur at the time of connection. Protruding electrode 4
The fabrication process of a and 4b is basically completed as described above, and the protruding electrodes 4a and 4b facing each other are connected so as to obtain an electrical connection.

【００２９】この接続工程では、すべての突起電極４
ａ，４ｂの接触を得るまで変形させることが必要とな
る。例えば、Ｎｉの突起電極４ａ，４ｂの高さばらつき
が半導体チップ１，２内の同じ面積の電極３ａ，３ｂ上
のＮｉ突起電極４ａ，４ｂで約０．５μｍあるとする
と、最小でも０．５μｍ以上Ｎｉ突起電極４ａ，４ｂを
変形させなければならず、素子にダメージを与える接合
荷重が必要となる。In this connection process, all the protruding electrodes 4
It is necessary to deform until the contact between a and 4b is obtained. For example, if the height variation of the Ni protruding electrodes 4a and 4b is about 0.5 μm for the Ni protruding electrodes 4a and 4b on the electrodes 3a and 3b having the same area in the semiconductor chips 1 and 2, the minimum is 0.5 μm. As described above, the Ni protruding electrodes 4a and 4b must be deformed, and a bonding load that damages the element is required.

【００３０】そこで素子にダメージを与えない荷重で接
合を実現するために、突起電極４ａ，４ｂ上部に接合方
法に合わせた導電材料層８を形成する。この導電材料層
８は、素子にダメージを与えない荷重以内で塑性変形
し、突起電極４ａ，４ｂの高さばらつきやチップ１，２
の持つ反りを吸収する必要がある。例えば、この条件に
適合する材料としてＩｎあるいはＩｎとＳｎ，Ｐｂ，Ｂ
ｉ，Ａｇ，Ｚｎとの合金を用いる。導電材料層８の形成
方法は導電材料の融液中に浸漬させることにより突起電
極４ａ，４ｂ上に選択的に形成する方法がコスト的に有
利である。また、導電材料層８として、樹脂と金属から
なる導電性ペーストを用いてもよい。導電性ペーストを
用いる場合は、導電性ペーストを突起電極４ａ，４ｂに
転写や、インジェクションのような既存の方法で形成で
きる。Therefore, in order to realize the bonding with a load that does not damage the device, a conductive material layer 8 is formed on the upper portions of the protruding electrodes 4a and 4b according to the bonding method. The conductive material layer 8 is plastically deformed within a load that does not damage the element, and the height variations of the protruding electrodes 4a and 4b and the chips 1 and 2 are increased.
It is necessary to absorb the warp of. For example, In or In and Sn, Pb, B may be used as a material that meets these conditions.
An alloy with i, Ag and Zn is used. As a method of forming the conductive material layer 8, a method of selectively forming the conductive material layer 8 on the protruding electrodes 4a and 4b by immersing the conductive material layer 8 in a melt of the conductive material is advantageous in terms of cost. Further, as the conductive material layer 8, a conductive paste made of resin and metal may be used. When the conductive paste is used, the conductive paste can be formed on the protruding electrodes 4a and 4b by an existing method such as transfer or injection.

【００３１】このように導電材料層８を形成し、Ｎｉの
突起電極４ａ，４ｂの高さばらつき、さらには導電材料
層８の高さばらつきを吸収させて接触を図った後に、加
熱拡散させるか、周囲の光硬化性絶縁性樹脂５を硬化さ
せて接続を終了する。すなわち、図２に示すように、第
２の半導体チップ２に絶縁性樹脂５を塗布し、半導体チ
ップ１および半導体チップ２を位置合わせし、絶縁性樹
脂５を介して加圧ツール１１で半導体チップ１を加圧す
る。このとき、素子領域６上の電極３ａに加わる圧力が
０．０２ｇ／μｍ2 以下にする。これにより、突起電極
４ａ，４ｂもしくは導電材料層８を塑性変形させて全突
起電極４ａ，４ｂもしくは導電材料層８を接触させ、こ
の状態で周囲の絶縁性樹脂５を硬化させることにより接
続を得る。In this way, the conductive material layer 8 is formed, the height variations of the Ni protruding electrodes 4a and 4b, and further the height variations of the conductive material layer 8 are absorbed to make contact, and then the heat diffusion is performed. The peripheral photo-curable insulating resin 5 is cured to complete the connection. That is, as shown in FIG. 2, the insulating resin 5 is applied to the second semiconductor chip 2, the semiconductor chip 1 and the semiconductor chip 2 are aligned, and the semiconductor chip is pressed by the pressing tool 11 through the insulating resin 5. Pressurize 1. At this time, the pressure applied to the electrode 3a on the element region 6 is set to 0.02 g / μm 2 or less. As a result, the protruding electrodes 4a, 4b or the conductive material layer 8 are plastically deformed to bring all the protruding electrodes 4a, 4b or the conductive material layer 8 into contact, and in this state, the surrounding insulating resin 5 is cured to obtain a connection. .

【００３２】この実施の形態によれば、第１の半導体チ
ップ１および第２の半導体チップ２の素子領域６上に形
成された電極３ａの面積を素子領域６上以外に形成され
た電極３ｂの面積よりも小さくしたので、素子領域６上
の電極３ａ上に形成された突起電極４ａの高さが素子領
域６上以外の電極３ｂ上に形成された突起電極４ｂの高
さよりも低くなり、それゆえ突起電極４ａ，４ｂの接合
時に、素子領域６上以外の突起電極４ｂに応力集中が生
じ、素子領域６上の突起電極４ａに応力集中が生じない
構造となる。このため、素子領域６上に電極３ａを形成
したＬＳＩの実装において、素子へのダメージを与える
ことなく実装できるため、信頼性の高い積層型ＬＳＩや
配線基板への実装が実現できる。According to this embodiment, the areas of the electrodes 3a formed on the element regions 6 of the first semiconductor chip 1 and the second semiconductor chip 2 are the same as those of the electrodes 3b formed on other than the element regions 6. Since the area is smaller than the area, the height of the bump electrode 4a formed on the electrode 3a on the element region 6 becomes lower than the height of the bump electrode 4b formed on the electrode 3b other than on the element region 6, Therefore, when the protruding electrodes 4a and 4b are joined, stress concentration occurs on the protruding electrodes 4b other than on the element region 6, and stress concentration does not occur on the protruding electrodes 4a on the element region 6. Therefore, in mounting an LSI in which the electrode 3a is formed on the element region 6, the element can be mounted without damaging the element, and thus mounting on a highly reliable laminated LSI or wiring board can be realized.

【００３３】また、第１の半導体チップ１および第２の
半導体チップ２の突起電極４ａ，４ｂが無電解めっき法
にて形成されているので、半導体チップ１，２を無電解
めっき液に浸漬するだけで突起電極４ａ，４ｂを形成で
き、低コストで製造できる。なお、第１の半導体チップ
１および第２の半導体チップ２の一方を無電解めっき法
にて形成してもよい。また、無電解めっき法にて形成さ
れた突起電極４ａ，４ｂの上部に、この突起電極４ａ，
４ｂより硬度が低い導電材料層８を形成したので、素子
にダメージを与えない荷重で接合することができる。す
なわち、接続時に導電材料層８が素子にダメージを与え
ない荷重以内で塑性変形することにより、突起電極４
ａ，４ｂの高さばらつきや半導体チップ１，２の持つ反
りを吸収し、素子領域６上の電極３ａに加わる圧力が素
子領域６上以外の電極３ｂに加わる圧力よりも小さくな
って素子にダメージを与えることはない。また、第１の
半導体チップ１と第２の半導体チップ２の電極３ａ，３
ｂを電気的に接続する工程において、素子領域６上の電
極３ａに加わる圧力が０．０２ｇ／μｍ2 以下であるの
で、素子にダメージを与えることはない。Further, since the protruding electrodes 4a and 4b of the first semiconductor chip 1 and the second semiconductor chip 2 are formed by the electroless plating method, the semiconductor chips 1 and 2 are immersed in the electroless plating solution. The protruding electrodes 4a and 4b can be formed only by itself, and the manufacturing cost can be reduced. One of the first semiconductor chip 1 and the second semiconductor chip 2 may be formed by electroless plating. In addition, the protruding electrodes 4a, 4b formed by the electroless plating method are provided on the protruding electrodes 4a, 4b.
Since the conductive material layer 8 having a hardness lower than that of 4b is formed, it is possible to perform bonding with a load that does not damage the element. That is, when the conductive material layer 8 is plastically deformed within a load that does not damage the element during connection,
The height variation of a and 4b and the warp of the semiconductor chips 1 and 2 are absorbed, and the pressure applied to the electrode 3a on the element region 6 becomes smaller than the pressure applied to the electrode 3b other than on the element region 6 to damage the element. Never give. In addition, the electrodes 3a, 3 of the first semiconductor chip 1 and the second semiconductor chip 2 are
In the step of electrically connecting b, since the pressure applied to the electrode 3a on the element region 6 is 0.02 g / μm 2 or less, the element is not damaged.

【００３４】なお、すべての電極が素子領域６上に形成
される場合には、素子領域６上以外に半導体チップ１，
２内に少なくとも３点、上記実施の形態と同様のダミー
電極を形成しておけばよい。また、第１の半導体チップ
１あるいは第２の半導体チップ２の少なくとも一方が、
配線基板である場合、例えば第２の半導体チップ２が配
線基板である場合においては、第１の半導体チップ１上
に突起電極４ａ，４ｂを形成し、導電材料層８を突起電
極４ａ，４ｂ上あるいは、配線基板上に形成することに
より実現できる。When all the electrodes are formed on the element region 6, the semiconductor chip 1,
It is sufficient to form at least three dummy electrodes in 2 in the same manner as in the above embodiment. Further, at least one of the first semiconductor chip 1 and the second semiconductor chip 2 is
In the case of a wiring board, for example, when the second semiconductor chip 2 is a wiring board, the protruding electrodes 4a and 4b are formed on the first semiconductor chip 1 and the conductive material layer 8 is formed on the protruding electrodes 4a and 4b. Alternatively, it can be realized by forming it on a wiring board.

【００３５】この発明の第２の実施の形態を図３に基づ
いて説明する。第１の実施の形態と異なる点は、保護膜
７により素子領域６上の電極３ａが分割されており、各
分割領域１０の面積が、素子領域６上以外に形成された
電極３ｂの面積よりも小さい点にある。保護膜７により
電極３ａが分割されることにより、各分割された電極３
ａ上の突起電極４ａは、素子領域６上以外に形成された
電極３ｂの突起電極４ｂよりも高さが低くなり、張り合
わせ時に、素子領域６上に形成された電極３ａへの応力
集中が防げるだけでなく、電流容量を確保できるため、
半導体チップの種類を選ばない。その他の構成効果は、
第１の実施の形態と同様である。A second embodiment of the present invention will be described with reference to FIG. The difference from the first embodiment is that the electrode 3a on the element region 6 is divided by the protective film 7, and the area of each divided region 10 is larger than the area of the electrode 3b formed on other than the element region 6. Is also small. Since the electrode 3a is divided by the protective film 7, each divided electrode 3
The height of the protruding electrode 4a on a is lower than the height of the protruding electrode 4b of the electrode 3b formed on other than the element region 6, so that stress concentration on the electrode 3a formed on the element region 6 can be prevented at the time of bonding. Not only that, because the current capacity can be secured,
Any type of semiconductor chip can be used. Other composition effects
This is the same as in the first embodiment.

【００３６】[0036]

【発明の効果】この発明の請求項１記載の半導体装置に
よれば、第１の半導体チップおよび第２の半導体チップ
の素子領域上に形成された電極の面積を素子領域上以外
に形成された電極の面積よりも小さくしたので、素子領
域上の電極上に形成された突起電極の高さが素子領域上
以外の電極上に形成された突起電極の高さよりも低くな
り、それゆえ突起電極の接合時に、素子領域上以外の突
起電極に応力集中が生じ、素子領域上の突起電極に応力
集中が生じない構造となる。このため、素子領域上に電
極を形成したＬＳＩの実装において、素子へのダメージ
を与えることなく実装できるため、信頼性の高い積層型
ＬＳＩや配線基板への実装が実現できる。According to the semiconductor device of the first aspect of the present invention, the areas of the electrodes formed on the element regions of the first semiconductor chip and the second semiconductor chip are formed outside the element region. Since it is smaller than the area of the electrode, the height of the protruding electrode formed on the electrode on the element region is lower than the height of the protruding electrode formed on the electrode other than the element region, and therefore At the time of bonding, stress concentration occurs on the protruding electrodes other than on the element region, and stress concentration does not occur on the protruding electrodes on the element region. Therefore, when mounting an LSI in which electrodes are formed on the element region, the element can be mounted without damaging the element, and thus mounting on a highly reliable laminated LSI or wiring board can be realized.

【００３７】請求項２記載の半導体装置によれば、第１
の半導体チップおよび第２の半導体チップの素子領域上
に形成された電極を絶縁膜により少なくとも２つ以上に
分割することにより、この分割された領域を素子領域上
以外に形成された電極よりも面積よりも小さくしたの
で、素子領域上の電極上に形成された突起電極の高さが
素子領域上以外の電極上に形成された突起電極の高さよ
りも低くなり、それゆえ突起電極の接合時に、素子領域
上以外の突起電極に応力集中が生じ、素子領域上の突起
電極に応力集中が生じない構造となるだけでなく電流容
量を確保できる。その他、請求項１と同様の効果が得ら
れる。According to the semiconductor device of the second aspect, the first
The electrodes formed on the element regions of the semiconductor chip and the second semiconductor chip are divided into at least two or more parts by the insulating film, so that the divided regions have an area larger than that of the electrodes formed other than on the element regions. Since the height of the protruding electrode formed on the electrode on the element region is lower than the height of the protruding electrode formed on the electrode other than on the element region, therefore, at the time of joining the protruding electrodes, The stress concentration occurs on the protruding electrodes other than on the element region, so that the stress concentration does not occur on the protruding electrodes on the element region, and the current capacity can be secured. In addition, the same effect as that of the first aspect can be obtained.

【００３８】請求項３では、第１の半導体チップおよび
第２の半導体チップの突起電極の少なくとも一方が無電
解めっき法にて形成されているので、半導体チップを無
電解めっき液に浸漬するだけで突起電極を形成でき、低
コストで製造できる。また、請求項１および２に記載の
ように、素子領域上の電極上に形成された突起電極の高
さが素子領域上以外の電極上に形成された突起電極の高
さよりも低くなるため、電極およびめっき液の状態によ
る突起電極の高さばらつきにより素子にダメージを与え
ることはない。その他の効果は請求項１または２と同様
である。In the third aspect, since at least one of the protruding electrodes of the first semiconductor chip and the second semiconductor chip is formed by the electroless plating method, the semiconductor chip can be simply immersed in the electroless plating solution. A protruding electrode can be formed, and it can be manufactured at low cost. Further, as described in claims 1 and 2, since the height of the protruding electrode formed on the electrode on the element region is lower than the height of the protruding electrode formed on the electrode other than the element region, There is no damage to the element due to height variations of the protruding electrodes due to the state of the electrodes and the plating solution. The other effects are similar to those of claim 1 or 2.

【００３９】請求項４では、第１の半導体チップおよび
第２の半導体チップの少なくとも一方が配線基板である
ので、配線基板への実装が実現できる。その他の効果は
請求項１または２と同様である。請求項５では、無電解
めっき法にて形成された突起電極の上部に、この突起電
極より硬度が低い導電材料層を形成したので、素子にダ
メージを与えない荷重で接合することができる。すなわ
ち、接続時に導電材料層が素子にダメージを与えない荷
重以内で塑性変形することにより、突起電極の高さばら
つきや半導体チップの持つ反りを吸収し、素子領域上の
電極に加わる圧力が素子領域上以外の電極に加わる圧力
よりも小さくなって素子にダメージを与えることはな
い。その他の効果は請求項１または２と同様である。In the fourth aspect, at least one of the first semiconductor chip and the second semiconductor chip is a wiring board, so that mounting on the wiring board can be realized. The other effects are similar to those of claim 1 or 2. According to the fifth aspect, since the conductive material layer having a hardness lower than that of the protruding electrode is formed on the protruding electrode formed by the electroless plating method, the element can be bonded with a load that does not damage the element. That is, when the conductive material layer is plastically deformed during connection within a load that does not damage the element, variations in height of the protruding electrodes and warpage of the semiconductor chip are absorbed, and the pressure applied to the electrodes on the element region is The pressure is smaller than the pressure applied to the electrodes other than the above and does not damage the device. The other effects are similar to those of claim 1 or 2.

【００４０】請求項６では、請求項５において導電材料
層としてＩｎあるいはＩｎにＳｎ，Ｐｂ，Ｂｉ，Ａｇ，
Ｚｎのうち少なくとも１つ以上を含む金属を用いること
により、接続時に導電材料層が素子にダメージを与えな
い荷重以内で塑性変形し、突起電極の高さばらつきや半
導体チップの持つ反りを吸収することができる。請求項
７では、請求項５において導電材料層を樹脂と金属から
なる導電性ペーストとすることにより、接続時に導電材
料層が素子にダメージを与えない荷重以内で塑性変形
し、突起電極の高さばらつきや半導体チップの持つ反り
を吸収することができる。In a sixth aspect of the present invention, as the conductive material layer of the fifth aspect, In or In containing Sn, Pb, Bi, Ag,
By using a metal containing at least one of Zn, the conductive material layer undergoes plastic deformation within a load that does not damage the element at the time of connection, and absorbs height variation of the protruding electrode and warpage of the semiconductor chip. You can According to a seventh aspect of the present invention, the conductive material layer according to the fifth aspect is a conductive paste made of a resin and a metal, so that the conductive material layer is plastically deformed within a load that does not damage an element at the time of connection, and the height of the protruding electrode is increased. It is possible to absorb variations and warpage of the semiconductor chip.

【００４１】この発明の請求項８記載の半導体装置の製
造方法によれば、素子領域上が素子領域上以外よりも面
積が小さくなるように第１の半導体チップおよび第２の
半導体チップの表面上の対応する位置に電極を形成する
ので、素子領域上の電極上に形成された突起電極が素子
領域上以外の電極上に形成された突起電極よりも高さが
低くなる。このため、第１の半導体チップあるいは第２
の半導体チップの裏面を加圧して突起電極の接合する時
に、素子領域上以外の突起電極に応力集中が生じ、素子
領域上の突起電極に応力集中が生じない構造となる。ま
た、突起電極が無電解めっき処理にて形成されているの
で、半導体チップを無電解めっき液に浸漬するだけで突
起電極を形成でき、低コストで製造できる。According to the method of manufacturing a semiconductor device according to the eighth aspect of the present invention, on the surface of the first semiconductor chip and the second semiconductor chip such that the area over the element region is smaller than the area over the element region. Since the electrodes are formed at the corresponding positions, the height of the protruding electrode formed on the electrode on the element region is lower than that of the protruding electrode formed on the electrode other than the element region. Therefore, the first semiconductor chip or the second semiconductor chip
When the back surface of the semiconductor chip is pressed to bond the protruding electrodes, stress concentration occurs on the protruding electrodes other than on the element region, and stress concentration does not occur on the protruding electrodes on the element region. Further, since the protruding electrodes are formed by the electroless plating treatment, the protruding electrodes can be formed only by immersing the semiconductor chip in the electroless plating solution, and the manufacturing cost can be reduced.

【００４２】請求項９では、請求項８において素子領域
上の電極に加わる圧力が０．０２ｇ／μｍ2 以下である
ので、素子にダメージを与えることはない。請求項１０
では、請求項８において導電材料層を構成する金属の融
液に第１の半導体チップあるいは第２の半導体チップの
少なくとも一方を浸漬させることにより、突起電極の上
部にこの突起電極よりも硬度が低い導電材料層を形成す
るので、素子にダメージを与えない荷重で接合すること
ができる。すなわち、接続時に導電材料層が素子にダメ
ージを与えない荷重以内で塑性変形することにより、突
起電極の高さばらつきや半導体チップの持つ反りを吸収
し、素子領域上の電極に加わる圧力が素子領域上以外の
電極に加わる圧力よりも小さくなって素子にダメージを
与えることはない。また、上記のように導電材料の融液
中に浸漬することにより導電材料層を形成したので、コ
スト的に有利である。In the ninth aspect, since the pressure applied to the electrode on the element region is 0.02 g / μm 2 or less in the eighth aspect, the element is not damaged. Claim 10
Then, according to claim 8, at least one of the first semiconductor chip and the second semiconductor chip is dipped in the melt of the metal forming the conductive material layer, so that the hardness is lower than the protruding electrode above the protruding electrode. Since the conductive material layer is formed, the elements can be bonded with a load that does not damage the element. That is, when the conductive material layer is plastically deformed during connection within a load that does not damage the element, variations in height of the protruding electrodes and warpage of the semiconductor chip are absorbed, and the pressure applied to the electrodes on the element region is The pressure is smaller than the pressure applied to the electrodes other than the above and does not damage the device. Further, since the conductive material layer is formed by immersing the conductive material in the melt of the conductive material as described above, it is advantageous in terms of cost.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明の第１の実施の形態の半導体装置の断
面図である。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

【図２】第１の実施の形態の半導体装置の製造方法を示
す断面図である。FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device of the first embodiment.

【図３】第２の実施の形態の半導体装置の断面図であ
る。FIG. 3 is a sectional view of a semiconductor device according to a second embodiment.

【符号の説明】[Explanation of symbols]

１ 第１の半導体チップ ２ 第２の半導体チップ ４ａ，４ｂ 突起電極 ５ 絶縁性樹脂 ６ 素子領域 ３ａ 素子領域上に形成されたＡｌ電極 ３ｂ 素子領域上以外に形成されたＡｌ電極 ７ 保護膜 ８ 導電材料層 1 1st semiconductor chip 2 2nd semiconductor chip 4a, 4b Projection electrode 5 Insulating resin 6 Element area 3a Al electrode formed on the element area 3b Al electrode formed on areas other than the element area 7 Protective film 8 Conductivity Material layer

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 第１の半導体チップと第２の半導体チッ
プの表面同士が絶縁性樹脂を介して互いに張り合わさ
れ、前記第１の半導体チップの表面上に位置する電極上
に形成された突起電極と、前記第２の半導体チップの表
面上に位置し前記第１の半導体チップの電極に対応する
電極上に形成された突起電極とが電気的に接続された半
導体装置であって、前記第１の半導体チップおよび第２
の半導体チップの素子領域上に形成された電極の面積が
前記素子領域上以外に形成された電極の面積よりも小さ
いことを特徴とする半導体装置。1. A projecting electrode formed on an electrode located on the surface of the first semiconductor chip, the surfaces of the first semiconductor chip and the second semiconductor chip being adhered to each other via an insulating resin. And a protruding electrode formed on an electrode corresponding to the electrode of the first semiconductor chip and located on the surface of the second semiconductor chip are electrically connected to each other. Semiconductor chip and second
The semiconductor device is characterized in that the area of the electrode formed on the element region of the semiconductor chip is smaller than the area of the electrode formed other than on the element region. 【請求項２】 第１の半導体チップと第２の半導体チッ
プの表面同士が絶縁性樹脂を介して互いに張り合わさ
れ、前記第１の半導体チップの表面上に位置する電極上
に形成された突起電極と、前記第２の半導体チップの表
面上に位置し前記第１の半導体チップの電極に対応する
電極上に形成された突起電極とが電気的に接続された半
導体装置であって、前記第１の半導体チップおよび第２
の半導体チップの素子領域上に形成された電極が絶縁膜
により少なくとも２つ以上に分割された領域からなり前
記分割された領域が前記素子領域上以外に形成された電
極よりも面積が小さいことを特徴とする半導体装置。2. A protruding electrode formed on an electrode located on the surface of the first semiconductor chip, the surfaces of the first semiconductor chip and the second semiconductor chip being adhered to each other via an insulating resin. And a protruding electrode formed on an electrode corresponding to the electrode of the first semiconductor chip and located on the surface of the second semiconductor chip are electrically connected to each other. Semiconductor chip and second
The electrode formed on the element region of the semiconductor chip is composed of at least two regions divided by an insulating film, and the divided region has a smaller area than the electrodes formed other than on the element region. Characteristic semiconductor device. 【請求項３】 第１の半導体チップおよび第２の半導体
チップの突起電極の少なくとも一方が無電解めっき法に
て形成された請求項１または２記載の半導体装置。3. The semiconductor device according to claim 1, wherein at least one of the protruding electrodes of the first semiconductor chip and the second semiconductor chip is formed by electroless plating. 【請求項４】 第１の半導体チップおよび第２の半導体
チップの少なくとも一方が配線基板である請求項１また
は２記載の半導体装置。4. The semiconductor device according to claim 1, wherein at least one of the first semiconductor chip and the second semiconductor chip is a wiring board. 【請求項５】 第１の半導体チップおよび第２の半導体
チップの突起電極の少なくとも一方が無電解めっき法に
て形成され、その上部に、無電解めっき法にて形成され
た突起電極より硬度が低い導電材料層を形成した請求項
１または２記載の半導体装置。5. At least one of the protruding electrodes of the first semiconductor chip and the second semiconductor chip is formed by an electroless plating method, and has a hardness higher than that of the protruding electrodes formed by an electroless plating method on the upper side thereof. The semiconductor device according to claim 1, wherein a low conductive material layer is formed. 【請求項６】 導電材料層がＩｎあるいはＩｎにＳｎ，
Ｐｂ，Ｂｉ，Ａｇ，Ｚｎのうち少なくとも１つ以上を含
む金属からなる請求項５記載の半導体装置。6. The conductive material layer is In or Sn in In,
The semiconductor device according to claim 5, which is made of a metal containing at least one of Pb, Bi, Ag, and Zn. 【請求項７】 導電材料層が樹脂と金属からなる導電性
ペーストである請求項５記載の半導体装置。7. The semiconductor device according to claim 5, wherein the conductive material layer is a conductive paste made of resin and metal. 【請求項８】 素子領域上が素子領域上以外よりも面積
が小さくなるように第１の半導体チップおよび第２の半
導体チップの表面上の対応する位置に電極を形成する工
程と、前記第１の半導体チップおよび第２の半導体チッ
プの電極上に無電解めっき処理により突起電極を形成す
る工程と、前記第１の半導体チップあるいは第２の半導
体チップの表面上に絶縁性樹脂を塗布する工程と、前記
第１の半導体チップおよび第２の半導体チップの突起電
極を位置合わせする工程と、前記第１の半導体チップあ
るいは第２の半導体チップの裏面を加圧し、前記絶縁性
樹脂を硬化させることにより前記第１の半導体チップと
第２の半導体チップの電極を電気的に接続する工程とか
らなる半導体装置の製造方法。8. A step of forming electrodes at corresponding positions on the surfaces of the first semiconductor chip and the second semiconductor chip so that the area of the element region is smaller than that of the area other than the element region. Forming a protruding electrode on the electrodes of the semiconductor chip and the second semiconductor chip by electroless plating, and applying an insulating resin on the surface of the first semiconductor chip or the second semiconductor chip. By aligning the protruding electrodes of the first semiconductor chip and the second semiconductor chip with each other, and pressing the back surface of the first semiconductor chip or the second semiconductor chip to cure the insulating resin. A method of manufacturing a semiconductor device, comprising a step of electrically connecting electrodes of the first semiconductor chip and the electrodes of the second semiconductor chip. 【請求項９】 第１の半導体チップと第２の半導体チッ
プの電極を電気的に接続する工程において、素子領域上
の電極に加わる圧力が０．０２ｇ／μｍ2 以下である請
求項８記載の半導体装置の製造方法。9. The pressure applied to the electrode on the element region is 0.02 g / μm 2 or less in the step of electrically connecting the electrodes of the first semiconductor chip and the second semiconductor chip. Manufacturing method of semiconductor device. 【請求項１０】 第１の半導体チップと第２の半導体チ
ップの電極上に突起電極を形成する工程において、導電
材料層を構成する金属の融液に前記第１の半導体チップ
あるいは第２の半導体チップの少なくとも一方を浸漬さ
せることにより、前記突起電極の上部にこの突起電極よ
りも硬度が低い導電材料層を形成する請求項８記載の半
導体装置の製造方法。10. In the step of forming protruding electrodes on the electrodes of the first semiconductor chip and the second semiconductor chip, the first semiconductor chip or the second semiconductor is added to the metal melt forming the conductive material layer. 9. The method for manufacturing a semiconductor device according to claim 8, wherein a conductive material layer having a hardness lower than that of the protruding electrode is formed on the protruding electrode by immersing at least one of the chips.
JP03179096A 1996-02-20 1996-02-20 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3279470B2 (en)

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