JPH09232426A - Manufacture of semiconductor device provided with multilayered interconnection structure - Google Patents
Manufacture of semiconductor device provided with multilayered interconnection structureInfo
- Publication number
- JPH09232426A JPH09232426A JP3658996A JP3658996A JPH09232426A JP H09232426 A JPH09232426 A JP H09232426A JP 3658996 A JP3658996 A JP 3658996A JP 3658996 A JP3658996 A JP 3658996A JP H09232426 A JPH09232426 A JP H09232426A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- silicon nitride
- forming
- film
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、層間絶縁膜の形成工
程を改良した多層配線構造を有する半導体装置の製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a multi-layered wiring structure in which an interlayer insulating film forming process is improved.
【０００２】[0002]
【従来の技術】半導体装置の集積度が増大するのにつれ
て、基板上に配線材料を多層に形成する、いわゆる多層
配線化が進んでおり、このような多層配線構造を有する
半導体装置の製造工程が複雑化すると共に、工程数が増
えている。2. Description of the Related Art As the degree of integration of semiconductor devices increases, so-called multi-layer wiring is being formed, in which wiring materials are formed in multiple layers on a substrate, and the manufacturing process of a semiconductor device having such a multi-layer wiring structure is increasing. The number of steps is increasing with the complexity.
【０００３】特に、多層配線の形成工程は、半導体装置
の製造価格を決める要因となるので、半導体装置を製造
するに要する価格の低減を図る上で製造工程を簡略化す
ること及び多層配線工程数を減らすことの要求は重要で
ある。ここで、従来の多層配線の形成工程について説明
する。In particular, since the process of forming the multi-layer wiring is a factor that determines the manufacturing cost of the semiconductor device, the manufacturing process can be simplified and the number of multi-layer wiring processes can be reduced in order to reduce the price required for manufacturing the semiconductor device. The requirement to reduce is important. Here, a conventional multilayer wiring forming process will be described.
【０００４】まず、基板上に下層配線用の第１の配線材
料を堆積後、下層配線のパターニングを行い、この下層
配線上に第１の絶縁膜を形成すると共に下層配線相互間
に絶縁膜を埋め込む。First, after depositing a first wiring material for lower layer wiring on a substrate, the lower layer wiring is patterned to form a first insulating film on the lower layer wiring and an insulating film is formed between the lower layer wirings. Embed.
【０００５】この時点では、前記下層配線のパターンな
どに依存して第１の絶縁膜の表面に段差が存在し、この
ままでは、この後の上層配線用の第２の配線材料の堆積
時および上層配線のパターニング時に悪影響を及ぼし、
上層配線の段切れによる断線、短絡などの重大な欠陥を
もたらすおそれがある。At this point, there is a step on the surface of the first insulating film depending on the pattern of the lower layer wiring, etc., and if it is left as it is, when the second wiring material for the upper layer wiring is deposited thereafter and the upper layer is formed. Adversely affects the patterning of wiring,
There is a risk of causing serious defects such as disconnection and short circuit due to disconnection of upper layer wiring.
【０００６】そこで、通常は、前記第１の絶縁膜上に第
２の配線材料を堆積する前に、その下地である第１の絶
縁膜の表面をレジストエッチバックにより平坦化して段
差を緩和した後、その上に第２の絶縁膜を形成してい
る。Therefore, usually, before depositing the second wiring material on the first insulating film, the surface of the underlying first insulating film is flattened by resist etch back to alleviate the step. After that, a second insulating film is formed on it.
【０００７】上記したような第１の絶縁膜と第２の絶縁
膜とが積層された従来の層間絶縁膜の形成工程は、１回
目の成膜をした後、この第１の絶縁膜を平坦化する工程
を経て、次いで２回目の成膜工程である第２の絶縁膜を
形成している。このような従来の層間絶縁膜の形成工程
は、前述したような多層配線工程の低減化の要求に反す
るものであった。In the conventional step of forming an interlayer insulating film in which the first insulating film and the second insulating film are laminated as described above, after the first film formation, the first insulating film is flattened. Then, the second insulating film, which is the second film forming process, is formed. Such a conventional process for forming an interlayer insulating film is contrary to the demand for reduction of the multilayer wiring process as described above.
【０００８】一方、上記したような第１の絶縁膜の表面
を平坦化する方法の代わりに、第１の絶縁膜上に絶縁材
料であるスピン・オン・グラス（Spin on Glass ；ＳＯ
Ｇ）膜を形成することにより、上層配線材料がその下地
の段差によって受ける影響を緩和する方法も知られてい
る。On the other hand, instead of the method of flattening the surface of the first insulating film as described above, spin on glass (SO) as an insulating material is formed on the first insulating film.
G) There is also known a method of forming a film to mitigate the influence of the step of the underlying layer on the upper wiring material.
【０００９】しかし、この方法は、ＳＯＧ膜の形成（焼
成）に際して多数回の熱処理工程が必要であり、上層配
線の信頼性を確保するためにＳＯＧ膜の不要部分をレジ
ストエッチバックにより除去する必要があり、結果的に
工程数が多く、やはり、前記したような多層配線工程の
低減化の要求に対して十分には応えることができなかっ
た。However, this method requires a large number of heat treatment steps when forming (baking) the SOG film, and it is necessary to remove unnecessary portions of the SOG film by resist etch back in order to ensure the reliability of the upper wiring. However, as a result, the number of steps is large, and again, it has not been possible to sufficiently meet the demand for reduction of the multi-layer wiring step as described above.
【００１０】ところで、近時、前述したような多層配線
工程の低減化の要求に応える技術の１つとして、層間絶
縁膜の形成に際して、ＳｉＨ4 ガスと、酸化剤であるＨ
2 Ｏ2 （過酸化水素水）とを低温（例えば０℃程度）で
且つ真空中で反応させることにより、下層配線上に自己
流動型（リフロー）のＳｉＯ2 膜（以下、リフローＳｉ
Ｏ2 膜という）を形成するプロセスが注目されている。By the way, recently, as one of the techniques for responding to the demand for reduction of the multilayer wiring process as described above, SiH 4 gas and H which is an oxidizer are formed when the interlayer insulating film is formed.
By reacting with 2 O 2 (hydrogen peroxide solution) at a low temperature (for example, about 0 ° C.) in a vacuum, a self-flowing type (reflow) SiO 2 film (hereinafter referred to as reflow Si) is formed on the lower wiring.
A process of forming an O 2 film) is drawing attention.
【００１１】この方法は、下層配線の配線相互間の絶縁
膜の埋め込みと絶縁膜表面の平坦化を同時に達成でき、
１回の成膜で平坦化までの工程を終了するので、多層配
線工程の低減化を実現できる。According to this method, the filling of the insulating film between the wirings of the lower layer wiring and the flattening of the insulating film surface can be achieved at the same time,
Since the steps up to planarization are completed by one film formation, it is possible to reduce the number of multilayer wiring steps.
【００１２】ところで、上記したようなリフローＳｉＯ
2 膜の形成方法により得られたリフローＳｉＯ2 膜は、
その反応形態から明らかなように、リフローＳｉＯ2 膜
の成膜中に水分（Ｈ2 Ｏ）が発生し、リフローＳｉＯ2
膜中に多量の水分が含まれる。このため、成膜中或いは
その後の必要な熱処理中に膜中の水分が半導体基板に形
成された半導体素子の信頼性その他に悪影響をもたらす
という欠点があった。By the way, the reflow SiO as described above is used.
The reflow SiO 2 film obtained by the method of forming the two films is
Its is apparent from the reaction form, water (H 2 O) is generated during formation of the reflow SiO 2 film, the reflow SiO 2
A large amount of water is contained in the film. For this reason, there is a drawback that the moisture in the film adversely affects the reliability and the like of the semiconductor element formed on the semiconductor substrate during the film formation or the necessary heat treatment thereafter.
【００１３】[0013]
【発明が解決しようとする課題】この発明は、上記欠点
を除去し、リフローＳｉＯ2 膜の成膜中に発生する水分
（Ｈ2 Ｏ）がその下地の半導体素子に与える影響を低減
することのできる層間絶縁膜の形成工程を改良した多層
配線構造を有する半導体装置の製造方法を提供すること
を目的とする。SUMMARY OF THE INVENTION The present invention eliminates the above drawbacks and reduces the influence of moisture (H 2 O) generated during the formation of a reflow SiO 2 film on the underlying semiconductor element. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a multilayer wiring structure, in which the process of forming an interlayer insulating film is improved.
【００１４】[0014]
【課題を解決するための手段】上記目的を達成するた
め、この発明の層間絶縁膜の形成工程を改良した多層配
線構造を有する半導体装置の製造方法は、半導体基板上
に下層配線を形成する工程と、前記半導体基板上及び前
記下層配線上に窒化珪素膜を形成する工程と、５Toll以
下の真空室内に、前記下層配線及び窒化珪素膜を形成後
の半導体基板を収容し、ＳｉＨ4 ガスおよびＨ2 Ｏ2 を
導入し、−１０℃以上＋１０℃以下の温度範囲内で互い
に反応させることによって、前記半導体基板上にリフロ
―形状を呈する酸化珪素膜を形成する酸化珪素膜形成工
程と、より構成される。In order to achieve the above object, a method of manufacturing a semiconductor device having a multilayer wiring structure, which is an improved method of forming an interlayer insulating film according to the present invention, includes a step of forming a lower layer wiring on a semiconductor substrate. And a step of forming a silicon nitride film on the semiconductor substrate and the lower wiring, and the semiconductor substrate on which the lower wiring and the silicon nitride film have been formed is housed in a vacuum chamber of 5 Toll or less, and SiH 4 gas and H 2 O 2 is introduced and reacted with each other within a temperature range of −10 ° C. or higher and + 10 ° C. or lower to form a reflow-shaped silicon oxide film on the semiconductor substrate. To be done.
【００１５】[0015]
【作用】リフローＳｉＯ2 膜の成膜中に水分（Ｈ2 Ｏ）
が発生し、半導体基板に形成された半導体素子に悪影響
を与えるのを防ぐため水分拡散のブロック層として、リ
フローＳｉＯ2 膜の成膜前に半導体基板上及び下層配線
上に窒化珪素膜を形成する。[Operation] Moisture (H 2 O) is generated during the formation of the reflow SiO 2 film.
A silicon nitride film is formed on the semiconductor substrate and the lower layer wiring before the formation of the reflow SiO 2 film as a moisture diffusion block layer in order to prevent the occurrence of an adverse effect on the semiconductor element formed on the semiconductor substrate. .
【００１６】[0016]
【発明の実施の形態】以下、この発明の一実施例につい
て図面を参照して説明する。まず、図１に示すように、
半導体基板（通常、シリコンウエハー）１０上の絶縁膜
１１を介して下層配線用の配線材料（例えばアルミニウ
ム）を例えばスパッタ法により堆積後、フォトリソグラ
フィ技術および反応性イオンエッチング（ＲＩＥ）技術
を用いて第１の配線材料のパターニングを行って下層配
線１２を形成する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, as shown in FIG.
A wiring material (for example, aluminum) for a lower layer wiring is deposited by, for example, a sputtering method via an insulating film 11 on a semiconductor substrate (usually a silicon wafer) 10, and then a photolithography technique and a reactive ion etching (RIE) technique are used. The lower wiring 12 is formed by patterning the first wiring material.
【００１７】次に、図２に示すように前記半導体基板１
０上及び前記下層配線１２上に窒化珪素膜１３を形成す
る。前記窒化珪素膜１３を形成する工程は、図３に示す
マルチチャンバータイプの減圧ＣＶＤ装置の真空室９０
の内、一方の真空室８１内の下部電極９２上に、下層配
線１２を形成後の半導体基板１０を載置し、これら下層
配線１２及び半導体基板１０の表面に、ＳｉＨ4 ガス供
給源およびＮＨ3 供給源からＳｉＨ4 ガスおよびＮＨ3
を上部電極９３のシャワーヘッドを用いて導入し、前記
半導体基板１０上及び前記下層配線１２上に窒化珪素膜
１３を形成する。Next, as shown in FIG. 2, the semiconductor substrate 1
A silicon nitride film 13 is formed on the lower layer wiring 12 and the lower layer wiring 12. The step of forming the silicon nitride film 13 is performed in the vacuum chamber 90 of the multi-chamber type low pressure CVD apparatus shown in FIG.
Among them, the semiconductor substrate 10 on which the lower layer wiring 12 is formed is placed on the lower electrode 92 in one of the vacuum chambers 81, and the SiH 4 gas supply source and the NH 3 gas are supplied on the surfaces of the lower layer wiring 12 and the semiconductor substrate 10. SiH 4 gas and NH 3 from the source
Is introduced by using the shower head of the upper electrode 93, and the silicon nitride film 13 is formed on the semiconductor substrate 10 and the lower layer wiring 12.
【００１８】前記窒化珪素膜１３を形成後の半導体基板
１０を、他方の真空室８２内の下部電極９４上にセット
し、ＳｉＨ4 ガス供給源およびＨ2 Ｏ2 供給源からチャ
ンバー内に上部電極９５を介して、ＳｉＨ4 ガスおよび
Ｈ2 Ｏ2 を導入して、５Ｔｏｒｒ（＝５×１３３．３２
２Ｐａ）以下の真空中、−１０℃以上＋１０℃以下の温
度範囲内（例えば０℃）で互いに反応させ、図４に示す
ように前記窒化珪素膜１３上にリフロー形状を有するリ
フローＳｉＯ2 膜１４を形成する。The semiconductor substrate 10 on which the silicon nitride film 13 has been formed is set on the lower electrode 94 in the other vacuum chamber 82, and the upper electrode is introduced into the chamber from the SiH 4 gas supply source and the H 2 O 2 supply source. SiH 4 gas and H 2 O 2 were introduced through 95 to obtain 5 Torr (= 5 × 133.32
2 Pa) or less, and a reflow SiO 2 film 14 having a reflow shape on the silicon nitride film 13 as shown in FIG. 4 by reacting with each other within a temperature range of −10 ° C. or higher and + 10 ° C. or lower (for example, 0 ° C.). To form.
【００１９】上述の窒化珪素膜１３は、リフローＳｉＯ
2 膜の成膜中に水分（Ｈ2 Ｏ）が発生し、半導体基板１
０に形成された半導体素子に悪影響を与えるのを防ぐた
め水分拡散のブロック層として、リフローＳｉＯ2 膜の
成膜前に半導体基板１０上及び下層配線１２上に形成さ
れるものである。The above-mentioned silicon nitride film 13 is a reflow SiO.
Water (H 2 O) is generated during the formation of the two films, and the semiconductor substrate 1
It is formed on the semiconductor substrate 10 and the lower wiring 12 before forming the reflow SiO 2 film as a moisture diffusion block layer in order to prevent the semiconductor element formed in 0 from being adversely affected.
【００２０】尚、図示してないが、前記リフローＳｉＯ
2 膜１４にコンタクトホール或いはビアホールを開口
し、上層配線用の配線材料を堆積後、パターニングを行
って上層配線を形成し、コンタクトホール或いはビアホ
ールを介して下層配線と接続し２層配線構造とされる。Although not shown, the reflow SiO
A contact hole or a via hole is opened in the 2 film 14, a wiring material for the upper layer wiring is deposited, and then patterning is performed to form an upper layer wiring, which is connected to the lower layer wiring through the contact hole or the via hole to form a two layer wiring structure. It
【００２１】尚、前記窒化珪素膜１３は、成膜後に、酸
素ガス若しくは亜酸化窒素ガス中で表面処理を行うこと
によって、親水性を高めることができる。又、前記窒化
珪素膜１３は、真空室８１内で成膜後に、一旦真空室外
に取り出し大気中に晒された後、再び真空中、即ち、真
空室８２内に移され、真空室８２内の下部電極９４上に
セットされる。次いで、前述したようにリフローＳｉＯ
2膜１４が前記窒化珪素膜１３上に形成される。この例
においても前記窒化珪素膜１３は、大気中に晒されるこ
とによって、親水性を高めることができる。The silicon nitride film 13 can be made more hydrophilic by subjecting it to a surface treatment in oxygen gas or nitrous oxide gas after film formation. After the silicon nitride film 13 is formed in the vacuum chamber 81, the silicon nitride film 13 is once taken out of the vacuum chamber, exposed to the atmosphere, and then moved again into the vacuum chamber, that is, in the vacuum chamber 82, and the inside of the vacuum chamber 82 is removed. It is set on the lower electrode 94. Then, as described above, reflow SiO
A 2 film 14 is formed on the silicon nitride film 13. Also in this example, the silicon nitride film 13 can be made more hydrophilic by exposing it to the atmosphere.
【００２２】更に、他の実施例として、前記窒化珪素膜
１３は、成膜後に、酸素ガス若しくは亜酸化窒素ガス中
で表面処理を行い、且つ大気中に晒すことによって、親
水性を高めることもできる。Further, as another embodiment, the silicon nitride film 13 may be surface-treated in oxygen gas or nitrous oxide gas after being formed and exposed to the atmosphere to increase hydrophilicity. it can.
【００２３】上述の実施例では、リフローＳｉＯ2 膜１
４中に発生する水分の拡散を防止するために設けられる
ブロック層として窒化珪素膜を用いたが、この窒化珪素
膜が他の酸化珪素膜を用いた場合にくらべ、水分の下地
への拡散防止効果が優れていることが図５に示すように
明らかであった。In the above embodiment, the reflow SiO 2 film 1 is used.
Although a silicon nitride film was used as a block layer provided to prevent the diffusion of moisture generated in 4 above, compared with the case where this silicon nitride film uses another silicon oxide film, the diffusion of moisture to the underlayer is prevented. It was clear that the effect was excellent as shown in FIG.
【００２４】即ち、図５は、横軸に電圧印加時間、縦軸
にコンダクタンスＧｍの劣化率を示し、ＮチャンネルＭ
ＯＳに一定電圧を印加した場合の異なる水分拡散のブロ
ック層の比較を示す。That is, in FIG. 5, the horizontal axis shows the voltage application time, the vertical axis shows the deterioration rate of the conductance Gm, and the N channel M
A comparison of different moisture diffusion block layers when a constant voltage is applied to the OS is shown.
【００２５】（ａ）で示す水分を含まないＳｉＨ4 ガス
を使用して成膜した酸化珪素膜（Ｐ−ＳｉＯ）だけでリ
フローＳｉＯ2 膜のない場合に対しては、劣るが、
（ｂ）で示す本発明の窒化珪素膜（Ｐ−ＳｉＮ膜：膜厚
１００nm）を形成後、リフローＳｉＯ2 膜を積層した場
合は、Ｇｍの劣化は少なく、ＭＯＳトランジスタへの影
響は少ないことが分かる。これに対し、（ｃ）に示す
（Ｐ−ＳｉＯ膜：膜厚１００nm）や、（ｄ）に示す（Ｐ
−ＳｉＯ膜：膜厚３００nm）などのようにＰ−ＳｉＮ膜
でない場合は、Ｇｍの劣化は大きく、素子の信頼性に問
題があることが分かる。Although it is inferior to the case shown in (a) in which only the silicon oxide film (P-SiO) formed by using SiH 4 gas containing no water and no reflow SiO 2 film is used,
When the reflow SiO 2 film is laminated after forming the silicon nitride film (P-SiN film: film thickness 100 nm) of the present invention shown in (b), the deterioration of Gm is small and the influence on the MOS transistor is small. I understand. On the other hand, (C) (P-SiO film: film thickness 100 nm) and (d) (P
It can be seen that when the film is not a P-SiN film (eg, -SiO film: film thickness 300 nm), Gm is greatly deteriorated and there is a problem in device reliability.
【００２６】[0026]
【発明の効果】以上詳述したように、この発明によれ
ば、リフローＳｉＯ2 膜の成膜中に水分（Ｈ2 Ｏ）が発
生し、半導体基板に形成された半導体素子に悪影響を与
えるのを防ぐため水分拡散のブロック層として、リフロ
ーＳｉＯ2 膜の成膜前に半導体基板上及び下層配線上に
窒化珪素膜を形成することにより、リフローＳｉＯ2 膜
の成膜中或いはその後の必要な熱処理中に発生する水分
が半導体基板に形成された半導体素子の信頼性その他に
悪影響をもたらすという弊害を除くことができる層間絶
縁膜構成を改良した多層配線構造を有する半導体装置の
製造方法を提供できる。As described above in detail, according to the present invention, moisture (H 2 O) is generated during the formation of the reflow SiO 2 film, which adversely affects the semiconductor element formed on the semiconductor substrate. As a moisture diffusion blocking layer, a silicon nitride film is formed on the semiconductor substrate and the lower wiring before the reflow SiO 2 film is formed to prevent heat treatment during or after the reflow SiO 2 film is formed. It is possible to provide a method for manufacturing a semiconductor device having a multilayer wiring structure with an improved interlayer insulating film structure, which can eliminate the adverse effect that moisture generated therein adversely affects the reliability and the like of a semiconductor element formed on a semiconductor substrate.
【図１】本発明の半導体装置の製造方法の一工程を示す
断面図。FIG. 1 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device of the present invention.
【図２】図１に示す工程に続く他の工程を示す断面図。FIG. 2 is a cross-sectional view showing another step that follows the step shown in FIG.
【図３】図２に示す工程に続く更に他の工程を示す断面
図。FIG. 3 is a cross-sectional view showing still another step following the step shown in FIG.
【図４】本発明の半導体装置の製造方法に用いられるダ
ブルチャンバー装置の概略構成図。FIG. 4 is a schematic configuration diagram of a double chamber device used in the method for manufacturing a semiconductor device of the present invention.
【図５】本発明に用いられる窒化珪素膜と、異なる水分
拡散ブロック層との特性の違いを示す比較図。FIG. 5 is a comparative diagram showing the difference in characteristics between the silicon nitride film used in the present invention and different moisture diffusion block layers.
１０……半導体基板 １２……下層配線 １３……窒化珪素膜 １４……リフローＳｉＯ2 膜10 ... Semiconductor substrate 12 ... Lower layer wiring 13 ... Silicon nitride film 14 ... Reflow SiO 2 film
Claims (4)
と、前記半導体基板上及び前記下層配線上に窒化珪素膜
を形成する工程と、５Torr以下の真空室内に、前記下層
配線及び窒化珪素膜を形成後の半導体基板を収容し、Ｓ
ｉＨ4 ガスおよびＨ2 Ｏ2 を導入し、−１０℃以上＋１
０℃以下の温度範囲内で互いに反応させることによっ
て、前記半導体基板上にリフロ―形状を呈する酸化珪素
膜を形成する酸化珪素膜形成工程と、よりなる多層配線
構造を有する半導体装置の製造方法。1. A step of forming a lower layer wiring on a semiconductor substrate, a step of forming a silicon nitride film on the semiconductor substrate and the lower layer wiring, and the lower layer wiring and the silicon nitride film in a vacuum chamber of 5 Torr or less. The semiconductor substrate after forming the
Introduce iH 4 gas and H 2 O 2 and -10 ° C or higher +1
A method of manufacturing a semiconductor device having a multi-layer wiring structure, comprising: a step of forming a silicon oxide film having a reflow shape on the semiconductor substrate by reacting with each other within a temperature range of 0 ° C. or less;
チャンバータイプの他の真空室内で前記窒化珪素膜を成
膜後、酸素ガス若しくは亜酸化窒素ガス中で表面処理を
行う工程を更に有する請求項１に記載の多層配線構造を
有する半導体装置の製造方法。2. The step of forming the silicon nitride film further includes the step of performing a surface treatment in oxygen gas or nitrous oxide gas after forming the silicon nitride film in another vacuum chamber of a multi-chamber type. A method of manufacturing a semiconductor device having the multilayer wiring structure according to claim 1.
導体基板上及び前記下層配線上に形成された窒化珪素膜
を前記他の真空室内から取り出し大気に晒す工程を更に
有する請求項１に記載の多層配線構造を有する半導体装
置の製造方法。3. The step of forming the silicon nitride film further comprises the step of taking out the silicon nitride film formed on the semiconductor substrate and on the lower wiring from the other vacuum chamber and exposing it to the atmosphere. A method for manufacturing a semiconductor device having the multilayer wiring structure described.
導体基板上及び前記下層配線上に形成された窒化珪素膜
を前記他の真空室内から取り出し大気に晒す工程と、再
び前記他の真空室内で前記窒化珪素膜を成膜後、酸素ガ
ス若しくは亜酸化窒素ガス中で表面処理を行う工程を更
に有する請求項１に記載の多層配線構造を有する半導体
装置の製造方法。4. The step of forming the silicon nitride film, the step of taking out the silicon nitride film formed on the semiconductor substrate and the lower wiring from the other vacuum chamber and exposing it to the atmosphere, and again the other vacuum. The method for manufacturing a semiconductor device having a multilayer wiring structure according to claim 1, further comprising a step of performing a surface treatment in oxygen gas or nitrous oxide gas after forming the silicon nitride film in a room.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3658996A JPH09232426A (en) | 1996-02-23 | 1996-02-23 | Manufacture of semiconductor device provided with multilayered interconnection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3658996A JPH09232426A (en) | 1996-02-23 | 1996-02-23 | Manufacture of semiconductor device provided with multilayered interconnection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09232426A true JPH09232426A (en) | 1997-09-05 |
Family
ID=12473973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3658996A Pending JPH09232426A (en) | 1996-02-23 | 1996-02-23 | Manufacture of semiconductor device provided with multilayered interconnection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09232426A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7317497B2 (en) | 2002-10-31 | 2008-01-08 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
-
1996
- 1996-02-23 JP JP3658996A patent/JPH09232426A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7317497B2 (en) | 2002-10-31 | 2008-01-08 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
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