JPH09213820A - Manufacture of non-volatile semiconductor memory device - Google Patents
Manufacture of non-volatile semiconductor memory deviceInfo
- Publication number
- JPH09213820A JPH09213820A JP8016395A JP1639596A JPH09213820A JP H09213820 A JPH09213820 A JP H09213820A JP 8016395 A JP8016395 A JP 8016395A JP 1639596 A JP1639596 A JP 1639596A JP H09213820 A JPH09213820 A JP H09213820A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- interlayer insulating
- silicon oxide
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、高信頼の層間絶縁
膜を持ち、電荷保持特性が優れていると同時に書換え信
頼性に優れた不揮発性半導体記憶装置の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a non-volatile semiconductor memory device having a highly reliable interlayer insulating film and having excellent charge retention characteristics and at the same time excellent rewriting reliability.
【０００２】[0002]
【従来の技術】不揮発性半導体記憶装置は、例えば図１
に示す断面構造を有している。ここで、１はシリコン基
板、２はフイールド酸化膜、３は電極、４はトンネル絶
縁膜、５は浮遊ゲート電極、６は層間絶縁膜、７は制御
ゲート電極、８はソース、９はドレイン、１０は絶縁膜
である。この不揮発性半導体記憶装置では、ドレイン９
に３.３Ｖ ，制御ゲート電極７に−７Ｖ，ソース８を開
放、基板１を接地することにより浮遊ゲート電極５に蓄
積した電子をドレイン９側に引き抜いて情報の書込みを
行う。この方法によれば、浮遊ゲート電極５中の電子が
ファウラ・ノルドハイム（Fowler−Nordheim）トンネル
電流(Ｆ−Ｎ電流)によってドレイン９側に引き抜かれ、
同時にドレイン９側から正孔がトンネル絶縁膜４中に注
入される。このように、高電界を印加して電流を流すト
ンネル絶縁膜は結晶のシリコン基板を熱酸化して形成さ
れている。一方、層間絶縁膜は、浮遊ゲート電極を構成
する多結晶シリコン膜を熱酸化するか、あるいは浮遊ゲ
ート電極上に化学気相成長法により堆積することにより
下層の酸化シリコン膜を形成したＳｉＯ2−Ｓｉ3Ｎ4−
ＳｉＯ2 積層膜（以後、ＯＮＯ膜と略）が多く用いられ
ている。2. Description of the Related Art A nonvolatile semiconductor memory device is shown in FIG.
The cross-sectional structure shown in FIG. Here, 1 is a silicon substrate, 2 is a field oxide film, 3 is an electrode, 4 is a tunnel insulating film, 5 is a floating gate electrode, 6 is an interlayer insulating film, 7 is a control gate electrode, 8 is a source, 9 is a drain, Reference numeral 10 is an insulating film. In this nonvolatile semiconductor memory device, the drain 9
To 3.3V, the control gate electrode 7 to -7V, the source 8 is opened, and the substrate 1 is grounded to extract the electrons accumulated in the floating gate electrode 5 to the drain 9 side to write information. According to this method, the electrons in the floating gate electrode 5 are extracted to the drain 9 side by the Fowler-Nordheim tunnel current (FN current),
At the same time, holes are injected into the tunnel insulating film 4 from the drain 9 side. As described above, the tunnel insulating film that applies a high electric field and allows a current to flow is formed by thermally oxidizing a crystalline silicon substrate. On the other hand, the interlayer insulating film is formed by thermally oxidizing the polycrystalline silicon film forming the floating gate electrode or depositing it on the floating gate electrode by chemical vapor deposition to form a lower silicon oxide film, SiO 2 −. Si 3 N 4 −
A SiO 2 laminated film (hereinafter abbreviated as ONO film) is often used.
【０００３】[0003]
【発明が解決しようとする課題】前記従来の不揮発性半
導体記憶装置では、デバイスを縮小し、メモリセルの高
密度化を達成するためには層間絶縁膜を薄膜化しなけれ
ばならず、漏洩電流を低く保ったままＯＮＯ膜の各層を
薄膜化することが必要となる。例えば、ＳｉＯ2換算膜
厚として１５ｎｍの膜厚のＯＮＯ膜では、下層ＳｉＯ2
膜５ｎｍ，Ｓｉ3Ｎ4膜１０ｎｍ，上層ＳｉＯ2 膜５ｎｍ
となっており、ＯＮＯ膜を１５ｎｍから１３ｎｍに薄膜
化する場合には、４ｎｍレベルのＳｉＯ2 膜が必要とな
る。In the conventional nonvolatile semiconductor memory device described above, the interlayer insulating film must be thinned in order to reduce the size of the device and achieve the high density of the memory cells. It is necessary to reduce the thickness of each layer of the ONO film while keeping it low. For example, in the case of an ONO film having a film thickness of 15 nm as the SiO 2 converted film thickness, the lower SiO 2 film
Film 5 nm, Si 3 N 4 film 10 nm, Upper SiO 2 film 5 nm
Therefore, when thinning the ONO film from 15 nm to 13 nm, a 4 nm level SiO 2 film is required.
【０００４】トンネル絶縁膜の信頼性については、文献
「アイ・イー・イー・イー インターナショナル リラ
イアビリティ フィジックス プロシーディングス １
８ページから２３ページ」に開示されているように、層
間絶縁膜の形成工程で９００℃以上の高温での工程があ
ると、トンネル絶縁膜中の電子捕獲準位が増大し、書換
えを繰り返すことによりトンネル絶縁膜中に電子が捕獲
され、書換え時間が長くなるという問題が生じる。ま
た、ＯＮＯ膜中のＳｉ3Ｎ4膜は７７０℃レベルの低温で
形成するが、強い応力を持つためにトンネル絶縁膜に影
響を及ぼす。前記文献に開示されているように、Ｓｉ3
Ｎ4膜の堆積では電子捕獲準位は増加しないものの、書
換え相当の高電界ストレスを印加することによりトンネ
ル絶縁膜の低電界漏洩電流が増大する。高電界ストレス
印加後の低電界漏洩電流の増大は、トンネル絶縁膜の薄
膜化とともに顕著となるため、低電界漏洩電流の低減は
今後のトンネル絶縁膜の薄膜化で最も重要な課題であ
る。Regarding the reliability of the tunnel insulating film, refer to the document "I-E-E International Reliability Physics Proceedings 1".
As disclosed in "Pages 8 to 23", if there is a step at a high temperature of 900 ° C or higher in the step of forming the interlayer insulating film, the electron trap level in the tunnel insulating film increases and rewriting is repeated. As a result, electrons are trapped in the tunnel insulating film, which causes a problem that the rewriting time becomes long. Further, the Si 3 N 4 film in the ONO film is formed at a low temperature of 770 ° C., but it has a strong stress and thus affects the tunnel insulating film. As disclosed in the above document, Si 3
Although the electron trap level does not increase in the deposition of the N 4 film, the low electric field leakage current of the tunnel insulating film increases by applying a high electric field stress equivalent to rewriting. The increase in the low electric field leakage current after the application of the high electric field stress becomes remarkable as the tunnel insulating film becomes thinner, and thus the reduction of the low electric field leakage current is the most important issue in the future thinning of the tunnel insulating film.
【０００５】本発明の目的は、層間絶縁膜自身の漏洩電
流を低く保ったまま、トンネル絶縁膜の信頼性を劣化さ
せない、信頼性の高い不揮発性半導体記憶装置の製造方
法を提供することにある。It is an object of the present invention to provide a highly reliable method for manufacturing a nonvolatile semiconductor memory device which does not deteriorate the reliability of the tunnel insulating film while keeping the leakage current of the interlayer insulating film itself low. .
【０００６】[0006]
【課題を解決するための手段】前記目的は、浮遊ゲート
電極上に酸化シリコン膜を形成後、一酸化窒素を含むガ
ス中、８５０℃以下の温度で酸化シリコン膜を加熱し、
酸化シリコン膜中に窒素を導入して層間絶縁膜とするこ
とにより達成される。The object is to form a silicon oxide film on a floating gate electrode and then heat the silicon oxide film at a temperature of 850 ° C. or lower in a gas containing nitric oxide.
This is achieved by introducing nitrogen into the silicon oxide film to form an interlayer insulating film.
【０００７】層間絶縁膜に単層の酸化シリコン膜を用い
るとＯＮＯ膜と比べ、薄膜化が容易となる。すなわち、
ＯＮＯ膜では今後の薄膜化に対して膜厚４ｎｍレベルの
膜堆積が必要であるが、単層膜を用いれば１３ｎｍレベ
ルの膜堆積を行うことになる。さらに、一酸化窒素によ
り窒素を導入して、酸化シリコン膜の一部を酸窒化シリ
コン膜とすることにより誘電率が高くなり、ＳｉＯ2 換
算膜厚を薄くすることが可能となる。If a single-layer silicon oxide film is used as the interlayer insulating film, it becomes easier to make it thinner than an ONO film. That is,
For the ONO film, it is necessary to deposit a film with a film thickness of 4 nm for future thinning, but if a single layer film is used, a film with a film thickness of 13 nm will be deposited. Further, nitrogen is introduced by nitric oxide and a part of the silicon oxide film is made into a silicon oxynitride film, whereby the dielectric constant is increased and the SiO 2 converted film thickness can be reduced.
【０００８】酸化シリコン膜中に窒素を導入して誘電率
を大きくする方法としては、他にアンモニアガス中で加
熱する方法，亜酸化窒素中で加熱する方法がある。アン
モニアを用いて窒素を導入した場合にはアンモニア中の
水素が窒素と同時に層間絶縁膜中に導入される。これ
は、層間絶縁膜中の電子捕獲準位を増大させ、不揮発性
半導体記憶装置の動作時に電子が層間絶縁膜中に捕獲さ
れ、デバイスのしきい値電圧の変動をもたらす。このた
め、水素を層間絶縁膜中から除去するためにドライ雰囲
気中で加熱して水素を除去するという工程が必要にな
る。一方、亜酸化窒素を用いた場合にはドライ雰囲気中
での加熱となり、かつ亜酸化窒素自身水素を持っていな
いことから層間絶縁膜中に水素に起因した電子捕獲準位
が形成されることはない。ところが、亜酸化窒素は反応
性が低く、多結晶シリコン膜からなる浮遊ゲート電極を
酸窒化するためには９００℃以上の温度が必要となる。
このため、９００℃以上の高温での熱処理によりトンネ
ル絶縁膜が劣化してメモリセルの書換え信頼性が低下す
る。Other methods for increasing the dielectric constant by introducing nitrogen into the silicon oxide film include heating in ammonia gas and heating in nitrous oxide. When nitrogen is introduced using ammonia, hydrogen in ammonia is introduced into the interlayer insulating film at the same time as nitrogen. This increases the electron trap level in the interlayer insulating film, and electrons are trapped in the interlayer insulating film during the operation of the nonvolatile semiconductor memory device, which causes a change in the threshold voltage of the device. Therefore, a step of removing hydrogen by heating in a dry atmosphere is required to remove hydrogen from the interlayer insulating film. On the other hand, when nitrous oxide is used, it is heated in a dry atmosphere, and since nitrous oxide itself does not have hydrogen, an electron trap level due to hydrogen is not formed in the interlayer insulating film. Absent. However, nitrous oxide has low reactivity, and a temperature of 900 ° C. or higher is required for oxynitriding the floating gate electrode made of a polycrystalline silicon film.
Therefore, the tunnel insulating film is deteriorated by the heat treatment at a high temperature of 900 ° C. or higher, and the rewriting reliability of the memory cell is lowered.
【０００９】これらに対し、一酸化窒素を用いた場合に
は水素を持たない雰囲気中での加熱が可能であり、かつ
８５０℃以下の温度で浮遊ゲート電極を構成する多結晶
シリコン膜を窒化することができる。これにより、酸化
シリコン膜中に電子捕獲準位を増大させることなく、誘
電率を大きくすることができ、薄膜化が容易となる。On the other hand, when nitric oxide is used, it can be heated in an atmosphere containing no hydrogen, and the polycrystalline silicon film forming the floating gate electrode is nitrided at a temperature of 850 ° C. or lower. be able to. As a result, the dielectric constant can be increased without increasing the electron trap level in the silicon oxide film, which facilitates thinning.
【００１０】酸化シリコン膜を化学気相成長法で形成す
る場合には、例えば、シリコンの供給源としてモノシラ
ン，ジシラン，テトラエトキシシラン等を用い、酸素の
供給源としては亜酸化窒素，酸素等を用いる。化学気相
成長法で酸化シリコン膜を形成した場合には膜中に水素
が残存するため、熱酸化膜に比べて水素に起因した電子
捕獲準位が多くなる。したがって、水素を含まない雰囲
気中で加熱し、水素を除去する必要がある。水素が離脱
した後にはダングリングボンドが生成されるため、窒素
を導入してダングリングボンドを終端する。これによ
り、漏洩電流を低減できる。When the silicon oxide film is formed by the chemical vapor deposition method, for example, monosilane, disilane, tetraethoxysilane or the like is used as a silicon supply source and nitrous oxide, oxygen or the like is used as an oxygen supply source. To use. When a silicon oxide film is formed by the chemical vapor deposition method, hydrogen remains in the film, so that the number of electron trap levels due to hydrogen is larger than that in the thermal oxide film. Therefore, it is necessary to remove hydrogen by heating in an atmosphere containing no hydrogen. Since dangling bonds are generated after hydrogen is released, nitrogen is introduced to terminate the dangling bonds. Thereby, the leakage current can be reduced.
【００１１】酸化シリコン膜の形成で、酸素の供給源の
ガス量を減少させると、堆積される酸化シリコン膜中の
原子数比Ｓｉ／Ｏが増大する。Ｓｉ／Ｏ比が０.５ より
大きい場合にはシリコンが過剰となり、一酸化窒素を含
むガス中で加熱することにより過剰のシリコンが窒化さ
れる。そこで、一酸化窒素中で熱処理後の絶縁膜中の酸
素と窒素の分布を調べた。In the formation of the silicon oxide film, if the gas amount of the oxygen supply source is reduced, the atomic number ratio Si / O in the deposited silicon oxide film increases. When the Si / O ratio is larger than 0.5, the silicon becomes excessive, and the excess silicon is nitrided by heating in a gas containing nitric oxide. Therefore, the distribution of oxygen and nitrogen in the insulating film after heat treatment in nitric oxide was investigated.
【００１２】従来のシリコン基板を熱酸化した膜を用い
た場合の結果を図４に、Ｓｉ／Ｏの原子数比が０.５ を
越える酸化シリコン膜をシリコン基板上に堆積した場合
について図５に示す。図４から熱酸化膜（Ｓｉ／Ｏの原
子数比が０.５ ）の場合には絶縁膜とシリコン基板との
界面をピークにして界面から２ｎｍ程度の範囲に窒素が
分布すること、図５からＳｉ／Ｏの原子数比が０.５ を
越える場合には絶縁膜とシリコン基板との界面のほか、
絶縁膜中にも窒素が導入され、窒素の極大値が膜中に存
在することがわかる。導入される窒素量の増大に伴い、
誘電率が大きくなるため、ＳｉＯ2 換算膜厚を薄くする
ことができる。FIG. 4 shows the result when a film obtained by thermally oxidizing a conventional silicon substrate is used, and FIG. 5 shows the case where a silicon oxide film having a Si / O atomic ratio exceeding 0.5 is deposited on the silicon substrate. Shown in. As shown in FIG. 4, in the case of a thermal oxide film (Si / O atomic ratio is 0.5), nitrogen is distributed in a range of about 2 nm from the interface with a peak at the interface between the insulating film and the silicon substrate. Therefore, when the atomic ratio of Si / O exceeds 0.5, in addition to the interface between the insulating film and the silicon substrate,
It can be seen that nitrogen is also introduced into the insulating film and the maximum value of nitrogen exists in the film. With the increase in the amount of nitrogen introduced,
Since the dielectric constant increases, the SiO 2 equivalent film thickness can be reduced.
【００１３】Ｓｉ3Ｎ4膜を用いずに、単層酸化シリコン
膜を一酸化窒素を含むガス中で加熱することにより応力
の小さい層間絶縁膜を形成でき、トンネル絶縁膜の低電
界漏洩電流を抑制することができる。By heating the single-layer silicon oxide film in a gas containing nitric oxide without using the Si 3 N 4 film, an interlayer insulating film with a small stress can be formed, and the low electric field leakage current of the tunnel insulating film can be reduced. Can be suppressed.
【００１４】[0014]
（実施例１）次に本発明の実施例を、図１に示した断面
を持つメモリセルを用いて説明する。(Embodiment 1) Next, an embodiment of the present invention will be described using a memory cell having a cross section shown in FIG.
【００１５】シリコン基板１をアンモニアと過酸化水素
を含んだ水溶液中に浸漬した後、フッ酸水溶液中で表面
酸化膜を除去し、これに続いてフィールド酸化膜２を形
成してから、シリコン基板１をパイロジェニック酸化に
より、８５０℃で膜厚９ｎｍのＳｉＯ2 膜を形成し、ト
ンネル絶縁膜４とした。After immersing the silicon substrate 1 in an aqueous solution containing ammonia and hydrogen peroxide, the surface oxide film is removed in a hydrofluoric acid aqueous solution, and subsequently the field oxide film 2 is formed, and then the silicon substrate is formed. 1 was subjected to pyrogenic oxidation to form a SiO 2 film having a film thickness of 9 nm at 850 ° C. and used as a tunnel insulating film 4.
【００１６】トンネル絶縁膜４上に、減圧化学気相成長
法によりモノシランとホスフィンを用いて３×１０20cm
-3のリンを含んだ多結晶シリコン膜を２００ｎｍだけ堆
積し、その後、窒素雰囲気中８００℃で２０分間加熱し
て、浮遊ゲート電極５とした。この後、多結晶シリコン
膜上に減圧化学気相成長法により亜酸化窒素を８００sc
cm，モノシランを２０sccmの流量で流して７５０℃で原
子数比Ｓｉ／Ｏが約０.５ の酸化シリコン膜（膜厚１８
ｎｍ）とした。On the tunnel insulating film 4, 3 × 10 20 cm 2 of monosilane and phosphine are formed by low pressure chemical vapor deposition.
A polycrystalline silicon film containing phosphorus of -3 was deposited to a thickness of 200 nm and then heated at 800 ° C. for 20 minutes in a nitrogen atmosphere to form a floating gate electrode 5. After that, 800 sc of nitrous oxide is deposited on the polycrystalline silicon film by low pressure chemical vapor deposition.
cm, monosilane at a flow rate of 20 sccm, and a silicon oxide film with an atomic ratio Si / O of about 0.5 (thickness 18
nm).
【００１７】これに続いて、窒素で希釈した５％の一酸
化窒素ガスに切り換え、８５０℃で１５分間加熱して、
窒素を酸化シリコン膜中に導入し、層間絶縁膜６とし
た。Following this, switching to 5% nitric oxide gas diluted with nitrogen, heating at 850 ° C. for 15 minutes,
Nitrogen was introduced into the silicon oxide film to form the interlayer insulating film 6.
【００１８】これとは別に、本発明の効果を確認する層
間絶縁膜６を次のようにして形成した。浮遊ゲート電極
５上に減圧化学気相成長法により亜酸化窒素を５００sc
cm，モノシランを２０sccmの流量で流して７５０℃でシ
リコン過剰な酸化シリコン膜（膜厚１８ｎｍ）とした。Separately from this, an interlayer insulating film 6 for confirming the effect of the present invention was formed as follows. Nitrous oxide (500sc) is deposited on the floating gate electrode 5 by low pressure chemical vapor deposition.
cm and monosilane were flown at a flow rate of 20 sccm to form a silicon oxide film (film thickness 18 nm) in excess of silicon at 750 ° C.
【００１９】これに続いて、窒素で希釈した５％の一酸
化窒素ガスに切り換え、８５０℃で１５分間加熱して、
窒素を酸化シリコン膜中に導入し、層間絶縁膜６とし
た。Following this, switching to 5% nitric oxide gas diluted with nitrogen, heating at 850 ° C. for 15 minutes,
Nitrogen was introduced into the silicon oxide film to form the interlayer insulating film 6.
【００２０】参照試料は、以下の２種類のものを作製し
た。The following two kinds of reference samples were prepared.
【００２１】一つは、多結晶シリコン膜を８００℃でド
ライ酸化雰囲気中で加熱し、膜厚５ｎｍのＳｉＯ2 膜を
形成し、減圧化学気相成長法によりＳｉ3Ｎ4膜を７７０
℃で膜厚１３ｎｍ堆積した。続いて、９００℃でＳｉ3
Ｎ4膜をパイロジェニック酸化して膜厚５ｎｍのＳｉＯ
2 膜を形成し、ＳｉＯ2 換算膜厚１５ｎｍのＯＮＯ膜を
もって層間絶縁膜６とした。First, a polycrystalline silicon film is heated at 800 ° C. in a dry oxidizing atmosphere to form a SiO 2 film having a film thickness of 5 nm, and a Si 3 N 4 film is formed by a low pressure chemical vapor deposition method to form a 770 Si 3 N 4 film.
A film thickness of 13 nm was deposited at ° C. Then, at 900 ° C., Si 3
Pyrogenic oxidation of the N 4 film to form a 5 nm thick SiO film
Two films were formed, and an ONO film having a SiO 2 converted film thickness of 15 nm was used as the interlayer insulating film 6.
【００２２】二つ目の層間絶縁膜の参照試料としては、
浮遊ゲート電極を構成する多結晶シリコン膜上に減圧化
学気相成長法でモノシランと亜酸化窒素とを用いて膜厚
５ｎｍのＳｉＯ2 膜を堆積し、８００℃で窒素雰囲気中
で１０分間加熱後、減圧化学気相成長法によりＳｉ3Ｎ4
膜を７７０℃で膜厚１０ｎｍ堆積した。続いて、減圧化
学気相成長法でモノシランと亜酸化窒素とを用いて膜厚
５ｎｍのＳｉＯ2 膜を堆積し、８００℃でパイロジェニ
ック酸化を３０分間行った。これにより、ＳｉＯ2 換算
膜厚１５ｎｍのＯＮＯ膜として層間絶縁膜６とした。As a reference sample for the second interlayer insulating film,
A SiO 2 film having a film thickness of 5 nm was deposited on the polycrystalline silicon film forming the floating gate electrode by low pressure chemical vapor deposition using monosilane and nitrous oxide, and heated at 800 ° C. in a nitrogen atmosphere for 10 minutes. , Si 3 N 4 by low pressure chemical vapor deposition
The film was deposited to a thickness of 10 nm at 770 ° C. Then, a 5 nm-thickness SiO 2 film was deposited using monosilane and nitrous oxide by the reduced pressure chemical vapor deposition method, and pyrogenic oxidation was performed at 800 ° C. for 30 minutes. As a result, the interlayer insulating film 6 was formed as an ONO film having a SiO 2 converted film thickness of 15 nm.
【００２３】以上、４種類の層間絶縁膜６上に減圧化学
気相成長法によりモノシランとホスフィンを用いて３×
１０20cm-3のリンを含んだ多結晶シリコン膜を２００ｎ
ｍだけ堆積し、その後窒素雰囲気中８００℃で２０分間
加熱することにより制御ゲート電極７を形成し、その後
ゲート加工を行ってから、ソース８，ドレイン９を形成
した。更に、硼素とリンとを含んだ酸化シリコン膜を堆
積した後加熱して平坦化した絶縁膜１０を形成した。こ
の後ソース８，ドレイン９上にコンタクト穴を開け、そ
の上に電極３を形成して、図１に示すようなメモリセル
を作製した。As described above, 3 × by using monosilane and phosphine on the four kinds of interlayer insulating films 6 by the low pressure chemical vapor deposition method.
200 n of polycrystalline silicon film containing 10 20 cm -3 of phosphorus
The control gate electrode 7 was formed by depositing only m, and then heating at 800 ° C. for 20 minutes in a nitrogen atmosphere, and after performing gate processing, the source 8 and the drain 9 were formed. Further, a silicon oxide film containing boron and phosphorus was deposited and then heated to form a flattened insulating film 10. After that, contact holes were opened on the source 8 and the drain 9, and the electrodes 3 were formed on the contact holes to fabricate a memory cell as shown in FIG.
【００２４】この構造の不揮発性半導体記憶装置を用い
て書換え特性を評価した。ゲートの全面を用いた浮遊ゲ
ート電極５への電荷の注入（消去）をＦ−Ｎ電流で行
い、浮遊ゲート電極５とドレイン９との間を用いたＦ−
Ｎ電流による電荷の引抜きを書込み動作とした。消去を
行う際には、制御ゲート電極７に＋１２Ｖ，ソース８，
ドレイン９，基板１を０Ｖにしたパルスを印加して、し
きい値電圧を確認しながら消去を行った。書込みを行う
際には、制御ゲート電極７に−７Ｖ，ドレイン９に＋
３.３Ｖ ，ソース８を開放にして、基板１を接地したパ
ルスを印加し、しきい値電圧を確認しながら書込みを行
った。Rewriting characteristics were evaluated using the nonvolatile semiconductor memory device having this structure. Charge injection (erasure) into the floating gate electrode 5 using the entire surface of the gate is performed by an F-N current, and F- using the space between the floating gate electrode 5 and the drain 9.
The write operation was the extraction of charges by the N current. When erasing, + 12V, source 8,
A pulse having 0V applied to the drain 9 and the substrate 1 was applied to erase while confirming the threshold voltage. When writing, the control gate electrode 7 has a voltage of -7 V and the drain 9 has a voltage of +
Writing was performed while applying a pulse of grounding the substrate 1 with the source 8 opened at 3.3 V and checking the threshold voltage.
【００２５】上記のメモリセル特性を、トンネル絶縁膜
４に膜厚９ｎｍのパイロジェニックＳｉＯ2 膜を用いた
メモリセルで、層間絶縁膜６を変えたときの書込み時間
の変動を図６に示す。層間絶縁膜６に単層酸化シリコン
膜を堆積し、一酸化窒素ガス中で加熱した場合には、酸
化シリコン膜の原子数比Ｓｉ／Ｏによらず、ＯＮＯ膜を
用いた場合と比べ、書込み時間の変動が抑えられてい
る。消去特性βについては四つのメモリセルとも差がな
かった。FIG. 6 shows the above-mentioned memory cell characteristics when the interlayer insulating film 6 is changed in a memory cell using a 9 nm-thickness pyrogenic SiO 2 film as the tunnel insulating film 4. When a single-layer silicon oxide film is deposited on the interlayer insulating film 6 and heated in a nitric oxide gas, the writing is performed regardless of the atomic ratio Si / O of the silicon oxide film as compared with the case of using the ONO film. Time fluctuation is suppressed. There is no difference in the erase characteristic β from the four memory cells.
【００２６】一方、電荷保持特性に関しては、１０5 回
書換え後のしきい値電圧の変動を図７に示す。しきい値
電圧の変動量は層間絶縁膜６の種類に依存して、熱酸化
によるＯＮＯ膜，化学気相成長法によるＯＮＯ膜，本発
明による一酸化窒素処理した酸化シリコン膜の順で少な
くなった。電荷保持特性に関しても、層間絶縁膜６に単
層酸化シリコン膜を堆積し、一酸化窒素ガス中で加熱し
た場合には、酸化シリコン膜の原子数比Ｓｉ／Ｏによら
ず、ＯＮＯ膜を用いた場合と比べ、書込み時間の変動が
抑えられている。On the other hand, regarding the charge retention characteristics, FIG. 7 shows the variation of the threshold voltage after rewriting 10 5 times. The fluctuation amount of the threshold voltage decreases depending on the type of the interlayer insulating film 6 in the order of the ONO film by thermal oxidation, the ONO film by the chemical vapor deposition method, and the silicon oxide film treated by nitric oxide according to the present invention. It was Regarding the charge retention characteristics, when a single-layer silicon oxide film is deposited on the interlayer insulating film 6 and heated in a nitric oxide gas, the ONO film is used regardless of the atomic ratio Si / O of the silicon oxide film. The fluctuation of the writing time is suppressed as compared with the case in which the writing time is reduced.
【００２７】（実施例２）次に本発明の実施例を図２に
示した断面を持つキャパシタを用いて説明する。(Embodiment 2) Next, an embodiment of the present invention will be described using a capacitor having a cross section shown in FIG.
【００２８】シリコン基板１１をアンモニアと過酸化水
素を含んだ水溶液中に浸漬した後、フッ酸水溶液中で表
面酸化膜を除去し、これに続いてフィールド酸化膜１２
を形成した。次に、フッ酸水溶液中で洗浄してシリコン
基板１１表面の自然酸化膜を除去後、減圧化学気相成長
法によりモノシランとホスフィンを用いて３×１０20cm
-3のリンを含んだ多結晶シリコン膜を２００ｎｍだけ堆
積し、その後窒素雰囲気中８００℃で２０分間加熱し
て、ドライエッチングにより加工を行って下部電極１３
とした。After immersing the silicon substrate 11 in an aqueous solution containing ammonia and hydrogen peroxide, the surface oxide film is removed in an aqueous hydrofluoric acid solution, and subsequently, the field oxide film 12 is formed.
Was formed. Next, after washing in a hydrofluoric acid aqueous solution to remove the natural oxide film on the surface of the silicon substrate 11, monosilane and phosphine are used to form 3 × 10 20 cm 2 by low pressure chemical vapor deposition.
-3 of phosphorus-containing polycrystalline silicon film is deposited to a thickness of 200 nm, then heated in a nitrogen atmosphere at 800 ° C. for 20 minutes and processed by dry etching to form the lower electrode 13.
And
【００２９】この後、下部電極１３上に減圧化学気相成
長法により亜酸化窒素を８００sccm，モノシランを２０
sccmの流量で流して７５０℃で原子数比Ｓｉ／Ｏが約
０.５の酸化シリコン膜（膜厚１８ｎｍ）とした。Then, 800 sccm of nitrous oxide and 20 monosilane are deposited on the lower electrode 13 by the low pressure chemical vapor deposition method.
A silicon oxide film (film thickness 18 nm) having an atomic ratio Si / O of about 0.5 was formed at 750 ° C. by flowing at a flow rate of sccm.
【００３０】これに続いて、アルゴンで希釈した１０％
の一酸化窒素ガスに切り換え、８５０℃で１５分間加熱
して、窒素を酸化シリコン膜中に導入し、絶縁膜１４と
した。This is followed by a 10% dilution with argon.
Nitrogen oxide gas was switched to and heated at 850 ° C. for 15 minutes to introduce nitrogen into the silicon oxide film to form the insulating film 14.
【００３１】この他、本発明の効果を確認する絶縁膜の
形成方法としては、下部電極１３上に減圧化学気相成長
法により亜酸化窒素を５００sccm，モノシランを２０sc
cmの流量で流して７５０℃でシリコン過剰の酸化シリコ
ン膜（膜厚１８ｎｍ）を形成した。これに続いて、アル
ゴンで希釈した１０％の一酸化窒素ガスに切り換え、８
５０℃で１５分間加熱して、窒素を酸化シリコン膜中に
導入し、絶縁膜１４とした。In addition, as a method of forming an insulating film for confirming the effects of the present invention, 500 sccm of nitrous oxide and 20 sc of monosilane are formed on the lower electrode 13 by low pressure chemical vapor deposition.
A silicon excess silicon oxide film (film thickness 18 nm) was formed at 750 ° C. by flowing at a flow rate of cm. Following this, switch to 10% nitric oxide gas diluted with argon,
After heating at 50 ° C. for 15 minutes, nitrogen was introduced into the silicon oxide film to form the insulating film 14.
【００３２】参照試料としては、以下の３種類のものを
作製した。As reference samples, the following three types were prepared.
【００３３】一つは、下部電極１３上に減圧化学気相成
長法により亜酸化窒素を８００sccm，モノシランを２０
sccmの流量で流して７５０℃で原子数比Ｓｉ／Ｏが約
０.５の酸化シリコン膜（膜厚１８ｎｍ）とした。これ
に続いて、窒素ガスに切り換え、８５０℃で３０分間加
熱して、絶縁膜１４とした。One is 800 sccm of nitrous oxide and 20 monosilane on the lower electrode 13 by the low pressure chemical vapor deposition method.
A silicon oxide film (film thickness 18 nm) having an atomic ratio Si / O of about 0.5 was formed at 750 ° C. by flowing at a flow rate of sccm. Following this, the gas was switched to nitrogen gas and heated at 850 ° C. for 30 minutes to form the insulating film 14.
【００３４】二つめは、下部電極１３を構成する多結晶
シリコン膜を８００℃でドライ酸化雰囲気中で加熱し、
膜厚５ｎｍのＳｉＯ2 膜を形成し、減圧化学気相成長法
によりＳｉ3Ｎ4膜を７７０℃で膜厚１３ｎｍ堆積した。
続いて、９００℃でＳｉ3Ｎ4膜をパイロジェニック酸化
して膜厚５ｎｍのＳｉＯ2 膜を形成し、ＳｉＯ2 換算膜
厚１５ｎｍのＯＮＯ膜をもって絶縁膜１４とした。Second, the polycrystalline silicon film forming the lower electrode 13 is heated at 800 ° C. in a dry oxidizing atmosphere,
A SiO 2 film having a film thickness of 5 nm was formed, and a Si 3 N 4 film was deposited at a film thickness of 13 nm at 770 ° C. by the low pressure chemical vapor deposition method.
Subsequently, the Si 3 N 4 film was pyrogenically oxidized at 900 ° C. to form a SiO 2 film having a film thickness of 5 nm, and an ONO film having a SiO 2 converted film thickness of 15 nm was used as the insulating film 14.
【００３５】三つめの絶縁膜１４の参照試料としては、
下部電極１３を構成する多結晶シリコン膜上に減圧化学
気相成長法でモノシランと亜酸化窒素とを用いて膜厚５
ｎｍのＳｉＯ2 膜を堆積し、８００℃で窒素雰囲気中で
１０分間加熱後、減圧化学気相成長法によりＳｉ3Ｎ4膜
を７７０℃で膜厚１０ｎｍ堆積した。続いて、減圧化学
気相成長法でモノシランと亜酸化窒素とを用いて膜厚５
ｎｍのＳｉＯ2 膜を堆積し、８００℃でパイロジェニッ
ク酸化を３０分間行った。これにより、ＳiＯ2換算膜厚
１５ｎｍのＯＮＯ膜として絶縁膜１４とした。As a reference sample for the third insulating film 14,
A film thickness of 5 is formed on the polycrystalline silicon film forming the lower electrode 13 by using low pressure chemical vapor deposition using monosilane and nitrous oxide.
nm SiO 2 film was deposited and heated at 800 ° C. in a nitrogen atmosphere for 10 minutes, and then a Si 3 N 4 film was deposited at 770 ° C. to a film thickness of 10 nm by a low pressure chemical vapor deposition method. Then, a film thickness of 5 is obtained by using monosilane and nitrous oxide by a reduced pressure chemical vapor deposition method.
nm SiO 2 film was deposited and pyrogenic oxidation was performed at 800 ° C. for 30 minutes. As a result, the insulating film 14 was formed as an ONO film having a SiO 2 equivalent film thickness of 15 nm.
【００３６】以上、５種類の絶縁膜１４上に減圧化学気
相成長法によりモノシランとホスフィンを用いてリンを
含んだ多結晶シリコン膜を２００ｎｍだけ堆積し、その
後窒素雰囲気中８００℃で２０分間加熱した。続いて、
ドライエッチングによりゲート加工を行って上部電極１
５を形成し、図２に示すようなキャパシタを作製した。As described above, a polycrystalline silicon film containing phosphorus is deposited to a thickness of 200 nm using monosilane and phosphine on the five types of insulating films 14 by low pressure chemical vapor deposition, and then heated in a nitrogen atmosphere at 800 ° C. for 20 minutes. did. continue,
Gate processing is performed by dry etching and the upper electrode 1
5 was formed to produce a capacitor as shown in FIG.
【００３７】この構造のキャパシタを用いて電流−電圧
特性を評価した。単層の酸化シリコン膜を用いた場合に
は、ＯＮＯ膜を用いた場合と比べ、Fowler−Nordheimト
ンネリングによって電流が流れるために図８に示すよう
に電界に対する電流密度の変化が急峻になる。一酸化窒
素を用いて窒素を導入することにより高電界での電流の
低下が見られた。計測装置の限界により、図８に示した
１０-12Ａ／cm2までしか測定できないが、図１に示す断
面を持つメモリセルの電荷保持特性で重要な１〜２ＭＶ
／cmの電界で十分低い漏洩電流になっていると考えられ
る。すなわち、化学気相成長法により堆積した酸化シリ
コン膜を一酸化窒素中で加熱した膜でも、不揮発性半導
体装置の層間絶縁膜，ＯＮＯ膜と遜色の無い電流−電圧
特性を示すことが分かった。The current-voltage characteristics were evaluated using the capacitor having this structure. When a single-layer silicon oxide film is used, a current flows due to Fowler-Nordheim tunneling as compared with the case where an ONO film is used, so that the current density changes steeply with respect to the electric field as shown in FIG. By introducing nitrogen using nitric oxide, a decrease in current in a high electric field was observed. Due to the limitation of the measuring device, it is possible to measure only up to 10 −12 A / cm 2 shown in FIG. 8, but 1-2 MV which is important for the charge retention characteristic of the memory cell having the cross section shown in FIG.
It is considered that the leakage current is sufficiently low with an electric field of / cm. That is, it was found that even a film obtained by heating a silicon oxide film deposited by the chemical vapor deposition method in nitric oxide exhibits current-voltage characteristics comparable to those of the interlayer insulating film and the ONO film of the nonvolatile semiconductor device.
【００３８】（実施例３）次に本発明の実施例を、図３
に示す断面を持つＭＯＳキャパシタを用いて説明する。(Embodiment 3) Next, an embodiment of the present invention will be described with reference to FIG.
Description will be made using a MOS capacitor having a cross section shown in FIG.
【００３９】シリコン基板４１をアンモニアと過酸化水
素を含んだ水溶液中に浸漬した後、フッ酸水溶液中で表
面酸化膜を除去し、これに続いてフィールド酸化膜４２
を形成してから、シリコン基板４１をパイロジェニック
酸化により、８５０℃で膜厚９ｎｍのＳｉＯ2 膜を形成
し、トンネル絶縁膜４３とした。トンネル絶縁膜４３上
に、減圧化学気相成長法によりモノシランとホスフィン
を用いて３×１０20cm-3のリンを含んだ多結晶シリコン
膜を２００ｎｍだけ堆積し、その後窒素雰囲気中８００
℃で２０分間加熱して、ゲート電極４４とした。この
後、多結晶シリコン膜上に減圧化学気相成長法により亜
酸化窒素を８００sccm，モノシランを２０sccmの流量で
流して７５０℃で原子数比Ｓｉ／Ｏが約０.５ の酸化シ
リコン膜（膜厚１８ｎｍ）とした。After immersing the silicon substrate 41 in an aqueous solution containing ammonia and hydrogen peroxide, the surface oxide film is removed in a hydrofluoric acid aqueous solution, and subsequently, the field oxide film 42.
Then, the silicon substrate 41 was pyrogenically oxidized to form a SiO 2 film having a film thickness of 9 nm at 850 ° C., which was used as a tunnel insulating film 43. On the tunnel insulating film 43, a polycrystalline silicon film containing phosphorus of 3 × 10 20 cm −3 is deposited to a thickness of 200 nm using monosilane and phosphine by low pressure chemical vapor deposition, and then 800 nm in a nitrogen atmosphere.
The gate electrode 44 was obtained by heating at 0 ° C. for 20 minutes. After that, nitrous oxide is flown at a flow rate of 800 sccm and monosilane at a flow rate of 20 sccm on the polycrystalline silicon film by a low pressure chemical vapor deposition method to give a silicon oxide film (film ratio of Si / O of about 0.5 at 750 ° C.). The thickness was 18 nm).
【００４０】これに続いて、窒素で希釈した５％の一酸
化窒素ガスに切り換え、２０分間加熱して、窒素を酸化
シリコン膜中に導入し、ゲート電極上の絶縁膜４５とし
た。Subsequently, the gas was switched to 5% nitric oxide gas diluted with nitrogen and heated for 20 minutes to introduce nitrogen into the silicon oxide film to form an insulating film 45 on the gate electrode.
【００４１】参照試料としては、以下の３種類のものを
作製した。The following three kinds of samples were prepared as reference samples.
【００４２】一つは、多結晶シリコン膜上に減圧化学気
相成長法により亜酸化窒素を８００sccm，モノシランを
２０sccmの流量で流して７５０℃で原子数比Ｓｉ／Ｏが
約０.５ の酸化シリコン膜（膜厚１８ｎｍ）とした。こ
れに続いて、窒素ガスに切り換え、８００℃で３０分間
加熱して、ゲート電極上の絶縁膜４５とした。One is to oxidize nitrous oxide at a flow rate of 800 sccm and monosilane at a flow rate of 20 sccm on a polycrystalline silicon film at a flow rate of 800 sccm and an atomic ratio Si / O of about 0.5 at 750 ° C. It was a silicon film (film thickness 18 nm). Subsequently, the atmosphere was changed to nitrogen gas and heated at 800 ° C. for 30 minutes to form an insulating film 45 on the gate electrode.
【００４３】二つめの電極上絶縁膜４５の参照試料とし
ては、多結晶シリコン膜を８００℃でドライ酸化雰囲気
中で加熱し、膜厚５ｎｍのＳｉＯ2 膜を形成し、減圧化
学気相成長法によりＳｉ3Ｎ4膜を７７０℃で膜厚１３ｎ
ｍ堆積した。続いて、９００℃でＳｉ3Ｎ4膜をパイロジ
ェニック酸化して膜厚５ｎｍのＳｉＯ2 膜を形成し、Ｓ
ｉＯ2 換算膜厚１５ｎｍのＯＮＯ膜をもって電極上絶縁
膜４５とした。As a reference sample for the second insulating film 45 on the electrode, a polycrystalline silicon film is heated at 800 ° C. in a dry oxidizing atmosphere to form a SiO 2 film having a film thickness of 5 nm, and the low pressure chemical vapor deposition method is used. The Si 3 N 4 film to a film thickness of 13n at 770 ° C.
m. Then, the Si 3 N 4 film is pyrogenically oxidized at 900 ° C. to form a 5 nm thick SiO 2 film.
An ONO film having a film thickness of 15 nm in terms of io 2 was used as the on-electrode insulating film 45.
【００４４】三つめのゲート電極上絶縁膜４５の参照試
料としては、多結晶シリコン浮遊ゲート電極を構成する
多結晶シリコン膜上に減圧化学気相成長法でモノシラン
と亜酸化窒素とを用いて膜厚５ｎｍのＳｉＯ2 膜を堆積
し、８００℃で窒素雰囲気中で１０分間加熱後、減圧化
学気相成長法によりＳｉ3Ｎ4膜を７７０℃で膜厚１０ｎ
ｍ堆積した。続いて、減圧化学気相成長法でモノシラン
と亜酸化窒素とを用いて膜厚５ｎｍのＳｉＯ2 膜を堆積
し、８００℃でパイロジェニック酸化を３０分間行っ
た。これにより、ＳｉＯ2 換算膜厚１５ｎｍのＯＮＯ膜
として電極上絶縁膜４５とした。As a reference sample of the third insulating film 45 on the gate electrode, a film of monocrystalline silicon and nitrous oxide was formed on the polycrystalline silicon film constituting the polycrystalline silicon floating gate electrode by the low pressure chemical vapor deposition method. A 5 nm thick SiO 2 film is deposited, heated at 800 ° C. in a nitrogen atmosphere for 10 minutes, and then a Si 3 N 4 film is formed at a temperature of 770 ° C. and a thickness of 10 n by a low pressure chemical vapor deposition method.
m. Then, a 5 nm-thickness SiO 2 film was deposited using monosilane and nitrous oxide by the reduced pressure chemical vapor deposition method, and pyrogenic oxidation was performed at 800 ° C. for 30 minutes. As a result, an on-electrode insulating film 45 was formed as an ONO film having a SiO 2 equivalent film thickness of 15 nm.
【００４５】以上、４種類の電極上絶縁膜４５をドライ
エッチングで加工して針当て用のコンタクト穴を形成
し、図３に示すようなＭＯＳキャパシタを作成した。こ
の構造のＭＯＳキャパシタを用いて、高電界ストレスに
よるトンネル絶縁膜４３の特性変動を評価した。As described above, the four kinds of insulating films 45 on the electrode were processed by dry etching to form contact holes for needle contact, and a MOS capacitor as shown in FIG. 3 was prepared. Using the MOS capacitor having this structure, the characteristic variation of the tunnel insulating film 43 due to high electric field stress was evaluated.
【００４６】図９に一定電流ストレス印加時(ゲート負
電圧，１０ｍＡ／cm2 )のゲート電圧の変動を示す。ス
トレス印加初期の正孔の捕獲によるゲート電圧の低下
は、どの場合にも違いが無かった。これに対し、電子の
捕獲量は熱酸化で形成したＯＮＯ膜，化学気相成長（Ｃ
ＶＤ）法で形成したＯＮＯ膜，本発明の順で小さくなっ
た。FIG. 9 shows the fluctuation of the gate voltage when a constant current stress is applied (negative gate voltage, 10 mA / cm 2 ). There was no difference in the reduction of the gate voltage due to the trapping of holes at the initial stage of stress application in any case. On the other hand, the amount of captured electrons is the ONO film formed by thermal oxidation, the chemical vapor deposition (C
The ONO film formed by the VD method became smaller in the order of the present invention.
【００４７】また、同じ定電流ストレス印加後の６ＭＶ
／cmにおける漏洩電流を図１０に示す。漏洩電流値は、
熱酸化で形成したＯＮＯ膜，化学気相成長（ＣＶＤ）法
で形成したＯＮＯ膜，本発明の順で小さくなった。スト
レス印加後の電子の捕獲量，低電界漏洩電流ともに、電
極上絶縁膜を酸化シリコン膜で形成した場合には窒素中
で加熱したか、一酸化窒素中で加熱したかによらず、同
じであった。すなわち、化学気相成長法により酸化シリ
コン膜を堆積して電極上絶縁膜を形成することにより、
トンネル絶縁膜に及ぼす影響を低減することができる。
これは、メモリセルで書換えを繰り返すことによる書込
み時間の増大としきい値電圧の変動とが抑制されること
と対応していると考えられる。6 MV after applying the same constant current stress
The leakage current at / cm is shown in FIG. The leakage current value is
The ONO film formed by thermal oxidation, the ONO film formed by the chemical vapor deposition (CVD) method, and the ONO film formed in the order of the present invention became smaller. The amount of trapped electrons after stress application and the low electric field leakage current are the same regardless of whether heating is performed in nitrogen or nitric oxide when the insulating film on the electrode is formed of a silicon oxide film. there were. That is, by depositing a silicon oxide film by a chemical vapor deposition method to form an insulating film on the electrode,
The influence on the tunnel insulating film can be reduced.
This is considered to correspond to the increase of the write time and the fluctuation of the threshold voltage which are caused by the repeated rewriting in the memory cell.
【００４８】[0048]
【発明の効果】本発明によれば、高電界ストレスによる
トンネル絶縁膜の電子捕獲準位，低電界漏洩電流を抑制
することができ、書込み時間の増大が起こらず、電荷保
持特性の良好な不揮発性半導体記憶装置の製造方法を提
供することができる。According to the present invention, the electron trap level of the tunnel insulating film and the low electric field leakage current due to the high electric field stress can be suppressed, the writing time does not increase, and the nonvolatile memory having a good charge retention characteristic is obtained. It is possible to provide a method for manufacturing a conductive semiconductor memory device.
【図１】不揮発性半導体記憶装置の断面図FIG. 1 is a cross-sectional view of a nonvolatile semiconductor memory device.
【図２】上部電極，下部電極とも多結晶シリコン膜で形
成したキャパシタの断面図。FIG. 2 is a cross-sectional view of a capacitor in which both an upper electrode and a lower electrode are formed of a polycrystalline silicon film.
【図３】ＭＯＳキャパシタの断面図。FIG. 3 is a sectional view of a MOS capacitor.
【図４】従来技術によって亜酸化窒素を用いて熱酸化膜
中に窒素を導入した膜の二次イオン質量分析の結果の説
明図。FIG. 4 is an explanatory diagram of a result of secondary ion mass spectrometry of a film in which nitrogen is introduced into a thermal oxide film by using nitrous oxide according to a conventional technique.
【図５】シリコン過剰の酸化シリコン膜を亜酸化窒素処
理した膜の二次イオン質量分析結果の説明図。FIG. 5 is an explanatory diagram of secondary ion mass spectrometry results of a film obtained by treating a silicon oxide film with excess silicon with nitrous oxide.
【図６】実施例１における不揮発性半導体記憶装置の書
込み特性図。FIG. 6 is a write characteristic diagram of the nonvolatile semiconductor memory device according to the first embodiment.
【図７】実施例１における不揮発性半導体記憶装置の電
荷保持特性の改善効果を示す説明図。FIG. 7 is an explanatory diagram showing the effect of improving the charge retention characteristics of the nonvolatile semiconductor memory device according to the first embodiment.
【図８】実施例２におけるキャパシタの電流−電圧特性
の改善効果を示す説明図。FIG. 8 is an explanatory diagram showing the effect of improving the current-voltage characteristic of the capacitor in the second embodiment.
【図９】実施例３におけるＭＯＳキャパシタのトンネル
絶縁膜のゲート電圧変動の改善効果を示す説明図。FIG. 9 is an explanatory diagram showing the effect of improving the gate voltage fluctuation of the tunnel insulating film of the MOS capacitor according to the third embodiment.
【図１０】実施例３におけるＭＯＳキャパシタのトンネ
ル絶縁膜の低電界漏洩電流の改善効果を示す説明図。FIG. 10 is an explanatory diagram showing the effect of improving the low electric field leakage current of the tunnel insulating film of the MOS capacitor according to the third embodiment.
１…シリコン基板、２…フィールド酸化膜、３…電極、
４…トンネル絶縁膜、５…浮遊ゲート電極、６…層間絶
縁膜、７…制御ゲート電極、８…ソース、９…ドレイ
ン、１０…絶縁膜。1 ... Silicon substrate, 2 ... Field oxide film, 3 ... Electrode,
4 ... Tunnel insulating film, 5 ... Floating gate electrode, 6 ... Interlayer insulating film, 7 ... Control gate electrode, 8 ... Source, 9 ... Drain, 10 ... Insulating film.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小林 孝 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 片山 敦子 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Takashi Kobayashi 1-280 Higashi Koikeku, Kokubunji City, Tokyo Metropolitan Institute of Hitachi, Ltd. (72) Atsuko Katayama 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Center
Claims (8)
絶縁膜を介して設けられた浮遊ゲート電極と、前記浮遊
ゲート電極上に少なくとも一部分が積層する形で層間絶
縁膜を介して設けられた制御ゲート電極と、前記半導体
基板内に互いに分離して設けられた第２導電型のソー
ス，ドレイン領域を備えた電気的に書換え可能な不揮発
性半導体記憶装置の製造方法において、酸化シリコン膜
を形成後一酸化窒素を含むガス中で加熱することにより
酸窒化シリコン膜層を含む層間絶縁膜を持つことを特徴
とする不揮発性半導体記憶装置の製造方法。1. A floating gate electrode provided on a semiconductor substrate having a first conductivity type via a tunnel insulating film, and at least a part of the floating gate electrode laminated on the floating gate electrode via an interlayer insulating film. In a method of manufacturing an electrically rewritable nonvolatile semiconductor memory device including a control gate electrode and a source / drain region of a second conductivity type provided separately from each other in the semiconductor substrate, a silicon oxide film is formed. A method of manufacturing a non-volatile semiconductor memory device, which comprises having an interlayer insulating film including a silicon oxynitride film layer by heating in a gas containing nitric oxide.
シリコン膜を一酸化窒素を含むガス中で加熱してできる
単層膜からなる不揮発性半導体記憶装置の製造方法。2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the interlayer insulating film is a single layer film formed by heating a silicon oxide film in a gas containing nitric oxide.
膜が酸化シリコン膜を窒素、あるいはアルゴンで希釈し
た一酸化窒素ガス中で加熱してできる単層膜からなる不
揮発性半導体記憶装置の製造方法。3. The non-volatile semiconductor memory device according to claim 1, wherein the interlayer insulating film is a single layer film formed by heating a silicon oxide film in nitrogen monoxide gas diluted with nitrogen or argon. Method.
素を含むガス中での加熱温度が850℃以下である不揮発
性半導体記憶装置の製造方法。4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein a heating temperature in a gas containing nitric oxide is 850 ° C. or lower.
酸化シリコン膜を化学気相成長法で形成する不揮発性半
導体記憶装置の製造方法。5. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, 2, 3, or 4, wherein the silicon oxide film is formed by a chemical vapor deposition method.
前記酸化シリコン膜の原子数比Ｓｉ／Ｏが０.５ より大
きい不揮発性半導体記憶装置の製造方法。6. The method of claim 1, 2, 3, 4, or 5,
A method for manufacturing a nonvolatile semiconductor memory device, wherein the atomic ratio Si / O of the silicon oxide film is larger than 0.5.
層間絶縁膜が浮遊ゲート電極と層間絶縁膜との界面に窒
素の分布の最大値を持ち、かつ層間絶縁膜中の水素濃度
が０.５％ 以下である不揮発性半導体記憶装置の製造方
法。7. The interlayer insulating film according to claim 2, 3, 4, or 5, wherein the interlayer insulating film has a maximum value of nitrogen distribution at the interface between the floating gate electrode and the interlayer insulating film, and the hydrogen concentration in the interlayer insulating film is A method for manufacturing a nonvolatile semiconductor memory device, which is 0.5% or less.
前記層間絶縁膜が浮遊ゲート電極と層間絶縁膜との界面
と層間絶縁膜中の２ケ所に窒素の分布の極大値を持ち、
かつ層間絶縁膜中の水素濃度が０.５ ％以下である不揮
発性半導体記憶装置の製造方法。8. The method according to claim 2, 3, 4, 5, or 6,
The interlayer insulating film has a maximum value of nitrogen distribution at the interface between the floating gate electrode and the interlayer insulating film and at two places in the interlayer insulating film,
A method for manufacturing a non-volatile semiconductor memory device having a hydrogen concentration of 0.5% or less in the interlayer insulating film.
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| JP01639596A JP3802945B2 (en) | 1996-02-01 | 1996-02-01 | Method for manufacturing nonvolatile semiconductor memory device |
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| WO2001069673A1 (en) * | 2000-03-13 | 2001-09-20 | Tadahiro Ohmi | Flash memory device and method for manufacturing the same, and method for forming dielectric film |
| JP2002261097A (en) * | 2000-12-28 | 2002-09-13 | Tadahiro Omi | Dielectric film and its formation method, semiconductor device, non-volatile semiconductor memory device and manufacturing method of semiconductor device |
| JP2007527610A (en) * | 2003-07-07 | 2007-09-27 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Method for controlling the characteristics and characteristics of a gate insulating layer based on electrical test data, and system for implementing the same |
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1996
- 1996-02-01 JP JP01639596A patent/JP3802945B2/en not_active Expired - Fee Related
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| WO2001069673A1 (en) * | 2000-03-13 | 2001-09-20 | Tadahiro Ohmi | Flash memory device and method for manufacturing the same, and method for forming dielectric film |
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