JPH09199950A - Protection circuit for amplifier - Google Patents

Protection circuit for amplifier

Info

Publication number
JPH09199950A
JPH09199950A JP8007178A JP717896A JPH09199950A JP H09199950 A JPH09199950 A JP H09199950A JP 8007178 A JP8007178 A JP 8007178A JP 717896 A JP717896 A JP 717896A JP H09199950 A JPH09199950 A JP H09199950A
Authority
JP
Japan
Prior art keywords
drain current
power amplifier
signal
drain
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8007178A
Other languages
Japanese (ja)
Inventor
Manabu Hosoya
学 細谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP8007178A priority Critical patent/JPH09199950A/en
Publication of JPH09199950A publication Critical patent/JPH09199950A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

PROBLEM TO BE SOLVED: To protect a power amplifier consisting of a FET from being destroyed due to an increased drain current caused by an increase in an input signal level or the like. SOLUTION: When a signal level from a terminal 2 is increased and a drain current of a power amplifier 1 is increased, a drain current detection section 5 detects an increase in the drain current based on a voltage drop across a resistor 4, a gain voltage control section 6 controls a gate voltage of the power amplifier 1 via a loop filter 7 to suppress the increase in the drain current. In the case that the drain current is increased regardless of the control of the gate voltage control section 6 and the signal level from the drain current detection section 5 is larger than a reference voltage 9, an output signal level from a comparator 8 goes to 'H' and the signal is fed to a switch circuit 3 via a latch circuit 10 to switch off the circuit 3. The latch circuit 10 is reset by a required reset signal 11.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は電界効果トランジスタ
（ＦＥＴ）を用いた電力増幅器の過電流保護回路に係
り、入力信号レベルの増加等でドレイン電流が増大し、
ＦＥＴが破壊に至るのを未然に防止するものに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overcurrent protection circuit for a power amplifier using a field effect transistor (FET), in which the drain current increases as the input signal level increases,
The present invention relates to a device that prevents a FET from being destroyed.

【０００２】[0002]

【従来の技術】無線通信装置の出力段等に用いる電力増
幅器をＦＥＴを用いて構成する場合、周囲温度の低下等
で前段の増幅器の出力信号レベルが増加し、あるいはノ
イズの混入により電力増幅器の入力信号レベルが過大に
なり、これによりドレイン電流が増大し、破壊に至る場
合がある。また、電力増幅器のゲート電圧を所要の正電
圧電源から負電圧を生成し、適宜の抵抗器により所要の
電圧に分圧して印加する場合、この負電圧を生成する回
路に異常（故障等）が生じた場合にゲート電圧が０Ｖと
なり、過剰ドレイン電流が流れ、電力増幅器が破壊する
という問題がある。2. Description of the Related Art When a power amplifier used in an output stage of a wireless communication device is constructed by using FETs, the output signal level of the amplifier in the preceding stage is increased due to a decrease in ambient temperature or the like, or noise is mixed in the power amplifier to cause a problem. The input signal level becomes excessive, which increases the drain current, which may lead to breakdown. In addition, when the gate voltage of the power amplifier is generated as a negative voltage from a required positive voltage power source and divided by a suitable resistor to be applied to the required voltage, an abnormality (fault, etc.) occurs in the circuit that generates this negative voltage. If it occurs, the gate voltage becomes 0 V, an excessive drain current flows, and the power amplifier is destroyed.

【０００３】[0003]

【発明が解決しようとする課題】本発明はこのような点
に鑑み、電力増幅器のドレイン電流を検出し、ドレイン
電流値に応じて電力増幅器のゲート電圧を制御し、ある
いはドレイン電流が所要値以上に増大した場合にドレイ
ン電源を遮断し、電力増幅器の破壊を未然に防ぐことに
ある。In view of the above, the present invention detects the drain current of the power amplifier and controls the gate voltage of the power amplifier according to the drain current value, or the drain current is equal to or more than a required value. When the power supply voltage increases, the drain power supply is shut off to prevent damage to the power amplifier.

【０００４】[0004]

【課題を解決するための手段】本発明は上述の課題を解
決するため、ＦＥＴを用いた電力増幅器のドレイン端子
およびドレイン電源の間に介挿した抵抗器と、抵抗器の
降下電圧に基づいて電力増幅器のドレイン電流を検出す
るドレイン電流検出部と、ドレイン電流検出部よりの信
号に基づいて電力増幅器のゲート電圧を制御し、ドレイ
ン電流の増加を抑止するゲート電圧制御部とを設け、あ
るいは、前記ドレイン電流検出部よりの信号を所要の基
準電圧と比較し、基準電圧より大きい場合に信号を出力
する比較器と、比較器よりの信号をラッチするラッチ回
路と、前記抵抗器と直列に介挿されラッチ回路よりの信
号で開放されるスイッチ回路とを設けてなる増幅器の保
護回路を提供するものである。In order to solve the above-mentioned problems, the present invention is based on a resistor inserted between a drain terminal and a drain power source of a power amplifier using an FET and a voltage drop of the resistor. A drain current detection unit that detects the drain current of the power amplifier, and a gate voltage control unit that controls the gate voltage of the power amplifier based on a signal from the drain current detection unit and suppresses an increase in the drain current, or A comparator that compares the signal from the drain current detection unit with a required reference voltage and outputs a signal when it is higher than the reference voltage, a latch circuit that latches the signal from the comparator, and a resistor connected in series with the resistor. The present invention provides a protection circuit for an amplifier, which is provided with a switch circuit which is inserted and opened by a signal from a latch circuit.

【０００５】[0005]

【作用】以上のように構成したので、本発明による増幅
器の保護回路においては、周囲温度の低下等で前段の増
幅器の出力信号レベルが増加し、あるいはノイズの混入
により電力増幅器の入力信号レベルが増加し、これによ
ってドレイン電流が増加した場合、ドレイン電流検出部
よりの信号に基づいて電力増幅器のゲート電圧を制御
し、ドレイン電流の増加を抑止し、これにより電力増幅
器を破壊から保護する。あるいは、ゲート電圧（負電
圧）を所要の正電圧電源から生成する場合、負電圧生成
回路に異常が生じ、ゲート電圧が０Ｖになり、ドレイン
電流が増大して所要の基準レベル以上になった場合、ド
レイン電源に介挿されているスイッチ回路を開放し、ド
レイン電源を遮断する。With the above construction, in the amplifier protection circuit according to the present invention, the output signal level of the amplifier at the preceding stage increases due to a decrease in ambient temperature or the input signal level of the power amplifier is increased due to the inclusion of noise. When the drain current increases due to the increase, the gate voltage of the power amplifier is controlled based on the signal from the drain current detector to suppress the increase of the drain current, thereby protecting the power amplifier from breakdown. Alternatively, when the gate voltage (negative voltage) is generated from a required positive voltage power source, an abnormality occurs in the negative voltage generation circuit, the gate voltage becomes 0 V, and the drain current increases and becomes equal to or higher than the required reference level. , The switch circuit inserted in the drain power supply is opened, and the drain power supply is shut off.

【０００６】[0006]

【実施例】以下、図面に基づいて本発明による増幅器の
保護回路の実施例を詳細に説明する。図１は本発明によ
る増幅器の保護回路の一実施例の要部ブロック図であ
る。図において、１は電力増幅器（ＰＡ）で、ＦＥＴで
構成され、端子２よりの信号を電力増幅するもので、例
えば、約2.4GHzで約200mW の高周波電力を出力する無線
通信装置の終段回路である。３はスイッチ回路、４は抵
抗器で、スイッチ回路３および抵抗器４はドレイン電源
Ｖddおよび電力増幅器１のドレイン端子Ｄの間に直列に
接続され、スイッチ回路３は通常オンしている。抵抗器
４は電力増幅器１のドレイン電流（Ｉd ）を検出するた
めのもので、電力増幅器１に必要なドレイン電圧の供給
に支障を生じないように充分に小さい値に設定する。５
はドレイン電流検出部で、抵抗器４の降下電圧に基づい
て電力増幅器１のドレイン電流（Ｉd ）を検出する。６
はゲート電圧制御部で、ドレイン電流検出部５よりの信
号に基づいて電力増幅器１のゲート電圧（Ｖgs）を生成
し、ループフィルタ７を介して電力増幅器１のゲート端
子Ｇに印加する。８は比較器で、ドレイン電流検出部５
よりの信号のレベルを所要の基準電圧９と比較し、基準
電圧９より大きい場合に信号を出力する。10はラッチ回
路で、比較器９よりの信号をラッチし、この信号をスイ
ッチ回路３に印加してオフにする。なお、ラッチ回路10
は所要の操作等によるリセット信号11で解除される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an amplifier protection circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of a main part of an embodiment of an amplifier protection circuit according to the present invention. In the figure, 1 is a power amplifier (PA), which is composed of an FET and amplifies a signal from a terminal 2, for example, a final circuit of a radio communication device which outputs a high frequency power of about 200 mW at about 2.4 GHz. Is. 3 is a switch circuit, 4 is a resistor, the switch circuit 3 and the resistor 4 are connected in series between the drain power supply Vdd and the drain terminal D of the power amplifier 1, and the switch circuit 3 is normally turned on. The resistor 4 is for detecting the drain current (Id) of the power amplifier 1, and is set to a sufficiently small value so as not to hinder the supply of the drain voltage required for the power amplifier 1. 5
Is a drain current detection unit that detects the drain current (Id) of the power amplifier 1 based on the voltage drop of the resistor 4. 6
Is a gate voltage control unit that generates a gate voltage (Vgs) of the power amplifier 1 based on a signal from the drain current detection unit 5 and applies it to the gate terminal G of the power amplifier 1 via the loop filter 7. Reference numeral 8 is a comparator, which is a drain current detection unit 5
The level of the signal is compared with the required reference voltage 9 and the signal is output when the level is higher than the reference voltage 9. A latch circuit 10 latches a signal from the comparator 9 and applies this signal to the switch circuit 3 to turn it off. The latch circuit 10
Is released by a reset signal 11 by a required operation.

【０００７】図２は本発明による増幅器の保護回路の他
の実施例の要部ブロック図である。図において、21はゲ
ート電圧生成部で、前記ドレイン電源Ｖdd（送信時のみ
電圧が供給される）とは別の電源Ｖdd′（常時供給され
る）よりの正電圧からゲート電圧Ｖgsを生成し、電力増
幅器１のゲート端子Ｇに供給する。その他の符号はそれ
ぞれ図１と同じであるので説明を省く。FIG. 2 is a block diagram of essential parts of another embodiment of the amplifier protection circuit according to the present invention. In the figure, reference numeral 21 denotes a gate voltage generator, which generates a gate voltage Vgs from a positive voltage from a power source Vdd '(which is always supplied) different from the drain power source Vdd (which is supplied only when transmitting), It is supplied to the gate terminal G of the power amplifier 1. The other reference numerals are the same as those in FIG. 1, and therefore their explanations are omitted.

【０００８】次に、本発明による増幅器の保護回路の動
作を説明する。まず、図１の場合、電力増幅器１はＦＥ
Ｔを用いて構成され、例えば、図３に示すような伝達特
性を有し、端子２より入力される信号レベルが設定され
た範囲内にある場合、ドレイン電源Ｖddからドレイン端
子Ｄに、ゲート端子Ｇに印加される電圧Ｖgs（例えば、
−1.5 Ｖ）に応じたドレイン電流Ｉd （例えば、250m
Ａ）が流れる。ところが、周囲温度の低下等で端子２に
入力する前段の増幅器からの信号レベルが増加し、ある
いは入力信号にノイズが加わってレベルが増加した場
合、ドレイン電流が増大し、抵抗器４の両端間の電圧が
上昇する。この電圧上昇はドレイン電流検出部５で検出
され、ゲート電圧制御部６は、ドレイン電流検出部５よ
りの信号に基づいて電力増幅器１のゲート電圧Ｖgsを負
方向に増加させ、ドレイン電流を減少させるように動作
し、ドレイン電流Ｉd の増加を抑えて電力増幅器１の破
壊を防止する。Next, the operation of the protection circuit for the amplifier according to the present invention will be described. First, in the case of FIG. 1, the power amplifier 1 is FE
If the signal level input from the terminal 2 is within the set range, the drain power supply Vdd is connected to the drain terminal D, and the gate terminal is connected. The voltage Vgs applied to G (for example,
Drain current Id (for example, 250m
A) flows. However, when the signal level from the amplifier at the previous stage input to the terminal 2 is increased due to a decrease in ambient temperature or the noise is added to the input signal to increase the level, the drain current is increased, and the drain current is increased between both ends of the resistor 4. Voltage rises. This increase in voltage is detected by the drain current detection unit 5, and the gate voltage control unit 6 increases the gate voltage Vgs of the power amplifier 1 in the negative direction based on the signal from the drain current detection unit 5 and decreases the drain current. Thus, the increase of the drain current Id is suppressed and the power amplifier 1 is prevented from being destroyed.

【０００９】上述のゲート電圧の制御ではドレイン電流
の増加を抑えきれず、抵抗器４の両端間の電圧が上昇
し、ドレイン電流検出部５の出力する信号レベルが上昇
し、このレベルが基準電圧９より高くなった場合、比較
器８の出力信号レベルが「Ｈ」となり、この信号はラッ
チ回路10でラッチされ、スイッチ回路３に印加されてオ
フに切換わり、電力増幅器１のドレイン電源を遮断し、
破壊を防止する。The above-mentioned control of the gate voltage cannot suppress the increase of the drain current, the voltage across the resistor 4 rises, the signal level output from the drain current detector 5 rises, and this level becomes the reference voltage. When it becomes higher than 9, the output signal level of the comparator 8 becomes "H", this signal is latched by the latch circuit 10, applied to the switch circuit 3 and turned off, and the drain power supply of the power amplifier 1 is cut off. Then
Prevent destruction.

【００１０】図２の場合、ゲート電圧生成部21に異常が
生じ、負電圧が生成されず、電力増幅器１のゲート電圧
Ｖgsが０Ｖになった場合、ドレイン電流Ｉd が過剰にな
り、抵抗器４の降下電圧が上昇する。この場合、上記同
様、比較器８に入力されるドレイン電流検出部５よりの
信号レベルが増大し、基準電圧９より高くなり、比較器
８の出力信号レベルが「Ｈ」となる。この信号はラッチ
回路10でラッチされ、スイッチ回路３に印加されてオフ
に切換え、電力増幅器１のドレイン電源を遮断し、破壊
を防止する。なお、ラッチ回路10は、所要の操作で出力
されるリセット信号11によりリセットされ、スイッチ回
路３をオンに復帰させる。In the case of FIG. 2, when the gate voltage generator 21 becomes abnormal and a negative voltage is not generated and the gate voltage Vgs of the power amplifier 1 becomes 0 V, the drain current Id becomes excessive and the resistor 4 The voltage drop of will rise. In this case, similarly to the above, the signal level input to the comparator 8 from the drain current detection unit 5 increases, becomes higher than the reference voltage 9, and the output signal level of the comparator 8 becomes “H”. This signal is latched by the latch circuit 10 and applied to the switch circuit 3 to turn it off, thereby cutting off the drain power source of the power amplifier 1 and preventing destruction. The latch circuit 10 is reset by the reset signal 11 output by a required operation, and returns the switch circuit 3 to the ON state.

【００１１】[0011]

【発明の効果】以上に説明したように、本発明による増
幅器の保護回路によれば、周囲温度の低下等で前段増幅
器の出力信号レベルが増加し、あるいはノイズの混入で
電力増幅器の入力信号レベルが増加し、ドレイン電流が
増大した場合、ドレイン電流の上昇に応じて電力増幅器
のゲート電圧を制御し、ドレイン電流の増大を抑え、ま
た、ゲート電圧の制御ではドレイン電流の増加を抑えき
れず、ドレイン電流が増大する、あるいは、ゲート電圧
生成部の故障等で電力増幅器のゲート電圧が０Ｖにな
り、過大なドレイン電流が流れた場合はドレイン電源の
供給路に介挿されているスイッチ回路を遮断するもので
あるから、電力増幅器の破壊を未然に保護できる有用な
ものである。As described above, according to the amplifier protection circuit of the present invention, the output signal level of the pre-stage amplifier increases due to a decrease in ambient temperature, or the input signal level of the power amplifier increases due to noise. When the drain current increases, the gate voltage of the power amplifier is controlled according to the increase of the drain current to suppress the increase of the drain current, and the control of the gate voltage cannot suppress the increase of the drain current. When the drain current increases or the gate voltage of the power amplifier becomes 0V due to a failure of the gate voltage generator, and an excessive drain current flows, the switch circuit inserted in the drain power supply path is shut off. Therefore, it is useful because it can protect the power amplifier from damage.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明による増幅器の保護回路の一実施例の要
部ブロック図である。FIG. 1 is a block diagram of a main part of an embodiment of a protection circuit for an amplifier according to the present invention.

【図２】本発明による増幅器の保護回路の他の実施例の
要部ブロック図である。FIG. 2 is a block diagram of a main part of another embodiment of a protection circuit for an amplifier according to the present invention.

【図３】電力増幅器を構成するＦＥＴの伝達特性の一例
である。FIG. 3 is an example of a transfer characteristic of an FET that constitutes a power amplifier.

【符号の説明】[Explanation of symbols]

１ 電力増幅器（ＦＥＴで構成） ３ スイッチ回路 ４ 抵抗器 ５ ドレイン電流検出部 ６ ゲート電圧制御部 ７ ループフィルタ ８ 比較器 ９ 基準電圧 10 ラッチ回路 11 リセット信号 21 ゲート電圧生成部 1 power amplifier (composed of FET) 3 switch circuit 4 resistor 5 drain current detection unit 6 gate voltage control unit 7 loop filter 8 comparator 9 reference voltage 10 latch circuit 11 reset signal 21 gate voltage generation unit

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 電界効果トランジスタを用いた電力増幅
器のドレイン端子およびドレイン電源の間に介挿した抵
抗器と、抵抗器の降下電圧に基づいて電力増幅器のドレ
イン電流を検出するドレイン電流検出部と、ドレイン電
流検出部よりの信号に基づいて電力増幅器のゲート電圧
を制御し、ドレイン電流の増加を抑止するゲート電圧制
御部とからなる増幅器の保護回路。1. A resistor inserted between a drain terminal and a drain power source of a power amplifier using a field effect transistor, and a drain current detection unit for detecting a drain current of the power amplifier based on a voltage drop of the resistor. , A gate voltage control unit that controls the gate voltage of the power amplifier based on a signal from the drain current detection unit and suppresses an increase in the drain current. 【請求項２】 電界効果トランジスタを用いた電力増幅
器のドレイン端子およびドレイン電源の間に介挿した抵
抗器と、抵抗器の降下電圧に基づいて電力増幅器のドレ
イン電流を検出するドレイン電流検出部と、ドレイン電
流検出部よりの信号を所要の基準電圧と比較し、基準電
圧より大きい場合に信号を出力する比較器と、比較器よ
りの信号をラッチするラッチ回路と、前記抵抗器と直列
に接続されラッチ回路よりの信号で開放されるスイッチ
回路とからなる増幅器の保護回路。2. A resistor inserted between a drain terminal and a drain power source of a power amplifier using a field effect transistor, and a drain current detection unit for detecting the drain current of the power amplifier based on the voltage drop of the resistor. , A comparator for comparing the signal from the drain current detector with a required reference voltage and outputting a signal when it is higher than the reference voltage, a latch circuit for latching the signal from the comparator, and the resistor connected in series An amplifier protection circuit consisting of a switch circuit that is opened by a signal from the latch circuit. 【請求項３】 電界効果トランジスタを用いた電力増幅
器のドレイン端子およびドレイン電源の間に介挿した抵
抗器と、抵抗器の降下電圧に基づいて電力増幅器のドレ
イン電流を検出するドレイン電流検出部と、ドレイン電
流検出部よりの信号に基づいて電力増幅器のゲート電圧
を制御し、ドレイン電流の増加を抑止するゲート電圧制
御部と、前記ドレイン電流検出部よりの信号を所要の基
準電圧と比較し、基準電圧より大きい場合に信号を出力
する比較器と、比較器よりの信号をラッチするラッチ回
路と、前記抵抗器と直列に接続されラッチ回路よりの信
号で開放されるスイッチ回路とを設けてなり、前記ゲー
ト電圧制御部による制御にてもなおドレイン電流が増加
した場合に前記スイッチ回路を作動させるようにした増
幅器の保護回路。3. A resistor inserted between a drain terminal and a drain power source of a power amplifier using a field effect transistor, and a drain current detection unit for detecting the drain current of the power amplifier based on the voltage drop of the resistor. A gate voltage control unit that controls the gate voltage of the power amplifier based on a signal from the drain current detection unit and suppresses an increase in the drain current, and compares the signal from the drain current detection unit with a required reference voltage, A comparator that outputs a signal when the voltage is higher than the reference voltage, a latch circuit that latches the signal from the comparator, and a switch circuit that is connected in series with the resistor and that is opened by the signal from the latch circuit are provided. A protection circuit for an amplifier, wherein the switch circuit is activated when the drain current still increases under the control of the gate voltage control unit. 【請求項４】 前記抵抗器は、前記電力増幅器の正常動
作時にドレイン端子に印加される電圧に支障を生じず、
かつ、ドレイン電流を検出するのに必要な値に設定した
ものでなる請求項１、請求項２または請求項３記載の増
幅器の保護回路。4. The resistor does not hinder the voltage applied to the drain terminal during normal operation of the power amplifier,
An amplifier protection circuit according to claim 1, 2 or 3, which is set to a value necessary for detecting the drain current. 【請求項５】 前記ラッチ回路は、所要のリセット信号
でリセットされるものでなる請求項２、請求項３または
請求項４記載の増幅器の保護回路。5. The amplifier protection circuit according to claim 2, wherein the latch circuit is reset by a required reset signal.
JP8007178A 1996-01-19 1996-01-19 Protection circuit for amplifier Pending JPH09199950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8007178A JPH09199950A (en) 1996-01-19 1996-01-19 Protection circuit for amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8007178A JPH09199950A (en) 1996-01-19 1996-01-19 Protection circuit for amplifier

Publications (1)

Publication Number Publication Date
JPH09199950A true JPH09199950A (en) 1997-07-31

Family

ID=11658831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8007178A Pending JPH09199950A (en) 1996-01-19 1996-01-19 Protection circuit for amplifier

Country Status (1)

Country Link
JP (1) JPH09199950A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7102445B2 (en) 2004-02-10 2006-09-05 Matsushita Electric Industrial Co., Ltd. Power amplifier module
US7205843B2 (en) 2003-12-25 2007-04-17 Matsushita Electric Industrial Co., Ltd. Protection circuit for power amplifier
DE102005009069B4 (en) * 2004-09-02 2008-05-29 Mitsubishi Denki K.K. Control circuit of a power semiconductor device and controlling integrated circuit
JP2008124685A (en) * 2006-11-10 2008-05-29 Kenwood Corp High frequency power amplifying circuit
JP2009100197A (en) * 2007-10-16 2009-05-07 Renesas Technology Corp Rf power amplifier apparatus, and power supply circuit to control power supply voltage of rf power amplifier
EP3748845A4 (en) * 2018-01-31 2021-11-10 ZTE Corporation Protection circuit and circuit protection method
US11996809B2 (en) 2018-10-17 2024-05-28 Murata Manufacturing Co., Ltd. Power amplifier circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7205843B2 (en) 2003-12-25 2007-04-17 Matsushita Electric Industrial Co., Ltd. Protection circuit for power amplifier
US7102445B2 (en) 2004-02-10 2006-09-05 Matsushita Electric Industrial Co., Ltd. Power amplifier module
DE102005009069B4 (en) * 2004-09-02 2008-05-29 Mitsubishi Denki K.K. Control circuit of a power semiconductor device and controlling integrated circuit
JP2008124685A (en) * 2006-11-10 2008-05-29 Kenwood Corp High frequency power amplifying circuit
JP2009100197A (en) * 2007-10-16 2009-05-07 Renesas Technology Corp Rf power amplifier apparatus, and power supply circuit to control power supply voltage of rf power amplifier
EP3748845A4 (en) * 2018-01-31 2021-11-10 ZTE Corporation Protection circuit and circuit protection method
US11996809B2 (en) 2018-10-17 2024-05-28 Murata Manufacturing Co., Ltd. Power amplifier circuit

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