JPH09199324A - Solenoid driving circuit - Google Patents

Solenoid driving circuit

Info

Publication number
JPH09199324A
JPH09199324A JP8007097A JP709796A JPH09199324A JP H09199324 A JPH09199324 A JP H09199324A JP 8007097 A JP8007097 A JP 8007097A JP 709796 A JP709796 A JP 709796A JP H09199324 A JPH09199324 A JP H09199324A
Authority
JP
Japan
Prior art keywords
solenoid
circuit
resistor
capacitor
switching element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8007097A
Other languages
Japanese (ja)
Inventor
Hideyuki Sakamoto
英之 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8007097A priority Critical patent/JPH09199324A/en
Publication of JPH09199324A publication Critical patent/JPH09199324A/en
Pending legal-status Critical Current

Links

Landscapes

  • Magnetically Actuated Valves (AREA)
  • Electronic Switches (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress the variation of delay time by providing a circuit which is connected in parallel to a switching element between a solenoid and the the switching element and suppress the variation of delay time when the solenoid comes into the non-energized state. SOLUTION: A solenoid SOL having an inductance is driven by a power MOSFET TR and further, the power MOSFET TR is driven by a microcomputer CPU with built-in ROM and RAM through a resistor R2. A diode D and a Zener diode ZD are connected in series between the gate and drain of the power MOSFET TR, and a capacitor C and a resistor R1 are connected in parallel between the drain and source of the MOSFET TR. Also, the delay of the closing time of the solenoid SOL is determined by not only a Zener clamp voltage but also the time constant of the capacitor and the resistor of a CR circuit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明はインダクタンスを持
つ負荷を駆動する駆動回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for driving a load having an inductance.

【０００２】[0002]

【従来の技術】従来の技術はインダクタンスを持つソレ
ノイドをパルス駆動するとき、負荷を通電から非通電に
した瞬間に発生するサージ電圧をツェナーダイオードで
クランプしていた。このクランプ時にはツェナーダイオ
ードを通って電流が流れるのでパルス駆動信号に対して
ソレノイドが非通電になるのが遅れる。このためソレノ
イドが非通電になる遅れ時間を測定し、補正をかけてい
た。例えば、その一例として、特開平4−348505 号公報
がある。2. Description of the Related Art In the prior art, when a solenoid having an inductance is pulse-driven, a Zener diode clamps a surge voltage generated at the moment when a load is switched from energized to de-energized. Since current flows through the Zener diode during this clamping, it is delayed that the solenoid is de-energized with respect to the pulse drive signal. Therefore, the delay time in which the solenoid is de-energized is measured and corrected. For example, as an example thereof, there is JP-A-4-348505.

【０００３】[0003]

【発明が解決しようとする課題】従来は、サージ電圧を
ツェナーダイオードのみでクランプしているため、パル
ス信号に対してソレノイドが非通電になる遅れ時間は非
通電になった瞬間のソレノイドに流れる初期電流とソレ
ノイドの抵抗，インダクタンスに依存する。そのため、
遅れ時間には、ばらつきがあるため必要とする精度が得
られなかった。Conventionally, since the surge voltage is clamped only by the Zener diode, the delay time in which the solenoid is de-energized with respect to the pulse signal is the initial time when the solenoid is de-energized. It depends on the current, the resistance of the solenoid, and the inductance. for that reason,
The required accuracy was not obtained due to variations in the delay time.

【０００４】[0004]

【課題を解決するための手段】上記目的を達成するため
に、本発明はソレノイドが非通電になる遅れ時間のばら
つきを抑える回路、つまり、コンデンサと抵抗（以下Ｃ
Ｒ回路と呼ぶ）を追加した。In order to achieve the above object, the present invention provides a circuit for suppressing variations in delay time in which a solenoid is de-energized, that is, a capacitor and a resistor (hereinafter C
R circuit) is added.

【０００５】ＣＲ回路を追加することによりソレノイ
ド，コンデンサ，抵抗の直列回路が作られたことにな
り、遅れ時間はコンデンサと抵抗の定数に依存するた
め、ばらつきは抑えられる。このことにより、正確な通
電時間制御を行うことができる。By adding a CR circuit, a series circuit of a solenoid, a capacitor, and a resistor is created, and the delay time depends on the constants of the capacitor and the resistor, so that the variation can be suppressed. As a result, accurate energization time control can be performed.

【０００６】[0006]

【発明の実施の形態】以下、本発明の一実施例を図１に
より説明する。インダクタンスを持つソレノイド：ＳＯ
ＬはパワーMOSFET：ＴＲにより駆動され、さらにパワー
MOSFETは抵抗Ｒ２を介してＲＯＭ，ＲＡＭを内蔵したマ
イクロコンピュータＣＰＵで駆動される。パワーMOSFE
T：ＴＲのゲートとドレイン間にはダイオードＤとツェ
ナーダイオードＺＤが直列に接続され、パワーMOSFET：
ＴＲのドレインとソース間にはコンデンサＣと抵抗Ｒ１
が並列に接続される。以下各素子は記号で表記する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. Solenoid with inductance: SO
L is driven by power MOSFET: TR
The MOSFET is driven by a microcomputer CPU having a built-in ROM and RAM via a resistor R2. Power MOSFE
A diode D and a zener diode ZD are connected in series between the gate and drain of T: TR, and the power MOSFET:
A capacitor C and a resistor R1 are placed between the drain and source of TR.
Are connected in parallel. Hereinafter, each element is represented by a symbol.

【０００７】図２に動作時の波形を示すＣＰＵの出力信
号Ｅ１がＬＯのときＴＲのドレイン電圧Ｅ２はＨＩ（ソ
レノイドの電源電圧であるＶＢと同一電圧）。ソレノイ
ドに流れる電流ＩＬは０である。When the output signal E1 of the CPU whose operating waveform is shown in FIG. 2 is LO, the drain voltage E2 of TR is HI (the same voltage as VB which is the power supply voltage of the solenoid). The current IL flowing through the solenoid is zero.

【０００８】ここでＥ１がＨＩになると、ＴＲがオンす
るためＥ２はＬＯとなる。ＩＬが流れ始めＩ１を越えた
ところまでの時間Ｔ１はソレノイドＳＯＬの開弁時間遅
れである。Ｅ１がＬＯの状態が続くとＩＬはさらに増加
する。Here, when E1 becomes HI, TR is turned on and E2 becomes LO. The time T1 until IL starts to flow and exceeds I1 is the valve opening time delay of the solenoid SOL. If E1 remains in the LO state, IL further increases.

【０００９】Ｅ１がＬＯになると、ＴＲがオフするため
Ｅ２はソレノイドのインダクタンスによりサージ電圧を
発生するが、ＺＤによりクランプされて一定の電圧ＥＺ
となる。ＩＬは低下を始めるがすぐには０にはならず、
Ｉ２まで低下するまでＴ２の時間がかかる。すなわち、
Ｔ２はソレノイド：ＳＯＬの閉弁時間の遅れである。こ
のＴ２はツェナークランプ電圧だけではなくＣＲ回路の
コンデンサと抵抗の定数によって決定するので、ソレノ
イドの閉弁時間の制御性が向上できる。When E1 becomes LO, TR is turned off so that E2 generates a surge voltage due to the inductance of the solenoid, but it is clamped by ZD and a constant voltage EZ is generated.
Becomes IL begins to drop, but does not immediately reach 0,
It takes T2 to decrease to I2. That is,
T2 is the delay of the valve closing time of the solenoid: SOL. Since this T2 is determined not only by the Zener clamp voltage but also by the constant of the capacitor and resistance of the CR circuit, the controllability of the valve closing time of the solenoid can be improved.

【００１０】[0010]

【発明の効果】本発明によればインダクタンスをもつソ
レノイドの閉弁時間を精度良く制御できるため制御性が
向上する。According to the present invention, the controllability is improved because the valve closing time of the solenoid having the inductance can be controlled with high accuracy.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例の回路図。FIG. 1 is a circuit diagram of one embodiment of the present invention.

【図２】図１の動作波形図。FIG. 2 is an operation waveform diagram of FIG.

【符号の説明】[Explanation of symbols]

ＳＯＬ…ソレノイド、ＴＲ…トランジスタ、ＺＤ…ツェ
ナーダイオード、CPU…マイクロコンピュータ。SOL ... solenoid, TR ... transistor, ZD ... zener diode, CPU ... microcomputer.

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】ソレノイドと、前記ソレノイドを駆動する
スイッチング素子と、前記スイッチング素子のサージ保
護回路と、前記スイッチング素子を駆動する機構を持つ
演算素子とを有するソレノイド駆動回路において、前記
ソレノイドと前記スイッチング素子間に前記スイッチン
グ素子と並列に接続され、前記ソレノイドが非通電にな
る遅れ時間のばらつきを抑える回路を有することを特徴
とするソレノイド通電時間制御回路。1. A solenoid drive circuit comprising a solenoid, a switching element for driving the solenoid, a surge protection circuit for the switching element, and an arithmetic element having a mechanism for driving the switching element. A solenoid energization time control circuit comprising a circuit which is connected between the elements in parallel with the switching element and which suppresses variation in delay time in which the solenoid is de-energized. 【請求項２】請求項１において、前記ソレノイドが非通
電になる遅れ時間のばらつきを抑える回路は、コンデン
サと抵抗であるソレノイド通電時間制御回路。2. The solenoid energization time control circuit according to claim 1, wherein the circuit for suppressing the variation in delay time in which the solenoid is de-energized is a capacitor and a resistor. 【請求項３】請求項１において、前記ソレノイドが非通
電になる遅れ時間のばらつきを抑える回路は、コンデン
サと抵抗の定数によって決定するソレノイド通電時間制
御回路。3. The solenoid energization time control circuit according to claim 1, wherein the circuit for suppressing the variation in delay time in which the solenoid is de-energized is determined by a constant of a capacitor and a resistor.
JP8007097A 1996-01-19 1996-01-19 Solenoid driving circuit Pending JPH09199324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8007097A JPH09199324A (en) 1996-01-19 1996-01-19 Solenoid driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8007097A JPH09199324A (en) 1996-01-19 1996-01-19 Solenoid driving circuit

Publications (1)

Publication Number Publication Date
JPH09199324A true JPH09199324A (en) 1997-07-31

Family

ID=11656585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8007097A Pending JPH09199324A (en) 1996-01-19 1996-01-19 Solenoid driving circuit

Country Status (1)

Country Link
JP (1) JPH09199324A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010103262A (en) * 2008-10-22 2010-05-06 Mitsubishi Heavy Ind Ltd Inductor drive circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010103262A (en) * 2008-10-22 2010-05-06 Mitsubishi Heavy Ind Ltd Inductor drive circuit
US8508201B2 (en) 2008-10-22 2013-08-13 Mitsubishi Heavy Industries, Ltd. Inductor driving circuit

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