JPH09194300A - Production of gaas substrate - Google Patents
Production of gaas substrateInfo
- Publication number
- JPH09194300A JPH09194300A JP124296A JP124296A JPH09194300A JP H09194300 A JPH09194300 A JP H09194300A JP 124296 A JP124296 A JP 124296A JP 124296 A JP124296 A JP 124296A JP H09194300 A JPH09194300 A JP H09194300A
- Authority
- JP
- Japan
- Prior art keywords
- arsenic
- ampoule
- gaas
- wafer
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＧａＡｓ基板の製
造方法に関し、特に結晶成長後のウェハアニール技術に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a GaAs substrate, and more particularly to a wafer annealing technique after crystal growth.
【０００２】[0002]
【従来の技術】ＧａＡｓ等の化合物半導体の単結晶を製
造する方法として、液体封止チョクラルスキー（ＬＥ
Ｃ）法、グラジェントフリージング（ＧＦ）法、垂直ブ
リッジマン（ＶＢ）法、水平ブリッジマン（ＨＢ）法な
どがあるが、いずれの方法も結晶と融液の間に温度勾配
を設けて融液を固化させることにより結晶の育成を行う
ものであるため、育成した結晶内の特性が不均一となる
のを避けることはできない。そのため、そのような育成
結晶から切り出した薄板状のウェハを基板として用いて
電子デバイスを作製しても、ウェハ面内でのデバイス特
性のばらつきが大きく、歩留まりが低下してしまうとい
う問題がある。例えば、アンドープまたはＣｒドープの
ＧａＡｓ単結晶よりなるウェハに作製した数多くのイオ
ン注入型のＦＥＴ（Field-Effect Transistor ）におい
ては、上述した不均一特性のために、ＦＥＴの各しきい
値電圧Ｖthがばらついてしまうという問題がある。2. Description of the Related Art Liquid-encapsulated Czochralski (LE) is used as a method for producing a single crystal of a compound semiconductor such as GaAs.
There are C) method, gradient freezing (GF) method, vertical Bridgman (VB) method, horizontal Bridgman (HB) method, etc., and all of them have a temperature gradient between the crystal and the melt. Since the crystal is grown by solidifying, it is unavoidable that the characteristics in the grown crystal become non-uniform. Therefore, even if an electronic device is manufactured by using a thin plate-shaped wafer cut out from such a grown crystal as a substrate, there is a problem that the device characteristics greatly vary within the wafer surface and the yield decreases. For example, in many ion-implanted FETs (Field-Effect Transistors) formed on a wafer made of undoped or Cr-doped GaAs single crystal, the threshold voltage Vth of each FET is There is a problem of variation.
【０００３】そこで、本出願人は、育成結晶から切り出
したウェハを、真空の石英アンプル中で、１１００℃を
超え融点未満の温度で３０分以上保持して第１段階アニ
ールを行い、次に１〜３０℃／min の降温速度で室温ま
で冷却し、該ウェハをエッチングし、その後非酸化性雰
囲気中で、７５０℃以上１１００℃以下の温度で２０分
以上保持して第２段階アニールを行った後、室温まで冷
却を行うようにした熱処理方法を提案している（特開平
２−１９２５００号公報に記載されている）。この提案
によれば、ウェハの面内特性が均一であり、かつＡＢエ
ッチングにより出現する微小欠陥（卵状ピット）の少な
いウェハを得ることができ、かかるウェハを基板として
用いることにより非常に安定した特性を有する電子デバ
イスを歩留まりよく製造できるという効果が得られる。Therefore, the applicant of the present invention performs a first stage annealing by holding a wafer cut out from a grown crystal in a vacuum quartz ampule at a temperature higher than 1100 ° C. and lower than the melting point for 30 minutes or more, and then 1 The wafer was cooled to room temperature at a temperature decrease rate of -30 ° C / min, the wafer was etched, and then a second stage annealing was performed in a non-oxidizing atmosphere at a temperature of 750 ° C or more and 1100 ° C or less for 20 minutes or more. After that, a heat treatment method is proposed in which it is cooled to room temperature (described in JP-A-2-192500). According to this proposal, it is possible to obtain a wafer in which the in-plane characteristics of the wafer are uniform and the number of minute defects (egg-shaped pits) that appear by AB etching is small, and it is very stable by using such a wafer as a substrate. It is possible to obtain an effect that an electronic device having characteristics can be manufactured with high yield.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、本出願
人による上記提案に基づくアニール方法により得られた
ウェハにおいては、その面内に局所的に抵抗率の高い領
域が生じたり、ウェハ外周部の抵抗率がその内側よりも
高くなったりして、マクロ的な抵抗率の不均一性が生じ
ることがあり、歩留まりの低下を招くおそれがある。However, in the wafer obtained by the annealing method based on the above proposal by the present applicant, a region having a high resistivity is locally generated in the surface thereof, or the resistance of the outer peripheral portion of the wafer is increased. The resistivity may be higher than that of the inside, and macroscopic nonuniformity of the resistivity may occur, which may lead to a decrease in yield.
【０００５】本発明は、上記事情に鑑みてなされたもの
で、ウェハ面内の抵抗率の均一性に優れたＧａＡｓ基板
を製造する方法を提供することを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a GaAs substrate having excellent uniformity of resistivity in the wafer surface.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明者らは上記先願のアニール方法について検討
を行った。その結果、上記方法では第２段階アニールを
開放系窒素雰囲気で行うため、アニール中にＧａＡｓウ
ェハから砒素（Ａｓ）が解離飛散し、その砒素の解離飛
散がウェハの面内で均一に起こらないことによってウェ
ハ面内の抵抗率にばらつきが生じるのではないかとの結
論を得た。そこで、本発明者らは、１段階目のアニール
のみならず２段階目のアニールも砒素雰囲気下で行え
ば、第２段階アニール時のウェハからの砒素の解離飛散
を抑制できると考えた。その考察に基づいて本発明者ら
は実験を行ったところ、第２段階アニール時に砒素の解
離飛散を起こり難くする分、第１段階アニール時に砒素
の解離飛散が起こり易いような条件としておく方が、砒
素の微小析出物（このウェハを基板としてデバイスを製
造する際に行なうエピタキシャル成長において、異常成
長を惹き起こす原因となる。）を低減する上で有効であ
るとの知見を得た。In order to achieve the above object, the present inventors have examined the annealing method of the above-mentioned prior application. As a result, in the above method, since the second stage annealing is performed in an open nitrogen atmosphere, arsenic (As) dissociates and scatters from the GaAs wafer during the annealing, and the dissociative scattering of the arsenic does not occur uniformly in the plane of the wafer. It was concluded that this may cause variations in the resistivity within the wafer surface. Therefore, the present inventors considered that dissociation and scattering of arsenic from the wafer during the second-stage annealing can be suppressed by performing not only the first-stage annealing but also the second-stage annealing in an arsenic atmosphere. The inventors of the present invention have conducted an experiment based on the above consideration, and as a result of making the dissociation and scattering of arsenic less likely to occur during the second-stage annealing, it is preferable to set the conditions such that the dissociation and scattering of arsenic easily occur during the first-stage annealing. , And found that it is effective in reducing arsenic microprecipitates (which causes abnormal growth in epitaxial growth performed when devices are manufactured using this wafer as a substrate).
【０００７】本発明は、上記知見等に基づきなされたも
ので、育成されたＧａＡｓ単結晶より切り出したウェハ
を、ＧａＡｓの化学量論平衡蒸気圧の０．６倍以下の砒
素圧雰囲気中で１０００℃以上１１５０℃以下の一定温
度で所定時間保持する第１段階アニールを行った後、一
旦４００℃以下まで冷却し、続いてＧａＡｓの化学量論
平衡蒸気圧の１．４倍以下の砒素圧雰囲気中で８００℃
以上１０００℃以下の一定温度で所定時間保持する第２
段階アニールを行った後、室温まで冷却するようにした
ことを特徴とする。それによって、第１段階アニール時
及び第２段階アニール時にウェハからの砒素の解離飛散
を適切に抑制することができるので、ウェハ面内で抵抗
率がばらつくのを防ぐことができるとともに、砒素の微
小析出物の密度を低く抑えることができる。The present invention has been made based on the above findings and the like, and a wafer cut out from a grown GaAs single crystal is subjected to 1000 times in an arsenic pressure atmosphere of 0.6 times or less of the stoichiometric equilibrium vapor pressure of GaAs. After performing the first-stage annealing at a constant temperature of ℃ to 1150 ℃ for a predetermined time, cool to 400 ℃ or less, and then arsenic pressure atmosphere of 1.4 times or less of the stoichiometric equilibrium vapor pressure of GaAs. 800 ℃ in
The second which is maintained at a constant temperature of not less than 1000 ° C for a predetermined time
After the stepwise annealing, it is characterized in that it is cooled to room temperature. As a result, dissociation and scattering of arsenic from the wafer can be appropriately suppressed during the first-stage annealing and the second-stage annealing, so that it is possible to prevent the resistivity from fluctuating in the plane of the wafer and to reduce the amount of arsenic It is possible to keep the density of the precipitate low.
【０００８】ここで、第１段階アニール時の砒素圧が
０．６倍以下であるのは、０．６倍を超えると砒素の析
出物の密度が高くなるからである。第１段階アニール時
の処理温度が１０００℃以上１１５０℃以下であるの
は、上限を超えると砒素の分解が著しく起こってＧａＡ
ｓウェハからの砒素の解離飛散を制御できなくなり、一
方、下限に満たないと砒素の析出物の密度が高くなるか
らである。The reason why the arsenic pressure during the first-stage annealing is 0.6 times or less is that the density of arsenic precipitates increases when the arsenic pressure exceeds 0.6 times. The processing temperature during the first-stage annealing is 1000 ° C. or higher and 1150 ° C. or lower.
This is because the dissociation and scattering of arsenic from the s-wafer cannot be controlled, and if the lower limit is not reached, the density of arsenic precipitates increases.
【０００９】また、第１段階アニール後の冷却温度が４
００℃以下であるのは、４００℃を超えるとエネルギー
準位が０．４０〜０．４５eVのミドルドナーが生成さ
れ、ウェハの抵抗率の均一性が悪くなったり、基板が半
絶縁性化されなくなるからである。Further, the cooling temperature after the first stage annealing is 4
The temperature below 00 ° C is that when 400 ° C is exceeded, a middle donor having an energy level of 0.40 to 0.45 eV is generated, the uniformity of the resistivity of the wafer is deteriorated, and the substrate is semi-insulating. Because it will disappear.
【００１０】さらに、第２段階アニール時の砒素圧が
１．４倍以下であるのは、１．４倍を超えると砒素の析
出物の密度が高くなるからである。第２段階アニール時
の処理温度が８００℃以上１０００℃以下であるのは、
その温度範囲を逸脱するとＥＬ２濃度の均一性が悪くな
ってウェハの抵抗率の均一性が低下するからである。Further, the reason why the arsenic pressure at the time of the second stage annealing is 1.4 times or less is that the density of the arsenic precipitate increases when it exceeds 1.4 times. The processing temperature during the second stage annealing is 800 ° C. or higher and 1000 ° C. or lower,
This is because if the temperature range is deviated, the uniformity of the EL2 concentration deteriorates and the uniformity of the resistivity of the wafer deteriorates.
【００１１】この発明において、第１段階アニール及び
第２段階アニール時の砒素圧は、好ましくはそれぞれの
熱処理温度におけるＧａＡｓの化学量論平衡蒸気圧の
０．０１倍以上であるとよい。その理由は、砒素圧が
０．０１倍に満たないとＧａＡｓの分解が起こり易くな
るからである。In the present invention, the arsenic pressure during the first-stage annealing and the second-stage annealing is preferably 0.01 times or more the stoichiometric equilibrium vapor pressure of GaAs at each heat treatment temperature. The reason is that if the arsenic pressure is less than 0.01 times, the decomposition of GaAs is likely to occur.
【００１２】また、第１段階アニールと第２段階アニー
ルとの間の冷却の際の温度は、好ましくは室温以上であ
るとよい。その理由は、室温よりも低い温度まで冷却す
るには別途冷却装置等が必要になり、熱処理炉の大型化
且つ複雑化を招くだけでなく、必要以上の冷却を行なう
ことによる時間的及び経済的な不利益をもたらすからで
ある。The temperature during cooling between the first-stage annealing and the second-stage annealing is preferably room temperature or higher. The reason is that a separate cooling device or the like is required to cool to a temperature lower than room temperature, which not only causes the heat treatment furnace to be large and complicated, but also requires time and cost due to excessive cooling. This is because it brings disadvantages.
【００１３】さらに、第２段階アニール時の処理温度
は、好ましくは９００℃以上９５０℃以下であるとよ
い。その範囲内の温度であれば、ＥＬ２の生成が均一に
起こるからである。Further, the processing temperature during the second stage annealing is preferably 900 ° C. or higher and 950 ° C. or lower. This is because if the temperature is within the range, EL2 is uniformly generated.
【００１４】ここで、本明細書中において、化学量論平
衡蒸気圧とは、「Journal of Crystal Growth 99 (199
0) 1-8 “STOICHIOMETRY CONTROL FOR GROWTH OF III-V
CRYSTALS”」の第３頁の右欄の第１１行目〜第１２行
目に記載されている式： ＰGaAs,opt＝２．６×１０6 ｅｘｐ［−１．０５（eV）
／（ｋＴ）］（Torr） で定義されるＰGaAs,optTorrのことである。In this specification, the stoichiometric equilibrium vapor pressure means "Journal of Crystal Growth 99 (199
0) 1-8 “STOICHIOMETRY CONTROL FOR GROWTH OF III-V
CRYSTALS "", page 3, right column, lines 11 to 12: P GaAs, opt = 2.6 x 10 6 exp [-1.05 (eV)
/ (KT)] (Torr), which is P GaAs, opt Torr.
【００１５】[0015]
【発明の実施の形態】以下に、本発明の実施形態につい
て説明する。Embodiments of the present invention will be described below.
【００１６】第１の実施形態は以下の通りである。先
ず、半絶縁性のアンドープＧａＡｓ単結晶インゴットか
ら切り出したウェハを、適量の砒素とともに石英製のア
ンプル内に真空封入する。封入する砒素の量は、１００
０℃以上１１５０℃以下の範囲の一定の熱処理温度（以
下、第１熱処理温度とする。）でアンプル内がＧａＡｓ
の化学量論平衡蒸気圧の０．６倍以下の砒素圧雰囲気と
なり、かつ８００℃以上１０００℃以下の範囲の一定の
熱処理温度（以下、第２熱処理温度とする。）でアンプ
ル内がＧａＡｓの化学量論平衡蒸気圧の１．４倍以下の
砒素圧雰囲気となる量である。そのアンプルを熱処理炉
内の均熱域に配置し、ヒーターにより加熱し、前記第１
熱処理温度で適当な時間保持して第１段階アニールを行
なう。しかる後、室温〜４００℃以下の温度まで冷却す
る。続いて、その状態のまま、再びヒーターにより加熱
して前記第２熱処理温度で適当な時間保持して第２段階
アニールを行なう。最後に、室温まで冷却して熱処理炉
からアンプルを取り出し、そのアンプル中からウェハを
取り出す。The first embodiment is as follows. First, a wafer cut from a semi-insulating undoped GaAs single crystal ingot is vacuum-sealed in an ampoule made of quartz together with an appropriate amount of arsenic. The amount of arsenic enclosed is 100
GaAs in the ampoule at a constant heat treatment temperature in the range of 0 ° C. to 1150 ° C. (hereinafter referred to as the first heat treatment temperature).
The stoichiometric equilibrium vapor pressure is less than 0.6 times the arsenic pressure atmosphere, and the inside of the ampoule is made of GaAs at a constant heat treatment temperature in the range of 800 ° C. to 1000 ° C. (hereinafter referred to as the second heat treatment temperature). This is an amount that creates an arsenic pressure atmosphere that is 1.4 times or less the stoichiometric equilibrium vapor pressure. The ampoule is placed in a soaking zone in a heat treatment furnace and heated by a heater to
The first stage annealing is performed by holding the heat treatment temperature for an appropriate time. Then, it is cooled to a temperature of room temperature to 400 ° C. or less. Then, in that state, the second heat treatment is performed again by heating with a heater and holding at the second heat treatment temperature for an appropriate time. Finally, after cooling to room temperature, the ampoule is taken out from the heat treatment furnace, and the wafer is taken out from the ampoule.
【００１７】第２の実施形態は以下の通りである。先
ず、半絶縁性のアンドープＧａＡｓ単結晶インゴットか
ら切り出したウェハを、適量の砒素とともに石英製のア
ンプル内に真空封入する。封入する砒素の量は、前記第
１熱処理温度でアンプル内がＧａＡｓの化学量論平衡蒸
気圧の０．６倍以下の砒素圧雰囲気となる量である。そ
のアンプルを熱処理炉内に設置し、ヒーターにより加熱
し、前記第１熱処理温度で適当な時間保持して第１段階
アニールを行なう。しかる後、室温付近まで冷却し、熱
処理炉からアンプルを取り出し、そのアンプル中からウ
ェハを取り出す。そして、取り出したウェハを適量の砒
素とともに再び石英製のアンプル内に真空封入する。新
たに封入する砒素の量は、前記第２熱処理温度でアンプ
ル内がＧａＡｓの化学量論平衡蒸気圧の１．４倍以下の
砒素圧雰囲気となる量である。その新たに真空封止した
アンプルを熱処理炉内の均熱域に配置し、ヒーターによ
り加熱し、前記第２熱処理温度で適当な時間保持して第
２段階アニールを行なう。最後に、室温まで冷却して熱
処理炉からアンプルを取り出し、そのアンプル中からウ
ェハを取り出す。The second embodiment is as follows. First, a wafer cut from a semi-insulating undoped GaAs single crystal ingot is vacuum-sealed in an ampoule made of quartz together with an appropriate amount of arsenic. The amount of arsenic to be encapsulated is such that the arsenic pressure atmosphere is 0.6 times or less the stoichiometric equilibrium vapor pressure of GaAs in the ampoule at the first heat treatment temperature. The ampoule is placed in a heat treatment furnace, heated by a heater, and held at the first heat treatment temperature for an appropriate period of time to perform the first stage annealing. Then, the temperature is cooled to around room temperature, the ampoule is taken out from the heat treatment furnace, and the wafer is taken out from the ampoule. Then, the taken-out wafer is vacuum-sealed again in an ampoule made of quartz together with an appropriate amount of arsenic. The amount of arsenic to be newly enclosed is such that the inside of the ampoule becomes an arsenic pressure atmosphere of 1.4 times the stoichiometric equilibrium vapor pressure of GaAs or less at the second heat treatment temperature. The newly vacuum-sealed ampoule is placed in a soaking zone in the heat treatment furnace, heated by a heater, and held at the second heat treatment temperature for an appropriate time to perform the second stage annealing. Finally, after cooling to room temperature, the ampoule is taken out from the heat treatment furnace, and the wafer is taken out from the ampoule.
【００１８】第３の実施形態は以下の通りである。先
ず、半絶縁性のアンドープＧａＡｓ単結晶インゴットか
ら切り出したウェハを、蒸気圧制御用元素（砒素）を入
れるリザーバ部を有する石英製のアンプル内に真空封入
する。その際、リザーバ部に適量の砒素を入れておく。
そのアンプルをウェハ部分が熱処理炉内の均熱域に位置
するように配置し、ヒーターにより加熱し、前記第１熱
処理温度で適当な時間保持して第１段階アニールを行な
う。その際、第１段階アニール中のアンプル内の砒素圧
がＧａＡｓの化学量論平衡蒸気圧の０．６倍以下となる
ようにリザーバ部の温度を調整する。しかる後、室温〜
４００℃以下の温度まで冷却する。続いて、その状態の
まま、再びヒーターにより加熱して前記第２熱処理温度
で適当な時間保持して第２段階アニールを行なう。その
際、第２段階アニール中のアンプル内の砒素圧がＧａＡ
ｓの化学量論平衡蒸気圧の１．４倍以下となるようにリ
ザーバ部の温度を調整する。最後に、室温まで冷却して
熱処理炉からアンプルを取り出し、そのアンプル中から
ウェハを取り出す。The third embodiment is as follows. First, a wafer cut out from a semi-insulating undoped GaAs single crystal ingot is vacuum-sealed in a quartz ampoule having a reservoir part for containing a vapor pressure control element (arsenic). At that time, an appropriate amount of arsenic is put in the reservoir part.
The ampoule is placed so that the wafer portion is located in the soaking zone in the heat treatment furnace, heated by a heater, and held at the first heat treatment temperature for an appropriate time to perform the first stage annealing. At that time, the temperature of the reservoir is adjusted so that the arsenic pressure in the ampoule during the first-stage annealing is 0.6 times or less the stoichiometric equilibrium vapor pressure of GaAs. After that, room temperature ~
Cool to a temperature below 400 ° C. Then, in that state, the second heat treatment is performed again by heating with a heater and holding at the second heat treatment temperature for an appropriate time. At that time, the arsenic pressure in the ampoule during the second-stage annealing was changed to GaA.
The temperature of the reservoir is adjusted so that the equilibrium vapor pressure of s becomes 1.4 times or less. Finally, after cooling to room temperature, the ampoule is taken out from the heat treatment furnace, and the wafer is taken out from the ampoule.
【００１９】このように、ＧａＡｓウェハを、ＧａＡｓ
の化学量論平衡蒸気圧の０．６倍以下の砒素圧雰囲気中
で１０００℃以上１１５０℃以下の一定温度で所定時間
保持した後、一旦４００℃以下まで冷却し、続いてＧａ
Ａｓの化学量論平衡蒸気圧の１．４倍以下の砒素圧雰囲
気中で８００℃以上１０００℃以下の一定温度で所定時
間保持するようにしたことにより、アニール時にウェハ
からの砒素の解離飛散を適切に抑制することができるの
で、ウェハ面内で抵抗率がばらつくのを防ぐことができ
るとともに、砒素の微小析出物の密度を低く抑えること
ができる。In this way, the GaAs wafer is
After maintaining at a constant temperature of 1000 ° C. or more and 1150 ° C. or less for a predetermined time in an arsenic pressure atmosphere of 0.6 times or less of the stoichiometric equilibrium vapor pressure of, then once cooling to 400 ° C. or less, and then Ga
By maintaining the temperature at a constant temperature of 800 ° C. or higher and 1000 ° C. or lower for a predetermined time in an arsenic pressure atmosphere that is 1.4 times the stoichiometric equilibrium vapor pressure of As, the dissociation and scattering of arsenic from the wafer during annealing is performed. Since it can be suppressed appropriately, it is possible to prevent the resistivity from varying within the wafer surface, and it is possible to suppress the density of the fine precipitates of arsenic to be low.
【００２０】[0020]
【実施例】以下、具体例を挙げて本発明の特徴とすると
ころを明らかとする。なお、本発明は、以下の各具体例
により何ら制限されるものではない。EXAMPLES The features of the present invention will be clarified below with reference to specific examples. The present invention is not limited to the following specific examples.
【００２１】先ず、ＬＥＣ法により半絶縁性のアンドー
プＧａＡｓ単結晶を育成し、その単結晶の上下端を切断
し、円筒研削を施した後、ウェハリングを行った。得ら
れた各ウェハについて、水酸化ナトリウム系のエッチャ
ントにより片面当たり約３０μｍずつのエッチングを行
った後、洗浄を行った。その後、それらのウェハ５枚ず
つをダミーのＧａＡｓウェハ４０枚ずつと一緒に計４５
枚ずつを複数の石英アンプル内に真空封入した。その
際、各アンプル内にウェハとともに適量の砒素を入れ、
１０７０℃における各アンプル内の砒素圧がＧａＡｓの
化学量論平衡蒸気圧の０．１〜１．０倍となるようにし
た。First, a semi-insulating undoped GaAs single crystal was grown by the LEC method, the upper and lower ends of the single crystal were cut, cylindrical grinding was performed, and then a wafer ring was performed. Each of the obtained wafers was etched with a sodium hydroxide-based etchant to a depth of about 30 μm per side, and then washed. After that, each of these 5 wafers is combined with 40 dummy GaAs wafers for a total of 45 wafers.
Each piece was vacuum-sealed in a plurality of quartz ampoules. At that time, put an appropriate amount of arsenic with each wafer in each ampoule,
The arsenic pressure in each ampoule at 1070 ° C. was adjusted to 0.1 to 1.0 times the stoichiometric equilibrium vapor pressure of GaAs.
【００２２】続いて、各アンプルを熱処理炉内にセット
して１０７０℃の温度で第１段階アニールを２時間行っ
た。その後、各アンプルを一旦室温付近まで冷却した
後、そのままの状態で再度昇温して９５０℃で第２段階
アニールを３〜７時間行った。そして、各アンプルを室
温まで冷却し、熱処理炉から取り出した。Subsequently, each ampoule was set in a heat treatment furnace and first-stage annealing was performed at a temperature of 1070 ° C. for 2 hours. After that, each ampoule was once cooled to around room temperature, then heated again in that state and second-stage annealing was performed at 950 ° C. for 3 to 7 hours. Then, each ampoule was cooled to room temperature and taken out from the heat treatment furnace.
【００２３】なお、比較として、従来法と同様に、上述
した第１段階アニールが終わったもののうち、１つのア
ンプルからウェハを取り出し、窒素ガス雰囲気中で９５
０℃の温度で第２段階目のアニールを行った。Incidentally, as a comparison, like the conventional method, a wafer is taken out from one of the ampules that have been subjected to the above-mentioned first-stage annealing and is subjected to 95% nitrogen atmosphere.
The second stage annealing was performed at a temperature of 0 ° C.
【００２４】上記各アンプルの熱処理条件を表１に示
す。Table 1 shows the heat treatment conditions for the above ampoules.
【００２５】[0025]
【表１】 [Table 1]
【００２６】得られた各ウェハについて、その表面を５
０〜６０μｍ鏡面研磨した後、Ｖａｎ ｄｅｒ Ｐａｕ
ｗ法により抵抗率と移動度を測定した。抵抗率の測定結
果を図１に示し、移動度の測定結果を図２に示す。な
お、上記従来法による比較例の測定結果を図１及び図２
の右縦軸に「従来法」として示す（後述する図６におい
ても同じ）。図１及び図２からわかるように、本発明を
適用して得られたウェハについては、抵抗率及び移動度
ともにアニール中の印加砒素圧の大きさの違いによる影
響は殆どなく、従来法により得られたウェハとの有意差
は認められなかった。The surface of each of the obtained wafers is
Van der Pau after 0-60 μm mirror polishing
The resistivity and the mobility were measured by the w method. The measurement result of the resistivity is shown in FIG. 1, and the measurement result of the mobility is shown in FIG. The measurement results of the comparative example by the above conventional method are shown in FIG. 1 and FIG.
Is shown as “conventional method” on the right vertical axis (also in FIG. 6 described later). As can be seen from FIGS. 1 and 2, for the wafer obtained by applying the present invention, there is almost no effect on the resistivity and the mobility due to the difference in the applied arsenic pressure during annealing, and the wafer obtained by the conventional method is obtained. No significant difference was observed with the wafers.
【００２７】また、３端子ガード法により各ウェハ面内
の抵抗率の均一性を調べた。抵抗率のマクロ分布につい
ては、ウェハの外周縁を５mmの幅で除き、面内全域につ
いて１mm間隔で測定し、抵抗率のミクロ分布について
は、ウェハの中心を通る線分布を０．１mm間隔で測定し
て、測定点の前後１mmの範囲の平均値からのずれの割合
の平均値として算出した。その結果、本発明を適用して
得られたウェハの抵抗率の面内均一性の相対標準偏差
は、ミクロスコピックには従来法により得られたウェハ
と同様に６．０±１．０％であり有意差はなかったが、
マクロスコピックには８．０±１．０％であり、従来法
により得られたウェハの９．０±１．０％に比べて改善
されていた。Further, the uniformity of the resistivity within each wafer surface was examined by the three-terminal guard method. For the macro distribution of resistivity, the outer peripheral edge of the wafer is excluded with a width of 5 mm, and the entire surface is measured at 1 mm intervals. For the micro distribution of resistivity, the line distribution passing through the center of the wafer is measured at 0.1 mm intervals. It was measured and calculated as the average value of the deviation rate from the average value in the range of 1 mm before and after the measurement point. As a result, the relative standard deviation of the in-plane uniformity of the resistivity of the wafer obtained by applying the present invention was 6.0 ± 1.0% in the microscopic scale as in the case of the wafer obtained by the conventional method. There was no significant difference,
Macroscopically, it was 8.0 ± 1.0%, which was improved compared to 9.0 ± 1.0% of the wafer obtained by the conventional method.
【００２８】また、図４及び図５に示すように、従来法
により得られたウェハでは抵抗率がウェハ外周部で高か
ったり、異常な分布であったりしていたが、図３に示す
ように、本発明を適用して得られたウェハでは外周部の
高抵抗化の程度及び発生頻度は著しく低減されていた。
抵抗率の異常発生率は、従来法により得られたウェハで
は１２％であったが、本発明を適用して得られたウェハ
では０％であり、改善されていた。なお、図３〜図５に
示すウェハの模式図において、点々を付した領域１、間
隔が一番広いハッチングを付した領域２、その次に間隔
が広いハッチングを付した領域３、最も間隔の狭いハッ
チングを付した領域４、格子模様を付した領域５の順に
抵抗率が低いことを表しており、また同じハッチングま
たは格子模様の領域の抵抗率は同程度であることを表し
ている。Further, as shown in FIGS. 4 and 5, in the wafer obtained by the conventional method, the resistivity was high at the outer peripheral portion of the wafer or had an abnormal distribution, but as shown in FIG. In the wafer obtained by applying the present invention, the degree of occurrence of high resistance in the outer peripheral portion and the frequency of occurrence were significantly reduced.
The abnormal occurrence rate of resistivity was 12% in the wafer obtained by the conventional method, but was 0% in the wafer obtained by applying the present invention, which was improved. In the schematic diagrams of the wafers shown in FIGS. 3 to 5, a dotted area 1, a hatched area 2 with the widest spacing, a hatched area 3 with the next widest spacing, and the widest spacing The regions 4 having narrow hatching and the regions 5 having a lattice pattern have lower resistivity in this order, and the regions having the same hatching or lattice pattern have the same resistivity.
【００２９】さらに、各ウェハについて、ＡＢエッチン
グを行い、砒素の析出物の密度（ＡＢ−ＥＰＤ）を調べ
た。その結果を図６に示す。本発明を適用して得られた
ウェハのＡＢ−ＥＰＤは、第１段階アニール中の印加砒
素圧が１０７０℃におけるＧａＡｓの化学量論平衡蒸気
圧の０．１５から０．６倍以下の範囲であれば０．５×
１０4 cm-2〜３×１０4 cm-2であり、従来法により得ら
れたウェハのＡＢ−ＥＰＤとほぼ同じであった。第１段
階アニール中の印加砒素圧が１０７０℃におけるＧａＡ
ｓの化学量論平衡蒸気圧の０．６倍を超えると、従来法
により得られたウェハのＡＢ−ＥＰＤよりも悪くなっ
た。Further, AB etching was performed on each wafer to examine the density of arsenic precipitates (AB-EPD). FIG. 6 shows the result. The AB-EPD of the wafer obtained by applying the present invention shows that the applied arsenic pressure during the first-step annealing is in the range of 0.15 to 0.6 times the stoichiometric equilibrium vapor pressure of GaAs at 1070 ° C. If there is 0.5 ×
It was 10 4 cm −2 to 3 × 10 4 cm −2 , which was almost the same as the AB-EPD of the wafer obtained by the conventional method. GaA at an applied arsenic pressure of 1070 ° C. during the first-stage annealing
Above 0.6 times the stoichiometric equilibrium vapor pressure of s, it became worse than AB-EPD of the wafer obtained by the conventional method.
【００３０】さらにまた、各ウェハ上にＭＢＥ（分子線
エピタキシー）法によりエピタキシャル成長膜を形成し
たところ、本発明を適用して得られたウェハでは従来同
様に低欠陥のエピタキシャル成長膜が得られた。Furthermore, when an epitaxial growth film was formed on each wafer by the MBE (molecular beam epitaxy) method, a low defect epitaxial growth film was obtained on the wafer obtained by applying the present invention as in the conventional case.
【００３１】[0031]
【発明の効果】本発明に係るＧａＡｓ基板の製造方法に
よれば、育成されたＧａＡｓ単結晶より切り出したウェ
ハを、ＧａＡｓの化学量論平衡蒸気圧の０．６倍以下の
砒素圧雰囲気中で１０００℃以上１１５０℃以下の一定
温度で所定時間保持する第１段階アニールを行った後、
一旦４００℃以下まで冷却し、続いてＧａＡｓの化学量
論平衡蒸気圧の１．４倍以下の砒素圧雰囲気中で８００
℃以上１０００℃以下の一定温度で所定時間保持する第
２段階アニールを行った後、室温まで冷却するようにし
たため、第１段階アニール時及び第２段階アニール時に
ウェハからの砒素の解離飛散を適切に抑制することがで
きるので、ウェハ面内で抵抗率がばらつくのを防ぐこと
ができるとともに、砒素の微小析出物の密度を低く抑え
ることができる。従って、電子デバイス作製用のウェハ
として好適であり、かかるウェハを基板として用いるこ
とにより、その上に結晶欠陥のより少ない半導体膜等を
エピタキシャル成長させることができ、非常に安定した
特性を有する電子デバイスを歩留まりよく製造できると
いう効果が得られる。According to the method of manufacturing a GaAs substrate of the present invention, a wafer cut out from a grown GaAs single crystal is placed in an arsenic pressure atmosphere of 0.6 times or less the stoichiometric equilibrium vapor pressure of GaAs. After performing the first-stage annealing in which a constant temperature of 1000 ° C. or more and 1150 ° C. or less is held for a predetermined time,
Once cooled to 400 ° C or less, then 800 in an arsenic pressure atmosphere of 1.4 times or less of the stoichiometric equilibrium vapor pressure of GaAs.
After performing the second-stage annealing in which the temperature is maintained at a constant temperature of ℃ to 1000 ° C for a predetermined time, the temperature is cooled to room temperature. Therefore, dissociation and scattering of arsenic from the wafer during the first-stage annealing and the second-stage annealing is appropriate. Therefore, it is possible to prevent the resistivity from fluctuating in the plane of the wafer and to suppress the density of fine arsenic precipitates to a low level. Therefore, it is suitable as a wafer for producing an electronic device, and by using such a wafer as a substrate, a semiconductor film having fewer crystal defects can be epitaxially grown thereon, and an electronic device having very stable characteristics can be obtained. The effect that it can be manufactured with high yield is obtained.
【図１】実施例により得られたウェハについて抵抗率と
第１段階アニール時の印加砒素圧との関係を示す特性図
である。FIG. 1 is a characteristic diagram showing the relationship between the resistivity and the applied arsenic pressure during first-stage annealing for the wafers obtained in the examples.
【図２】実施例により得られたウェハについて移動度と
第１段階アニール時の印加砒素圧との関係を示す特性図
である。FIG. 2 is a characteristic diagram showing the relationship between the mobility and the applied arsenic pressure during the first-stage annealing for the wafers obtained in the examples.
【図３】実施例により得られたウェハについて面内の抵
抗率分布の典型的なパターンを示す模式図である。FIG. 3 is a schematic diagram showing a typical pattern of in-plane resistivity distribution for a wafer obtained in an example.
【図４】従来法により得られたウェハについて面内の抵
抗率分布が異常なパターンを示す模式図である。FIG. 4 is a schematic diagram showing a pattern in which an in-plane resistivity distribution is abnormal for a wafer obtained by a conventional method.
【図５】従来法により得られたウェハについて面内の抵
抗率分布がウェハ外周部で高くなっているパターンを示
す模式図である。FIG. 5 is a schematic diagram showing a pattern in which the in-plane resistivity distribution of the wafer obtained by the conventional method is high at the outer peripheral portion of the wafer.
【図６】実施例により得られたウェハについてＡＢ−Ａ
ＰＤと第１段階アニール時の印加砒素圧との関係を示す
特性図である。FIG. 6 AB-A for wafers obtained in the example
It is a characteristic view which shows the relationship between PD and the applied arsenic pressure at the time of 1st step annealing.
Claims (4)
たウェハを、ＧａＡｓの化学量論平衡蒸気圧の０．６倍
以下の砒素圧雰囲気中で１０００℃以上１１５０℃以下
の一定温度で所定時間保持する第１段階アニールを行っ
た後、一旦４００℃以下まで冷却し、続いてＧａＡｓの
化学量論平衡蒸気圧の１．４倍以下の砒素圧雰囲気中で
８００℃以上１０００℃以下の一定温度で所定時間保持
する第２段階アニールを行った後、室温まで冷却するよ
うにしたことを特徴とするＧａＡｓ基板の製造方法。1. A wafer cut out from a grown GaAs single crystal is held at a constant temperature of 1000 ° C. or more and 1150 ° C. or less for a predetermined time in an arsenic pressure atmosphere of 0.6 times or less the stoichiometric equilibrium vapor pressure of GaAs. After performing the first-stage annealing, the temperature is once cooled to 400 ° C. or lower, and then at a constant temperature of 800 ° C. to 1000 ° C. in an arsenic pressure atmosphere of 1.4 times the stoichiometric equilibrium vapor pressure of GaAs or less. A method of manufacturing a GaAs substrate, characterized in that after performing a second stage annealing for holding for a predetermined time, it is cooled to room temperature.
上１１５０℃以下の一定温度におけるＧａＡｓの化学量
論平衡蒸気圧の０．０１倍以上０．６倍以下の砒素圧雰
囲気中で行なうことを特徴とする請求項１記載のＧａＡ
ｓ基板の製造方法。2. The first stage annealing is performed in an arsenic pressure atmosphere of 0.01 to 0.6 times the stoichiometric equilibrium vapor pressure of GaAs at a constant temperature of 1000 to 1150 ° C. GaA according to claim 1, characterized in that
s Substrate manufacturing method.
１０００℃以下の一定温度におけるＧａＡｓの化学量論
平衡蒸気圧の０．０１倍以上１．４倍以下の砒素圧雰囲
気中で行なうことを特徴とする請求項１または２記載の
ＧａＡｓ基板の製造方法。3. The second step annealing is performed in an arsenic pressure atmosphere of 0.01 to 1.4 times the stoichiometric equilibrium vapor pressure of GaAs at a constant temperature of 800 to 1000 ° C. 3. The method for manufacturing a GaAs substrate according to claim 1, which is characterized in that.
００℃以上９５０℃以下の温度で行うことを特徴とする
請求項１、２または３記載のＧａＡｓ基板の製造方法。4. The second stage anneal, preferably 9
The method for producing a GaAs substrate according to claim 1, 2 or 3, which is performed at a temperature of not less than 00 ° C and not more than 950 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP124296A JPH09194300A (en) | 1995-11-14 | 1996-01-09 | Production of gaas substrate |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7-295168 | 1995-11-14 | ||
| JP29516895 | 1995-11-14 | ||
| JP124296A JPH09194300A (en) | 1995-11-14 | 1996-01-09 | Production of gaas substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09194300A true JPH09194300A (en) | 1997-07-29 |
Family
ID=26334428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP124296A Pending JPH09194300A (en) | 1995-11-14 | 1996-01-09 | Production of gaas substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09194300A (en) |
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|---|---|---|---|---|
| US8025729B2 (en) | 2005-07-01 | 2011-09-27 | Freiberger Compound Materials Gmbh | Device and process for heating III-V wafers, and annealed III-V semiconductor single crystal wafer |
| WO2014153734A1 (en) * | 2013-03-27 | 2014-10-02 | Beijing Tongmei Xtal Technology Co., Ltd. | Controllable oxygen concentration in semiconductor substrate |
| WO2019058483A1 (en) * | 2017-09-21 | 2019-03-28 | 住友電気工業株式会社 | Semi-insulating gallium arsenide crystal substrate |
| JP2021155330A (en) * | 2019-04-02 | 2021-10-07 | 住友電気工業株式会社 | Semi-insulating gallium arsenide crystal substrate |
-
1996
- 1996-01-09 JP JP124296A patent/JPH09194300A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8025729B2 (en) | 2005-07-01 | 2011-09-27 | Freiberger Compound Materials Gmbh | Device and process for heating III-V wafers, and annealed III-V semiconductor single crystal wafer |
| JP2014212326A (en) * | 2005-07-01 | 2014-11-13 | フライベルガー・コンパウンド・マテリアルズ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツングＦｒｅｉｂｅｒｇｅｒ Ｃｏｍｐｏｕｎｄ Ｍａｔｅｒｉａｌｓ Ｇｍｂｈ | I annealing group iii-v semiconductor single crystal wafer |
| US9181633B2 (en) | 2005-07-01 | 2015-11-10 | Freiberger Compound Materials Gmbh | Device and process for heating III-V wafers, and annealed III-V semiconductor single crystal wafer |
| WO2014153734A1 (en) * | 2013-03-27 | 2014-10-02 | Beijing Tongmei Xtal Technology Co., Ltd. | Controllable oxygen concentration in semiconductor substrate |
| WO2019058483A1 (en) * | 2017-09-21 | 2019-03-28 | 住友電気工業株式会社 | Semi-insulating gallium arsenide crystal substrate |
| US11024705B2 (en) | 2017-09-21 | 2021-06-01 | Sumitomo Electric Industries, Ltd. | Semi-insulating gallium arsenide crystal substrate |
| JP2021155330A (en) * | 2019-04-02 | 2021-10-07 | 住友電気工業株式会社 | Semi-insulating gallium arsenide crystal substrate |
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