JPH0918338A - Pll frequency synthesizer - Google Patents
Pll frequency synthesizerInfo
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- JPH0918338A JPH0918338A JP7164346A JP16434695A JPH0918338A JP H0918338 A JPH0918338 A JP H0918338A JP 7164346 A JP7164346 A JP 7164346A JP 16434695 A JP16434695 A JP 16434695A JP H0918338 A JPH0918338 A JP H0918338A
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はPLL周波数シンセサイ
ザに関し、特に移動無線機等に用いられる分数分周方式
を用いたPLL周波数シンセサイザに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer and, more particularly, to a PLL frequency synthesizer using a fractional frequency dividing method used for mobile radio equipment and the like.
【0002】[0002]
【従来の技術】近年、移動体通信、例えば、携帯電話や
コードレス電話等においては、それらの需要の増大にと
もない使用周波数帯が高周波帯域に移行してゆくととも
に、多チャネル化の要求が強くなってきている。したが
って、高い周波数精度のチャネル周波数への切替が必要
になり、また、高速切替すなわち高速ロックの要求が高
まってきている。局部発振周波数源として多チャネルお
よび高速ロックの要求に対応して非同期状態での位相比
較周波数を高く設定できる分数分周方式のPLL周波数
シンセサイザが、広く用いられるようになってきてい
る。2. Description of the Related Art In recent years, in mobile communications, for example, portable telephones and cordless telephones, the use frequency band has shifted to a high frequency band with an increase in demand for them, and the demand for multi-channel transmission has increased. Is coming. Therefore, it is necessary to switch to a channel frequency with high frequency accuracy, and the demand for high-speed switching, that is, high-speed lock is increasing. As a local oscillation frequency source, a PLL frequency synthesizer of a fractional frequency division system capable of setting a high phase comparison frequency in an asynchronous state in response to a request for multi-channel and high-speed lock has been widely used.
【0003】従来のこの種のPLL周波数シンセサイザ
は、例えば特開昭61−245629号公報(文献1)
記載のN分数型周波数シンセサイザのように、分周比P
とP+1との2モードの分周器すなわちプリスケーラを
前置し、データN,AをそれぞれカウントするNおよび
Aの2つのカウンタから成るプログラマブルカウンタと
を備え、これら2つのデータNとAを、n進の累算器お
よび加算器を用いることにより増減させることにより一
定の周期における平均分周比を分数として実現するとい
う方式である。A conventional PLL frequency synthesizer of this kind is disclosed, for example, in Japanese Patent Application Laid-Open No. 61-245629 (Document 1).
As in the N-fraction type frequency synthesizer described, the dividing ratio P
And a programmable counter composed of two counters N and A for counting data N and A, respectively, in front of a two-mode frequency divider or prescaler of P + 1 and P + 1. In this method, the average division ratio in a fixed period is realized as a fraction by increasing or decreasing the number by using a hexadecimal accumulator and an adder.
【0004】文献1記載の従来のPLL周波数シンセサ
イザをブロックで示す図4を参照すると、この従来のP
LL周波数シンセサイザは、制御データA,Nの供給に
応答して入力のVCO信号Vの周波数fvを所定の分周
比で分周し周波数fpの出力信号Fpを出力する可変分
周回路100と、出力信号Fpの周波数fpと基準信号
Fpの周波数frと比較し差信号pcを出力する位相比
較器200と、差信号pcを平滑して制御信号dcを出
力するLPF300と、制御信号dcの電圧に応答して
発振周波数fvが制御され出力信号FO,Vを出力する
VCO400とを備える。FIG. 4 is a block diagram showing a conventional PLL frequency synthesizer described in Document 1. Referring to FIG.
The LL frequency synthesizer divides the frequency fv of the input VCO signal V by a predetermined frequency division ratio in response to the supply of the control data A and N, and outputs an output signal Fp of the frequency fp; A phase comparator 200 that compares the frequency fp of the output signal Fp with the frequency fr of the reference signal Fp and outputs a difference signal pc, an LPF 300 that smoothes the difference signal pc and outputs a control signal dc, and a voltage of the control signal dc. A VCO 400 for controlling the oscillation frequency fv in response and outputting the output signals FO and V.
【0005】可変分周回路100は、制御信号MCの供
給に応答して入力信号Vの周波数fvのPおよびP+1
分周のいずれか一方の動作を行い周波数fsのプリスケ
ール信号Q2を出力するプリスケーラ1と、データN,
ACの制御により設定される分周比で信号Q2を分周し
出力信号Fpおよび制御信号MCを出力するプログラマ
ブルカウンタ3と、TFFから成る累算器41と加算器
42とを含みデータN,Aと基準信号Frの供給に応答
して信号Frの2周期毎に1回データAに+1したデー
タN,ACを出力する制御回路4とを備える。The variable frequency dividing circuit 100 responds to the control signal MC by supplying P and P + 1 of the frequency fv of the input signal V.
A prescaler 1 for performing either one of frequency division operations and outputting a prescale signal Q2 having a frequency fs;
Data N, A including a programmable counter 3 for dividing the signal Q2 at a dividing ratio set by the control of the AC and outputting the output signal Fp and the control signal MC, an accumulator 41 comprising a TFF, and an adder 42 And a control circuit 4 that outputs data N and AC obtained by adding +1 to data A once every two cycles of the signal Fr in response to the supply of the reference signal Fr.
【0006】プリスケーラ1は、OR信号ORの供給に
応答して分周比がP/4,P/4+1のいずれか一方に
設定され信号sを出力する可変分周器11と、信号sの
供給に応答して動作し各々2分周の信号Q1,Q2をそ
れぞれ出力する2段のT型フリップフロップ(TFF)
F11,F12と、信号MC,Q1,Q2のOR演算を
行い信号ORを出力する3入力のOR回路14とを備え
る。The prescaler 1 includes a variable frequency divider 11 that outputs a signal s with a division ratio set to one of P / 4 and P / 4 + 1 in response to the supply of an OR signal OR, and a supply of a signal s. A two-stage T-type flip-flop (TFF) that operates in response to and outputs signals Q1 and Q2 each of which is divided by 2
F11 and F12, and a three-input OR circuit 14 that performs an OR operation on the signals MC, Q1 and Q2 and outputs a signal OR.
【0007】次に、図4および動作タイムチャートを示
す図5を参照して、従来のPLL周波数シンセサイザの
動作について説明すると、まず、説明の便宜上、プリス
ケーラ1の基本分周比Pを16、VCO400の出力信
号Vの周波数fvを2473MHz、位相比較器200
の基準信号Frの周波数frを2Mzとする。この場合
の所要分周比は1236.5となる。ここで、制御回路
4に供給するデータN,Aをそれぞれ77,4と設定す
る。まず、制御回路4の累算器41は、基準信号Frの
供給に応答し2周期毎に1回+1命令を加算器42に出
力し、加算器42はデータAに+1を加算しデータAC
=5をデータN=77とともに出力し、プログラムカウ
ンタ3に供給する。Next, the operation of the conventional PLL frequency synthesizer will be described with reference to FIG. 4 and FIG. 5 showing an operation time chart. First, for convenience of explanation, the basic frequency division ratio P of the prescaler 1 is set to 16, and the VCO 400 The frequency fv of the output signal V of 2473 MHz and the phase comparator 200
The frequency fr of the reference signal Fr is set to 2Mz. The required frequency division ratio in this case is 1236.5. Here, the data N and A to be supplied to the control circuit 4 are set to 77 and 4, respectively. First, the accumulator 41 of the control circuit 4 outputs a +1 instruction to the adder 42 once every two cycles in response to the supply of the reference signal Fr, and the adder 42 adds +1 to the data A and outputs the data AC
= 5 is output together with the data N = 77 and is supplied to the program counter 3.
【0008】プリスケーラ1はトータルカウント数であ
るデータN=77を1周期とする制御信号MCのHレベ
ルに応答して基本分周比P=16、信号MCのLレベル
に応答してP+1=17のそれぞれの入力信号Vに対す
る出力信号Q2の分周比が制御される。The prescaler 1 has a basic division ratio P = 16 in response to the H level of the control signal MC having one cycle of data N = 77 as the total count number, and has P + 1 = 17 in response to the L level of the signal MC. Of the output signal Q2 with respect to each of the input signals V is controlled.
【0009】したがって、ある周期において信号MCの
H,L各レべル期間が信号Q2のトータルカウント値7
7のうちのそれぞれ73,4周期分であるとすると、次
の周期では信号MCのH,L各レべル期間が信号Q2の
それぞれ72,5周期分となる。これにより、信号Fp
の周波数fpは2473MHzの1236分周に対応す
る2.0008MHzから1237分周対応の1.99
92MHzに変化する。Therefore, in a certain period, the H and L level periods of the signal MC correspond to the total count value 7 of the signal Q2.
Assuming that they are 73 and 4 cycles of 7, respectively, in the next cycle, the H and L level periods of the signal MC are 72 and 5 cycles of the signal Q2, respectively. Thereby, the signal Fp
The frequency fp of 2.99 MHz corresponding to 1236 frequency division of 2473 MHz is 1.99 corresponding to 1237 frequency division.
Changes to 92 MHz.
【0010】入力のVCO信号Vの周波数fvに対する
プリスケーラ1の2つの分周比をそれぞれP,P+1と
すると、平均分周比M2avは次式で表される。Assuming that the two division ratios of the prescaler 1 with respect to the frequency fv of the input VCO signal V are P and P + 1, the average division ratio M2av is expressed by the following equation.
【0011】 M2av=[(N−A)P+A(P+1) +{(N−(A+1)P+(A+1)(P+1)}]/2 =NP+A+1/2…………………………………………………………(1) これは、いわゆるP+1/2分周動作であり、上記のP
=16,N=77,A=4を(1)式に代入すると、次
のようになる。M2av = [(N−A) P + A (P + 1) + {(N− (A + 1) P + (A + 1) (P + 1)}] / 2 = NP + A + / ······················· ... (1) This is a so-called P + / frequency dividing operation.
= 16, N = 77, A = 4 into the equation (1), the result is as follows.
【0012】 M2av=77×16+4+1/2=1236.5 すなわち、平均分周比は1236.5となり対応の出力
周波数fpは2.0000MHzとなる。M2av = 77 × 16 + 4 + / = 1236.5 That is, the average frequency division ratio is 1236.5, and the corresponding output frequency fp is 2.0000 MHz.
【0013】また、プログラマブルカウンタ3に供給す
るデータACの値はPと同一すなわち16まで必要とな
るので加算器42は5ビット以上の加算器である必要が
ある。The value of the data AC supplied to the programmable counter 3 is the same as P, that is, up to 16, so that the adder 42 must be an adder of 5 bits or more.
【0014】ここで、半導体集積回路上に形成する場
合、2入力ORの回路規模を2セルとすると、累算器4
1のTFFは8セル、1ビットの加算器は9セル程度の
規模となり、5ビットの加算器42の場合は9×5=4
5セルとなり、制御回路4として53セル程度の回路規
模となる。Here, when formed on a semiconductor integrated circuit, if the circuit scale of a 2-input OR is 2 cells, the accumulator 4
The TFF of 1 has a scale of about 8 cells and the adder of 1 bit has about 9 cells, and in the case of the adder 42 of 5 bits, 9 × 5 = 4
There are five cells, and the control circuit 4 has a circuit scale of about 53 cells.
【0015】[0015]
【発明が解決しようとする課題】上述した従来のPLL
周波数シンセサイザは、制御回路としてプログラマブル
カウンタに供給する分周比のデータN,Aに対して、+
1命令を出力する2進の累算器とこの+1命令を受けて
データN,Aに加算した分周比命令を出力するビット長
の長い加算器とを必要とするため、制御回路の構成が複
雑化となり回路規模の増大要因となるという欠点があっ
た。SUMMARY OF THE INVENTION The above-mentioned conventional PLL
The frequency synthesizer applies +/- to the frequency division ratio data N and A supplied to the programmable counter as a control circuit.
Since a binary accumulator that outputs one instruction and an adder with a long bit length that outputs a division ratio instruction obtained by receiving this +1 instruction and adding it to data N and A are required, the configuration of the control circuit is reduced. There is a disadvantage that it becomes complicated and causes an increase in circuit scale.
【0016】[0016]
【課題を解決するための手段】本発明のPLL周波数シ
ンセサイザは、第1,第2の制御データの供給に応答し
て被分周信号を所定の分周比で分周し分周出力信号を出
力する可変分周回路と、前記分周出力信号のの周波数と
基準信号の周波数とを比較し差信号を出力する位相比較
回路と、前記差信号を平滑して周波数制御信号を出力す
るローパスフィルタ回路と、前記周波数制御信号の供給
に応答して発振周波数が制御され前記被分周信号を出力
する電圧制御発振回路を備えるPLL周波数シンセサイ
ザにおいて、前記可変分周回路が、第1,第2の分周制
御信号の供給に応答して前記被分周信号の第1および第
2の分周比のいずれか一方の分周動作を選択的に行いプ
リスケール信号を出力するプリスケーラ回路と、前記第
1,第2の制御データにより設定される第3の分周比で
前記プリスケール信号を分周し前記分周出力信号と前記
第1,第2の制御データ対応の前記第1の分周制御信号
とを出力するプログラマブルカウンタと、前記プリスケ
ール信号と前記分周制御信号との論理演算を行い論理信
号を出力する第1の論理回路と前記論理信号を予め定め
た第4の分周比で分周し前記第2の分周制御信号を出力
する分周回路とを含む制御回路とを備えて構成されてい
る。A PLL frequency synthesizer according to the present invention divides a frequency-divided signal by a predetermined frequency division ratio in response to supply of first and second control data, and generates a frequency-divided output signal. A variable frequency divider for outputting the frequency-divided output signal, a phase comparator for comparing the frequency of the frequency-divided output signal with the frequency of the reference signal, and outputting a difference signal, and a low-pass filter for smoothing the difference signal and outputting a frequency control signal And a PLL frequency synthesizer including a circuit and a voltage-controlled oscillation circuit whose oscillation frequency is controlled in response to the supply of the frequency control signal and outputs the frequency-divided signal. A prescaler circuit for selectively performing one of the first and second frequency division operations of the frequency-divided signal in response to supply of a frequency division control signal and outputting a prescale signal; 1, the second control data Programmable to divide the prescale signal at a third division ratio set by a frequency divider and output the divided output signal and the first divided control signal corresponding to the first and second control data. A counter, a first logic circuit that performs a logical operation on the prescale signal and the frequency division control signal and outputs a logic signal, and the logic signal is frequency-divided by a predetermined fourth frequency division ratio and the second logic circuit is divided. And a control circuit including a frequency dividing circuit for outputting the frequency dividing control signal.
【0017】[0017]
【実施例】次に、本発明の実施例を図4と共通の構成要
素には共通の参照文字/数字を付して同様にブロックで
示す図1を参照すると、この図に示す本実施例のPLL
周波数シンセサイザは、従来と共通の位相比較器200
と、LPF300と、VCO400とに加えて、可変分
周回路100の代りに簡易化した制御回路2を備え制御
データA,Nの供給に応答して入力のVCO信号Vの周
波数fvを所定の分周比で分周し周波数fpの出力信号
Fpを出力する可変分周回路100Aを備える。FIG. 1 is a block diagram showing an embodiment of the present invention, in which components common to those in FIG. 4 are denoted by common reference characters / numbers. PLL
The frequency synthesizer has a common phase comparator 200
And a simplified control circuit 2 in place of the variable frequency dividing circuit 100 in addition to the LPF 300 and the VCO 400, and in response to the supply of the control data A and N, the frequency fv of the input VCO signal V A variable frequency dividing circuit 100A is provided which divides the frequency by a frequency ratio and outputs an output signal Fp having a frequency fp.
【0018】可変分周回路器100Aは、従来と共通の
プログラムカウンタ3に加えて、プリスケーラ1の代り
に制御信号MCの供給に応答して入力信号Vの周波数f
vのPおよびP+1分周のいずれか一方の動作を行い周
波数fsのプリスケール信号Q2を出力するプリスケー
ラ1Aと、制御信号MCとプリスケール信号Q2とのO
R演算を行い信号C3を出力するOR回路21と信号C
3の供給に応答して2分周信号Q3を出力するTFF2
2とを備える制御回路2とを備える。The variable frequency divider 100A responds to the supply of the control signal MC in place of the prescaler 1 in addition to the program counter 3 common to the prior art, and the frequency f of the input signal V.
A prescaler 1A that performs one of the P and P + 1 frequency division operations of v and outputs a prescale signal Q2 having a frequency fs, and an O of a control signal MC and a prescale signal Q2
An OR circuit 21 that performs an R operation and outputs a signal C3 and a signal C
TFF2 that outputs a frequency-divided-by-2 signal Q3 in response to the supply of CFF3
And a control circuit 2 comprising
【0019】プリスケーラ1Aは、従来と共通の可変分
周器11と、TFFF11,F12とに加えて、OR回
路13の代りに信号MC,Q1,Q2,およびQ3のO
R演算を行い信号ORを出力する4入力のOR回路13
Aを備える。The prescaler 1A includes, in addition to the variable frequency divider 11 and the TFFFs 11 and F12 which are common to the prior art, the Oss of signals MC, Q1, Q2 and Q3 instead of the OR circuit 13.
Four-input OR circuit 13 for performing R operation and outputting signal OR
A is provided.
【0020】次に、図1および動作タイムチャートを示
す図2を参照して本実施例の動作について説明すると、
説明の便宜上従来と同様に、プリスケーラ1の基本分周
比Pを16、VCO400の出力信号Vの周波数fvを
2473MHz、位相比較器200の基準信号Frの周
波数frを2Mzとし、したがって、所要分周比は12
36.5となるものとする。Next, the operation of this embodiment will be described with reference to FIG. 1 and FIG. 2 showing an operation time chart.
For convenience of explanation, the basic frequency division ratio P of the prescaler 1 is 16, the frequency fv of the output signal V of the VCO 400 is 2473 MHz, and the frequency fr of the reference signal Fr of the phase comparator 200 is 2 Mz, as in the prior art. The ratio is 12
36.5.
【0021】プログラムカウンタ3にはデータNとして
従来と同様プリスケーラ1Aの出力信号Q2のトータル
カウント値N=77を、データAとして信号Q2のLレ
ベルの期間の信号Q2のカウント数A=9をそれぞれ設
定する。プリスケーラ1Aの制御信号MCのLレベルの
期間は、N=77に対応する1周期のうち、出力信号Q
2のカウント数A=9に対応する幅となる。信号MCの
Hレベルの期間はカウント値77−9=68に対応し、
出力信号Q2は従来のプリスケーラ1と同様に16分周
を反復する。The program counter 3 stores the total count value N = 77 of the output signal Q2 of the prescaler 1A as the data N and the count number A = 9 of the signal Q2 during the L-level period of the signal Q2 as the data A. Set. During the L level period of the control signal MC of the prescaler 1A, the output signal Q in one cycle corresponding to N = 77
The width corresponds to the count number A = 9 of 2. The H level period of the signal MC corresponds to the count value 77-9 = 68,
The output signal Q2 repeats frequency division by 16 similarly to the conventional prescaler 1.
【0022】次に、信号MCが0すなわちLレベルにな
ると、OR回路21は前状態のプリスケーラ1Aの出力
Q2と信号MCとのOR演算結果である信号C3をTF
F22に供給し、TFF22は信号C3を2分周し、出
力信号Q3として1,0を反復して出力する。これによ
りOR回路13に供給される信号MC,Q3の各々が
0,0の場合は出力信号Q2は次の状態で17分周信号
を出力する。次に信号MC,Q3の各々が0,1の場合
は信号MCが1の時と同様に出力信号Q2は次の状態で
16分周信号を出力する。Next, when the signal MC becomes 0, that is, the L level, the OR circuit 21 outputs a signal C3 which is an OR operation result of the output Q2 of the prescaler 1A in the previous state and the signal MC to the TF.
F2, the TFF 22 divides the frequency of the signal C3 by 2, and repeatedly outputs 1, 0 as an output signal Q3. Accordingly, when the signals MC and Q3 supplied to the OR circuit 13 are 0 and 0, respectively, the output signal Q2 outputs a 17-frequency-divided signal in the following state. Next, when the signals MC and Q3 are 0 and 1, respectively, the output signal Q2 outputs a 16-frequency-divided signal in the following state as in the case where the signal MC is 1.
【0023】その結果、信号MCの0の時、プリスケー
ラ1Aは2回に1回17分周信号を出力信号Q2として
出力する。したがって、信号MCのLレベル期間を設定
するデータAが奇数である場合、ある状態で信号MCが
0で出力信号Q2が17分周信号の出力で開始したとき
は、次に信号MCが1から0に変化したとき自動的に1
6分周信号出力で始まる。As a result, when the signal MC is 0, the prescaler 1A outputs a 17-divided signal twice as an output signal Q2. Therefore, when the data A for setting the L-level period of the signal MC is an odd number, if the signal MC is 0 and the output signal Q2 starts to output the 17-frequency-divided signal in a certain state, then the signal MC changes from 1 to 1 Automatically 1 when changed to 0
It starts with the divide-by-6 signal output.
【0024】入力のVCO信号Vの周波数fvに対する
プリスケーラ1Aの2つの分周比をそれぞれP,P+1
とすると、平均分周比M1avは次式で表される。 M1av=(N−A)P+A{P+(P+1)}/2=NP+A/2…(2) 上記のP=16,N=77,A=9を(2)式に代入す
ると、次のようになる。The two division ratios of the prescaler 1A with respect to the frequency fv of the input VCO signal V are represented by P and P + 1, respectively.
Then, the average division ratio M1av is expressed by the following equation. M1av = (N−A) P + A {P + (P + 1)} / 2 = NP + A / 2 (2) Substituting the above P = 16, N = 77, A = 9 into the equation (2) gives the following: Become.
【0025】 M1av=77×16+9/2=1236.5 すなわち、OR回路21とTFF22とを付加するだけ
で従来と同様のP+1/2分周(P:自然数)の分数分
周を実現できる。M1av = 77 × 16 + 9/2 = 1236.5 In other words, by simply adding the OR circuit 21 and the TFF 22, a fractional frequency division of P + / frequency division (P: natural number) as in the related art can be realized.
【0026】この場合、従来と同様に、2入力ORの回
路規模を2セルとすると、TFF22は8セル、したが
って制御回路2として10セル程度の回路規模となる。
従来と比較すると、TFF22と累算器41は同規模で
あるので、2入力のOR回路21と5ビットの加算器4
2の差である43セル分回路規模を低減できる。In this case, assuming that the circuit scale of the two-input OR is two cells as in the conventional case, the TFF 22 has eight cells, and therefore the control circuit 2 has a circuit scale of about ten cells.
Compared with the conventional case, the TFF 22 and the accumulator 41 have the same scale, so that the two-input OR circuit 21 and the 5-bit adder 4
The circuit scale can be reduced by 43 cells, which is the difference between the two.
【0027】次に、本発明の第2の実施例の可変分周回
路100Bを図1の可変分周回路100Aとと共通の構
成要素には共通の参照文字/数字を付して同様にブロッ
クで示す図3を参照すると、本実施例の上述の第1の実
施例に対する相違点は、プリスケーラ1Aの代りにOR
信号ORの供給に応答して分周比がk,k+1のいずれ
か一方に設定され信号sを出力する可変分周器11Aと
縦続接続されたj段のTFFF1〜TFFFjから成る
分周器12とを備えるプリスケーラ1Bと、制御回路2
の代りに分周比がqの分周器23を備える制御回路2A
とを備えることである(k,j,qは正の整数)。Next, a variable frequency dividing circuit 100B according to a second embodiment of the present invention will be described in the same manner as the variable frequency dividing circuit 100A of FIG. Referring to FIG. 3 shown in FIG. 3, the difference of the present embodiment from the above-described first embodiment is that OR is provided instead of the prescaler 1A.
A frequency divider 12 composed of j stages of TFFF1 to TFFFj connected in cascade with a variable frequency divider 11A that outputs a signal s with the frequency division ratio set to one of k and k + 1 in response to the supply of the signal OR; And a control circuit 2
Circuit 2A including a frequency divider 23 having a frequency division ratio q instead of
And (where k, j, and q are positive integers).
【0028】図3を参照して本実施例の動作について説
明すると、まず、分周器23の出力信号Q3のHレベル
の期間は(q−r)周期、Lレベルの期間はr(q未満
の正の整数)周期とする。m=k・2i と置けば、制御
信号MCが1のときは分周器23の出力Q3はm分周信
号出力を反復する。制御信号MCが0の場合、出力Q3
はm,(m+1)分周の各出力が(q−r)周期,r周
期の割合から成るq周期で交互に繰り返され、信号MC
がq周期するとその状態に復帰するので、平均分周数は
時式で表される。The operation of the present embodiment will be described with reference to FIG. 3. First, the period of the H level of the output signal Q3 of the frequency divider 23 is (qr) periods, and the period of the L level is r (less than q). Is a positive integer). If m = k · 2 i is set, when the control signal MC is 1, the output Q3 of the frequency divider 23 repeats the m-frequency-divided signal output. When the control signal MC is 0, the output Q3
In the signal MC, the outputs of the m and (m + 1) frequency divisions are alternately repeated at q periods which are the ratios of (qr) periods and r periods.
Returns to that state after q cycles, the average frequency division number is represented by a time formula.
【0029】 M3av=(N−A)m+A{(q−r)m+r(m+1)}/q =Nm+Ar/q (m=k・2i )…………………………………(3) したがって、自由な分数分周数を設定することが可能と
なる。M3av = (N−A) m + Aq (q−r) m + r (m + 1)} / q = Nm + Ar / q (m = k · 2 i ) ··············· 3) Therefore, it is possible to freely set the fractional frequency division number.
【0030】例えば、分周器23を3分周器にした場
合、Hレベルを2周期、Lレベルを1周期とすれば、
(3)式より、 M3av=Nm+Ar/q=Nm+A・1/3=Nm+0.333・A となる。また同じ3分周期でもHレベルを1周期、Lレ
ベルを2周期にすれば M3av=Nm+A・2/3=Nm+0.667・A に設定できる。For example, when the frequency divider 23 is a three-frequency divider, if the H level is two periods and the L level is one period,
From the equation (3), M3av = Nm + Ar / q = Nm + A.1 / 3 = Nm + 0.333.A In addition, if the H level is set to one cycle and the L level is set to two cycles in the same three-minute cycle, M3av = Nm + AA / 2/3 = Nm + 0.667 ・ A can be set.
【0031】本実施例の制御回路と従来の制御回路との
回路規模の差は、第1の実施例と同様にOR回路21と
加算器42との差であり、上記m分周が2(s-1) ≦m<
2sであれば従来はsビット以上の加算器42が必要と
なり、加算器42は9×sセル程度の回路規模となる。
したがってこの実施例の制御回路は従来より(9×s−
2)セル程度分回路規模を低減できる。The difference in circuit scale between the control circuit of the present embodiment and the conventional control circuit is the difference between the OR circuit 21 and the adder 42, as in the first embodiment, and the m division is 2 ( s-1) ≤m <
In the case of 2 s , an adder 42 of s bits or more is conventionally required, and the adder 42 has a circuit size of about 9 × s cells.
Therefore, the control circuit of this embodiment is conventionally (9 × s−
2) The circuit scale can be reduced by about a cell.
【0032】[0032]
【発明の効果】以上説明したように、本発明のPLL周
波数シンセサイザは、可変分周回路が、プリスケール信
号と第1の分周制御信号との論理演算を行い論理信号を
出力する論理回路とこの論理信号を分周し第2の分周制
御信号を出力する分周回路とをとを含む制御回路とを備
えているので、プリスケーラ出力信号の制御回路を論理
回路と分周器のみで構成することにより、複雑な加算器
などは不要となるので制御回路の回路規模を小さくする
ことが可能となるという効果がある。As described above, in the PLL frequency synthesizer of the present invention, the variable frequency dividing circuit performs a logical operation on the prescale signal and the first frequency dividing control signal and outputs a logical signal. And a frequency divider for dividing the logic signal and outputting a second frequency division control signal. Therefore, the control circuit for the prescaler output signal is composed of only the logic circuit and the frequency divider. This eliminates the need for a complicated adder or the like, so that the circuit scale of the control circuit can be reduced.
【図面の簡単な説明】[Brief description of the drawings]
【図1】本発明のPLL周波数シンセサイザの第1の実
施例を示すブロック図である。FIG. 1 is a block diagram showing a first embodiment of a PLL frequency synthesizer according to the present invention.
【図2】本実施例のPLL周波数シンセサイザにおける
動作の一例を示すタイムチャートである。FIG. 2 is a time chart showing an example of the operation of the PLL frequency synthesizer of this embodiment.
【図3】本発明の第2の実施例の可変分周回路を示すブ
ロック図である。FIG. 3 is a block diagram showing a variable frequency dividing circuit according to a second embodiment of the present invention.
【図4】従来のPLL周波数シンセサイザの一例を示す
ブロック図である。FIG. 4 is a block diagram illustrating an example of a conventional PLL frequency synthesizer.
【図5】従来のPLL周波数シンセサイザにおける動作
の一例を示すタイムチャートである。FIG. 5 is a time chart showing an example of the operation of a conventional PLL frequency synthesizer.
1,1A,1B プリスケーラ 2,2A,4 制御回路 3 プログラマブルカウンタ 11,11A 可変分周器 12,23 分周器 13,13A,13B,21 OR回路 22,F11,F12 TFF 100,100A,100B 可変分周回路 200 位相比較器 300 LPF 400 VCO 1, 1A, 1B Prescaler 2, 2A, 4 Control circuit 3 Programmable counter 11, 11A Variable divider 12, 23 Divider 13, 13A, 13B, 21 OR circuit 22, F11, F12 TFF 100, 100A, 100B Variable Dividing circuit 200 Phase comparator 300 LPF 400 VCO
Claims (5)
て被分周信号を所定の分周比で分周し分周出力信号を出
力する可変分周回路と、前記分周出力信号のの周波数と
基準信号の周波数とを比較し差信号を出力する位相比較
回路と、前記差信号を平滑して周波数制御信号を出力す
るローパスフィルタ回路と、前記周波数制御信号の供給
に応答して発振周波数が制御され前記被分周信号を出力
する電圧制御発振回路を備えるPLL周波数シンセサイ
ザにおいて、 前記可変分周回路が、第1,第2の分周制御信号の供給
に応答して前記被分周信号の第1および第2の分周比の
いずれか一方の分周動作を選択的に行いプリスケール信
号を出力するプリスケーラ回路と、 前記第1,第2の制御データにより設定される第3の分
周比で前記プリスケール信号を分周し前記分周出力信号
と前記第1,第2の制御データ対応の前記第1の分周制
御信号とを出力するプログラマブルカウンタと、 前記プリスケール信号と前記分周制御信号との論理演算
を行い論理信号を出力する第1の論理回路と前記論理信
号を予め定めた第4の分周比で分周し前記第2の分周制
御信号を出力する分周回路とを含む制御回路とを備える
ことを特徴とするPLL周波数シンセサイザ。1. A variable frequency dividing circuit for dividing a frequency-divided signal at a predetermined frequency division ratio in response to supply of first and second control data and outputting a frequency division output signal, and the frequency division output. A phase comparison circuit that compares the frequency of the signal with the frequency of the reference signal and outputs a difference signal, a low-pass filter circuit that smoothes the difference signal and outputs a frequency control signal, and responds to the supply of the frequency control signal. In a PLL frequency synthesizer including a voltage controlled oscillator circuit whose oscillation frequency is controlled to output the frequency-divided signal, the variable frequency dividing circuit is responsive to the supply of the first and second frequency-division control signals. A prescaler circuit that selectively performs one of the first and second frequency division ratios of the frequency division signal to output a prescale signal; and a prescaler circuit that is set by the first and second control data. The prescale with a division ratio of 3 A programmable counter that divides the frequency and outputs the divided output signal and the first divided control signal corresponding to the first and second control data; and a prescale signal and the divided control signal. Control including a first logic circuit that performs a logic operation and outputs a logic signal, and a frequency divider circuit that divides the logic signal by a predetermined fourth frequency division ratio and outputs the second frequency division control signal A PLL frequency synthesizer comprising: a circuit.
給に応答して前記被分周信号を分周比k,k+1(kは
正の整数)のいずれか一方で分周し可変分周信号を出力
する可変分周器と、 縦続接続され前記可変分周信号をそれぞれ2分周して第
1〜第j(jは正の整数)の分周信号を出力しこの第j
の分周信号が前記プリスケール信号である第1〜第jの
フリップフロップ回路と、 前記第1,第2の分周制御信号と前記第1〜第jの分周
信号との論理演算を行いこの論理演算値対応の前記選択
信号を出力する第2の論理回路とを備えることを特徴と
する請求項1記載のPLL周波数シンセサイザ。2. The prescaler circuit divides the frequency-divided signal by any one of frequency division ratios k and k + 1 (k is a positive integer) in response to the supply of the selection signal to generate a variable frequency division signal. A variable frequency divider for outputting and a frequency-divided signal that is cascaded and frequency-divides the variable frequency-divided signal by two to output frequency-divided signals of 1st to j-th (j is a positive integer).
A first to a j-th flip-flop circuit whose divided signal is the prescale signal; and performing a logical operation of the first and second divided control signals and the first to j-th divided signals 2. The PLL frequency synthesizer according to claim 1, further comprising a second logic circuit that outputs the selection signal corresponding to the logical operation value.
1の分周制御信号の1周期に出力する前記プリスケール
信号の総数が前記第1の制御データ値に対応しこの第1
の分周制御信号のLレベル期間に出力する前記プリスケ
ール信号の数が前記第2の制御データ値に対応するよう
制御する分周制御信号発生回路を備えることを特徴とす
る請求項1記載のPLL周波数シンセサイザ。3. The total number of the prescale signals output by the programmable counter in one cycle of the first frequency division control signal corresponds to the first control data value.
2. A frequency division control signal generation circuit for controlling the number of the prescale signals output during the L level period of the frequency division control signal to correspond to the second control data value. PLL frequency synthesizer.
であることを特徴とする請求項1または2記載のPLL
周波数シンセサイザ。4. The PLL according to claim 1, wherein said first and second logic circuits are OR circuits.
Frequency synthesizer.
を特徴とする請求項2記載のPLL周波数シンセサイ
ザ。5. The PLL frequency synthesizer according to claim 2, wherein the k is 4 and the j is 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7164346A JP2827968B2 (en) | 1995-06-29 | 1995-06-29 | PLL frequency synthesizer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP7164346A JP2827968B2 (en) | 1995-06-29 | 1995-06-29 | PLL frequency synthesizer |
Publications (2)
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JPH0918338A true JPH0918338A (en) | 1997-01-17 |
JP2827968B2 JP2827968B2 (en) | 1998-11-25 |
Family
ID=15791427
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JP7164346A Expired - Lifetime JP2827968B2 (en) | 1995-06-29 | 1995-06-29 | PLL frequency synthesizer |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62209405A (en) * | 1986-03-04 | 1987-09-14 | Fujikura Ltd | Optical fiber cable |
-
1995
- 1995-06-29 JP JP7164346A patent/JP2827968B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62209405A (en) * | 1986-03-04 | 1987-09-14 | Fujikura Ltd | Optical fiber cable |
JPH0442649B2 (en) * | 1986-03-04 | 1992-07-14 | Fujikura Densen Kk |
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Publication number | Publication date |
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JP2827968B2 (en) | 1998-11-25 |
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