JPH0918145A - Multilayer ceramic board - Google Patents

Multilayer ceramic board

Info

Publication number
JPH0918145A
JPH0918145A JP7163453A JP16345395A JPH0918145A JP H0918145 A JPH0918145 A JP H0918145A JP 7163453 A JP7163453 A JP 7163453A JP 16345395 A JP16345395 A JP 16345395A JP H0918145 A JPH0918145 A JP H0918145A
Authority
JP
Japan
Prior art keywords
electrode terminal
multilayer ceramic
ceramic board
main circuit
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7163453A
Other languages
Japanese (ja)
Inventor
Shigetoshi Segawa
茂俊 瀬川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7163453A priority Critical patent/JPH0918145A/en
Publication of JPH0918145A publication Critical patent/JPH0918145A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Abstract

PURPOSE: To prevent a multilayer ceramic board from cracking in the vicinity of electrode terminal thereof due to difference of coefficient of thermal expansion at the time of connecting the multilayer ceramic board mounting a semiconductor chip with a main circuit board. CONSTITUTION: A multilayer ceramic board 1 is provided, on the electrode terminal 3 thereof, with an outermost layer covering the electrode terminal 3 while partially exposing the inside thereof having small diameter. The electrode terminal 3 is reinforced, at the outer circumferential part thereof, by the multilayer ceramic board 1 itself.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、ＢＧＡ（ボールグリッ
ドアレイ）やＬＧＡ（ランドグリッドアレイ）方式で実
装を行う、半導体実装用のセラミック多層基板に関する
ものであり、特に半導体を搭載した前記基板と、メイン
回路基板との接続構造を改善するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic multi-layer substrate for semiconductor mounting, which is mounted by a BGA (ball grid array) or LGA (land grid array) system, and particularly to the above-mentioned substrate on which a semiconductor is mounted. , The connection structure with the main circuit board is improved.

【０００２】[0002]

【従来の技術】近年、電子機器の小型化及び回路のデジ
タル化に伴い、高密度な回路基板が要求されてきてい
る。ＩＣのピン数の増加に伴い、半導体モジュールの形
態は、ＱＦＰに代わって、ＢＧＡやＬＧＡタイプが主流
となりつつある。2. Description of the Related Art In recent years, with the miniaturization of electronic devices and the digitization of circuits, high density circuit boards have been required. With the increase in the number of IC pins, BGA and LGA type semiconductor modules are becoming the mainstream instead of QFP.

【０００３】図３は従来の半導体モジュールの断面図を
示すものであり、セラミック多層基板１の表面には、半
導体チップ２を搭載しており、その裏面にはメイン回路
基板４との接続に用いる、ＢＧＡ，ＬＧＡ用の電極３端
子を形成している。またメイン回路基板４にも電極端子
３に対向して電極端子５を形成してあり、セラミック多
層基板１とメイン回路基板４とは、半田６を介して接続
している。FIG. 3 is a cross-sectional view of a conventional semiconductor module, in which a semiconductor chip 2 is mounted on the front surface of a ceramic multilayer substrate 1 and used for connection with a main circuit board 4 on the back surface thereof. , 3 electrodes for BGA, LGA are formed. Further, an electrode terminal 5 is formed on the main circuit board 4 so as to face the electrode terminal 3, and the ceramic multilayer board 1 and the main circuit board 4 are connected via solder 6.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら上記従来
の半導体実装モジュールにおいては、樹脂製のメイン回
路基板４と、セラミック多層基板１との熱膨張係数が異
なるため次のような問題があった。すなわちヒートサイ
クル試験（例えば−５５℃〜＋１２５℃）を行うと、そ
の応力により、樹脂製のメイン回路基板４に比べ強度の
弱いセラミック多層基板１には、電極端子３の外周端付
近からその内部にわたってクラック７が入ってしまう。However, in the above-described conventional semiconductor mounting module, the resin main circuit board 4 and the ceramic multi-layer substrate 1 have different thermal expansion coefficients, and thus have the following problems. That is, when a heat cycle test (for example, −55 ° C. to + 125 ° C.) is performed, the stress causes the ceramic multi-layer substrate 1 which is weaker in strength than the resin main circuit board 4 to reach the inside from the outer peripheral edge of the electrode terminal 3. Cracks 7 will be introduced all over.

【０００５】そこで本発明は、セラミック基板に形成す
る電極端子の構造を改善することにより、上述のような
クラックの発生を防止することを目的とする。Therefore, an object of the present invention is to prevent the occurrence of the above-mentioned cracks by improving the structure of the electrode terminals formed on the ceramic substrate.

【０００６】[0006]

【課題を解決するための手段】上記課題を解決するため
に、本発明のセラミック多層基板は、表面に半導体素子
が実装され、裏面が半田電極を介してメイン回路基板に
接続されるセラミック多層基板において、前記メイン回
路基板との接続のために電極端子を形成したさらにその
上層に、前記電極端子の径小な部分を残して被覆する最
外層を形成したことを特徴とするものである。In order to solve the above-mentioned problems, a ceramic multilayer substrate of the present invention has a semiconductor element mounted on the front surface and a back surface connected to a main circuit board via a solder electrode. In the above, the outermost layer covering the electrode terminal for connection with the main circuit board is further formed on the upper layer of the electrode terminal.

【０００７】[0007]

【作用】上記構成によれば、セラミック多層基板に形成
する電極端子を、その外周部を被覆することによって、
メイン回路基板との間で熱膨張係数の差から生じる応力
は分散する。このためセラミック多層基板と電極端子と
の接続強度は高まり、クラックの発生を防止できる。According to the above construction, by covering the outer peripheral portion of the electrode terminal formed on the ceramic multilayer substrate,
The stress resulting from the difference in coefficient of thermal expansion with the main circuit board is dispersed. For this reason, the connection strength between the ceramic multilayer substrate and the electrode terminals is increased, and the occurrence of cracks can be prevented.

【０００８】[0008]

【実施例】以下、本発明のセラミック多層基板の実施例
について、図面を参照しながら説明する。図１は本発明
の一実施例における半導体モジュールの断面図であり、
図２はセラミック多層基板の平面図を示している。Embodiments of the ceramic multilayer substrate of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor module according to an embodiment of the present invention.
FIG. 2 shows a plan view of the ceramic multilayer substrate.

【０００９】本実施例のセラミック多層基板１は、グリ
ーンシート積層体の表面に、メイン回路基板４との接続
に用いる電極端子３を形成した後、さらにその上面に、
電極端子３に対向する位置に、前記電極端子３に比べ径
小な貫通孔を形成したグリーンシートを積層する。In the ceramic multilayer substrate 1 of this embodiment, after the electrode terminals 3 used for connection with the main circuit board 4 are formed on the surface of the green sheet laminated body, further, on the upper surface thereof,
A green sheet having a through hole having a smaller diameter than that of the electrode terminal 3 is laminated at a position facing the electrode terminal 3.

【００１０】そしてこの積層体を脱バインダーし焼成す
ると、外周が被覆されその径小な内部が部分的に露出し
た電極端子３を形成することができる。Then, by removing the binder and firing the laminated body, it is possible to form the electrode terminal 3 whose outer periphery is covered and whose small inside is partially exposed.

【００１１】[0011]

【発明の効果】以上の様に本発明のセラミック多層基板
は、電極端子の外周端をさらに最外層により被覆してい
る。このため熱膨張係数の差により、セラミック多層基
板から電極端子を引き離そうとする応力が働いても、電
極端子の端部を把持し補強しているので、クラックなど
は発生せず、信頼性の高い半導体モジュールを提供する
ことができる。As described above, in the ceramic multilayer substrate of the present invention, the outer peripheral end of the electrode terminal is further covered with the outermost layer. Therefore, even if the stress that pulls the electrode terminal away from the ceramic multilayer substrate is exerted due to the difference in the coefficient of thermal expansion, the end portion of the electrode terminal is gripped and reinforced, so cracks do not occur and the reliability is high. A semiconductor module can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例におけるセラミック多層基板
を使用した半導体モジュールの断面図FIG. 1 is a sectional view of a semiconductor module using a ceramic multilayer substrate according to an embodiment of the present invention.

【図２】同基板の平面図FIG. 2 is a plan view of the board.

【図３】従来のセラミック多層基板を使用した半導体モ
ジュールの断面図FIG. 3 is a sectional view of a semiconductor module using a conventional ceramic multilayer substrate.

【符号の説明】[Explanation of symbols]

１ セラミック多層基板 ２ 半導体チップ ３，５ 電極端子 ４ メイン回路基板 ６ 半田 ７ クラック 1 Ceramic Multilayer Substrate 2 Semiconductor Chip 3,5 Electrode Terminal 4 Main Circuit Board 6 Solder 7 Crack

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】表面に半導体素子が実装され、裏面が半田
電極を介してメイン回路基板に接続されるセラミック多
層基板において、前記メイン回路基板との接続のために
電極端子を形成したさらにその上層に、前記電極端子の
径小な部分を残して被覆する最外層を形成したことを特
徴とするセラミック多層基板。1. A ceramic multilayer substrate having a semiconductor element mounted on the front surface and a back surface connected to a main circuit board via a solder electrode, further comprising electrode terminals formed for connection to the main circuit board. A ceramic multilayer substrate, wherein an outermost layer covering the electrode terminal while leaving a small diameter portion thereof is formed.
JP7163453A 1995-06-29 1995-06-29 Multilayer ceramic board Pending JPH0918145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7163453A JPH0918145A (en) 1995-06-29 1995-06-29 Multilayer ceramic board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7163453A JPH0918145A (en) 1995-06-29 1995-06-29 Multilayer ceramic board

Publications (1)

Publication Number Publication Date
JPH0918145A true JPH0918145A (en) 1997-01-17

Family

ID=15774179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7163453A Pending JPH0918145A (en) 1995-06-29 1995-06-29 Multilayer ceramic board

Country Status (1)

Country Link
JP (1) JPH0918145A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7323770B2 (en) 2001-02-06 2008-01-29 Renesas Technology Corp. Hybrid integrated circuit device, and method for fabricating the same, and electronic device
JP2009246300A (en) * 2008-03-31 2009-10-22 Tdk Corp Surface mounted part, method for manufacturing therefor, and mounting method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7323770B2 (en) 2001-02-06 2008-01-29 Renesas Technology Corp. Hybrid integrated circuit device, and method for fabricating the same, and electronic device
US7518228B2 (en) 2001-02-06 2009-04-14 Renesas Technology Corp. Hybrid integrated circuit device, and method for fabricating the same, and electronic device
US7755182B2 (en) 2001-02-06 2010-07-13 Renesas Technology Corp. Hybrid integrated circuit device, and method for fabricating the same, and electronic device
US7902656B2 (en) 2001-02-06 2011-03-08 Renesas Electronics Corporation Hybrid integrated circuit device, and method for fabricating the same, and electronic device
US8084852B2 (en) 2001-02-06 2011-12-27 Renesas Electronics Corporation Hybrid integrated circuit device, and method for fabricating the same, and electronic device
US8222734B2 (en) 2001-02-06 2012-07-17 Renesas Electronics Corporation Hybrid integrated circuit device and electronic device
US8581395B2 (en) 2001-02-06 2013-11-12 Renesas Electronics Corporation Hybrid integrated circuit device and electronic device
JP2009246300A (en) * 2008-03-31 2009-10-22 Tdk Corp Surface mounted part, method for manufacturing therefor, and mounting method

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