JPH09181334A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH09181334A JPH09181334A JP33629895A JP33629895A JPH09181334A JP H09181334 A JPH09181334 A JP H09181334A JP 33629895 A JP33629895 A JP 33629895A JP 33629895 A JP33629895 A JP 33629895A JP H09181334 A JPH09181334 A JP H09181334A
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- layer
- current
- semiconductor
- voltage
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は電力変換機器に用
いられる電力用ダイオードなどの半導体装置に関する。The present invention relates to a semiconductor device such as a power diode used for power conversion equipment.
【０００２】[0002]
【従来の技術】電力変換機器に用いられる電力用ダイオ
ードは低オン電圧と高速スイッチング性が要求される。
低耐圧素子ではショットキーダイオードがこの特性を兼
ね備えているが、ショットキーダイオードを高耐圧化す
ると、オン電圧が大幅に増大すると共に、漏れ電流の大
幅な増加がある。このためショットキーダイオードは一
般に高耐圧では使用されていない。2. Description of the Related Art A power diode used in a power conversion device is required to have a low on-voltage and a high speed switching property.
In a low breakdown voltage element, a Schottky diode also has this characteristic, but if the Schottky diode is made to have a high breakdown voltage, the ON voltage is greatly increased and the leakage current is also greatly increased. For this reason, Schottky diodes are generally not used in high breakdown voltage.
【０００３】図４は高耐圧で使用されている従来のｐｉ
ｎダイオードの断面図を示す。ｎ-層１の一方の面にｐ
層７、他方にｎ+ 層２を形成し、ｐ層７、ｎ+ 層２のそ
れぞれの表面にアノード電極３、カソード電極４を形成
する。このｐｉｎダイオードはオン状態で伝導度変調を
利用しているので高耐圧でもオン電圧を低下させること
ができる。しかし、ｐｉｎダイオードが逆回復する時
に、伝導度変調によって生じた過剰キャリアを掃き出す
ために大きな逆回復電流が流れ、スイッチング損失が増
大する。逆回復電流を抑制するためにライフタイムキラ
ーを導入するとオン電圧が増大する。つまりオン電圧と
スイッチング損失はトレードオフの関係にある。FIG. 4 shows a conventional pi used for high breakdown voltage.
A sectional view of an n-diode is shown. p on one side of n - layer 1
The layer 7 and the n + layer 2 are formed on the other side, and the anode electrode 3 and the cathode electrode 4 are formed on the respective surfaces of the p layer 7 and the n + layer 2. Since this pin diode uses conductivity modulation in the ON state, the ON voltage can be lowered even with a high breakdown voltage. However, when the pin diode reversely recovers, a large reverse recovery current flows because it sweeps out excess carriers generated by conductivity modulation, and switching loss increases. If a lifetime killer is introduced to suppress the reverse recovery current, the on-voltage will increase. That is, the on-voltage and the switching loss have a trade-off relationship.
【０００４】図５は従来のｐ- ｉｎダイオードの断面図
を示す。図４と異なるのは、ｐ層７がｐ- 領域８とｐ+
領域９とで形成されている点である。ｐ- 領域８の存在
で、この層からの正孔の注入が抑制され、オン状態での
過剰キャリアを下げることができ、逆回復電流を小さく
でき、一方、ｐ+ 領域９の存在でオン電圧の低下ができ
る。FIG. 5 shows a cross-sectional view of a conventional p - in diode. The difference from FIG. 4 is that the p layer 7 has p − regions 8 and p + regions.
This is a point formed with the region 9. The presence of the p − region 8 suppresses the injection of holes from this layer, can reduce the excess carriers in the on-state, and can reduce the reverse recovery current, while the presence of the p + region 9 enables the on-voltage to be generated. Can be reduced.
【０００５】[0005]
【発明が解決しようとする課題】しかし、このｐ- ｉｎ
ダイオードは定格電流領域では良好なオン特性を示す
が、回路異常等で流れるサージ電流領域のような大電流
領域ではｐ- 領域８からの正孔の注入がｐｉｎダイオー
ドのｐ層７からの注入と比べかなり低くなるために、オ
ン電圧がかなり増大する。However, this p - in
The diode exhibits good ON characteristics in the rated current region, but in a large current region such as a surge current region which flows due to a circuit abnormality or the like, holes are injected from the p − region 8 as compared with injection from the p layer 7 of the pin diode. Since it is much lower than the above, the on-voltage is considerably increased.
【０００６】この発明の目的は、前記の課題を解決し
て、逆回復電流が小さく、かつ、定格電流領域およびサ
ージ電流領域でのオン電圧を低減できる半導体装置を提
供することにある。An object of the present invention is to solve the above problems and to provide a semiconductor device having a small reverse recovery current and a reduced on-voltage in the rated current region and the surge current region.
【０００７】[0007]
【課題を解決するための手段】前記の目的を達成するた
めに、高濃度の第１導電形の第１半導体層上に低濃度の
第１導電形の第２半導体層が形成され、第２半導体層上
に低濃度の第２導電形の第１半導体領域と高濃度の第２
導電形の第２半導体領域とが隣接して選択的に形成さ
れ、第１半導体層表面にオーミック接続する第１金属電
極が形成され、第１半導体領域表面と第２半導体領域表
面とにオーミック接続する第２金属電極が形成される構
造とする。前記の第１半導体領域の表面濃度が１×１０
15ｃｍ-3ないし１×１０17ｃｍ-3で、かつ、第２半導体
領域の表面濃度が１×１０18ｃｍ-3ないし１×１０21ｃ
ｍ-3であるとよい。また第１半導体領域または第２半導
体領域が複数個形成され、その表面形状がストライプ状
もしくはセル状であるとよい。In order to achieve the above-mentioned object, a second semiconductor layer of low concentration first conductivity type is formed on a high concentration first semiconductor layer of first conductivity type, and a second semiconductor layer of low concentration is formed. A first semiconductor region of a second conductivity type having a low concentration and a second semiconductor region having a high concentration of
A second semiconductor region having a conductivity type is selectively formed adjacent to the first semiconductor layer, a first metal electrode is formed on the surface of the first semiconductor layer for ohmic connection, and an ohmic connection is formed on the surface of the first semiconductor region and the surface of the second semiconductor region. The second metal electrode is formed. The surface concentration of the first semiconductor region is 1 × 10
15 cm −3 to 1 × 10 17 cm −3 , and the surface concentration of the second semiconductor region is 1 × 10 18 cm −3 to 1 × 10 21 c
It is good to be m -3 . Further, it is preferable that a plurality of first semiconductor regions or second semiconductor regions be formed and the surface shape thereof be stripe-like or cell-like.
【０００８】図６はｐｉｎダイオードのｐ層の表面濃度
を変えたときの電流・電圧特性を示す。縦軸が電流密度
で横軸がオン電圧を示し、ｐ層の表面濃度は１×１０16
から１×１０19ｃｍ-3まで変化させた。ｐ層の表面濃度
を下げるとオン電圧が上昇し、電流密度とオン電圧の積
で表される発生損失密度も増大する。例えば、図中の発
生損失密度一定カーブ上で比べた場合、１×１０16ｃｍ
-3の電流密度は１×１０19ｃｍ-3の電流密度の半分程度
に減少する。サージ電流領域の電流密度を上げるにはｐ
層の表面濃度を所定の高さまで上げる必要がある。また
ｐ+ 領域の表面濃度はｐ領域の表面濃度よりさらに高く
するとよい。FIG. 6 shows current / voltage characteristics when the surface concentration of the p layer of the pin diode is changed. The vertical axis represents the current density and the horizontal axis represents the on-voltage. The surface concentration of the p layer is 1 × 10 16.
To 1 × 10 19 cm −3 . When the surface concentration of the p layer is lowered, the ON voltage rises, and the generated loss density represented by the product of the current density and the ON voltage also increases. For example, when compared on the curve of the generated loss density shown in the figure, 1 × 10 16 cm
-3 current density is reduced to about half the current density of 1 × 10 19 cm -3. To increase the current density in the surge current area, p
It is necessary to increase the surface concentration of the layer to a certain height. The surface concentration of the p + region may be higher than that of the p region.
【０００９】図７はｐｉｎダイオードのｐ層の表面濃度
を変えたときの逆回復電流波形図を示す。ｐ領域の表面
濃度が小さくなると逆回復電流は小さくなり、ソフトリ
カバリー（逆回復電流の減衰率が小さいこと）となる。FIG. 7 shows a reverse recovery current waveform diagram when the surface concentration of the p layer of the pin diode is changed. When the surface concentration of the p region becomes small, the reverse recovery current becomes small and soft recovery (the attenuation rate of the reverse recovery current is small) is achieved.
【００１０】[0010]
【発明の実施の形態】図１はこの発明の第１実施例で、
同図（ａ）は平面図、同図（ｂ）は同図（ａ）をＹ−Ｙ
線で切断した断面図を示す。同図（ａ）は電極を剥離し
た状態を示し、同図（ｂ）では電極が形成されている状
態を示す。バッファ層となるｎ+ 層２上にｎ- 層１がエ
ピタキシャル成長などにより形成され、ｎ- 層１の表面
層にｐ層をイオン注入で形成した後、ｐ層より深くｐ形
不純物を選択的に導入して、ｐ + 領域５とｐ領域６を形
成する。同図（ａ）ではｐ領域６をｐ+ 領域５で取り囲
んでいるが、逆の場合でもよい。このときはｎ- 層１の
表面層に不純物導入マスクを利用してｐ領域６とｐ+ 領
域５とを隣接して選択的に形成する。また、ｐ領域６の
表面濃度とｐ+ 領域５の表面濃度の中間の表面濃度を有
する領域を追加して複数個形成してもよい。しかし、こ
のような中間の領域を追加すると製造工程が増すため、
実用的にはｐ領域６とｐ+ 領域５の２種類がよい。ま
た、カソード電極４とアノード電極３はオーミック性の
電極材料であるＡｌ−Ｓｉを蒸着することで形成され
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a first embodiment of the present invention.
The figure (a) is a top view, the figure (b) shows the figure (a) YY.
A sectional view taken along a line is shown. In the figure (a), the electrode is peeled off.
The state in which electrodes are formed is shown in FIG.
State. Buffer layer n+N on layer 2-Layer 1 is
Formed by epitaxial growth, etc.-Layer 1 surface
After forming the p-layer in the layer by ion implantation, p-type deeper than the p-layer
By introducing impurities selectively, p +Form region 5 and p region 6
To achieve. In FIG. 7A, the p region 6 is set to p+Surrounded by Area 5
However, the reverse is also possible. Then n-Layer 1
Using the impurity introduction mask in the surface layer, p regions 6 and p+Territory
Regions 5 and 5 are formed adjacently and selectively. In addition, in the p region 6
Surface concentration and p+With a surface density intermediate between the surface density of area 5
A plurality of regions may be added to form a plurality of regions. But this
Since adding an intermediate area such as increases the manufacturing process,
Practically p region 6 and p+Two types of area 5 are preferable. Ma
In addition, the cathode electrode 4 and the anode electrode 3 have ohmic characteristics.
It is formed by depositing Al-Si, which is an electrode material
You.
【００１１】このダイオードはｐ形の領域がｐ+ 領域５
とｐ領域６の２種類で形成されるため、ｎ- 層１との接
合もｐ+ ｎ- 接合とｐｎ- 接合の２種類となる。従っ
て、ダイオードの通電電流が小さい領域では、えん層電
圧（フェルミレベル差で生じる半導体内部の電圧）が小
さいｐｎ- 接合に電流が流れ、通電電流が大きくなると
オン電圧が増大してえん層電圧の大きいｐ+ ｎ- 接合に
も電流は流れるようになる。従って、定格電流領域（サ
ージ電流と比べかなり小さい領域てある）ではオン電圧
の比較的小さい領域となるため、電流はｐｎ- 接合部を
流れ、従って、ｐ領域６からの正孔の注入が少なく、過
剰キャリアの量は少なくなるので逆回復電流は小さく、
逆回復損失も小さくなる。また逆回復電流波形もソフト
リカバリーとなる。一方、サージ電流領域ではオン電圧
が大きくなり、えん層電圧の大きいｐ+ ｎ- 接合を通し
て流れる電流が支配的となり、このｐ+ 領域５からの多
量の正孔の注入により、大電流領域でもオン電圧は比較
的小さくなる。実用的には定格電流領域での逆回復電流
を小さく、ソフトリカバリーとするためにはｐ領域６の
表面濃度を１×１０15ｃｍ-3〜１×１０17ｃｍ-3の範囲
がよく（さらに望ましくは１×１０16ｃｍ-3〜１×１０
17ｃｍ-3の範囲がよい）、サージ電流領域でのオン電圧
を比較的小さく抑制するためにはｐ+ 領域５の表面濃度
を１×１０18ｃｍ-3〜１×１０21の範囲がよい。尚、逆
回復電流が小さいということはダイオードの逆回復耐量
が大きいことを意味し、また大電流領域でのオン電圧が
大きくないことはサージ電流耐量が大きいことを意味す
る。In this diode, the p-type region is the p + region 5
And the p region 6, the junction with the n − layer 1 is also two types of p + n − junction and pn − junction. Therefore, in the region where the current flowing through the diode is small, a current flows through the pn - junction with a small engraving layer voltage (voltage inside the semiconductor caused by the Fermi level difference), and when the energizing current increases, the on-voltage increases and the engraving layer voltage increases. A current also flows through the large p + n - junction. Therefore, in the rated current region (which is considerably smaller than the surge current), the on-state voltage is relatively small, so that the current flows through the pn - junction, so that the injection of holes from the p region 6 is small. , The amount of excess carriers is small, so the reverse recovery current is small,
Reverse recovery loss is also small. The reverse recovery current waveform also becomes soft recovery. On the other hand, in the surge current region, the ON voltage becomes large, and the current flowing through the p + n - junction having a large arm layer voltage becomes dominant, and due to the injection of a large amount of holes from the p + region 5, the ON current also becomes large. The voltage is relatively small. Practically, the reverse recovery current in the rated current region is small, and in order to achieve soft recovery, the surface concentration of the p region 6 is preferably in the range of 1 × 10 15 cm −3 to 1 × 10 17 cm −3 (more Desirably 1 × 10 16 cm −3 to 1 × 10
17 good range of cm -3), in order to relatively suppressed small on-voltage of the surge current region a surface concentration of the p + regions 5 1 × 10 18 cm -3 ~1 × 10 21 range of good . It should be noted that a small reverse recovery current means that the reverse recovery withstand capability of the diode is large, and that the on-voltage in the large current region is not large means that the surge current withstand capability is large.
【００１２】図２はこの発明の第２実施例で、同図
（ａ）は平面図、同図（ｂ）は同図（ａ）をＸ−Ｘ線で
切断した断面図を示す。同図（ａ）は電極を剥離した状
態を示し、同図（ｂ）では電極が形成されている状態を
示す。第１実施例のｐ領域６を複数個ストライプ状に配
置したものである。勿論、ｐ領域６とｐ+ 領域５を入替
えても構わない。その場合は、前記したようにｎ- 層１
の表面層に不純物導入マスクを利用してｐ領域６とｐ+
領域５とを隣接して選択的に形成する。またｐ領域６お
よびｐ+ 領域５の表面濃度については第１実施例と同じ
である。また、この構造の長所はｐ領域６の表面濃度が
低くなった場合でも、逆バイアス時にｐ+ 領域５からｐ
領域６に延びる空乏層でｐ領域６がピンチオフし、その
ため、耐圧の低下を防ぐことができる。この考えは図５
で示すｐ- ｉｎダイオードであるＳＳＤ（Static Shiel
ding Diode）やＳＦＤ（Softand Fast Recavary Diode)
でも同様であるが、これらのダイオードのｐ+ 領域の形
成は耐圧を維持することのみが目的であり、一方、この
発明のダイオードでは大電流領域で積極的に電流を流し
オン電圧の増大を抑制することが目的である。従って、
ｐ+ 領域形成の目的が従来のダイオードとこの発明のダ
イオードでは大きく異なる。FIG. 2 shows a second embodiment of the present invention. FIG. 2 (a) is a plan view and FIG. 2 (b) is a sectional view taken along line XX of FIG. 2 (a). The figure (a) shows the state where the electrode was peeled off, and the figure (b) shows the state where the electrode is formed. A plurality of p regions 6 of the first embodiment are arranged in stripes. Of course, the p region 6 and the p + region 5 may be exchanged. In that case, as described above, n − layer 1
Of the p region 6 and p + using the impurity introduction mask on the surface layer of
Regions 5 and 5 are formed adjacently and selectively. The surface concentrations of p region 6 and p + region 5 are the same as in the first embodiment. In addition, the advantage of this structure is that even when the surface concentration of the p region 6 becomes low, the p + region 5 to the p region 5 are reverse-biased when reverse biased.
In the depletion layer extending to the region 6, the p region 6 is pinched off, and therefore the breakdown voltage can be prevented from lowering. This idea is shown in Figure 5.
SSD (Static Shiel) which is a p - in diode
Ding Diode) and SFD (Soft and Fast Recavary Diode)
However, similarly, the formation of the p + region of these diodes is intended only to maintain the breakdown voltage. On the other hand, in the diode of the present invention, the current is positively flowed in the large current region to suppress the increase of the on-voltage. The purpose is to do. Therefore,
The purpose of forming the p + region is significantly different between the conventional diode and the diode of the present invention.
【００１３】図３はこの発明の第３実施例で、同図
（ａ）は平面図、同図（ｂ）は同図（ａ）をＸ−Ｘ線で
切断した断面図を示す。同図（ａ）は電極を剥離した状
態を示し、同図（ｂ）では電極が形成されている状態を
示す。図２（ａ）との違いはｐ領域の平面形状が円形の
セル状となっている点であり、その他は同一である。
尚、ｐ領域の平面形状は多角形でも勿論よい。FIG. 3 shows a third embodiment of the present invention. FIG. 3 (a) is a plan view and FIG. 3 (b) is a sectional view taken along line XX in FIG. 3 (a). The figure (a) shows the state where the electrode was peeled off, and the figure (b) shows the state where the electrode is formed. The difference from FIG. 2A is that the planar shape of the p region is a circular cell shape, and the others are the same.
The plane shape of the p region may be polygonal.
【００１４】[0014]
【発明の効果】この発明によれば、ｐ領域とｐ+ 領域の
２種類のｐ形の領域を設け、それらの表面濃度を所定の
値に制御することで、従来のダイオードよりも、定格電
流領域における逆回復特性（逆回復耐量やソフトリカバ
リーなど）と大電流領域におけるサージ電流耐量を大幅
に向上させる。According to the present invention, two types of p-type regions, a p region and ap + region, are provided and their surface concentrations are controlled to a predetermined value, so that the rated current is higher than that of the conventional diode. Reverse recovery characteristics (reverse recovery withstand and soft recovery) in the area and surge current withstand in the large current area are greatly improved.
【図１】この発明の第１実施例で、（ａ）は平面図、
（ｂ）は（ａ）をＹ−Ｙ線で切断した断面図FIG. 1 is a plan view of a first embodiment of the present invention,
(B) is sectional drawing which cut | disconnected (a) by the YY line.
【図２】この発明の第２実施例で、（ａ）は平面図、
（ｂ）は（ａ）をＸ−Ｘ線で切断した断面図FIG. 2 is a second embodiment of the present invention, (a) is a plan view,
(B) is a cross-sectional view taken along line XX of (a)
【図３】この発明の第３実施例で、（ａ）は平面図、
（ｂ）は（ａ）をＸ−Ｘ線で切断した断面図FIG. 3 is a plan view of a third embodiment of the present invention,
(B) is a cross-sectional view taken along line XX of (a)
【図４】高耐圧で使用されている従来のｐｉｎダイオー
ドの断面図FIG. 4 is a cross-sectional view of a conventional pin diode used for high breakdown voltage.
【図５】従来のｐ- ｉｎダイオードの断面図FIG. 5 is a sectional view of a conventional p - in diode.
【図６】ｐｉｎダイオードのｐ層の表面濃度を変えたと
きの電流・電圧特性図FIG. 6 is a current / voltage characteristic diagram when the surface concentration of the p layer of the pin diode is changed.
【図７】ｐｉｎダイオードのｐ層の表面濃度を変えたと
きの逆回復電流波形図FIG. 7 is a reverse recovery current waveform diagram when the surface concentration of the p layer of the pin diode is changed.
１ ｎ- 領域 ２ ｎ+ 領域 ３ アノード電極 ４ カソード電極 ５ ｐ+ 領域 ６ ｐ領域 ７ ｐ層 ８ ｐ- 領域 ９ ｐ+ 領域1 n − Region 2 n + Region 3 Anode Electrode 4 Cathode Electrode 5 p + Region 6 p Region 7 p Layer 8 p − Region 9 p + Region
Claims (4)
濃度の第１導電形の第２半導体層が形成され、第２半導
体層上に低濃度の第２導電形の第１半導体領域と高濃度
の第２導電形の第２半導体領域とが隣接して選択的に形
成され、第１半導体層表面にオーミック接続する第１金
属電極が形成され、第１半導体領域表面と第２半導体領
域表面とにオーミック接続する第２金属電極が形成され
ることを特徴とする半導体装置。1. A second semiconductor layer having a low concentration first conductivity type is formed on a first semiconductor layer having a high concentration first conductivity type, and a second semiconductor layer having a low concentration second conductivity type is formed on a second semiconductor layer. A first semiconductor region and a high-concentration second conductivity type second semiconductor region are selectively formed adjacent to each other, and a first metal electrode is formed on the surface of the first semiconductor layer to make ohmic contact; A semiconductor device having a second metal electrode formed in ohmic contact with the surface of the second semiconductor region.
ｍ-3ないし１×１０ 17ｃｍ-3で、かつ第２半導体領域の
表面濃度が１×１０18ｃｍ-3ないし１×１０ 21ｃｍ-3で
あることを特徴とする請求項１記載の半導体装置。2. The surface concentration of the first semiconductor region is 1 × 10.Fifteenc
m-3Or 1 × 10 17cm-3And in the second semiconductor region
Surface concentration is 1 × 1018cm-3Or 1 × 10 twenty onecm-3so
The semiconductor device according to claim 1, wherein the semiconductor device is present.
面形状がストライプ状もしくはセル状であることを特徴
とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein a plurality of first semiconductor regions are formed and the surface shape thereof is a stripe shape or a cell shape.
面形状がストライプ状もしくはセル状であることを特徴
とする請求項１記載の半導体装置。4. The semiconductor device according to claim 1, wherein a plurality of second semiconductor regions are formed, and the surface shape is a stripe shape or a cell shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33629895A JPH09181334A (en) | 1995-12-25 | 1995-12-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33629895A JPH09181334A (en) | 1995-12-25 | 1995-12-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09181334A true JPH09181334A (en) | 1997-07-11 |
Family
ID=18297667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33629895A Pending JPH09181334A (en) | 1995-12-25 | 1995-12-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09181334A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002502128A (en) * | 1998-02-02 | 2002-01-22 | ユニアックス コーポレイション | X-Y addressable electrical microswitch array and sensor matrix using the same |
| JP2006019528A (en) * | 2004-07-01 | 2006-01-19 | Fuji Electric Holdings Co Ltd | Semiconductor apparatus |
| JP2008047565A (en) * | 2006-08-10 | 2008-02-28 | Denso Corp | Diode |
| JP2018029150A (en) * | 2016-08-19 | 2018-02-22 | サンケン電気株式会社 | Semiconductor device |
-
1995
- 1995-12-25 JP JP33629895A patent/JPH09181334A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002502128A (en) * | 1998-02-02 | 2002-01-22 | ユニアックス コーポレイション | X-Y addressable electrical microswitch array and sensor matrix using the same |
| JP2006019528A (en) * | 2004-07-01 | 2006-01-19 | Fuji Electric Holdings Co Ltd | Semiconductor apparatus |
| JP2008047565A (en) * | 2006-08-10 | 2008-02-28 | Denso Corp | Diode |
| JP2018029150A (en) * | 2016-08-19 | 2018-02-22 | サンケン電気株式会社 | Semiconductor device |
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