JPH09172021A - Semiconductor device and manufacturing method and packaging method thereof - Google Patents
Semiconductor device and manufacturing method and packaging method thereofInfo
- Publication number
- JPH09172021A JPH09172021A JP7349355A JP34935595A JPH09172021A JP H09172021 A JPH09172021 A JP H09172021A JP 7349355 A JP7349355 A JP 7349355A JP 34935595 A JP34935595 A JP 34935595A JP H09172021 A JPH09172021 A JP H09172021A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- chip
- electrodes
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1183—Reworking, e.g. shaping
- H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【目次】以下の順序で本発明を説明する。 発明の属する技術分野 従来の技術（図６及び図７） 発明が解決しようとする課題（図８） 課題を解決するための手段 発明の実施の形態（図１〜図５） 発明の効果[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD OF THE INVENTION Conventional Technology (FIGS. 6 and 7) Problem to be Solved by the Invention (FIG. 8) Means for Solving the Problem Embodiments of the Invention (FIGS. 1 to 5)
【０００２】[0002]
【発明の属する技術分野】本発明は半導体装置、半導体
装置の製造方法及び実装方法に関し、例えばベアチツプ
型のＩＣチツプに適用して好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing the semiconductor device and a method of mounting the semiconductor device, and is suitable for application to, for example, a bare chip type IC chip.
【０００３】[0003]
【従来の技術】近年、電子機器の小型化に伴い、基板へ
の電子部品の高密度実装技術が注目されている。この種
の高密度実装技術として、例えばＩＣチツプをモールド
せずに裸のまま基板上に実装する方法（以下、これをベ
アチツプ実装方法と呼ぶ）が提案され、実施されてい
る。2. Description of the Related Art In recent years, with the miniaturization of electronic devices, a high-density mounting technique of electronic components on a substrate has attracted attention. As a high-density mounting technique of this kind, for example, a method of mounting an IC chip on a substrate without molding it without molding (hereinafter referred to as a bare chip mounting method) has been proposed and implemented.
【０００４】実際上このようなベアチツプ実装方法とし
て例えばフリツプチツプ実装法があり、このフリツプチ
ツプ実装法として例えば異方性導電膜を介してＩＣチツ
プと基板とを直接接続するものがある。この異方性導電
膜を用いるフリツプチツプ実装法では、以下の手順によ
りＩＣチツプを基板上に実装している。In practice, there is, for example, a flip-chip mounting method as such a bare-chip mounting method, and as this flip-chip mounting method, for example, there is one in which the IC chip and the substrate are directly connected via an anisotropic conductive film. In the flip chip mounting method using this anisotropic conductive film, the IC chip is mounted on the substrate by the following procedure.
【０００５】すなわち図６（Ａ）に示すように、例えば
めつき法やボールボンデイング法を用いてＩＣチツプ１
に設けられた各パツド１Ａ上に金（Ａｕ）やはんだ等で
表面が平坦なバンプ２を形成すると共に、基板３上に形
成された各ランド３Ａを覆うように異方性導電膜４を所
定の厚さに形成する。続いて図６（Ｂ）に示すように、
ＩＣチツプ１のパツド１Ａが形成されている回路面１Ｂ
を基板３のランド３Ａが設けられている回路面３Ｂ側に
対向させてＩＣチツプ１を異方性導電膜４に位置決めし
てマウントした後、各バンプ２が異方性導電膜４に埋め
込まれるようにＩＣチツプ１を所定の圧力で基板３に押
し当てることにより、ＩＣチツプ１を基板３上に実装す
る。That is, as shown in FIG. 6A, the IC chip 1 is manufactured by using, for example, a plating method or a ball bonding method.
Bumps 2 having a flat surface are formed with gold (Au), solder or the like on each pad 1A provided on the substrate 1, and an anisotropic conductive film 4 is provided so as to cover each land 3A formed on the substrate 3. To the thickness of. Then, as shown in FIG. 6 (B),
The circuit surface 1B on which the pad 1A of the IC chip 1 is formed
The IC chip 1 is positioned and mounted on the anisotropic conductive film 4 by facing the circuit surface 3B side of the substrate 3 on which the land 3A is provided, and then each bump 2 is embedded in the anisotropic conductive film 4. Thus, the IC chip 1 is mounted on the substrate 3 by pressing the IC chip 1 against the substrate 3 with a predetermined pressure.
【０００６】ここで異方性導電膜４は例えばエポキシ樹
脂等の樹脂中に５〜20〔μｍ〕程度の導電性粒子（Ａｕ
等）が分散されてなる導電材料であり、ＩＣチツプ１と
基板３によつて挟み込まれた方向だけに導電性を示すも
のであり、基板３に平行な方向には導電性を示さないも
のである。従つて図７に示すように、異方性導電膜４中
に存在する導電性粒子４ＡによつてＩＣチツプ１及び基
板３のそれぞれ対応するバンプ２及びランド３Ａが電気
的に接合され、これによりＩＣチツプ１と基板３とが電
気的に接続されるようになされている。Here, the anisotropic conductive film 4 is made of, for example, a resin such as an epoxy resin and conductive particles (Au) of about 5 to 20 [μm].
Etc. are dispersed in the conductive material, exhibit conductivity only in the direction sandwiched by the IC chip 1 and the substrate 3, and do not exhibit conductivity in the direction parallel to the substrate 3. is there. Therefore, as shown in FIG. 7, the bumps 2 and the lands 3A corresponding to the IC chip 1 and the substrate 3 are electrically joined by the conductive particles 4A present in the anisotropic conductive film 4. The IC chip 1 and the substrate 3 are electrically connected.
【０００７】[0007]
【発明が解決しようとする課題】ところで近年、ＩＣの
高集積化に伴つてＩＣチツプ１上に形成される各パツド
１Ｂ間のフアインピツチ化が急速に進展しており、この
ような状況において、上述の異方性導電膜４を用いたフ
リツプチツプ実装法によつてＩＣチツプ１を基板３上に
実装する場合、フアインピツチ化に対応して異方性導電
膜４中の導電性粒子４Ａの数を増やさなければならな
い。By the way, in recent years, with the high integration of ICs, the progress of fine pitch between the pads 1B formed on the IC chip 1 is rapidly progressing. When the IC chip 1 is mounted on the substrate 3 by the flip-chip mounting method using the anisotropic conductive film 4, the number of the conductive particles 4A in the anisotropic conductive film 4 is increased corresponding to the fine pitch. There must be.
【０００８】ところが異方性導電膜４中の導電性粒子４
Ａの数が増えると、図８に示すように、ＩＣチツプ１の
各パツド１Ｂ間及び基板３上の各ランド３Ａ間のピツチ
が小さいため、異方性導電膜４中の導電性粒子４Ａが隣
接するバンプ２間及びランド３Ａ間に跨がつた状態でバ
ンプ２とランド３Ａが接合され、この結果電気的にシヨ
ートするおそれがあつた。However, the conductive particles 4 in the anisotropic conductive film 4
As the number of A increases, as shown in FIG. 8, the pitch between the pads 1B of the IC chip 1 and between the lands 3A on the substrate 3 becomes small. The bumps 2 and the lands 3A are bonded to each other in a state of straddling the adjacent bumps 2 and the lands 3A, and as a result, there is a risk of electrical shorting.
【０００９】このような問題を解決する１つの方法とし
て、異方性導電膜４に代えて絶縁膜を用い、ＩＣチツプ
１を基板３に対して所定の圧力で押し当てて各バンプ２
をそれぞれ対応するランド３に直接接合させることによ
りＩＣチツプ１と基板３とを電気的に接続する方法が考
えられる。ところがこの方法では、バンプ２の表面が平
坦であるため各バンプ２によつて絶縁膜を突き破つて各
バンプ２を対応する各ランド３Ａに接合させるとは困難
であり、またバンプ２とランド３Ａ間に絶縁膜が残つて
接続不良を起こすおそれがあつた。As one method for solving such a problem, an insulating film is used in place of the anisotropic conductive film 4, and the IC chip 1 is pressed against the substrate 3 with a predetermined pressure to form each bump 2.
A method may be considered in which the IC chip 1 and the substrate 3 are electrically connected to each other by directly bonding the respective to the corresponding lands 3. However, in this method, since the surface of the bump 2 is flat, it is difficult to break through the insulating film by each bump 2 to join each bump 2 to each corresponding land 3A. There is a risk that an insulating film will remain between them and cause a connection failure.
【００１０】さらにバンプ２の形成方法によつては、パ
ツト１Ｂ上に形成された各バンプ２の高さが不均一にな
り、このような状態でＩＣチツプ１を基板３に実装した
場合、全てのバンプ２を確実にランド３Ａに接合させる
ことができず、接続不良を起こすおそれがあつた。Further, according to the method of forming the bumps 2, the heights of the bumps 2 formed on the pad 1B become uneven, and when the IC chip 1 is mounted on the substrate 3 in such a state, However, the bumps 2 could not be reliably joined to the lands 3A, and there was a risk of defective connections.
【００１１】本発明は以上の点を考慮してなされたもの
で、基板上への実装の信頼性を向上し得る半導体装置、
当該半導体装置の製造方法及び信頼性を向上し得る実装
方法を提案しようとするものである。The present invention has been made in consideration of the above points, and is a semiconductor device capable of improving the reliability of mounting on a substrate,
It is intended to propose a manufacturing method of the semiconductor device and a mounting method capable of improving reliability.
【００１２】[0012]
【課題を解決するための手段】かかる課題を解決するた
め第１の発明においては、半導体装置は、当該半導体装
置の一面に設けられた複数の電極と、当該各電極上にそ
れぞれ形成された錐形状のバンプとを有する。In order to solve such a problem, in the first invention, a semiconductor device has a plurality of electrodes provided on one surface of the semiconductor device and cones formed on the respective electrodes. And a bump having a shape.
【００１３】また第２の発明においては、半導体装置の
一面に形成された複数の電極上にそれぞれ所定の導電部
材を供給し、各電極上にそれぞれ供給された各導電部材
を錐形状に成型する。In the second aspect of the invention, a predetermined conductive member is supplied onto each of a plurality of electrodes formed on one surface of the semiconductor device, and each conductive member supplied onto each electrode is shaped into a cone. .
【００１４】さらに第３の発明においては、一面に複数
のバンプが形成された半導体装置の当該一面を、それぞ
れ基板上に設けられた対応する接合部を覆うように形成
された絶縁膜に押しつけることにより、各バンプを対応
する各接合部に接合する工程を経て基板上に半導体装置
を実装する実装方法において、半導体装置の一面に形成
された各電極上にそれぞれ所定の導電部材を供給し、各
電極上にそれぞれ供給された各導電部材を錐形状に成型
し、半導体装置を絶縁膜上に位置決めしてマウントした
後、半導体装置を所定の圧力で基板に押しつけることに
より、各導電部材をそれぞれ対応する各接合部に圧着す
る。Further, in the third invention, the one surface of the semiconductor device having a plurality of bumps formed on the one surface is pressed against an insulating film formed so as to cover the corresponding joint portions provided on the substrate, respectively. Thus, in the mounting method of mounting the semiconductor device on the substrate through the step of bonding each bump to the corresponding bonding portion, a predetermined conductive member is supplied onto each electrode formed on one surface of the semiconductor device, Each conductive member supplied to the electrode is molded into a cone shape, the semiconductor device is positioned and mounted on the insulating film, and then the semiconductor device is pressed against the substrate with a predetermined pressure to correspond each conductive member. Crimp to each joint.
【００１５】第１の発明においては、半導体装置の各電
極上にそれぞれ形成された各バンプが錐形状であるの
で、当該半導体装置の電極間ピツチが小さい場合でも、
半導体装置を基板上に実装した際、各バンプを基板の対
応する電極に確実に接合させることができるので、接続
不良を確実に防止することができる。In the first aspect of the present invention, since each bump formed on each electrode of the semiconductor device has a conical shape, even if the pitch between the electrodes of the semiconductor device is small,
When the semiconductor device is mounted on the substrate, each bump can be surely joined to the corresponding electrode of the substrate, so that the connection failure can be surely prevented.
【００１６】第２の発明においては、半導体装置の一面
に形成された複数の電極上にそれぞれ所定の導電部材を
供給し、各電極上にそれぞれ供給された各導電部材を錐
形状に成型したことにより、当該半導体装置の電極間ピ
ツチが小さい場合でも、半導体装置を基板上に実装した
際、各バンプを基板の対応する電極に確実に接合させる
ことができるので、接続不良を確実に防止することがで
きる。In the second invention, a predetermined conductive member is supplied onto each of a plurality of electrodes formed on one surface of the semiconductor device, and each conductive member supplied onto each electrode is molded into a pyramidal shape. Thus, even when the pitch between the electrodes of the semiconductor device is small, when the semiconductor device is mounted on the substrate, each bump can be reliably bonded to the corresponding electrode of the substrate, so that the connection failure can be reliably prevented. You can
【００１７】第３の発明においては、半導体装置の各電
極上にそれぞれ供給された各導電部材を錐形状に成型
し、半導体装置を絶縁膜上に位置決めしてマウントした
後、半導体装置を所定の圧力で基板に押しつけて、各導
電部材をそれぞれ対応する各接合部に圧着することによ
り、各導電部材を基板の対応する電極に確実に接合させ
ることができるので、接続不良を確実に防止することが
できる。In the third aspect of the invention, each conductive member supplied on each electrode of the semiconductor device is molded into a conical shape, the semiconductor device is positioned and mounted on the insulating film, and then the semiconductor device is predetermined. By pressing against the substrate with pressure and crimping each conductive member to each corresponding joint part, each conductive member can be surely joined to the corresponding electrode on the substrate, so it is possible to reliably prevent connection failure. You can
【００１８】[0018]
【発明の実施の形態】以下図面について、本発明の一実
施例を詳述する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.
【００１９】図１において、１０は全体として実施例に
よるベアチツプ型のＩＣチツプを示し、基板１１との対
向面１０Ａ上に当該ＩＣチツプ１０と基板１１とを接合
する例えばＡｕでなるバンプ１２が、ＩＣチツプ１０の
対向面１０Ａに設けられた各パツド１０Ｂ上にそれぞれ
ほぼ同じ高さでほぼ円錐形状に形成されている。すなわ
ちこのＩＣチツプ１０は、当該ＩＣチツプ１０を基板１
１上に実装した際、各パツド１０Ｂ上にそれぞれ形成さ
れた各バンプ１２が、基板１１の対応するランド１１Ａ
とそれぞれ直接接合することにより基板１１上に実装さ
れ得るようになされている。In FIG. 1, reference numeral 10 indicates a bare chip type IC chip according to the embodiment as a whole, and a bump 12 made of, for example, Au for bonding the IC chip 10 and the substrate 11 is formed on a surface 10A facing the substrate 11. The pads 10B provided on the facing surface 10A of the IC chip 10 have substantially the same height and a substantially conical shape. In other words, this IC chip 10 uses the IC chip 10 for the substrate 1
1 is mounted on the pad 10, the bumps 12 formed on the pads 10B respectively correspond to the corresponding lands 11A on the substrate 11.
It can be mounted on the substrate 11 by directly bonding the respective components.
【００２０】この場合、図２に示すように、各バンプ１
２は全体としてほぼ円錐形状に形成されており、ＩＣチ
ツプ１０を基板１１上に実装した際、各バンプ１２の円
錐部１２Ａが基板１１の対応する各ランド１１Ａを覆う
ように形成された絶縁膜１３を突き破ることにより、基
板１１上の対応するランド１１Ａにそれぞれ接合し得る
ようになされている。In this case, as shown in FIG. 2, each bump 1
2 is formed in a substantially conical shape as a whole, and when the IC chip 10 is mounted on the substrate 11, an insulating film formed so that the conical portion 12A of each bump 12 covers each corresponding land 11A of the substrate 11. By breaking through 13, the respective lands 11A on the substrate 11 can be joined to each other.
【００２１】実際上このＩＣチツプ１０は、以下の工程
により製造することができる。すなわちまずＩＣチツプ
１０上に設けられた各パツド１０Ｂ上にボールボンデイ
ング法によつてＡｕでなる導電部材１２′を供給（図３
（Ａ））した後、先端部２０Ａに円錐形状の凹部２０Ｂ
が設けられたセラミツクスでなるバンプ成型装置２０
（図４（Ａ））を導電部材１２′の真上から導電部材１
２′に近接する方向に降下移動させて（図３（Ｂ））、
バンプ成型装置２０の凹部２０Ｂを導電部材１２′に所
定の圧力で押し当てる（図３（Ｃ））。その後バンプ成
型装置２０を導電部材１２′から離反する方向に上昇さ
せる（図３（Ｄ））。In practice, this IC chip 10 can be manufactured by the following steps. That is, first, a conductive member 12 'made of Au is supplied onto each pad 10B provided on the IC chip 10 by a ball bonding method (see FIG. 3).
(A)), the conical recess 20B is formed on the tip 20A.
Bump forming apparatus 20 made of ceramics provided with
(FIG. 4A) shows the conductive member 1 from directly above the conductive member 12 '.
Move it downward in the direction of 2 '(Fig. 3 (B)),
The recess 20B of the bump forming device 20 is pressed against the conductive member 12 'with a predetermined pressure (FIG. 3 (C)). After that, the bump forming device 20 is lifted in a direction away from the conductive member 12 '(FIG. 3D).
【００２２】ここで図４（Ａ）に示すように、バンプ成
型装置２０には駆動部２１が設けられており、バンプ成
型装置２０は駆動部２１の制御に基づいて、導電部材１
２′の突起部１２Ａ′がバンプ成型装置２０の凹部２０
Ｂ内に嵌め込まれるように位置決めされるようになされ
ている。この場合、各導電部材１２′はボールボンデイ
ング法によつて形成されることにより、図３（Ａ）に示
すように突起部１２Ａ′が形成され、しかも導電部材１
２′として展延性に優れたＡｕを用いているので、バン
プ成型装置２０によつて突起部１２Ａ′を容易に円錐部
１２Ａに成型し得る。As shown in FIG. 4 (A), the bump forming apparatus 20 is provided with a drive unit 21, and the bump forming apparatus 20 is controlled by the drive unit 21 to control the conductive member 1.
The 2'projection 12A 'is the recess 20 of the bump molding apparatus 20.
It is positioned so that it can be fitted into B. In this case, each conductive member 12 'is formed by the ball bonding method to form the projection 12A' as shown in FIG.
Since Au having excellent spreadability is used as 2 ', the projection 12A' can be easily formed into the conical portion 12A by the bump forming apparatus 20.
【００２３】従つてバンプ成型装置２０の凹部２０Ｂを
各導電部材１２′に所定の圧力で押し当てることによ
り、導電部材１２′の突起部１２Ａ′をバンプ成型装置
２０の凹部２０Ｂに応じた円錐形状の円錐部１２Ａを有
するバンプ１２に成型することができると共に、各バン
プ１２の高さをほぼ同じ高さに形成することができる。
かくして図１に示すようなほぼ同じ高さで円錐形状でな
るバンプ１２を有するＩＣチツプ１０を製造することが
できる。Accordingly, by pressing the concave portion 20B of the bump forming apparatus 20 against each conductive member 12 'with a predetermined pressure, the protrusion 12A' of the conductive member 12 'is shaped like a cone corresponding to the concave portion 20B of the bump forming apparatus 20. The bumps 12 having the conical portions 12A can be molded, and the heights of the bumps 12 can be formed to be substantially the same.
Thus, it is possible to manufacture the IC chip 10 having the conical bumps 12 at substantially the same height as shown in FIG.
【００２４】以上の構成において、このＩＣチツプ１０
は、以下の工程により基板１１上に実装することができ
る。すなわちまず図５（Ａ）に示すように、ＩＣチツプ
１０の回路面１０Ａ側を基板１１の絶縁膜１３側に対向
させてＩＣチツプ１０を絶縁膜１３上に位置決めしてマ
ウントした後、ＩＣチツプ１０を例えば１バンプ当たり
20ｇ／Ｆ〜50ｇ／Ｆの圧力で基板１１に押しつける。In the above structure, the IC chip 10
Can be mounted on the substrate 11 by the following steps. That is, first, as shown in FIG. 5A, the IC chip 10 is positioned and mounted on the insulating film 13 with the circuit surface 10A side of the IC chip 10 facing the insulating film 13 side of the substrate 11, and then the IC chip 10 is mounted. 10 per bump
The substrate 11 is pressed with a pressure of 20 g / F to 50 g / F.
【００２５】この場合、図５（Ｂ）に示すように、この
ＩＣチツプ１０は、各バンプ１２の円錐部１２Ａが絶縁
膜１３を突き破つて対応するランド１１Ａにそれぞれ当
接した後、図５（Ｃ）に示すように、対応する各ランド
１１Ａの表面にならつてほぼ平坦に変形されて対応する
ランド１１Ａと面接触し、これによりＩＣチツプ１０と
基板１１とが接続される。In this case, as shown in FIG. 5B, in the IC chip 10, after the conical portion 12A of each bump 12 breaks through the insulating film 13 and comes into contact with the corresponding land 11A, the IC chip 10 shown in FIG. As shown in (C), the surface of each corresponding land 11A is deformed to be substantially flat and comes into surface contact with the corresponding land 11A, whereby the IC chip 10 and the substrate 11 are connected.
【００２６】従つてこのＩＣチツプ１０では、円錐形状
でなるバンプ１２によつて絶縁膜１３を突き破ることが
できるので、各バンプ１２を基板１１の対応するランド
１１Ｂにそれぞれ直接接合させることができ、これによ
り、ＩＣチツプ１０のパツド１０Ｂ間のピツチが小さい
場合でも、ＩＣチツプ１０を基板１１上に実装した際、
各パツド１２を基板１１の対応する各ランド１１Ａ上に
確実に接合させることができるので、接続不良を確実に
回避することができる。Therefore, in the IC chip 10, since the insulating film 13 can be pierced by the bumps 12 having a conical shape, each bump 12 can be directly bonded to the corresponding land 11B of the substrate 11, Accordingly, even when the pitch between the pads 10B of the IC chip 10 is small, when the IC chip 10 is mounted on the substrate 11,
Since each pad 12 can be surely joined to each corresponding land 11A of the substrate 11, the connection failure can be surely avoided.
【００２７】また円錐形状でなるバンプ１２によつて絶
縁膜１３を突き破ることができるので各バンプ１２と各
ランド１１Ａとの間に絶縁膜１３が残ることを防止する
ことができ、これにより接続不良を回避することができ
る。さらにＩＣチツプ１０の各バンプ１０Ｂと基板１１
の各ランド１１Ａとを面接触させることができるので、
各バンプ１０Ｂとランド１１Ａとの接合の信頼性を一段
と向上させることができる。Further, since the insulating film 13 can be pierced by the cone-shaped bumps 12, it is possible to prevent the insulating film 13 from remaining between the bumps 12 and the lands 11A, which results in a defective connection. Can be avoided. Further, each bump 10B of the IC chip 10 and the substrate 11
Since each land 11A can be brought into surface contact,
The reliability of the bonding between each bump 10B and the land 11A can be further improved.
【００２８】さらにバンプ１２を円錐状に成型したこと
により、各ランド１１Ａが絶縁膜１３で覆われた基板１
１に適用し得るので、従来のように異方性導電膜４で覆
われた基板３に比して、ＩＣチツプが基板に実装された
実装基板の製造コストを低減することができる。さらに
ＩＣチツプ１０の各パツド１０Ｂ上にバンプ成型装置２
０を用いて円錐形状のバンプ１２を形成したことによ
り、ＩＣチツプ１０の各パツド１０Ｂ上にほぼ同じ高さ
を有するバンプ１２を形成し得るので、ＩＣチツプ１０
の各パツドと基板１１の対応するランド１１Ａとを一段
と確実に接合することができる。Further, by forming the bumps 12 into a conical shape, the substrate 1 in which each land 11A is covered with the insulating film 13 is formed.
Therefore, the manufacturing cost of the mounting board in which the IC chip is mounted on the board can be reduced as compared to the conventional board 3 covered with the anisotropic conductive film 4. Further, a bump forming device 2 is provided on each pad 10B of the IC chip 10.
Since the bumps 12 having a conical shape are formed by using 0, the bumps 12 having substantially the same height can be formed on each pad 10B of the IC chip 10.
The respective pads and the corresponding lands 11A of the substrate 11 can be more reliably joined.
【００２９】以上の構成によれば、ＩＣチツプ１０の各
パツド１２上にボールボンデイング法によつて展延性に
優れたＡｕでなる導電部材１２′を供給し、バンプ成型
装置２０の凹部２０Ｂを各導電部材１２′の突起部１２
Ａ′に押し当てて各導電部材１２′をほぼ同じ高さの円
錐形状でなるバンプ１２に成型することにより、ＩＣチ
ツプ１０のパツド１０Ｂ間のピツチが小さい場合でも、
ＩＣチツプ１０を基板１１に実装した際、ＩＣチツプ１
０の各バンプ１２を基板１１の対応する各ランド１１Ａ
に確実に接合させることができるので接続不良を確実に
防止し得、かくして基板１１上への実装の信頼性を向上
し得るＩＣチツプ１０と、基板１１上への実装の信頼性
を向上し得るＩＣチツプ１０の製造方法と、信頼性を向
上し得る実装方法とを実現することができる。According to the above construction, the conductive member 12 'made of Au having excellent spreadability is supplied onto each pad 12 of the IC chip 10 by the ball bonding method, and the recesses 20B of the bump forming apparatus 20 are formed in the respective recesses 20B. Projection 12 of conductive member 12 '
Even if the pitch between the pads 10B of the IC chip 10 is small, the conductive members 12 'are pressed against A'and molded into the bumps 12 having a conical shape having substantially the same height.
When the IC chip 10 is mounted on the substrate 11, the IC chip 1
Each bump 12 of 0 to the corresponding land 11A of the substrate 11
The IC chip 10 and the IC chip 10 which can improve the reliability of the mounting on the substrate 11 and the reliability of the mounting on the substrate 11 can be improved because the connection failure can be surely prevented. The manufacturing method of the IC chip 10 and the mounting method capable of improving the reliability can be realized.
【００３０】なお上述の実施例においては、円錐形状の
凹部２０Ｂを有するバンプ成型装置２０を用いて、バン
プ成型装置２０の当該凹部２０Ｂを導電部材１２′の突
起部１２Ａ′に押し当てることにより各導電部材１２′
の突起部１２Ａ′を円錐形状に成型して円錐部１２Ａを
有するバンプ１２に成型した場合について述べたが、本
発明はこれに限らず、図４（Ｂ）に示すように、先端部
３０Ａに四角錐状の凹部３０Ｂを有するバンプ成型装置
３０を用いて、バンプ成型装置３０の当該凹部３０Ｂを
導電部材１２′の突起部１２Ａ′に押し当てることによ
り各導電部材１２′の突起部１２Ａ′を四角錐形状に成
型して四角錐部を有するバンプ１２に成型してもよい。In the above embodiment, the bump forming apparatus 20 having the conical recess 20B is used, and the recess 20B of the bump forming apparatus 20 is pressed against the protrusion 12A 'of the conductive member 12'. Conductive member 12 '
The case where the protrusion 12A ′ of the above is molded into a conical shape to form the bump 12 having the conical portion 12A has been described. However, the present invention is not limited to this, and as illustrated in FIG. By using the bump forming apparatus 30 having the quadrangular pyramid-shaped concave portion 30B, the concave portion 30B of the bump forming apparatus 30 is pressed against the protruding portion 12A 'of the conductive member 12' so that the protruding portion 12A 'of each conductive member 12' is removed. It may be molded into a quadrangular pyramid shape to form the bump 12 having a quadrangular pyramid portion.
【００３１】この場合、バンプ成型装置３０は、駆動部
３１の制御に基づいて導電部材１２′の突起部１２Ａ′
がバンプ成型装置３０の凹部３０Ｂ内に嵌め込まれるよ
うに位置決めする。In this case, the bump forming apparatus 30 controls the protrusions 12A 'of the conductive member 12' under the control of the drive unit 31.
Are positioned so that they are fitted into the concave portions 30B of the bump forming apparatus 30.
【００３２】また上述の実施例においては、加工性に優
れたセラミツクスでなるバンプ成型装置２０を用いた場
合について述べたが、本発明はこれに限らず、ステンレ
スや鉄等、要はバンプ１２に用いる材料より硬いもので
あればこの他種々の材料でなるバンプ成型装置を用いて
もよい。さらに上述の実施例においては、ＩＣチツプ１
０の各パツド１０Ｂ上にそれぞれ供給された各導電部材
１２′をほぼ円錐形状のバンプ１２に成型した場合につ
いて述べたが、本発明はこれに限らず、三角錐形状や四
角錐形状等、要は錐形状であればこの他種々の錐形状に
形成してもよい。この場合、バンプ成型装置の凹部を所
望の錐形状に合わせて作成する。Further, in the above-mentioned embodiment, the case where the bump forming apparatus 20 made of ceramic having excellent workability is used is described. However, the present invention is not limited to this, and the essential point is to use the bump 12 such as stainless steel or iron. A bump forming apparatus made of various other materials may be used as long as it is harder than the material used. Further, in the above embodiment, the IC chip 1
The case where each conductive member 12 'supplied on each pad 0B of No. 0 is molded into the substantially conical bump 12 has been described. If it is a pyramidal shape, it may be formed in various other conical shapes. In this case, the concave portion of the bump molding device is formed in accordance with a desired conical shape.
【００３３】さらに上述の実施例においては、ＩＣチツ
プ１０の回路面１０Ａ上に形成された各パツド１０Ｂ上
に供給する導電部材としてＡｕを用いた場合について述
べたが、本発明はこれに限らず、ＩＣチツプ１０の回路
面１０Ａ上に形成された各パツド１０Ｂ上に供給する導
電部材として、Ａｕにパラジウムを混ぜたものやはんだ
等、要は錐形状に形成し易い展延性に優れたものであれ
ばこの他種々の導電部材を各パツド１０Ｂ上に供給して
もよい。Further, in the above-mentioned embodiment, the case where Au is used as the conductive member to be supplied onto each pad 10B formed on the circuit surface 10A of the IC chip 10 has been described, but the present invention is not limited to this. The conductive member to be supplied onto each pad 10B formed on the circuit surface 10A of the IC chip 10 is a mixture of Au and palladium, a solder, etc. If necessary, various other conductive members may be supplied onto the pads 10B.
【００３４】さらに上述の実施例においては、ＩＣチツ
プ１０を１バンプ当たり20ｇ／Ｆ〜50ｇ／Ｆの圧力で基
板１１に押しつけた場合について述べたが、本発明はこ
れに限らず、要は各バンプ１２が絶縁膜１３を突き破つ
て基板１１の対応する各ランド１１Ａに接合させること
ができれば、この他種々の圧力値でＩＣチツプ１０を基
板１１に押しつけるようにしてもよい。Further, in the above-mentioned embodiment, the case where the IC chip 10 is pressed against the substrate 11 at a pressure of 20 g / F to 50 g / F per bump has been described, but the present invention is not limited to this, and the point is that each If the bumps 12 can break through the insulating film 13 and bond to the corresponding lands 11A of the substrate 11, the IC chip 10 may be pressed against the substrate 11 with various pressure values.
【００３５】さらに上述の実施例においては、半導体装
置としてベアチツプ型のＩＣチツプ１０に本発明を適用
した場合について述べたが、本発明はこれに限らず、半
導体装置としてこの他種々の半導体装置に適用し得る。
さらに上述の実施例においては、ボールボンデイング法
によつてＩＣチツプ１０の各パツド１０Ｂ上にそれぞれ
Ａｕでなる導電部材１２′を供給した場合について述べ
たが、本発明はこれに限らず、ＩＣチツプ１０の各パツ
ド１０Ｂ上にそれぞれ導電部材を供給する方法として
は、この他種々の方法を適用し得る。Further, in the above-described embodiments, the case where the present invention is applied to the bare chip type IC chip 10 as the semiconductor device has been described, but the present invention is not limited to this, and various other semiconductor devices can be used as the semiconductor device. Applicable.
Further, in the above-described embodiment, the case where the conductive members 12 'made of Au are supplied on the pads 10B of the IC chip 10 by the ball bonding method has been described, but the present invention is not limited to this. Various other methods can be applied to the method for supplying the conductive members onto the pads 10B of the pad 10.
【００３６】[0036]
【発明の効果】上述のように第１の発明によれば、半導
体装置は、その一面に設けられた複数の電極と、当該各
電極上に錐形状に成型されたバンプとを有することによ
り、当該半導体装置の電極間ピツチが小さい場合でも、
半導体装置を基板上に実装した際、各バンプを基板の対
応する電極に確実に接合させることができるので接続不
良を確実に防止することができ、かくして基板への実装
の信頼性を向上し得る半導体装置を実現することができ
る。As described above, according to the first invention, the semiconductor device has the plurality of electrodes provided on one surface thereof and the bumps formed on the respective electrodes in the shape of a cone. Even if the pitch between the electrodes of the semiconductor device is small,
When the semiconductor device is mounted on the substrate, each bump can be surely bonded to the corresponding electrode of the substrate, so that the connection failure can be surely prevented, and thus the reliability of mounting on the substrate can be improved. A semiconductor device can be realized.
【００３７】また第２の発明によれば、半導体装置の一
面に形成された複数の電極上にそれぞれ所定の導電部材
を供給し、各電極上にそれぞれ供給された各導電部材を
錐形状に成型することにより、当該半導体装置の電極間
ピツチが小さい場合でも、半導体装置を基板上に実装し
た際、各バンプを基板の対応する電極に確実に接合させ
ることができるので接続不良を確実に防止することがで
き、かくして基板への実装の信頼性を向上し得る半導体
装置の製造方法を実現することができる。According to the second aspect of the invention, a predetermined conductive member is supplied onto each of a plurality of electrodes formed on one surface of the semiconductor device, and each conductive member supplied onto each electrode is shaped into a cone. By doing so, even when the pitch between the electrodes of the semiconductor device is small, when the semiconductor device is mounted on the substrate, each bump can be reliably bonded to the corresponding electrode of the substrate, so that the connection failure is surely prevented. Thus, it is possible to realize a method for manufacturing a semiconductor device that can improve the reliability of mounting on a substrate.
【００３８】さらに第３の発明においては、一面に複数
のバンプが形成された半導体装置の当該一面を、それぞ
れ基板上に設けられた対応する接合部を覆うように形成
された絶縁膜に押しつけることにより、各バンプを対応
する各接合部に接合する工程を経て基板上に半導体装置
を実装する実装方法において、半導体装置の一面に形成
された各電極上にそれぞれ所定の導電部材を供給し、各
電極上にそれぞれ供給された各導電部材を錐形状に成型
し、半導体装置を絶縁膜上に位置決めしてマウントした
後、半導体装置を所定の圧力で基板に押しつけて、各導
電部材をそれぞれ対応する各接合部に圧着することによ
り、半導体装置及び基板の電極間ピツチが小さい場合で
も各導電部材を基板の対応する電極に確実に接合させる
ことができるので接続不良を確実に防止することがで
き、かくして信頼性を向上し得る実装方法を実現するこ
とができる。Further, in the third aspect of the invention, the one surface of the semiconductor device having a plurality of bumps formed on one surface is pressed against an insulating film formed so as to cover the corresponding joint portions provided on the substrate, respectively. Thus, in the mounting method of mounting the semiconductor device on the substrate through the step of bonding each bump to the corresponding bonding portion, a predetermined conductive member is supplied onto each electrode formed on one surface of the semiconductor device, Each conductive member supplied on the electrode is molded into a conical shape, the semiconductor device is positioned and mounted on the insulating film, and then the semiconductor device is pressed against the substrate with a predetermined pressure to correspond each conductive member to each other. By crimping to each joint, each conductive member can be surely joined to the corresponding electrode on the substrate even when the pitch between the electrodes of the semiconductor device and the substrate is small. It is possible to reliably prevent connection failure, thus it is possible to realize a mounting method capable of improving the reliability.
【図１】本発明の実施例によるＩＣチツプの構成を示す
略線的断面図である。FIG. 1 is a schematic cross-sectional view showing the structure of an IC chip according to an embodiment of the present invention.
【図２】本発明の実施例によるバンプの形状の説明に供
する断面図である。FIG. 2 is a cross-sectional view provided for explaining a shape of a bump according to an embodiment of the present invention.
【図３】本発明の実施例によるＩＣチツプの製造工程を
示す略線的断面図である。FIG. 3 is a schematic cross-sectional view showing a manufacturing process of an IC chip according to an embodiment of the present invention.
【図４】バンプ成型装置の概略構成を示す略線的断面図
である。FIG. 4 is a schematic cross-sectional view showing a schematic configuration of a bump molding device.
【図５】ＩＣチツプの基板への実装工程を示す略線的断
面図である。FIG. 5 is a schematic cross-sectional view showing a process of mounting an IC chip on a substrate.
【図６】従来の異方性導電膜を用いたフリツプチツプ実
装によるＩＣチツプの基板への実装工程を示す略線的断
面図である。FIG. 6 is a schematic cross-sectional view showing a process of mounting an IC chip on a substrate by flip chip mounting using a conventional anisotropic conductive film.
【図７】従来の異方性導電膜を用いたフリツプチツプ実
装におけるバンプとランドの接続状態の説明に供する略
線的断面図である。FIG. 7 is a schematic cross-sectional view for explaining a connection state of bumps and lands in a flip-chip mounting using a conventional anisotropic conductive film.
【図８】フアインピツチ化による電気的シヨートの説明
に供する略線的断面図である。FIG. 8 is a schematic cross-sectional view for explaining an electrical short by fine pitching.
１、１０……ＩＣチツプ、１Ａ、１０Ｂ……パツド、１
Ｂ、３Ｂ、１０Ａ、１１Ｂ……回路面、２、１２……バ
ンプ、３、１１……基板、３Ａ、１１Ａ……ランド、４
……異方性導電膜、１２′……導電部材、１３……絶縁
膜、２０、３０……バンプ成型装置、２０Ａ、３０Ａ…
…バンプ成型装置の先端部、２０Ｂ……円錐形状の凹
部、３０Ｂ……四角錐形状の凹部。1, 10 ... IC chip, 1A, 10B ... Pad, 1
B, 3B, 10A, 11B ... Circuit surface, 2, 12 ... Bump, 3, 11 ... Substrate, 3A, 11A ... Land, 4
... anisotropic conductive film, 12 '... conductive member, 13 ... insulating film, 20,30 ... bump forming device, 20A, 30A ...
... Tip of bump forming device, 20B ... conical recess, 30B ... pyramidal recess.
Claims (8)
具えることを特徴とする半導体装置。1. A semiconductor device comprising a plurality of electrodes provided on one surface and cone-shaped bumps respectively formed on the electrodes.
る請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein each of the bumps is made of gold.
上にそれぞれ所定の導電部材を供給する第１の工程と、 各上記電極上にそれぞれ供給された各上記導電部材を錐
形状に成型する第２の工程とを具えることを特徴とする
半導体装置の製造方法。3. A first step of supplying a predetermined conductive member to each of a plurality of electrodes formed on one surface of a semiconductor device, and molding each of the conductive members supplied to each of the electrodes into a cone shape. And a second step of manufacturing the semiconductor device.
上記導電部材を供給する ことを特徴とする請求項３に
記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 3, wherein in the first step, the conductive member is supplied onto each of the electrodes by a ball bonding method.
導電部材に押し当てることにより各上記導電部材を錐形
状に成型することを特徴とする請求項３に記載の半導体
装置の製造方法。5. In the second step, each of the conductive members is shaped into a cone by pressing the recess of a jig having a conical recess on one surface against the conductive member. The method for manufacturing a semiconductor device according to claim 3, wherein
する請求項３に記載の半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 3, wherein each of the conductive members is made of gold.
置の当該一面を、それぞれ上記基板上に設けられた対応
する接合部を覆うように形成された絶縁膜に押しつける
ことにより、各上記バンプを対応する各上記接合部に接
合する工程を経て上記基板上に上記半導体装置を実装す
る実装方法において、 上記半導体装置の上記一面に形成された各上記電極上に
それぞれ所定の導電部材を供給する第１の工程と、 各上記電極上にそれぞれ供給された各上記導電部材を錐
形状に成型する第２の工程と、 上記半導体装置を上記絶縁膜上に位置決めしてマウント
した後、上記半導体装置を所定の圧力で上記基板に押し
つけることにより、各上記導電部材をそれぞれ対応する
各上記接合部に圧着する第３の工程とを具えることを特
徴とする実装方法。7. The bumps are formed by pressing the one surface of a semiconductor device having a plurality of bumps formed on one surface against an insulating film formed so as to cover the corresponding joints provided on the substrate, respectively. In the mounting method of mounting the semiconductor device on the substrate through the step of bonding to each corresponding bonding portion, a predetermined conductive member is supplied onto each of the electrodes formed on the one surface of the semiconductor device. A first step, a second step of molding each of the conductive members supplied on each of the electrodes into a conical shape, and positioning and mounting the semiconductor device on the insulating film, and then the semiconductor device. And a third step of pressing each of the conductive members to each of the corresponding joints by pressing the substrate with a predetermined pressure onto the substrate.
する請求項７に記載の実装方法。8. The mounting method according to claim 7, wherein each of the conductive members is made of gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7349355A JPH09172021A (en) | 1995-12-19 | 1995-12-19 | Semiconductor device and manufacturing method and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7349355A JPH09172021A (en) | 1995-12-19 | 1995-12-19 | Semiconductor device and manufacturing method and packaging method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09172021A true JPH09172021A (en) | 1997-06-30 |
Family
ID=18403213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7349355A Pending JPH09172021A (en) | 1995-12-19 | 1995-12-19 | Semiconductor device and manufacturing method and packaging method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09172021A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1117075A (en) * | 1997-04-28 | 1999-01-22 | Nitto Denko Corp | Semiconductor device |
| WO1999004424A1 (en) * | 1997-07-15 | 1999-01-28 | Hitachi, Ltd. | Semiconductor device, mounting structure thereof and method of fabrication thereof |
| WO2001006558A1 (en) * | 1999-07-16 | 2001-01-25 | Matsushita Electric Industrial Co., Ltd. | Package of semiconductor device and method of manufacture thereof |
| US6495922B2 (en) | 2000-03-14 | 2002-12-17 | Kabushiki Kaisha Toshiba | Semiconductor device with pointed bumps |
| US6975036B2 (en) * | 2002-04-01 | 2005-12-13 | Nec Electronics Corporation | Flip-chip semiconductor device utilizing an elongated tip bump |
| DE102006036728A1 (en) * | 2006-08-05 | 2008-02-07 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Semiconductor chips contacting method for e.g. printed circuit board layer, involves applying conductive bumps on contact areas, where bumps penetrate one layer formed during connection of metal layer with surface of board layer |
-
1995
- 1995-12-19 JP JP7349355A patent/JPH09172021A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1117075A (en) * | 1997-04-28 | 1999-01-22 | Nitto Denko Corp | Semiconductor device |
| WO1999004424A1 (en) * | 1997-07-15 | 1999-01-28 | Hitachi, Ltd. | Semiconductor device, mounting structure thereof and method of fabrication thereof |
| KR100426914B1 (en) * | 1997-07-15 | 2004-04-13 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and method of fabrication thereof |
| EP1022775A4 (en) * | 1997-07-15 | 2005-05-11 | Hitachi Ltd | Semiconductor device, mounting structure thereof and method of fabrication thereof |
| US7390732B1 (en) | 1997-07-15 | 2008-06-24 | Hitachi, Ltd. | Method for producing a semiconductor device with pyramidal bump electrodes bonded onto pad electrodes arranged on a semiconductor chip |
| US7090482B2 (en) | 1999-07-16 | 2006-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device package manufacturing method and semiconductor device package manufactured by the method |
| WO2001006558A1 (en) * | 1999-07-16 | 2001-01-25 | Matsushita Electric Industrial Co., Ltd. | Package of semiconductor device and method of manufacture thereof |
| US6780668B1 (en) | 1999-07-16 | 2004-08-24 | Matsushita Electric Industrial Co., Ltd. | Package of semiconductor device and method of manufacture thereof |
| US6495922B2 (en) | 2000-03-14 | 2002-12-17 | Kabushiki Kaisha Toshiba | Semiconductor device with pointed bumps |
| US6975036B2 (en) * | 2002-04-01 | 2005-12-13 | Nec Electronics Corporation | Flip-chip semiconductor device utilizing an elongated tip bump |
| US7579211B2 (en) | 2002-04-01 | 2009-08-25 | Nec Electronics Corporation | Flip-chip semiconductor device utilizing an elongated tip bump |
| DE102006036728A1 (en) * | 2006-08-05 | 2008-02-07 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Semiconductor chips contacting method for e.g. printed circuit board layer, involves applying conductive bumps on contact areas, where bumps penetrate one layer formed during connection of metal layer with surface of board layer |
| US8042724B2 (en) | 2006-08-05 | 2011-10-25 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Method for electrically connecting to a contact of a microelectronic component on a circuit board or substrate |
| DE102006036728B4 (en) * | 2006-08-05 | 2017-01-19 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method for the electrical contacting of microelectronic components on a printed circuit board |
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