JPH09162229A - Semiconductor unit and method of packaging semiconductor chip - Google Patents
Semiconductor unit and method of packaging semiconductor chipInfo
- Publication number
- JPH09162229A JPH09162229A JP7315397A JP31539795A JPH09162229A JP H09162229 A JPH09162229 A JP H09162229A JP 7315397 A JP7315397 A JP 7315397A JP 31539795 A JP31539795 A JP 31539795A JP H09162229 A JPH09162229 A JP H09162229A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit board
- sealing resin
- semiconductor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/325—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子と封止
樹脂との密着力を高めた半導体ユニット及び半導体素子
の実装方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor unit in which the adhesion between a semiconductor element and a sealing resin is enhanced and a method for mounting the semiconductor element.
【０００２】[0002]
【従来の技術】従来、回路基板の入出力端子電極に半導
体素子を実装し半導体ユニットを形成する際、半田付け
を用いたワイヤボンディング方法が広く利用されてい
た。しかし、半導体素子のパッケ−ジの小型化及び接続
端子数の増加等に伴い、接続端子の間隔が狭くなり、従
来の半田付け技術で対処することが次第に困難になって
きた。そこで、集積回路チップ等の半導体素子を回路基
板の入出力端子電極上に直接実装することにより、実装
面積を小型化し、効率的使用を図ろうとする方法が提案
されてきた。特に、半導体装置を回路基板にフェイスダ
ウン状態でフリップチップ実装する方法は、半導体装置
と回路基板との電気的接続を一括して行うことができる
こと及び接続後の機械的強度が強いことから有用な方法
であるとされている。2. Description of the Related Art Conventionally, when a semiconductor element is mounted on an input / output terminal electrode of a circuit board to form a semiconductor unit, a wire bonding method using soldering has been widely used. However, with the miniaturization of the package of the semiconductor element and the increase in the number of connection terminals, the distance between the connection terminals has become narrower, and it has become gradually difficult to cope with the problems by the conventional soldering technique. Therefore, there has been proposed a method in which a semiconductor element such as an integrated circuit chip is directly mounted on the input / output terminal electrodes of the circuit board to reduce the mounting area and achieve efficient use. In particular, a method of flip-chip mounting a semiconductor device on a circuit board in a face-down state is useful because the semiconductor device and the circuit board can be electrically connected together and the mechanical strength after connection is strong. It is said to be a method.
【０００３】例えば、工業調査会、１９８０年１月１５
日発行、日本マイクロエレクトロニクス協会編、「ＩＣ
化実装技術」には、半田メッキ法を用いた実装方法が記
載されている。この実装方法を図１０を参照しつつ説明
する。図１０において、（ａ）は従来の半導体素子の半
田バンプの概略構成を示す断面図、（ｂ）は従来の半田
メッキ法を用いた実装方法により形成された半導体ユニ
ットの概略構成を示す断面図である。半導体素子（ＩＣ
基板）１１６の電極パッド１１３を回路基板１１９の入
出力端子電極１１８に接続する場合、（ａ）に示すよう
に、半導体素子１１６の電極パッド１１３上に密着金属
膜１１２及び拡散防止金属膜１１１を蒸着法によって形
成し、さらに、この上に半田からなる電気的接続接点
（以下、半田バンプという）１１０をメッキ法により形
成する。次に、このようにして形成されたＩＣチップ
を、（ｂ）に示すようにフェイスダウン状態で、半田バ
ンプ１１０が入出力端子電極１１８上に当接するように
位置合わせを行い、回路基板１１９上に載置する。その
後、この半導体装置の実装体（半導体ユニット）を高温
に加熱することにより、半田バンプ１１０を回路基板１
１９の入出力端子電極１１８に融着する。For example, Industrial Research Committee, January 15, 1980.
Published by Japan Microelectronics Association, "IC
The "mounting technology" describes a mounting method using a solder plating method. This mounting method will be described with reference to FIG. In FIG. 10, (a) is a sectional view showing a schematic structure of a solder bump of a conventional semiconductor element, and (b) is a sectional view showing a schematic structure of a semiconductor unit formed by a mounting method using a conventional solder plating method. Is. Semiconductor element (IC
When the electrode pad 113 of the substrate 116 is connected to the input / output terminal electrode 118 of the circuit board 119, the adhesion metal film 112 and the diffusion prevention metal film 111 are provided on the electrode pad 113 of the semiconductor element 116 as shown in FIG. It is formed by a vapor deposition method, and an electrical connection contact (hereinafter referred to as a solder bump) 110 made of solder is further formed thereon by a plating method. Next, the IC chip thus formed is aligned so that the solder bumps 110 contact the input / output terminal electrodes 118 in a face-down state as shown in FIG. Place on. Then, the solder bumps 110 are attached to the circuit board 1 by heating the mounted body (semiconductor unit) of this semiconductor device to a high temperature.
It is fused to the input / output terminal electrode 118 of 19.
【０００４】また、導電性接着剤を用いた半導体素子の
実装方法も提案されている。図１１に示すように、半導
体素子１２６の電極パッド１２３上にワイヤボンディン
グ法又はメッキ法により電気的接続接点（Ａｕバンプ）
１２０を形成し、Ａｕバンプ１２０を導電性接着剤（接
合層）１２５を介して回路基板１２９の入出力端子電極
１２８に接続する。この場合、先に半導体素子１２６の
Ａｕバンプ１２０に導電性接着剤１２５を転写し、次に
回路基板１２９の入出力端子電極１２８にＡｕバンプ１
２０が当接するように位置合わせをし、最後に導電性接
着剤１２５を硬化して電気的接続を得る。さらに、接続
を補強するために、封止樹脂により半導体ユニットを封
止することも提案されている。この場合、さらに封止樹
脂の封入及び硬化工程を必要とする。A method of mounting a semiconductor device using a conductive adhesive has also been proposed. As shown in FIG. 11, electrical connection contacts (Au bumps) are formed on the electrode pads 123 of the semiconductor element 126 by wire bonding or plating.
120 is formed, and the Au bumps 120 are connected to the input / output terminal electrodes 128 of the circuit board 129 via the conductive adhesive (bonding layer) 125. In this case, the conductive adhesive 125 is first transferred to the Au bumps 120 of the semiconductor element 126, and then the Au bumps 1 are applied to the input / output terminal electrodes 128 of the circuit board 129.
Aligning so that 20 abuts, and finally the conductive adhesive 125 is cured to obtain an electrical connection. Further, it has been proposed to seal the semiconductor unit with a sealing resin in order to reinforce the connection. In this case, a sealing resin encapsulation and curing process is further required.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体素子の実装方法及びそれにより形成された半
導体ユニットは、次のような問題点を有していた。第１
に、半導体ユニット製作工程中における温度差又は信頼
性試験等において、半導体素子、回路基板及び封止樹脂
の熱膨張係数の差に起因して、熱衝撃時の熱膨張による
応力によりバルク部（導電性接着剤を介してバンプに対
向している部分）に亀裂や剥離が発生する。また、吸湿
により導電性接着剤の接着力が低下した場合にもバルク
部に亀裂や剥離が発生する場合がある。バルク部に亀裂
や剥離が発生すると、接合界面部が不安定になり、電気
的接続点（Ａｕバンプ）１２０の抵抗値が増大するおそ
れがある。第２に、半導体素子と封止樹脂との境界での
剥離や、封止樹脂そのものにおける亀裂が発生すると、
半導体ユニットの劣化を早め、信頼性を著しく損なう。However, the conventional method for mounting a semiconductor element and the semiconductor unit formed by the conventional method have the following problems. First
In the temperature difference during the semiconductor unit manufacturing process or the reliability test, due to the difference in the thermal expansion coefficient of the semiconductor element, the circuit board and the sealing resin, the bulk part (conductive Cracks and peeling occur in the portion facing the bump via the adhesive. Further, even if the adhesive strength of the conductive adhesive is reduced due to moisture absorption, cracks or peeling may occur in the bulk portion. When a crack or peeling occurs in the bulk portion, the joint interface portion becomes unstable, and the resistance value of the electrical connection point (Au bump) 120 may increase. Secondly, if peeling occurs at the boundary between the semiconductor element and the sealing resin or cracks occur in the sealing resin itself,
It accelerates deterioration of the semiconductor unit and significantly impairs reliability.
【０００６】本発明は上記従来例の問題点を解決するた
めになされたものであり、半導体素子と封止樹脂との密
着力を高め、寿命の劣化を抑えることを可能とする半導
体ユニット及びそれに適する半導体素子の実装方法を提
供することを目的とする。The present invention has been made in order to solve the above-mentioned problems of the conventional example, and a semiconductor unit capable of increasing the adhesion between the semiconductor element and the sealing resin and suppressing the deterioration of the life, and the same. An object of the present invention is to provide a suitable semiconductor element mounting method.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するた
め、本発明の半導体ユニットは、回路基板の端子電極に
フェイスダウン状態で半導体素子を実装した半導体ユニ
ットであって、前記半導体素子に設けられた突起電極を
前記回路基板の前記端子電極に接合層を介して電気的に
接続し、かつ前記半導体素子と前記回路基板との間隙及
び前記半導体素子の側面が無機物の剛体フィラ−及び有
機物の樹脂を含む封止樹脂で機械的に補強され、前記剛
体フィラーは前記突起電極と前記端子電極の接合部を囲
むように前記回路基板側に分布するように構成されてい
る。To achieve the above object, a semiconductor unit of the present invention is a semiconductor unit in which a semiconductor element is mounted face down on a terminal electrode of a circuit board, and the semiconductor unit is provided on the semiconductor element. A protruding electrode is electrically connected to the terminal electrode of the circuit board via a bonding layer, and the gap between the semiconductor element and the circuit board and the side surface of the semiconductor element are made of an inorganic rigid filler and an organic resin. The rigid filler is mechanically reinforced with a sealing resin containing, and is distributed to the circuit board side so as to surround the joint between the protruding electrode and the terminal electrode.
【０００８】上記構成において、前記突起電極は、断面
積の異なる少なくとも２つの部分を有し、断面積の小さ
い側を前記回路基板側に配置したことが好ましい。ま
た、上記各構成において、前記半導体素子の回路が設け
られている面及び側面のうち、前記有機物の樹脂と接触
している部分の表面に凹凸が設けられていることが好ま
しい。また、上記各構成において、前記突起電極は、Ａ
ｕ、Ｃｕ、Ａｌ、半田及びこれらの合金から選択された
いずれかで形成されていることが好ましい。また、上記
各構成において、前記接合層は導電性接着剤で構成され
ていることが好ましい。または、上記各構成において、
前記接合層は異方性導電材で構成されていることが好ま
しい。また、上記各構成において、前記封止樹脂はｐＨ
≦８であることが好ましい。In the above structure, it is preferable that the bump electrode has at least two portions having different cross-sectional areas, and the side having the smaller cross-sectional area is arranged on the circuit board side. Further, in each of the above-described configurations, it is preferable that, of the surfaces of the semiconductor element on which the circuit is provided and the side surfaces thereof, irregularities are provided on the surfaces of the portions that are in contact with the organic resin. In each of the above configurations, the protruding electrode is A
It is preferably formed of any one selected from u, Cu, Al, solder and alloys thereof. Further, in each of the above configurations, it is preferable that the joining layer is made of a conductive adhesive. Or, in each of the above configurations,
The bonding layer is preferably made of an anisotropic conductive material. Further, in each of the above configurations, the sealing resin has a pH
It is preferable that ≦ 8.
【０００９】また、本発明の別の半導体ユニットは、回
路基板の端子電極にフェイスダウン状態で半導体素子を
実装した半導体ユニットであって、前記回路基板上に前
記半導体素子のほぼ全面に対向するように設けられた異
方性導電層を介して、前記半導体素子に設けられた突起
電極と前記回路基板の前記端子電極とを電気的に接続
し、かつ少なくとも前記回路基板と前記半導体素子の側
面が無機物の剛体フィラ−及び有機物の樹脂を含む封止
樹脂で機械的に補強され、前記剛体フィラーは前記回路
基板側に分布しているように構成されている。上記構成
において、前記異方性導電層は、前記半導体素子と前記
回路基板との隙間とほぼ等しい厚みを有し、前記半導体
素子と前記回路基板との隙間を封止することが好まし
い。Another semiconductor unit of the present invention is a semiconductor unit in which a semiconductor element is mounted face down on a terminal electrode of a circuit board, and the semiconductor element is arranged on the circuit board so as to face substantially the entire surface of the semiconductor element. Via the anisotropic conductive layer provided in, electrically connecting the protruding electrode provided in the semiconductor element and the terminal electrode of the circuit board, and at least the side surface of the circuit board and the semiconductor element The rigid filler is mechanically reinforced by a sealing resin containing an inorganic rigid filler and an organic resin, and the rigid filler is distributed on the circuit board side. In the above structure, it is preferable that the anisotropic conductive layer has a thickness substantially equal to a gap between the semiconductor element and the circuit board, and seals the gap between the semiconductor element and the circuit board.
【００１０】一方、本発明の半導体素子の実装方法は、
半導体素子の回路上の所定位置に突起電極を形成し、前
記半導体素子を回路基板に対してフェイスダウン状態に
し、その状態で前記突起電極を接合層を介して前記回路
基板の端子電極に電気的に接続し、前記半導体素子と前
記回路基板との間隙及び前記半導体素子の側面を機械的
に補強するために無機物の剛体フィラ−及び有機物の樹
脂を含む第１の封止樹脂を注入し、前記半導体素子の回
路が設けられている面及び側面の少なくとも一部をと接
触するように有機物の樹脂のみで構成された第２の封止
樹脂を注入するように構成されている。On the other hand, the semiconductor element mounting method of the present invention is
A protruding electrode is formed at a predetermined position on the circuit of the semiconductor element, the semiconductor element is placed facedown with respect to the circuit board, and in this state, the protruding electrode is electrically connected to the terminal electrode of the circuit board through the bonding layer. And injecting a first sealing resin containing an inorganic rigid filler and an organic resin to mechanically reinforce the gap between the semiconductor element and the circuit board and the side surface of the semiconductor element, The second sealing resin composed only of the organic resin is injected so as to contact at least a part of the surface and the side surface of the semiconductor element on which the circuit is provided.
【００１１】上記構成において、前記第１の封止樹脂の
有機物の樹脂と前記第２の封止樹脂の有機物の樹脂は同
一であることが好ましい。また、上記各構成において、
前記半導体素子の側面及び回路が設けられている面の回
路を除いた部分の少なくとも一部を、前記半導体素子と
同じ材料又は無機物の砥粒で摩擦し、凹凸を形成するこ
とが好ましい。または、上記構成において、前記半導体
素子の側面及び回路が設けられている面の回路を除いた
部分の少なくとも一部に、前記半導体素子と同じ材料又
は無機物の砥粒を高温圧着し、凹凸を形成することが好
ましい。また、上記各構成において、先に前記半導体素
子と前記回路基板との間隙の前記回路基板側に前記第１
の封止樹脂を注入し、次に前記半導体素子と前記回路基
板との間隙の前記半導体素子側に前記第２の封止樹脂を
注入することが好ましい。または、上記各構成におい
て、先に前記半導体素子と前記回路基板との間隙の前記
半導体素子側に前記第２の封止樹脂を注入し、次に前記
半導体素子と前記回路基板との間隙の前記回路基板側に
前記第１の封止樹脂を注入することが好ましい。In the above structure, the organic resin of the first sealing resin and the organic resin of the second sealing resin are preferably the same. Further, in each of the above configurations,
It is preferable that at least a part of the side surface of the semiconductor element and the surface on which the circuit is provided, excluding the circuit, is rubbed with abrasive grains of the same material as the semiconductor element or an inorganic substance to form irregularities. Alternatively, in the above structure, at least a part of the side surface of the semiconductor element and the surface where the circuit is provided, excluding the circuit, is subjected to high-temperature pressure bonding with abrasive grains of the same material as the semiconductor element or an inorganic material to form irregularities. Preferably. Further, in each of the above-mentioned configurations, the first portion is first provided on the circuit board side in the gap between the semiconductor element and the circuit board.
It is preferable that the second sealing resin be injected into the gap between the semiconductor element and the circuit board on the side of the semiconductor element. Alternatively, in each of the above configurations, the second sealing resin is first injected into the semiconductor element side of the gap between the semiconductor element and the circuit board, and then the gap between the semiconductor element and the circuit board is removed. It is preferable to inject the first sealing resin into the circuit board side.
【００１２】また、本発明の別の半導体素子の実装方法
は、半導体素子の回路上の所定位置に突起電極を形成
し、回路基板上の前記半導体素子のほぼ全面に対向する
位置に異方性導電層を形成し、前記半導体素子を回路基
板に対してフェイスダウン状態にし、その状態で前記突
起電極を前記異方性導電層を介して前記回路基板の端子
電極に電気的に接続し、少なくとも前記回路基板と前記
半導体素子の側面を機械的に補強するために無機物の剛
体フィラ−及び有機物の樹脂を含む封止樹脂を前記剛体
フィラーが前記回路基板側に分布するように塗布するよ
うに構成されている。上記構成において、前記封止樹脂
は、無機物の剛体フィラ−及び有機物の樹脂を含む第１
の封止樹脂と有機物の樹脂のみで構成された第２の封止
樹脂からなり、前記第１の封止樹脂を前記回路基板側に
塗布し、前記第２の封止樹脂を前記半導体素子側に塗布
することが好ましい。Further, according to another method of mounting a semiconductor element of the present invention, a protruding electrode is formed at a predetermined position on the circuit of the semiconductor element, and anisotropy is provided at a position facing substantially the entire surface of the semiconductor element on the circuit board. A conductive layer is formed, the semiconductor element is placed in a face-down state with respect to the circuit board, and in that state, the protruding electrode is electrically connected to the terminal electrode of the circuit board through the anisotropic conductive layer, In order to mechanically reinforce the side surfaces of the circuit board and the semiconductor element, a rigid resin of an inorganic material and a sealing resin containing an organic resin are applied so that the rigid filler is distributed to the circuit board side. Has been done. In the above structure, the sealing resin may include a rigid filler of an inorganic material and a resin of an organic material.
And a second sealing resin composed only of an organic resin, the first sealing resin is applied to the circuit board side, and the second sealing resin is applied to the semiconductor element side. It is preferable to apply it to.
【００１３】[0013]
【発明の実施の形態】以下に、本発明の半導体ユニット
及びそれに適する半導体素子の実装方法の各実施形態を
図面を参照しつつ説明する。 （第１の実施形態）図１に示す第１の実施形態におい
て、（ａ）は側面１及び回路が設けられている面におけ
る回路を除いた部分２に凹凸が設けられている半導体素
子６を回路基板９上に実装した半導体ユニットの構成を
示す断面図であり、（ｂ）は側面１及び回路が設けられ
ている面における回路を除いた部分２に凹凸が設けられ
ていない半導体素子６を回路基板９上に実装した半導体
ユニットの構成を示す断面図である。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor unit and a semiconductor element mounting method suitable for the same according to the present invention will be described below with reference to the drawings. (First Embodiment) In the first embodiment shown in FIG. 1, (a) shows a semiconductor element 6 in which unevenness is provided on a side surface 1 and a portion 2 excluding a circuit on a surface on which a circuit is provided. It is sectional drawing which shows the structure of the semiconductor unit mounted on the circuit board 9, (b) shows the semiconductor element 6 in which the unevenness is not provided in the part 2 except the circuit in the side surface 1 and the surface in which the circuit is provided. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor unit mounted on a circuit board 9.
【００１４】図１の（ａ）及び（ｂ）において、半導体
素子（ＩＣ基板）６の電極パッド３上に突起電極（バン
プ）７が形成されている。突起電極７は２段の突起形状
を有し、断面積の大きい第１の部分７ａとそれよりも断
面積の小さい部分７ｂで構成されている。また、断面積
の大きい部分７ａが半導体素子６側に、断面積の小さい
部分７ｂが回路基板９側に対向するように配置されてい
る。突起電極７の断面積の小さい部分７ｂと回路基板９
の端子電極８とは、例えば導電性接着剤等で構成された
導電層５により電気的に接続されている。半導体素子６
と回路基板９との隙間及び半導体素子６の側面１を機械
的に補強するように、剛体フィラー４ａを含む封止樹脂
４が注入及び塗布されている。剛体フィラー４ａは、接
合層５を含む突起電極７と端子電極８の接合部を囲むよ
うに、回路基板９側に分布されている。また、半導体素
子６の回路の側面１及び回路が設けられている面におけ
る回路を除いた部分２は封止樹脂４の樹脂成分のみと接
触しており、封止樹脂４の剛体フィラ−４ａは、見掛け
上回路基板９側に沈降している。In FIGS. 1A and 1B, protruding electrodes (bumps) 7 are formed on the electrode pads 3 of the semiconductor element (IC substrate) 6. The protruding electrode 7 has a two-step protruding shape, and is composed of a first portion 7a having a large cross-sectional area and a portion 7b having a smaller cross-sectional area. Further, a portion 7a having a large cross-sectional area is arranged on the semiconductor element 6 side and a portion 7b having a small cross-sectional area is arranged on the circuit board 9 side. Circuit board 9 and portion 7b having a small cross-sectional area of protruding electrode 7
The terminal electrode 8 is electrically connected to the terminal electrode 8 by the conductive layer 5 made of a conductive adhesive or the like. Semiconductor element 6
A sealing resin 4 containing a rigid filler 4a is injected and applied so as to mechanically reinforce the gap between the semiconductor substrate 6 and the side surface 1 of the semiconductor element 6. The rigid fillers 4 a are distributed on the circuit board 9 side so as to surround the joint portion between the protruding electrode 7 including the joint layer 5 and the terminal electrode 8. Further, the side surface 1 of the circuit of the semiconductor element 6 and the portion 2 of the surface on which the circuit is provided excluding the circuit are in contact with only the resin component of the sealing resin 4, and the rigid body filler-4a of the sealing resin 4 is , Apparently settled on the circuit board 9 side.
【００１５】接合層５としての導電性接着剤は、転写法
や印刷法により突起電極７の断面積の小さい部分７ｂの
周囲に塗布される。２段突起状の突起電極７を用いるこ
とにより、必要量以上の導電性接着剤が、突起電極７の
先端部（断面積の小さい部分７ｂの周囲）に付着するこ
とを防止することができ、適量の導電性接着剤を塗布す
ることができる。なお、図１の（ａ）に示すように、半
導体素子６の側面１及び回路が設けられている面におけ
る回路を除いた部分２に凹凸を設けることにより、半導
体素子６と封止樹脂４の有機物樹脂成分との接触面積が
大きくなり、密着性が向上する。The conductive adhesive as the bonding layer 5 is applied around the portion 7b having a small cross-sectional area of the protruding electrode 7 by a transfer method or a printing method. By using the two-step protruding electrode 7, it is possible to prevent an excessive amount of conductive adhesive from adhering to the tip portion of the protruding electrode 7 (around the portion 7b having a small cross-sectional area). A suitable amount of conductive adhesive can be applied. As shown in FIG. 1A, unevenness is provided on the side surface 1 of the semiconductor element 6 and the portion 2 of the surface on which the circuit is provided, excluding the circuit, so that the semiconductor element 6 and the sealing resin 4 are formed. The contact area with the organic resin component is increased and the adhesion is improved.
【００１６】剛体フィラー４ａとしては、例えばＳｉＯ
2を用いる。また、封止樹脂４の樹脂成分としては、例
えばエポキシ系樹脂を用いる。エポキシ系樹脂の場合、
複数の成分（例えば２成分）の混合の割合に応じて粘性
や硬化時間等が異なる。例えば、樹脂成分のｐＨ≦８、
特に好ましくは３≦ｐＨ≦８の場合、剛体フィラー４ａ
を均一に分布させることができ、かつ硬化時間中に剛体
フィラー４ａが沈殿しない程度の粘性を得ることができ
る。樹脂成分のｐＨがこの範囲から外れると、樹脂の粘
性が高すぎて剛体フィラー４ａを均一部分布させること
ができなかったり、あるいは粘性が低すぎて硬化するま
でに剛体フィラー４ａが沈殿してしまい、均一な分布を
得ることができなくなる。また、突起電極７の材料とし
ては、Ａｕ、Ｃｕ、Ａｌ等を用いることができ、ワイヤ
ボンディング法やメッキ法等により半導体素子６の電極
パッド３上に形成する。As the rigid filler 4a, for example, SiO
Use 2 . As the resin component of the sealing resin 4, for example, epoxy resin is used. In the case of epoxy resin,
The viscosity, the curing time, etc. differ depending on the mixing ratio of a plurality of components (for example, two components). For example, the pH of the resin component ≦ 8,
Particularly preferably, when 3 ≦ pH ≦ 8, the rigid filler 4a
Can be evenly distributed, and viscosity can be obtained to such an extent that the rigid filler 4a does not precipitate during the curing time. If the pH of the resin component is out of this range, the viscosity of the resin is too high to distribute the rigid filler 4a in a uniform portion, or the viscosity is too low and the rigid filler 4a precipitates before curing. , It becomes impossible to obtain a uniform distribution. Further, Au, Cu, Al or the like can be used as the material of the bump electrode 7, and the bump electrode 7 is formed on the electrode pad 3 of the semiconductor element 6 by a wire bonding method, a plating method or the like.
【００１７】（第２の実施形態）図２に示す第２の実施
形態において、（ａ）は側面３１及び回路が設けられて
いる面における回路を除いた部分３２に凹凸が設けられ
ている半導体素子３６を回路基板３９上に実装した半導
体ユニットの構成を示す断面図であり、（ｂ）は側面３
１及び回路が設けられている面における回路を除いた部
分３２に凹凸が設けられていない半導体素子３６を回路
基板３９上に実装した半導体ユニットの構成を示す断面
図である。上記第１の実施形態と比較して、突起電極３
０が２段突起形状の代りに半田バンプで構成されている
点が異なる。また、半導体素子３６の電極パッド３３上
には金属膜３７が形成され、その上に突起電極（半田バ
ンプ）３０が半田メッキ法により形成されている。(Second Embodiment) In the second embodiment shown in FIG. 2, (a) shows a semiconductor in which the side surface 31 and a portion 32 excluding the circuit on the surface on which the circuit is provided have irregularities. It is sectional drawing which shows the structure of the semiconductor unit which mounted the element 36 on the circuit board 39, (b) is side surface 3. FIG.
1 is a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 36 having no unevenness provided on a portion 32 excluding a circuit on a surface provided with a circuit 1 and a circuit is mounted on a circuit board 39. FIG. Compared to the first embodiment, the protruding electrode 3
The difference is that 0 is formed of solder bumps instead of the two-step projection shape. A metal film 37 is formed on the electrode pad 33 of the semiconductor element 36, and a protruding electrode (solder bump) 30 is formed on the metal film 37 by a solder plating method.
【００１８】突起電極３０と回路基板３９の端子電極３
８とは、例えば導電性接着剤等で構成された導電層３５
により電気的に接続されている。半導体素子３６と回路
基板３９との隙間及び半導体素子３６の側面３１を機械
的に補強するように、剛体フィラー３４ａを含む封止樹
脂３４が注入及び塗布されている。剛体フィラー３４ａ
は、接合層３５を含む突起電極３０と端子電極３８の接
合部を囲むように、回路基板３９側に分布されている。
また、半導体素子３６の回路の側面３１及び回路が設け
られている面における回路を除いた部分３２は封止樹脂
３４の樹脂成分のみと接触しており、封止樹脂３４の剛
体フィラ−３４ａは、見掛け上回路基板３９側に沈降し
ている。なお、封止樹脂３４の樹脂成分及び剛体フィラ
−３４ａ等は上記第１の実施例と同様である。第２の実
施形態では、突起電極３０として半田バンプを用いたの
で、突起電極３０を形成するために要するコストを低減
することができる。The protruding electrode 30 and the terminal electrode 3 of the circuit board 39
8 is a conductive layer 35 made of a conductive adhesive or the like, for example.
Are electrically connected to each other. A sealing resin 34 including a rigid filler 34a is injected and applied so as to mechanically reinforce the gap between the semiconductor element 36 and the circuit board 39 and the side surface 31 of the semiconductor element 36. Rigid filler 34a
Are distributed on the circuit board 39 side so as to surround the joint portion between the protruding electrode 30 including the joint layer 35 and the terminal electrode 38.
In addition, the side surface 31 of the circuit of the semiconductor element 36 and the portion 32 of the surface on which the circuit is provided excluding the circuit are in contact with only the resin component of the sealing resin 34, and the rigid body filler 34a of the sealing resin 34 is , Apparently settled on the circuit board 39 side. The resin component of the sealing resin 34, the rigid filler 34a, and the like are the same as those in the first embodiment. In the second embodiment, since the solder bump is used as the protruding electrode 30, the cost required to form the protruding electrode 30 can be reduced.
【００１９】（第３の実施形態）図３に示す第３の実施
形態において、（ａ）は側面４１及び回路が設けられて
いる面における回路を除いた部分４２に凹凸が設けられ
ている半導体素子４６を回路基板４９上に実装した半導
体ユニットの構成を示す断面図であり、（ｂ）は側面４
１及び回路が設けられている面における回路を除いた部
分４２に凹凸が設けられていない半導体素子４６を回路
基板４９上に実装した半導体ユニットの構成を示す断面
図である。上記第１の実施形態と比較して、突起電極４
７が２段突起形状の代りに１段突起形状に構成されてい
る点が異なる。(Third Embodiment) In a third embodiment shown in FIG. 3, (a) is a semiconductor in which a side surface 41 and a portion 42 excluding the circuit on the surface on which the circuit is provided have irregularities. It is sectional drawing which shows the structure of the semiconductor unit which mounted the element 46 on the circuit board 49, (b) is side surface 4.
1 is a cross-sectional view showing the configuration of a semiconductor unit in which a semiconductor element 46 having no unevenness is mounted on a circuit board 49 in a portion 42 except a circuit on a surface on which a circuit 1 and a circuit are provided. Compared with the first embodiment, the protruding electrode 4
The difference is that 7 is formed in a one-step projection shape instead of a two-step projection shape.
【００２０】突起電極４７と回路基板４９の端子電極４
８とは、例えば導電性接着剤等で構成された導電層４５
により電気的に接続されている。半導体素子４６と回路
基板４９との隙間及び半導体素子４６の側面４１を機械
的に補強するように、剛体フィラー４４ａを含む封止樹
脂４４が注入及び塗布されている。剛体フィラー４４ａ
は、接合層４５を含む突起電極４７と端子電極４８の接
合部を囲むように、回路基板４９側に分布されている。
また、半導体素子４６の回路の側面４１及び回路が設け
られている面における回路を除いた部分４２は封止樹脂
４４の樹脂成分のみと接触しており、封止樹脂４４の剛
体フィラ−４４ａは、見掛け上回路基板４９側に沈降し
ている。なお、封止樹脂４４の樹脂成分及び剛体フィラ
−４４ａ等は上記第１の実施例と同様である。第３の実
施形態では、突起電極４７として１段突起形状を用いた
ので、突起電極４７を形成するために要するコストを低
減することができる。The protruding electrode 47 and the terminal electrode 4 of the circuit board 49
8 is, for example, a conductive layer 45 made of a conductive adhesive or the like.
Are electrically connected to each other. A sealing resin 44 containing a rigid filler 44a is injected and applied so as to mechanically reinforce the gap between the semiconductor element 46 and the circuit board 49 and the side surface 41 of the semiconductor element 46. Rigid filler 44a
Are distributed on the circuit board 49 side so as to surround the joint portion between the protruding electrode 47 including the joint layer 45 and the terminal electrode 48.
Further, the side surface 41 of the circuit of the semiconductor element 46 and the portion 42 excluding the circuit on the surface where the circuit is provided are in contact with only the resin component of the sealing resin 44, and the rigid filler 44a of the sealing resin 44 is , Apparently settled on the circuit board 49 side. The resin component of the sealing resin 44, the rigid filler 44a, and the like are the same as those in the first embodiment. In the third embodiment, since the one-step protrusion shape is used as the protrusion electrode 47, the cost required to form the protrusion electrode 47 can be reduced.
【００２１】（第４の実施形態）図４に示す第４の実施
形態において、（ａ）は側面５１及び回路が設けられて
いる面における回路を除いた部分５２に凹凸が設けられ
ている半導体素子５６を回路基板５９上に実装した半導
体ユニットの構成を示す断面図であり、（ｂ）は側面５
１及び回路が設けられている面における回路を除いた部
分５２に凹凸が設けられていない半導体素子５６を回路
基板５９上に実装した半導体ユニットの構成を示す断面
図である。上記第１の実施形態と比較して、突起電極５
７と端子電極５８とを電気的に接続するための導電層５
５として、導電性接着剤の代りに異方性導電材料を用い
た点が異なる。(Fourth Embodiment) In a fourth embodiment shown in FIG. 4, (a) shows a semiconductor in which a side surface 51 and a portion 52 excluding the circuit on the surface on which the circuit is provided have irregularities. It is sectional drawing which shows the structure of the semiconductor unit which mounted the element 56 on the circuit board 59, (b) is side surface 5.
1 is a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 56 having no unevenness is mounted on a circuit board 59 except a portion 52 on a surface on which a circuit 1 and a circuit are provided. Compared with the first embodiment, the protruding electrode 5
Conductive layer 5 for electrically connecting 7 and the terminal electrode 58
5, the difference is that an anisotropic conductive material is used instead of the conductive adhesive.
【００２２】異方性導電材料で構成された導電層５５
は、半導体素子５６のほぼ全面と対向するように、回路
基板５９上に設けられている。異方性導電材料は、例え
ば導電性フィラーを含有する接着剤やゴム等であり、圧
力が加えられた部分にのみ、その圧力の方向に導電性を
示し、それ以外の部分及び方向には絶縁性を示す。従っ
て、突起電極５７の先端を異方性導電材料である導電層
５５に押しつけることにより、突起電極５７とそれに対
向する端子電極５８間のみ電気的に接続され、突起電極
５７とそれに対向しない他の端子電極との間、突起電極
５７どうしの間、及び端子電極５８どうしの間は絶縁さ
れている。A conductive layer 55 made of an anisotropic conductive material
Are provided on the circuit board 59 so as to face almost the entire surface of the semiconductor element 56. The anisotropic conductive material is, for example, an adhesive or rubber containing a conductive filler, and shows conductivity in the direction of the pressure only in the portion where the pressure is applied, and insulates the other portions and the direction. Shows sex. Therefore, by pressing the tip of the bump electrode 57 against the conductive layer 55 which is an anisotropic conductive material, only the bump electrode 57 and the terminal electrode 58 facing the bump electrode 57 are electrically connected, and the bump electrode 57 and other terminal electrodes not facing the bump electrode 57 are electrically connected. The terminal electrodes are insulated from each other, the protruding electrodes 57 are insulated from each other, and the terminal electrodes 58 are insulated from each other.
【００２３】半導体素子５６と回路基板５９との隙間及
び半導体素子５６の側面５１を機械的に補強するよう
に、剛体フィラー５４ａを含む封止樹脂５４が注入及び
塗布されている。剛体フィラー５４ａは、接合層５５を
含む突起電極５７と端子電極５８の接合部を囲むよう
に、回路基板５９側に分布されている。また、半導体素
子５６の回路の側面５１及び回路が設けられている面に
おける回路を除いた部分５２は封止樹脂５４の樹脂成分
のみと接触しており、封止樹脂５４の剛体フィラ−５４
ａは、見掛け上回路基板５９及びその上の導電層５５側
に沈降している。なお、封止樹脂５４の樹脂成分及び剛
体フィラ−５４ａ等は上記第１の実施例と同様である。
第４の実施形態では、導電層５５として、導電性接着剤
の代りに、回路基板５９上に半導体素子６６のほぼ全面
に対向するように異方性導電材料を設けたので、各突起
電極５７の先端部にそれぞれ導電性接着剤を塗布する工
程が不要になる。A sealing resin 54 containing a rigid filler 54a is injected and applied so as to mechanically reinforce the gap between the semiconductor element 56 and the circuit board 59 and the side surface 51 of the semiconductor element 56. The rigid filler 54a is distributed on the circuit board 59 side so as to surround the joint between the protruding electrode 57 including the joint layer 55 and the terminal electrode 58. Further, the side surface 51 of the circuit of the semiconductor element 56 and the portion 52 excluding the circuit on the surface where the circuit is provided are in contact with only the resin component of the sealing resin 54, and the rigid filler 54 of the sealing resin 54.
The a is apparently deposited on the circuit board 59 and the conductive layer 55 side above it. The resin component of the sealing resin 54, the rigid filler 54a, and the like are the same as those in the first embodiment.
In the fourth embodiment, as the conductive layer 55, instead of the conductive adhesive, an anisotropic conductive material is provided on the circuit board 59 so as to face substantially the entire surface of the semiconductor element 66. The step of applying a conductive adhesive to each of the tip ends of the is unnecessary.
【００２４】（第５の実施形態）図５に示す第５の実施
形態において、（ａ）は側面６１及び回路が設けられて
いる面における回路を除いた部分６２に凹凸が設けられ
ている半導体素子６６を回路基板６９上に実装した半導
体ユニットの構成を示す断面図であり、（ｂ）は側面６
１及び回路が設けられている面における回路を除いた部
分６２に凹凸が設けられていない半導体素子６６を回路
基板６９上に実装した半導体ユニットの構成を示す断面
図である。上記第４の実施形態と比較して、異方性導電
材料で構成された導電層６５が半導体素子６６と回路基
板６９の隙間の全域に設けられており、封止樹脂６４は
回路基板６９と半導体素子６６の側面６１を機械的に補
強するようにのみ塗布されている点が異なる。(Fifth Embodiment) In a fifth embodiment shown in FIG. 5, (a) is a semiconductor in which unevenness is provided on a side surface 61 and a portion 62 excluding a circuit on a surface on which a circuit is provided. It is sectional drawing which shows the structure of the semiconductor unit which mounted the element 66 on the circuit board 69, (b) is side surface 6.
1 is a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 66 having no unevenness on a portion 62 excluding a circuit on a surface on which a circuit 1 and a circuit are provided is mounted on a circuit board 69. Compared to the fourth embodiment, a conductive layer 65 made of an anisotropic conductive material is provided in the entire gap between the semiconductor element 66 and the circuit board 69, and the sealing resin 64 is provided on the circuit board 69. The difference is that it is applied only so as to mechanically reinforce the side surface 61 of the semiconductor element 66.
【００２５】導電層６５として用いられる異方性導電材
料は、半導体素子６６と回路基板６９の間隙とほぼ等し
い厚みを有し、半導体素子６６の突起電極６７が設けら
れている部分のみ、突起電極６７の高さ分だけ圧縮され
る。そのため、突起電極６７とそれに対向する端子電極
６８との間のみ電気的に接続され、他の部分は絶縁され
ている。第５の実施形態によれば、半導体素子６６の側
面６１に塗布するだけでよく、封止樹脂６４を半導体素
子６６と回路基板６９の隙間に注入する工程が不要とな
る。The anisotropic conductive material used as the conductive layer 65 has a thickness approximately equal to the gap between the semiconductor element 66 and the circuit board 69, and only the portion of the semiconductor element 66 where the protruding electrode 67 is provided has a protruding electrode. It is compressed by the height of 67. Therefore, only the protruding electrode 67 and the terminal electrode 68 facing it are electrically connected, and the other portions are insulated. According to the fifth embodiment, only the side surface 61 of the semiconductor element 66 needs to be applied, and the step of injecting the sealing resin 64 into the gap between the semiconductor element 66 and the circuit board 69 is unnecessary.
【００２６】（第６の実施形態）第６の実施形態は半導
体素子の実装方法に関するものであり、特に、図１から
図５の各（ａ）に示すような半導体素子の側面及び回路
が設けられている面における回路を除いた部分に凹凸を
形成する工程に関する。図６に示す一例は、砥石又は砥
粒７５を用いて半導体素子の側面及び回路が設けられて
いる面における回路を除いた部分７１を摩擦することに
より凹凸を形成する方法を示している。砥石又は砥粒７
５は、半導体素子と同じ材料又は無機物の砥粒、例えば
ＳｉＯ2で形成されている。また、図７に示す他の例で
は、半導体素子と同じ材料又は無機物の砥粒８５、例え
ばＳｉＯ2 を、半導体素子の側面及び回路が設けられて
いる面８１に、３００℃、３００ｇ／ｃｍ2 以上で高温
圧着させることにより、凹凸を形成する方法を示してい
る。この様に、半導体素子の側面及び回路が設けられて
いる面における回路を除いた部分に凹凸を形成すること
により、封止樹脂との接触面積を増加させ、半導体素子
と封止樹脂及び回路基板との密着性を向上させることが
できる。(Sixth Embodiment) The sixth embodiment relates to a method of mounting a semiconductor element, and in particular, a side surface and a circuit of the semiconductor element as shown in each (a) of FIGS. 1 to 5 are provided. The present invention relates to a step of forming unevenness on a part of the surface where the circuit is removed. The example shown in FIG. 6 shows a method of forming unevenness by rubbing a portion 71 on the side surface of the semiconductor element and the surface on which the circuit is provided, excluding the circuit, using a grindstone or abrasive grains 75. Whetstone or grain 7
Reference numeral 5 is formed of abrasive grains of the same material as the semiconductor element or inorganic, for example, SiO 2 . Further, in another example shown in FIG. 7, abrasive grains 85 of the same material or inorganic material as the semiconductor element, such as SiO 2 , are applied to the side surface of the semiconductor element and the surface 81 on which the circuit is provided at 300 ° C. and 300 g / cm 2. The method for forming irregularities by high-temperature pressure bonding has been described above. Thus, by forming the unevenness on the side surface of the semiconductor element and on the surface where the circuit is provided, excluding the circuit, the contact area with the sealing resin is increased, and the semiconductor element, the sealing resin, and the circuit board. The adhesiveness with can be improved.
【００２７】（第７の実施形態）第７の実施形態は半導
体素子の実装方法に関するものであり、特に、図１から
図４に示す各実施形態における封止樹脂の注入及び塗布
方法に関する。図８に示す一例では、まず、無機物の剛
体フィラ−、例えばＳｉＯ2と有機物の樹脂、例えばエ
ポキシ系樹脂で構成された第１の封止樹脂９２が、ノズ
ル９１を介して半導体素子９６と回路基板９９との間隙
に注入される。次に、注入された部分９４の少なくとも
一部に、有機物の樹脂のみで構成された第２の封止樹脂
９３が塗布される。また、図９に示す他の例では、ま
ず、有機物の樹脂のみで構成された第２の封止樹脂１０
２が、ノズル１０１を介して半導体素子１０６と回路基
板１０９との間隙に注入される。次に、注入された部分
１０４の少なくとも一部に、無機物の剛体フィラ−と有
機物の樹脂で構成された第１の封止樹脂１０３が塗布さ
れる。(Seventh Embodiment) The seventh embodiment relates to a method for mounting a semiconductor element, and particularly to a method for injecting and applying a sealing resin in each of the embodiments shown in FIGS. 1 to 4. In the example shown in FIG. 8, first, a rigid filler made of an inorganic material, for example, SiO 2 and a first sealing resin 92 made of an organic resin, for example, an epoxy-based resin, are connected to a semiconductor element 96 and a circuit via a nozzle 91. It is injected into the gap with the substrate 99. Next, the second sealing resin 93 composed only of the organic resin is applied to at least a part of the injected portion 94. In another example shown in FIG. 9, first, the second sealing resin 10 composed only of the organic resin is used.
2 is injected into the gap between the semiconductor element 106 and the circuit board 109 via the nozzle 101. Next, the first sealing resin 103 composed of an inorganic rigid filler and an organic resin is applied to at least a part of the injected portion 104.
【００２８】第１の封止樹脂の有機物樹脂成分と第２の
封止樹脂の有機物樹脂成分は、基本的に同様の性質を有
していればよく、必ずしも同一である必要はない。しか
しながら、両者を同一とすることにより、図１から図５
に示すように、見掛け上単一の（１層の）封止樹脂にお
いて剛体フィラーが回路基板側に沈降しているように構
成することができる。この場合、第１の封止樹脂と第２
の封止樹脂との界面を事実上なくすことができ、第１の
封止樹脂と第２の封止樹脂との界面に置ける剥離やひび
割れ等を防止することができる。The organic resin component of the first encapsulating resin and the organic resin component of the second encapsulating resin may basically have the same properties, and are not necessarily the same. However, by making both the same, it is possible to use
As shown in (1), it is possible to configure the apparently single (one layer) encapsulating resin such that the rigid filler is deposited on the circuit board side. In this case, the first sealing resin and the second sealing resin
The interface with the sealing resin can be virtually eliminated, and peeling, cracking and the like that can be placed at the interface between the first sealing resin and the second sealing resin can be prevented.
【００２９】[0029]
【発明の効果】以上説明したように、本発明の第１の半
導体ユニットは、回路基板の端子電極にフェイスダウン
状態で半導体素子を実装したものであって、半導体素子
に設けられた突起電極を回路基板の端子電極に接合層を
介して電気的に接続し、かつ半導体素子と回路基板との
間隙及び半導体素子の側面が無機物の剛体フィラ−及び
有機物の樹脂を含む封止樹脂で機械的に補強され、剛体
フィラーが突起電極と端子電極の接合部を囲むように回
路基板側に分布するように構成されている。すなわち、
半導体素子に設けられた突起電極と回路基板の端子電極
の接合部が剛体フィラーにより強化された封止樹脂で補
強され、さらに半導体素子の回路のある面及び側面の少
なくとも一部は、封止樹脂の有機物の樹脂のみと接触し
ているので、半導体素子と封止樹脂及び封止樹脂と回路
基板との間の密着力が高まり、半導体素子、回路基板及
び封止樹脂の熱膨張率の違いより発生する応力、特に半
導体素子と封止樹脂とに間において生じる応力による剥
離又は封止樹脂そのものの亀裂を防止することができ
る。ここで、封止樹脂中の剛体フィラーを突起電極と端
子電極の接合部を囲むように回路基板側に分布させてい
るので、封止樹脂の熱膨張率が不均一となり、半導体素
子、回路基板及び封止樹脂の間の熱膨張率の差を緩和す
ることができる。As described above, according to the first semiconductor unit of the present invention, the semiconductor element is mounted face down on the terminal electrode of the circuit board, and the protruding electrode provided on the semiconductor element is provided. It is electrically connected to the terminal electrodes of the circuit board through a bonding layer, and the gap between the semiconductor element and the circuit board and the side surface of the semiconductor element are mechanically sealed with a rigid filler of an inorganic material and a sealing resin containing an organic resin. It is reinforced so that the rigid filler is distributed on the circuit board side so as to surround the joint between the protruding electrode and the terminal electrode. That is,
The joint between the protruding electrode provided on the semiconductor element and the terminal electrode on the circuit board is reinforced with a sealing resin reinforced with a rigid filler, and at least a part of the surface and side surface of the circuit of the semiconductor element is a sealing resin. Since it is in contact with only the resin of the organic substance, the adhesion between the semiconductor element and the sealing resin and between the sealing resin and the circuit board is increased, and the difference in the coefficient of thermal expansion between the semiconductor element, the circuit board and the sealing resin is It is possible to prevent peeling or cracking of the sealing resin itself due to generated stress, particularly stress generated between the semiconductor element and the sealing resin. Here, since the rigid filler in the sealing resin is distributed on the circuit board side so as to surround the joint between the protruding electrode and the terminal electrode, the thermal expansion coefficient of the sealing resin becomes uneven, and the semiconductor element, the circuit board The difference in the coefficient of thermal expansion between the sealing resin and the sealing resin can be reduced.
【００３０】突起電極に断面積の異なる少なくとも２つ
の部分を設け、断面積の小さい側を回路基板側に配置す
ることにより、導電層として用いられる、例えば導電性
接着剤が必要以上に突起電極の先端部に付着するのを防
止し、適量の導電性接着剤を塗布することができる。ま
た、半導体素子の回路が設けられている面及び側面のう
ち、有機物の樹脂と接触する部分の表面に凹凸を設ける
ことにより、半導体素子と有機物の樹脂との接触面積が
増加し、半導体素子と封止樹脂との密着力を更に高くす
ることができる。By providing at least two portions having different cross-sectional areas on the protruding electrode and arranging the side having the smaller cross-sectional area on the circuit board side, a conductive adhesive, for example, a conductive adhesive, is used for the protruding electrode more than necessary. It is possible to prevent adhesion to the tip portion and apply an appropriate amount of conductive adhesive. In addition, by providing unevenness on the surface of the portion where the circuit of the semiconductor element is provided and the side surface which is in contact with the organic resin, the contact area between the semiconductor element and the organic resin is increased, The adhesion with the sealing resin can be further increased.
【００３１】また、突起電極を、Ａｕ、Ｃｕ、Ａｌ、半
田及びこれらの合金から選択されたいずれかで形成する
ことにより、従来から用いられている半導体素子の実装
方法を突起電極形成工程にそのまま用いることができ
る。また、接合層として導電性接着剤を用いることによ
り、突起電極の先端部に導電性接着剤を塗布した後、突
起電極と端子電極の位置合せを行い、最後に導電性接着
剤を硬化させることができ、突起電極と端子電極の位置
合せ精度を高くすることができる。または、接合層とし
て異方性導電材を用いることにより、突起電極と端子電
極に接合部を異方性導電材自体で囲むことができ、接合
部の機械的強度を高くすることができる。また、封止樹
脂としてｐＨ≦８、特に好ましくは３≦ｐＨ≦８のもの
を用いることにより、適度な粘性及び硬化時間等を得る
ことができ、剛体フィラーを回路基板側に沈降するよう
に分布させた状態を維持することができる。Further, by forming the protruding electrode from any one selected from Au, Cu, Al, solder and alloys thereof, the conventionally used semiconductor element mounting method is directly applied to the protruding electrode forming step. Can be used. Also, by using a conductive adhesive as the bonding layer, after applying the conductive adhesive to the tip of the protruding electrode, align the protruding electrode and the terminal electrode, and finally cure the conductive adhesive. Therefore, the alignment accuracy of the protruding electrode and the terminal electrode can be increased. Alternatively, by using an anisotropic conductive material as the bonding layer, the bonding portion can be surrounded by the anisotropic conductive material itself between the protruding electrode and the terminal electrode, and the mechanical strength of the bonding portion can be increased. Also, by using a sealing resin having a pH of ≦ 8, particularly preferably 3 ≦ pH ≦ 8, an appropriate viscosity and curing time can be obtained, and the rigid filler is distributed so as to settle on the circuit board side. It is possible to maintain the condition.
【００３２】また、本発明の第２の半導体ユニットは、
回路基板の端子電極にフェイスダウン状態で半導体素子
を実装したものであって、回路基板上に半導体素子のほ
ぼ全面に対向するように設けられた異方性導電層を介し
て、半導体素子に設けられた突起電極と回路基板の端子
電極とを電気的に接続し、かつ少なくとも回路基板と半
導体素子の側面が無機物の剛体フィラ−及び有機物の樹
脂を含む封止樹脂で機械的に補強され、剛体フィラーは
前記回路基板側に分布しているように構成されている。
すなわち、異方性導電層は、突起電極とそれに対向する
端子電極間のみを電気的に接続し、突起電極とそれとは
対向しない他の端子電極との間、突起電極どうしの間、
及び端子電極どうしの間を絶縁する。従って、一の異方
性導電層を形成するだけで、すべての突起電極とそれら
に対向する端子電極とを電気的に接続することができ、
各突起電極の先端に導電性接着剤等を塗布する工程を省
略することができる。また、異方性導電層の厚みを半導
体素子と回路基板との隙間とほぼ等しくし、半導体素子
と回路基板との隙間を封止させることにより、封止樹脂
を半導体素子と回路基板との間に注入する工程を省略す
ることができる。The second semiconductor unit of the present invention is
A semiconductor element is mounted face down on a terminal electrode of a circuit board, and is provided on the semiconductor element through an anisotropic conductive layer provided on the circuit board so as to face almost the entire surface of the semiconductor element. Electrically connecting the protruding electrodes and the terminal electrodes of the circuit board, and at least the side surfaces of the circuit board and the semiconductor element are mechanically reinforced by a rigid resin of an inorganic substance and a resin of an organic substance, and a rigid body. The filler is configured to be distributed on the circuit board side.
That is, the anisotropic conductive layer electrically connects only the protruding electrode and the terminal electrode facing it, between the protruding electrode and another terminal electrode that does not face it, between the protruding electrodes,
And to insulate between the terminal electrodes. Therefore, by forming only one anisotropic conductive layer, it is possible to electrically connect all the protruding electrodes and the terminal electrodes facing them,
The step of applying a conductive adhesive or the like to the tip of each protruding electrode can be omitted. In addition, the thickness of the anisotropic conductive layer is made substantially equal to the gap between the semiconductor element and the circuit board, and the gap between the semiconductor element and the circuit board is sealed so that the sealing resin is applied between the semiconductor element and the circuit board. The step of injecting into can be omitted.
【００３３】一方、本発明の半導体素子の実装方法は、
半導体素子の回路上の所定位置に突起電極を形成し、半
導体素子を回路基板に対してフェイスダウン状態にし、
その状態で突起電極を接合層を介して回路基板の端子電
極に電気的に接続し、半導体素子と回路基板との間隙及
び半導体素子の側面を機械的に補強するために無機物の
剛体フィラ−及び有機物の樹脂を含む第１の封止樹脂を
注入し、半導体素子の回路が設けられている面及び側面
の少なくとも一部をと接触するように有機物の樹脂のみ
で構成された第２の封止樹脂を注入するように構成され
ている。すなわち、上記本発明の第１の半導体ユニット
を製造するために、封止樹脂を剛体フィラーを含む第１
の封止樹脂と剛体フィラーを含まない第２の封止樹脂の
２工程に分けて注入するようにしたものである。その結
果、見掛け上回路基板側に剛体フィラーが沈降したよう
に分布させることができる。On the other hand, the semiconductor element mounting method of the present invention is
A protruding electrode is formed at a predetermined position on the circuit of the semiconductor element, and the semiconductor element is placed facedown with respect to the circuit board.
In this state, the protruding electrode is electrically connected to the terminal electrode of the circuit board through the bonding layer, and the rigid body filler of an inorganic material and the inorganic filler are used to mechanically reinforce the gap between the semiconductor element and the circuit board and the side surface of the semiconductor element. A second encapsulation made of only an organic resin so as to inject a first encapsulating resin containing an organic resin and to contact at least a part of a surface and a side surface of a semiconductor element on which circuits are provided. It is configured to inject resin. That is, in order to manufacture the above-mentioned first semiconductor unit of the present invention, the sealing resin is used as a first resin containing a rigid filler.
The sealing resin and the second sealing resin containing no rigid filler are separately injected in two steps. As a result, it is possible to distribute the rigid filler as if it were settled on the apparent circuit board side.
【００３４】第１の封止樹脂の有機物の樹脂と第２の封
止樹脂の有機物の樹脂は同様の性質を有していればよ
く、材料は特に限定されない。しかし、両者が同じ成分
であればなお好ましい。また、半導体素子の側面及び回
路が設けられている面の回路を除いた部分の少なくとも
一部を半導体素子と同じ材料又は無機物の砥粒で摩擦
し、または、半導体素子の側面及び回路が設けられてい
る面の回路を除いた部分の少なくとも一部に半導体素子
と同じ材料又は無機物の砥粒を高温圧着し、凹凸面を形
成することにより、半導体素子と有機物の樹脂との接触
面積が増加し、半導体素子と封止樹脂との密着力を更に
高くすることができる。The organic resin of the first sealing resin and the organic resin of the second sealing resin may have the same properties, and the materials are not particularly limited. However, it is more preferable if both are the same component. In addition, at least a part of the side surface of the semiconductor element and the surface where the circuit is provided, excluding the circuit, is rubbed with abrasive grains of the same material as the semiconductor element or an inorganic material, or the side surface and the circuit of the semiconductor element are provided. At least a part of the surface except the circuit is pressure-bonded with abrasive particles of the same material as the semiconductor element or an inorganic material to form an uneven surface, thereby increasing the contact area between the semiconductor element and the organic resin. Further, the adhesive force between the semiconductor element and the sealing resin can be further increased.
【００３５】前述の第１の封止樹脂と第２の封止樹脂の
注入順序は特に限定されず、先に半導体素子と回路基板
との間隙の回路基板側に第１の封止樹脂を注入し、次に
半導体素子と回路基板との間隙の半導体素子側に第２の
封止樹脂を注入してもよいし、または、先に半導体素子
と回路基板との間隙の半導体素子側に第２の封止樹脂を
注入し、次に半導体素子と回路基板との間隙の回路基板
側に第１の封止樹脂を注入してもよい。そのため、半導
体素子の形状等に応じて注入しやすい方を先に注入すれ
ばよく、半導体素子の実装方法に自由度を持たせること
ができる。The order of injecting the first sealing resin and the second sealing resin is not particularly limited, and the first sealing resin is first injected into the circuit board side of the gap between the semiconductor element and the circuit board. Then, the second sealing resin may be injected into the semiconductor element side of the gap between the semiconductor element and the circuit board, or the second sealing resin may be injected into the semiconductor element side of the gap between the semiconductor element and the circuit board first. Alternatively, the first sealing resin may be injected into the gap between the semiconductor element and the circuit board on the circuit board side. Therefore, depending on the shape of the semiconductor element and the like, the one that is easier to inject may be injected first, and the degree of freedom in mounting the semiconductor element can be increased.
【００３６】また、本発明の別の半導体素子の実装方法
は、半導体素子の回路上の所定位置に突起電極を形成
し、回路基板上の半導体素子のほぼ全面に対向する位置
に異方性導電層を形成し、半導体素子を回路基板に対し
てフェイスダウン状態にし、その状態で突起電極を異方
性導電層を介して回路基板の端子電極に電気的に接続
し、少なくとも回路基板と半導体素子の側面を機械的に
補強するために無機物の剛体フィラ−及び有機物の樹脂
を含む封止樹脂を剛体フィラーが回路基板側に分布する
ように塗布するように構成されている。すなわち、この
方法により、上記本発明の第２の半導体ユニットを製造
することができる。また、封止樹脂を、無機物の剛体フ
ィラ−及び有機物の樹脂を含む第１の封止樹脂と有機物
の樹脂のみで構成された第２の封止樹脂の２工程に分離
し、第１の封止樹脂を回路基板側に塗布し、第２の封止
樹脂を半導体素子側に塗布することにより、見掛け上回
路基板側に剛体フィラーが沈降したように分布させるこ
とができる。Further, according to another method of mounting a semiconductor element of the present invention, a protruding electrode is formed at a predetermined position on the circuit of the semiconductor element, and anisotropic conductive is provided at a position facing substantially the entire surface of the semiconductor element on the circuit board. A layer is formed, the semiconductor element is placed facedown with respect to the circuit board, and in that state, the protruding electrode is electrically connected to the terminal electrode of the circuit board through the anisotropic conductive layer, and at least the circuit board and the semiconductor element. In order to mechanically reinforce the side surface of the resin, a sealing resin containing an inorganic rigid filler and an organic resin is applied so that the rigid filler is distributed to the circuit board side. That is, the second semiconductor unit of the present invention can be manufactured by this method. Further, the sealing resin is separated into two steps of a first sealing resin containing a rigid inorganic filler and an organic resin, and a second sealing resin composed only of an organic resin, and a first sealing resin is obtained. By applying the stop resin on the circuit board side and the second sealing resin on the semiconductor element side, the rigid filler can be distributed as if it were apparently settled on the circuit board side.
【図１】本発明の半導体ユニット及び半導体素子の実装
方法の第１の実施形態を示す図であり、（ａ）は側面１
及び回路が設けられている面における回路を除いた部分
２に凹凸が設けられている半導体素子６を回路基板９上
に実装した半導体ユニットの構成を示す断面図、（ｂ）
は側面１及び回路が設けられている面における回路を除
いた部分２に凹凸が設けられていない半導体素子６を回
路基板９上に実装した半導体ユニットの構成を示す断面
図である。FIG. 1 is a diagram showing a first embodiment of a mounting method of a semiconductor unit and a semiconductor element of the present invention, in which (a) is a side surface 1;
And a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 6 in which unevenness is provided on a portion 2 excluding the circuit on the surface provided with the circuit is mounted on a circuit board 9, (b)
FIG. 3 is a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 6 having no unevenness provided on a side surface 1 and a portion 2 except a circuit on a surface provided with a circuit is mounted on a circuit board 9.
【図２】本発明の半導体ユニット及び半導体素子の実装
方法の第２の実施形態を示す図であり、（ａ）は側面３
１及び回路が設けられている面における回路を除いた部
分３２に凹凸が設けられている半導体素子３６を回路基
板３９上に実装した半導体ユニットの構成を示す断面
図、（ｂ）は側面３１及び回路が設けられている面にお
ける回路を除いた部分３２に凹凸が設けられていない半
導体素子３６を回路基板３９上に実装した半導体ユニッ
トの構成を示す断面図である。FIG. 2 is a diagram showing a second embodiment of a mounting method of a semiconductor unit and a semiconductor element of the present invention, in which (a) is a side surface 3;
1 and a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 36 in which irregularities are provided on a portion 32 excluding the circuit on the surface on which the circuit is provided is mounted on a circuit board 39, and FIG. FIG. 9 is a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 36 having no unevenness on a portion other than a circuit on a surface on which a circuit is provided is mounted on a circuit board 39.
【図３】本発明の半導体ユニット及び半導体素子の実装
方法の第３の実施形態を示す図であり、（ａ）は側面４
１及び回路が設けられている面における回路を除いた部
分４２に凹凸が設けられている半導体素子４６を回路基
板４９上に実装した半導体ユニットの構成を示す断面
図、（ｂ）は側面４１及び回路が設けられている面にお
ける回路を除いた部分４２に凹凸が設けられていない半
導体素子４６を回路基板４９上に実装した半導体ユニッ
トの構成を示す断面図である。FIG. 3 is a diagram showing a third embodiment of a mounting method of a semiconductor unit and a semiconductor element of the present invention, in which (a) is a side surface 4;
1 and a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 46 in which irregularities are provided on a portion 42 excluding the circuit on the surface on which the circuit is provided is mounted on a circuit board 49, and FIG. FIG. 11 is a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 46 having no unevenness provided on a portion other than a circuit on a surface provided with a circuit is mounted on a circuit board 49.
【図４】本発明の半導体ユニット及び半導体素子の実装
方法の第４の実施形態を示す図であり、（ａ）は側面５
１及び回路が設けられている面における回路を除いた部
分５２に凹凸が設けられている半導体素子５６を回路基
板５９上に実装した半導体ユニットの構成を示す断面
図、（ｂ）は側面５１及び回路が設けられている面にお
ける回路を除いた部分５２に凹凸が設けられていない半
導体素子５６を回路基板５９上に実装した半導体ユニッ
トの構成を示す断面図である。FIG. 4 is a diagram showing a fourth embodiment of a mounting method of a semiconductor unit and a semiconductor element of the present invention, in which (a) is a side surface 5;
1 and a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 56 in which unevenness is provided on a portion 52 on the surface where the circuit is provided is provided on a circuit board 59, FIG. FIG. 9 is a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 56 having no unevenness on a portion of the surface on which the circuit is provided except the circuit is mounted on a circuit board 59.
【図５】本発明の半導体ユニット及び半導体素子の実装
方法の第５の実施形態を示す図であり、（ａ）は側面６
１及び回路が設けられている面における回路を除いた部
分６２に凹凸が設けられている半導体素子６６を回路基
板６９上に実装した半導体ユニットの構成を示す断面
図、（ｂ）は側面６１及び回路が設けられている面にお
ける回路を除いた部分６２に凹凸が設けられていない半
導体素子６６を回路基板６９上に実装した半導体ユニッ
トの構成を示す断面図である。FIG. 5 is a diagram showing a fifth embodiment of a method of mounting a semiconductor unit and a semiconductor element of the present invention, in which (a) is a side surface 6;
1 and a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 66 having irregularities is provided on a portion 62 excluding the circuit on the surface on which the circuit is provided is mounted on a circuit board 69, FIG. FIG. 11 is a cross-sectional view showing a configuration of a semiconductor unit in which a semiconductor element 66 having no unevenness on a portion of the surface on which the circuit is provided except the circuit is mounted on a circuit board 69.
【図６】半導体素子の実装方法に関する第６の実施形態
を示す図であり、図１から図５の各（ａ）に示すような
半導体素子の側面及び回路が設けられている面における
回路を除いた部分を砥石又は砥粒で摩擦することにより
凹凸を形成する工程を示す図である。FIG. 6 is a diagram showing a sixth embodiment relating to a method for mounting a semiconductor element, and shows a circuit on a side surface of a semiconductor element and a surface on which a circuit is provided as shown in each (a) of FIGS. 1 to 5; It is a figure which shows the process of forming unevenness by rubbing the removed part with a grindstone or an abrasive grain.
【図７】本発明の半導体素子の実装方法に関する第６の
実施形態を示す図であり、図１から図５の各（ａ）に示
すような半導体素子の側面及び回路が設けられている面
における回路を除いた部分に砥粒を高温圧着することに
より凹凸を形成する工程を示す図である。FIG. 7 is a diagram showing a sixth embodiment of the method for mounting a semiconductor element of the present invention, the side surface of the semiconductor element and the surface provided with a circuit as shown in each (a) of FIGS. 1 to 5. FIG. 6 is a diagram showing a step of forming irregularities by hot-pressing abrasive grains to a portion excluding the circuit in FIG.
【図８】本発明の半導体素子の実装方法に関する第７の
実施形態を示す図であり、半導体素子と回路基板との間
に封止樹脂を注入する方法の一例を示す図である。FIG. 8 is a diagram showing a seventh embodiment of a semiconductor element mounting method of the invention, and is a diagram showing an example of a method of injecting a sealing resin between a semiconductor element and a circuit board.
【図９】本発明の半導体素子の実装方法に関する第７の
実施形態を示す図であり、半導体素子と回路基板との間
に封止樹脂を注入する方法の他の例を示す図である。FIG. 9 is a diagram showing a seventh embodiment of a semiconductor element mounting method of the invention, and is a diagram showing another example of a method of injecting a sealing resin between a semiconductor element and a circuit board.
【図１０】（ａ）は従来の半導体素子における半田バン
プの概略構成を示す断面図であり、（ｂ）は従来の半導
体ユニットの概略構成を示す断面図である。10A is a sectional view showing a schematic configuration of a solder bump in a conventional semiconductor element, and FIG. 10B is a sectional view showing a schematic configuration of a conventional semiconductor unit.
【図１１】従来の導電性接着剤を用いた半導体ユニット
の概略構成を示す断面図FIG. 11 is a sectional view showing a schematic configuration of a semiconductor unit using a conventional conductive adhesive.
１ ：半導体素子の側面 ２ ：半導体素子の回路が設けられている面の回路以外
の部分 ３ ：電極パッド ４ ：封止樹脂 ４ａ：剛体フィラー ５ ：導電層（導電性接着剤） ６ ：半導体素子 ７ ：突起電極 ７ａ：断面積の大きい部分 ７ｂ：断面積の小さい部分 ８ ：端子電極 ９ ：回路基板 ３０ ：突起電極（半田バンプ） ３１ ：半導体素子の側面 ３２ ：半導体素子の回路が設けられている面の回路以
外の部分 ３３ ：電極パッド ３４ ：封止樹脂 ３４ａ：剛体フィラー ３５ ：導電層（導電性接着剤） ３６ ：半導体素子 ３７ ：金属膜 ３８ ：端子電極 ３９ ：回路基板 ４１ ：半導体素子の側面 ４２ ：半導体素子の回路が設けられている面の回路以
外の部分 ４３ ：電極パッド ４４ ：封止樹脂 ４４ａ：剛体フィラー ４５ ：導電層（導電性接着剤） ４６ ：半導体素子 ４７ ：突起電極 ４８ ：端子電極 ４９ ：回路基板 ５１ ：半導体素子の側面 ５２ ：半導体素子の回路が設けられている面の回路以
外の部分 ５３ ：電極パッド ５４ ：封止樹脂 ５４ａ：剛体フィラー ５５ ：導電層（異方性導電材） ５６ ：半導体素子 ５７ ：突起電極 ５８ ：端子電極 ５９ ：回路基板 ６１ ：半導体素子の側面 ６２ ：半導体素子の回路が設けられている面の回路以
外の部分 ６３ ：電極パッド ６４ ：封止樹脂 ６４ａ：剛体フィラー ６５ ：導電層（異方性導電材） ６６ ：半導体素子 ６７ ：突起電極 ６８ ：端子電極 ６９ ：回路基板 ７１ ：半導体素子の側面 ７５ ：砥石又は砥粒 ８１ ：半導体素子の側面 ８５ ：砥粒 ９１ ：ノズル ９２ ：第１の封止樹脂 ９３ ：第２の封止樹脂 ９４ ：封止樹脂の塗布された部分 ９６ ：半導体素子 ９９ ：回路基板 １０１ ：ノズル １０２ ：第２の封止樹脂 １０３ ；第１の封止樹脂 １０４ ：封止樹脂の塗布された部分 １０６ ：半導体素子 １０９ ：回路基板1: Side surface of semiconductor element 2: Portion other than the circuit on the surface of semiconductor element circuit 3: Electrode pad 4: Sealing resin 4a: Rigid filler 5: Conductive layer (conductive adhesive) 6: Semiconductor element 7: Projection electrode 7a: Large cross-section area 7b: Small cross-section area 8: Terminal electrode 9: Circuit board 30: Projection electrode (solder bump) 31: Side surface of semiconductor element 32: Semiconductor circuit is provided Part other than the circuit on the surface 33: Electrode pad 34: Sealing resin 34a: Rigid filler 35: Conductive layer (conductive adhesive) 36: Semiconductor element 37: Metal film 38: Terminal electrode 39: Circuit board 41: Semiconductor element Side surface 42 of the semiconductor element circuit other than the circuit 43: Electrode pad 44: Sealing resin 44a: Rigid filler 45: Conductive layer (conductive contact) Adhesive) 46: Semiconductor element 47: Projection electrode 48: Terminal electrode 49: Circuit board 51: Side surface of semiconductor element 52: Portion other than the circuit on the surface of the semiconductor element on which the circuit is provided 53: Electrode pad 54: Sealing Resin 54a: Rigid filler 55: Conductive layer (anisotropic conductive material) 56: Semiconductor element 57: Projection electrode 58: Terminal electrode 59: Circuit board 61: Side surface of semiconductor element 62: Surface on which circuit of semiconductor element is provided Other than the circuit 63: Electrode pad 64: Sealing resin 64a: Rigid filler 65: Conductive layer (anisotropic conductive material) 66: Semiconductor element 67: Projection electrode 68: Terminal electrode 69: Circuit board 71: Semiconductor element Side surface 75: Grindstone or abrasive grain 81: Side surface of semiconductor element 85: Abrasive grain 91: Nozzle 92: First sealing resin 93: Second sealing resin 94: Sealing Resin-applied portion 96: Semiconductor element 99: Circuit board 101: Nozzle 102: Second sealing resin 103; First sealing resin 104: Encapsulating resin-coated portion 106: Semiconductor element 109: Circuit substrate
Claims (17)
態で半導体素子を実装した半導体ユニットであって、前
記半導体素子に設けられた突起電極を前記回路基板の前
記端子電極に接合層を介して電気的に接続し、かつ前記
半導体素子と前記回路基板との間隙及び前記半導体素子
の側面が無機物の剛体フィラ−及び有機物の樹脂を含む
封止樹脂で機械的に補強され、前記剛体フィラーは前記
突起電極と前記端子電極の接合部を囲むように前記回路
基板側に分布している半導体ユニット。1. A semiconductor unit in which a semiconductor element is mounted facedown on a terminal electrode of a circuit board, wherein a protruding electrode provided on the semiconductor element is electrically connected to the terminal electrode of the circuit board via a bonding layer. Electrically connected, and the gap between the semiconductor element and the circuit board and the side surface of the semiconductor element are mechanically reinforced with a sealing resin containing an inorganic rigid filler and an organic resin, and the rigid filler is the protrusion. A semiconductor unit distributed on the side of the circuit board so as to surround a joint between an electrode and the terminal electrode.
とも２つの部分を有し、断面積の小さい側を前記回路基
板側に配置した請求項１記載の半導体ユニット。2. The semiconductor unit according to claim 1, wherein the bump electrode has at least two portions having different cross-sectional areas, and the side having the smaller cross-sectional area is arranged on the circuit board side.
面及び側面のうち、前記有機物の樹脂と接触している部
分の表面に凹凸が設けられている請求項１又は２記載の
半導体ユニット。3. The semiconductor unit according to claim 1, wherein unevenness is provided on a surface of a portion of the surface of the semiconductor element on which the circuit is provided and a side surface of the semiconductor element that is in contact with the organic resin.
田及びこれらの合金から選択されたいずれかで形成され
ている請求項１から３のいずれかに記載の半導体ユニッ
ト。4. The semiconductor unit according to claim 1, wherein the protruding electrode is formed of any one selected from Au, Cu, Al, solder and alloys thereof.
いる請求項１から４のいずれかに記載の半導体ユニッ
ト。5. The semiconductor unit according to claim 1, wherein the bonding layer is made of a conductive adhesive.
いる請求項１から４のいずれかに記載の半導体ユニッ
ト。6. The semiconductor unit according to claim 1, wherein the bonding layer is made of an anisotropic conductive material.
から６のいずれかに記載の半導体ユニット。7. The encapsulating resin has a pH ≦ 8.
7. The semiconductor unit according to any one of 1 to 6.
態で半導体素子を実装した半導体ユニットであって、前
記回路基板上に前記半導体素子のほぼ全面に対向するよ
うに設けられた異方性導電層を介して、前記半導体素子
に設けられた突起電極と前記回路基板の前記端子電極と
を電気的に接続し、かつ少なくとも前記回路基板と前記
半導体素子の側面が無機物の剛体フィラ−及び有機物の
樹脂を含む封止樹脂で機械的に補強され、前記剛体フィ
ラーは前記回路基板側に分布している半導体ユニット。8. A semiconductor unit in which a semiconductor element is mounted face down on a terminal electrode of a circuit board, the anisotropic conductive layer being provided on the circuit board so as to face substantially the entire surface of the semiconductor element. Through, electrically connect the protruding electrode provided on the semiconductor element and the terminal electrode of the circuit board, and at least the side surface of the circuit board and the semiconductor element is an inorganic rigid filler and an organic resin. A semiconductor unit in which the rigid filler is mechanically reinforced with a sealing resin containing, and the rigid filler is distributed on the circuit board side.
前記回路基板との隙間とほぼ等しい厚みを有し、前記半
導体素子と前記回路基板との隙間を封止する請求項８記
載の半導体ユニット。9. The anisotropic conductive layer has a thickness substantially equal to a gap between the semiconductor element and the circuit board, and seals the gap between the semiconductor element and the circuit board. Semiconductor unit.
電極を形成し、前記半導体素子を回路基板に対してフェ
イスダウン状態にし、その状態で前記突起電極を接合層
を介して前記回路基板の端子電極に電気的に接続し、前
記半導体素子と前記回路基板との間隙及び前記半導体素
子の側面を機械的に補強するために無機物の剛体フィラ
−及び有機物の樹脂を含む第１の封止樹脂を注入し、前
記半導体素子の回路が設けられている面及び側面の少な
くとも一部と接触するように有機物の樹脂のみで構成さ
れた第２の封止樹脂を注入する半導体素子の実装方法。10. A projecting electrode is formed at a predetermined position on a circuit of a semiconductor element, the semiconductor element is placed facedown with respect to a circuit board, and in this state, the projecting electrode is formed on the circuit board via a bonding layer. A first sealing resin containing a rigid inorganic filler and an organic resin to electrically connect to a terminal electrode and mechanically reinforce the gap between the semiconductor element and the circuit board and the side surface of the semiconductor element. And a second sealing resin composed only of an organic resin so as to come into contact with at least a part of the surface and side surface of the semiconductor element on which the circuit is provided.
前記第２の封止樹脂の有機物の樹脂が同じ成分である請
求項１０記載の半導体素子の実装方法。11. The method of mounting a semiconductor element according to claim 10, wherein the organic resin of the first sealing resin and the organic resin of the second sealing resin are the same component.
られている面の回路を除いた部分の少なくとも一部を、
前記半導体素子と同じ材料又は無機物の砥粒で摩擦し、
凹凸を形成する請求項１０又は１１記載の半導体素子の
実装方法。12. At least a part of a side surface of the semiconductor element and a surface on which a circuit is provided, excluding a circuit,
Rubbing with the same material as the semiconductor element or inorganic abrasive grains,
The method for mounting a semiconductor element according to claim 10, wherein unevenness is formed.
られている面の回路を除いた部分の少なくとも一部に、
前記半導体素子と同じ材料又は無機物の砥粒を高温圧着
し、凹凸を形成する請求項１０又は１１記載の半導体素
子の実装方法。13. A side surface of the semiconductor element and at least a part of a surface provided with a circuit excluding a circuit,
The method for mounting a semiconductor element according to claim 10 or 11, wherein abrasive grains of the same material as that of the semiconductor element or an inorganic material are pressure-bonded at high temperature to form irregularities.
の間隙の前記回路基板側に前記第１の封止樹脂を注入
し、次に前記半導体素子と前記回路基板との間隙の前記
半導体素子側に前記第２の封止樹脂を注入する請求項１
０から１３のいずれかに記載の半導体素子の実装方法。14. The first sealing resin is first injected into the circuit board side of the gap between the semiconductor element and the circuit board, and then the semiconductor element in the gap between the semiconductor element and the circuit board. The second sealing resin is injected into the side.
14. The method for mounting a semiconductor device according to any one of 0 to 13.
の間隙の前記半導体素子側に前記第２の封止樹脂を注入
し、次に前記半導体素子と前記回路基板との間隙の前記
回路基板側に前記第１の封止樹脂を注入する請求項１０
から１３のいずれかに記載の半導体素子の実装方法。15. The circuit board in the gap between the semiconductor element and the circuit board is first injected into the gap between the semiconductor element and the circuit board in the semiconductor element side. The said 1st sealing resin is inject | poured into the side.
14. The method for mounting a semiconductor device according to any one of 1 to 13.
電極を形成し、回路基板上の前記半導体素子のほぼ全面
に対向する位置に異方性導電層を形成し、前記半導体素
子を回路基板に対してフェイスダウン状態にし、その状
態で前記突起電極を前記異方性導電層を介して前記回路
基板の端子電極に電気的に接続し、少なくとも前記回路
基板と前記半導体素子の側面を機械的に補強するために
無機物の剛体フィラ−及び有機物の樹脂を含む封止樹脂
を前記剛体フィラーが前記回路基板側に分布するように
塗布する半導体素子の実装方法。16. A projection electrode is formed at a predetermined position on a circuit of a semiconductor element, and an anisotropic conductive layer is formed on a circuit board at a position facing substantially the entire surface of the semiconductor element, and the semiconductor element is formed on the circuit board. The face-down state, the protruding electrodes are electrically connected to the terminal electrodes of the circuit board through the anisotropic conductive layer in that state, and at least the side surfaces of the circuit board and the semiconductor element are mechanically connected. A method of mounting a semiconductor element, wherein a sealing resin containing an inorganic rigid filler and an organic resin for reinforcement is applied so that the rigid filler is distributed to the circuit board side.
−及び有機物の樹脂を含む第１の封止樹脂と有機物の樹
脂のみで構成された第２の封止樹脂からなり、前記第１
の封止樹脂を前記回路基板側に塗布し、前記第２の封止
樹脂を前記半導体素子側に塗布する請求項１６記載の半
導体素子の実装方法。17. The sealing resin comprises a first sealing resin containing a rigid filler of an inorganic material and an organic resin, and a second sealing resin composed of only an organic resin.
17. The method for mounting a semiconductor element according to claim 16, wherein the sealing resin is applied to the circuit board side, and the second sealing resin is applied to the semiconductor element side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31539795A JP3343317B2 (en) | 1995-12-04 | 1995-12-04 | Semiconductor unit and method of mounting semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31539795A JP3343317B2 (en) | 1995-12-04 | 1995-12-04 | Semiconductor unit and method of mounting semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09162229A true JPH09162229A (en) | 1997-06-20 |
| JP3343317B2 JP3343317B2 (en) | 2002-11-11 |
Family
ID=18064907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31539795A Expired - Lifetime JP3343317B2 (en) | 1995-12-04 | 1995-12-04 | Semiconductor unit and method of mounting semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3343317B2 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5981313A (en) * | 1996-10-02 | 1999-11-09 | Nec Corporation | Structure and method for packaging a semiconductor device |
| WO2000033374A1 (en) * | 1998-12-02 | 2000-06-08 | Seiko Epson Corporation | Anisotropic conductor film, semiconductor chip, and method of packaging |
| JP2000286297A (en) * | 1999-01-29 | 2000-10-13 | Matsushita Electric Ind Co Ltd | Mounting method for electronic component and its device |
| JP2000286298A (en) * | 1999-01-29 | 2000-10-13 | Matsushita Electric Ind Co Ltd | Method for mounting electronic component and device thereof |
| JP2007288228A (en) * | 1999-01-29 | 2007-11-01 | Matsushita Electric Ind Co Ltd | Electronic component mounting method, and apparatus thereof |
| US7683482B2 (en) | 1999-01-29 | 2010-03-23 | Panasonic Corporation | Electronic component unit |
| JP2011077167A (en) * | 2009-09-29 | 2011-04-14 | Toshiba Corp | Mounting method for electronic component |
| JP2011091461A (en) * | 2011-02-10 | 2011-05-06 | Toshiba Corp | Apparatus and magnetic force application device |
| JP2011134750A (en) * | 2009-12-22 | 2011-07-07 | Panasonic Electric Works Co Ltd | Semiconductor device |
| US20170338193A1 (en) * | 2014-10-24 | 2017-11-23 | Danfoss Silicon Power Gmbh | Power semiconductor module with short-circuit failure mode |
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|---|---|---|---|---|
| JPH0329207A (en) * | 1988-12-05 | 1991-02-07 | Hitachi Chem Co Ltd | Composition for circuit connection and connection method and connection structure of semiconductor chip using the composition |
| JPH03224245A (en) * | 1990-01-30 | 1991-10-03 | Sanken Electric Co Ltd | Manufacture of circuit board device |
| JPH04127548A (en) * | 1990-09-19 | 1992-04-28 | Fujitsu Ltd | Semiconductor device |
| JPH0513119A (en) * | 1991-07-04 | 1993-01-22 | Sharp Corp | Tape connector for connecting electronic parts |
| JPH0653279A (en) * | 1992-07-31 | 1994-02-25 | Fujitsu Ltd | Connecting method for board using conductive adhesive to chip |
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0329207A (en) * | 1988-12-05 | 1991-02-07 | Hitachi Chem Co Ltd | Composition for circuit connection and connection method and connection structure of semiconductor chip using the composition |
| JPH03224245A (en) * | 1990-01-30 | 1991-10-03 | Sanken Electric Co Ltd | Manufacture of circuit board device |
| JPH04127548A (en) * | 1990-09-19 | 1992-04-28 | Fujitsu Ltd | Semiconductor device |
| JPH0513119A (en) * | 1991-07-04 | 1993-01-22 | Sharp Corp | Tape connector for connecting electronic parts |
| JPH0653279A (en) * | 1992-07-31 | 1994-02-25 | Fujitsu Ltd | Connecting method for board using conductive adhesive to chip |
| JPH08195414A (en) * | 1995-01-12 | 1996-07-30 | Toshiba Corp | Semiconductor device |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5981313A (en) * | 1996-10-02 | 1999-11-09 | Nec Corporation | Structure and method for packaging a semiconductor device |
| WO2000033374A1 (en) * | 1998-12-02 | 2000-06-08 | Seiko Epson Corporation | Anisotropic conductor film, semiconductor chip, and method of packaging |
| US6414397B1 (en) | 1998-12-02 | 2002-07-02 | Seiko Epson Corporation | Anisotropic conductive film, method of mounting semiconductor chip, and semiconductor device |
| JP2000286297A (en) * | 1999-01-29 | 2000-10-13 | Matsushita Electric Ind Co Ltd | Mounting method for electronic component and its device |
| JP2000286298A (en) * | 1999-01-29 | 2000-10-13 | Matsushita Electric Ind Co Ltd | Method for mounting electronic component and device thereof |
| JP2007288228A (en) * | 1999-01-29 | 2007-11-01 | Matsushita Electric Ind Co Ltd | Electronic component mounting method, and apparatus thereof |
| US7683482B2 (en) | 1999-01-29 | 2010-03-23 | Panasonic Corporation | Electronic component unit |
| US8007627B2 (en) | 1999-01-29 | 2011-08-30 | Panasonic Corporation | Electronic component mounting method and apparatus |
| JP2011077167A (en) * | 2009-09-29 | 2011-04-14 | Toshiba Corp | Mounting method for electronic component |
| JP2011134750A (en) * | 2009-12-22 | 2011-07-07 | Panasonic Electric Works Co Ltd | Semiconductor device |
| JP2011091461A (en) * | 2011-02-10 | 2011-05-06 | Toshiba Corp | Apparatus and magnetic force application device |
| US20170338193A1 (en) * | 2014-10-24 | 2017-11-23 | Danfoss Silicon Power Gmbh | Power semiconductor module with short-circuit failure mode |
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|---|---|
| JP3343317B2 (en) | 2002-11-11 |
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