JPH09129849A - Capacitor of semiconductor element and its preparation - Google Patents
Capacitor of semiconductor element and its preparationInfo
- Publication number
- JPH09129849A JPH09129849A JP8001741A JP174196A JPH09129849A JP H09129849 A JPH09129849 A JP H09129849A JP 8001741 A JP8001741 A JP 8001741A JP 174196 A JP174196 A JP 174196A JP H09129849 A JPH09129849 A JP H09129849A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- electrode
- semiconductor device
- manufacturing
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子のキャ
パシター及びその製造方法に係るもので、詳しくは、高
集積（high-intergrated）ＤＲＡＭ（dynamic random
access memory）素子のキャパシターとして必要な高
誘電膜キャパシターに適合する半導体素子のキャパシタ
ー及びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device and a method of manufacturing the same, and more particularly to a high-intergrated DRAM (dynamic random)
The present invention relates to a semiconductor device capacitor suitable for a high dielectric film capacitor required as a capacitor for an access memory device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、半導体素子の高集積化に伴い、１
６Ｍｂｉｔｓ及び６４ＭｂｉｔｓのＤＲＡＭは量産され
ているが、２５６Ｍｂｉｔｓ、１ＧｂｉｔのＤＲＡＭは
未だ開発段階である。即ち、該ＤＲＡＭの高集積化に従
い単位セル（ｃｅｌｌ）のキャパシタンス領域が減小す
るので、その縮小された領域で所望のキャパシタンスを
得る研究が活発に行われている。従って、高誘電体材料
（high dielectric constant material）のキャパシタ
ー誘導体フィールムを用い、高誘電体薄膜を形成する研
究が進行されており、該高誘電体材料の物質は複合酸化
物の形態として、主に、ＢａＳｒＴｉＯ3 （ＢＳＴ）、
ＢａＴｉＯ3 、ＳｒＴｉＯ3 、ＰｂＺｒＯ3 等が用いら
れている。2. Description of the Related Art Conventionally, with the increasing integration of semiconductor devices, 1
DRAMs of 6 Mbits and 64 Mbits are mass-produced, but DRAMs of 256 Mbits and 1 Gbit are still in the development stage. That is, since the capacitance area of a unit cell is reduced in accordance with the high integration of the DRAM, studies for obtaining a desired capacitance in the reduced area are being actively conducted. Therefore, research is underway to form a high dielectric thin film using a capacitor dielectric film of a high dielectric constant material, and the substance of the high dielectric material is mainly in the form of complex oxide. , BaSrTiO 3 (BST),
BaTiO 3 , SrTiO 3 , PbZrO 3 and the like are used.
【０００３】且つ、このような複合酸化物の形態は、６
００ー７００℃の高温下でフィールムの蒸着が行われる
ため、該高温に適合する電極の物質及び電極の構造を得
ることが主要な課題となっている。そこで、従来多結晶
シリコンを電極の材料として用いていたが、該多結晶シ
リコンは蒸着の際、酸化して拡散されるので、その酸化
をある程度抑止する物質を用いるべきであった。従っ
て、高誘電体膜をキャパシター誘導体に用いるときは、
電極の構造を多層に構成し、該誘電体と基板間の拡散を
防止する拡散障壁層（diffusion barrier）と、酸化を
ある程度抑制し電導性を有する電極層と、基板との電気
的連結を行う接続プラグと、を夫々形成していた。[0003] The form of such a composite oxide is 6
Since the film is deposited at a high temperature of 00 to 700 ° C., obtaining a material of the electrode and a structure of the electrode suitable for the high temperature has been a major issue. Therefore, although polycrystalline silicon has been conventionally used as a material for the electrodes, since the polycrystalline silicon is oxidized and diffused during vapor deposition, a substance that suppresses the oxidation to some extent should be used. Therefore, when using a high dielectric film for a capacitor derivative,
The electrode structure is configured in multiple layers, and a diffusion barrier layer (diffusion barrier) that prevents diffusion between the dielectric and the substrate, and an electrode layer that suppresses oxidation to some extent and has electrical conductivity are electrically connected to the substrate. The connection plug and the plug were formed respectively.
【０００４】即ち、従来、半導体素子のキャパシター及
びその製造方法においては、図２に示したように、半導
体基板１上に一双の絶縁ゲート電極２ａ、２ｂを有する
ＦＥＴトランジスタ（図示せず）が形成され、それらゲ
ート電極２ａ、２ｂ上に絶縁層３が形成され、該絶縁層
３の中央基板１上に接続ホールが食刻形成されて該接続
ホール内基板１上にソース叉はドレイン領域６が形成さ
れ、該ソース叉はドレイン領域６上面接続ホール内に多
結晶シリコンプラグ４が形成され、それら多結晶シリコ
ンプラグ４及び絶縁層上面にキャパシター５が形成され
ていた。且つ、該キャパシター５の構造及び形成段階に
おいては、先ず、前記多結晶シリコンプラグ４及び絶縁
層３上面所定部位にＴａ叉はＴｉＮのような導電性物質
の障壁層９が形成され、該障壁層９上に下部電極７ａが
形成され、それら下部電極７ａ上面及び障壁層９両方側
面にＢａＳｒＴｉＯ3 の誘電フィールム８が被覆され、
該誘電フィールム８上に上部電極７ｂが形成されてい
た。That is, in a conventional capacitor for a semiconductor device and a method for manufacturing the same, an FET transistor (not shown) having a pair of insulated gate electrodes 2a and 2b is formed on a semiconductor substrate 1 as shown in FIG. Then, the insulating layer 3 is formed on the gate electrodes 2a and 2b, and the connection hole is formed on the central substrate 1 of the insulating layer 3 to form the source or drain region 6 on the substrate 1 in the connection hole. The polycrystalline silicon plug 4 was formed in the upper surface connection hole of the source or drain region 6, and the capacitor 5 was formed on the polycrystalline silicon plug 4 and the upper surface of the insulating layer. In addition, in the structure and formation of the capacitor 5, first, a barrier layer 9 of a conductive material such as Ta or TiN is formed on a predetermined portion of the upper surface of the polycrystalline silicon plug 4 and the insulating layer 3, and the barrier layer is formed. A lower electrode 7a is formed on the upper surface of the lower electrode 7a, and a side surface of both of the lower electrode 7a and the barrier layer 9 is covered with a dielectric film 8 of BaSrTiO 3 .
The upper electrode 7b was formed on the dielectric film 8.
【０００５】[0005]
【発明が解決しようとする課題】然るに、このような従
来半導体素子のキャパシター及びその製造方法において
は、次のような不都合な点があった。、下部電極７ａ
及び障壁層９の積層された上面及び両方側面に誘電フィ
ールム８を被覆するようになっているため、該誘電フィ
ールム８の被覆の際、積層段のコーナー１０ａ、１０ｂ
部位に充填漏泄が発生し、該充填漏泄部位にＳｉＯ2 の
ような絶縁物質が蒸着され易いという憂いがあった。
、誘電フィールム８の蒸着される間、障壁層９の両方
側壁は露出されるため高温の障壁層９が酸化して接触抵
抗を起こし、該障壁層９両方側壁面の酸化物により該障
壁層９と下部電極７ａ間の接着性が低下される。、障
壁層９両方側壁面の酸化により該障壁層９と多結晶シリ
コンプラグ４間の接着性が低下し、該多結晶シリコンプ
ラグ４の表面が酸化する憂いがあった。However, in the conventional capacitor for the semiconductor device and the manufacturing method thereof, there are the following inconveniences. , Lower electrode 7a
Since the upper surface and both side surfaces of the barrier layer 9 which are stacked are coated with the dielectric film 8, the corners 10a and 10b of the stacked steps are coated when the dielectric film 8 is coated.
There has been a concern that a leakage of filling occurs at the portion and an insulating material such as SiO 2 is likely to be deposited on the portion of the filling leakage.
During the deposition of the dielectric film 8, both sidewalls of the barrier layer 9 are exposed, so that the high temperature barrier layer 9 oxidizes and causes contact resistance. The adhesion between the lower electrode 7a and the lower electrode 7a is reduced. The adhesion between the barrier layer 9 and the polycrystalline silicon plug 4 is reduced due to oxidation of the side wall surfaces of both the barrier layer 9 and the surface of the polycrystalline silicon plug 4 is oxidized.
【０００６】[0006]
【課題を解決するための手段】本発明の目的は、多層電
極形成時のエッチングを容易に行い、キャパシター面積
の縮小に伴うミスアラインの発生を減らし得る半導体素
子のキャパシター及びその製造方法を提供しようとする
ものである。叉、本発明の他の目的は、プラグの表面酸
化によりキャパシターの性能が低下する現象を防止し、
障壁層の酸化により体積が膨張し応力を受けて電極が割
れる現象を防止し得る半導体素子のキャパシター及びそ
の製造方法を提供しようとするものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitor of a semiconductor device and a method of manufacturing the same, which can easily perform etching when forming a multilayer electrode and reduce the occurrence of misalignment due to the reduction of the capacitor area. To do. Another object of the present invention is to prevent the phenomenon that the performance of the capacitor is deteriorated by the surface oxidation of the plug,
It is an object of the present invention to provide a capacitor for a semiconductor device and a method for manufacturing the same, which can prevent a phenomenon that an electrode is cracked due to expansion of volume due to oxidation of a barrier layer and stress.
【０００７】このような本発明の目的は、半導体基板上
に形成され接続ホールを有した絶縁膜と、該絶縁膜の接
続ホール内に該絶縁膜の厚さよりも低い厚さを有して形
成されたプラグと、該接続ホール内のプラグ上面に形成
された障壁層のＴｉＮプラグと、それらＴｉＮプラグ及
び絶縁膜上に形成されたキャパシター第１電極と、該キ
ャパシター第１電極上に形成された誘電体層と、該誘電
体層上に形成されたキャパシター第２電極と、を備えた
半導体素子のキャパシター及びその製造方法を提供する
ことにより達成される。It is an object of the present invention to form an insulating film formed on a semiconductor substrate and having a connection hole, and to have a thickness lower than the thickness of the insulating film in the connection hole of the insulating film. Plug, a TiN plug of a barrier layer formed on the upper surface of the plug in the connection hole, a capacitor first electrode formed on the TiN plug and the insulating film, and a capacitor first electrode formed on the capacitor first electrode This is achieved by providing a capacitor of a semiconductor device including a dielectric layer and a capacitor second electrode formed on the dielectric layer, and a method for manufacturing the same.
【０００８】[0008]
【発明の実施の形態】以下、本発明の実施の形態に対し
説明する。本発明に係る半導体素子のキャパシターにお
いては、図１（Ｊ）に示したように、半導体基板２０上
に形成され接続ホール２９を有した絶縁膜２８と、該絶
縁膜のＴｉＮプラグ３５と、それらＴｉＮプラグ３５及
び絶縁膜２８の接続ホール２９内に該絶縁膜２８の厚さ
よりも低い厚さを有して形成されたプラグ３２と、該接
続ホール２９内のプラグ３２上面に形成された障壁層２
８上に形成されたキャパシター第１電極３６と、該キャ
パシター第１電極３６上に形成された誘電体層４０と、
該誘電体層４０上に形成されたキャパシター第２電極４
２と、を備えている。Embodiments of the present invention will be described below. In the capacitor of the semiconductor element according to the present invention, as shown in FIG. 1 (J), the insulating film 28 formed on the semiconductor substrate 20 and having the connection hole 29, the TiN plug 35 of the insulating film, and A plug 32 formed in the connection hole 29 of the TiN plug 35 and the insulating film 28 with a thickness lower than that of the insulating film 28, and a barrier layer formed on the upper surface of the plug 32 in the connection hole 29. Two
8, a capacitor first electrode 36 formed on the capacitor 8, and a dielectric layer 40 formed on the capacitor first electrode 36,
Capacitor second electrode 4 formed on the dielectric layer 40
2 is provided.
【０００９】そして、本発明に係る半導体素子のキャパ
シターを製造する方法においては、図１（Ａ）に示した
ように、基板２０上に所定形状のゲート電極２２とｎ+
形不純物拡散（ソース／ドレイン）領域２４、２５とフ
ィールド酸化膜２６とを夫々形成する。次いで、それら
ゲート電極２２、ｎ+ 不純物拡散（ソース／ドレイン）
領域２４、２５及びフィールド酸化膜２６上に、図１
（Ｂ）に示したように、３０００Å厚さの絶縁膜２８を
化学蒸着法により蒸着する。次いで、図１（Ｃ）に示し
たように、該絶縁膜２８の所定部位に写真食刻を施しキ
ャパシターストレージノード（capacitor storage nod
e）の形成される接続ホール２９を形成する。その後、
それら接続ホール２９及び絶縁膜２８上に２０００Å厚
さの多結晶シリコン層３０を低圧化学蒸着法により蒸着
する。In the method of manufacturing the capacitor of the semiconductor device according to the present invention, as shown in FIG. 1A, the gate electrode 22 and n + having a predetermined shape are formed on the substrate 20.
Form impurity diffusion (source / drain) regions 24 and 25 and a field oxide film 26, respectively. Then, those gate electrodes 22, n + impurity diffusion (source / drain)
On the regions 24 and 25 and the field oxide 26, FIG.
As shown in (B), an insulating film 28 having a thickness of 3000 Å is deposited by a chemical vapor deposition method. Then, as shown in FIG. 1C, a predetermined portion of the insulating film 28 is photo-etched to form a capacitor storage node.
The connection hole 29 in which e) is formed is formed. afterwards,
A 2000 Å thick polycrystalline silicon layer 30 is deposited on the connection holes 29 and the insulating film 28 by a low pressure chemical vapor deposition method.
【００１０】次いで、図１（Ｄ）に示したように、該多
結晶シリコン層３０をＣｌ2 ／Ｏ 2 エッチング液を用い
３０００Åの厚さにエッチバックして除去し、前記接続
ホール２９内の絶縁膜２８上面から約１０００Å下方側
にプラグ３２を形成する。この場合、該プラグ３２は多
結晶シリコンにて形成される。次いで、図１（Ｅ）に示
したように、それらプラグ３２及び第１絶縁膜２８上に
障壁層の役割をするＴｉＮ層３４を１５００Åの厚さに
蒸着するが、この場合、該ＴｉＮ層３４は、Ｔａ、Ｗ、
Ｍｏの金属合金及びそれらの金属ケイ化物中何れ一つに
て代替することもできる。Then, as shown in FIG.
The crystalline silicon layer 30 is ClTwo/ O TwoWith etching solution
Etch back to a thickness of 3000Å to remove,
About 1000Å lower side from the upper surface of the insulating film 28 in the hole 29
Then, the plug 32 is formed. In this case, the plug 32 has many
It is made of crystalline silicon. Then, as shown in FIG.
As described above, on the plug 32 and the first insulating film 28,
The TiN layer 34, which functions as a barrier layer, has a thickness of 1500Å.
Evaporation is performed. In this case, the TiN layer 34 is formed of Ta, W,
Any one of Mo metal alloys and their metal silicides
Can be replaced.
【００１１】次いで、図１（Ｆ）に示したように、該Ｔ
ｉＮ層３４をＢＣｌ3 ／ＣＬ2 エッチバック液を用いＲ
ＩＥ（Reactive Ion Etching）法により１５００Åの厚
さにエッチングし、前記接続ホール２９内のプラグ３２
上にＴｉＮプラグ２３を形成する。次いで、図１（Ｇ）
に示したように、それらＴｉＮプラグ３５及び絶縁膜２
８上に２０００Å厚さのキャパシター第１電極３６をス
パッタリング法により蒸着するが、この場合、該第１電
極３６はＰｔを使用し、Ｐｔの代わりに、Ｐｄ、Ｒｕ、
ＲｕＯ2 及び電導性を有する酸化物中何れ一つを使用す
ることができる。Then, as shown in FIG.
The iN layer 34 is formed into R using BCl 3 / CL 2 etchback solution.
The plug 32 in the connection hole 29 is etched to a thickness of 1500Å by the IE (Reactive Ion Etching) method.
A TiN plug 23 is formed on top. Next, FIG.
As shown in, the TiN plug 35 and the insulating film 2
A 2000Å-thick capacitor first electrode 36 is deposited on the electrode 8 by a sputtering method. In this case, Pt is used as the first electrode 36, and Pd, Ru,
Any one of RuO 2 and an electrically conductive oxide can be used.
【００１２】次いで、図１（Ｈ）に示したように、該キ
ャパシター第１電極３６上面にマスク用の感光膜３８を
形成し、Ｐｔのキャパシター第１電極３６には写真食刻
を施してキャパシターストレージノードの形成される領
域を形成し、ＢＣｌ3 ／Ｃｌ2 エッチング液を用いてＲ
ＩＥ法によりエッチングを施し所定形状のキャパシター
第１電極３６を形成する。その後、図１（Ｉ）に示した
ように、該キャパシター第１電極３６上の感光膜３８
は、Ｈ2 ＳＯ4 ／Ｈ2 Ｏ2 湿式溶液（wet solution）に
浸漬（dipping）して完全に除去する。Next, as shown in FIG. 1H, a photosensitive film 38 for a mask is formed on the upper surface of the capacitor first electrode 36, and the Pt capacitor first electrode 36 is photo-etched to form a capacitor. Form a region where a storage node will be formed, and use a BCl 3 / Cl 2 etchant to remove R
Etching is performed by the IE method to form the capacitor first electrode 36 having a predetermined shape. Thereafter, as shown in FIG. 1 (I), a photosensitive film 38 on the capacitor first electrode 36 is formed.
Is completely removed by dipping in H 2 SO 4 / H 2 O 2 wet solution.
【００１３】次いで、図１（Ｊ）に示したように、それ
らキャパシター第１電極３６及び絶縁膜２８上に５００
Å厚さの誘電体層４０を化学蒸着法により蒸着するが、
この場合、該誘電体層４０は３以上の誘電常数を有する
ＢａＳｒＴｉＯ3 、ＳｒＴｉＯ3 、ＢａＴｉＯ3 、Ｐｂ
ＺｒＯ3 、ＰＺＴ、及びＰＬＺＴでなるグループから選
択された何れ一つの物質を用いる。その後、該誘電体層
４０上にＰｔのキャパシター第２電極４２を蒸着する
が、この場合該Ｐｔの代わりにＷ叉はＴｉＮを使用する
こともできる。Next, as shown in FIG. 1 (J), 500 is formed on the capacitor first electrode 36 and the insulating film 28.
The dielectric layer 40 having a thickness of Å is deposited by the chemical vapor deposition method.
In this case, the dielectric layer 40 is made of BaSrTiO 3 , SrTiO 3 , BaTiO 3 , Pb having a dielectric constant of 3 or more.
Any one substance selected from the group consisting of ZrO 3 , PZT, and PLZT is used. After that, a Pt capacitor second electrode 42 is deposited on the dielectric layer 40. In this case, W or TiN may be used instead of Pt.
【００１４】このように製造される本発明に係る半導体
素子のキャパシターにおいては、Ｐｔの薄膜をエッチン
グして簡単にキャパシター第１電極を形成するようにな
るため、従来よりも電極の形成工程が極めて容易に行わ
れる。且つ、ノードの接続とノードのパターン間にミス
アライン（mis-align）が発生しても、単結晶シリコン
プラグは露出されず、障壁層のＴｉＮプラグが露出され
るため、従来障壁層の酸化により電極が割れる現象が防
止されキャパシターの信頼性が向上される。In the capacitor of the semiconductor device according to the present invention manufactured as described above, since the Pt thin film is etched to easily form the first electrode of the capacitor, the electrode forming process is much more difficult than in the prior art. Easily done. Moreover, even if mis-alignment occurs between the node connection and the node pattern, the single crystal silicon plug is not exposed and the TiN plug of the barrier layer is exposed. The phenomenon of cracking is prevented and the reliability of the capacitor is improved.
【００１５】[0015]
【発明の効果】以上、説明したように、本発明に係る半
導体素子のキャパシター及びその製造方法においては、
絶縁膜の接続ホール内に障壁層のＴｉＮプラグを形成
し、該ＴｉＮプラグ上にキャパシター第１電極を被覆形
成してなるため、従来の誘電体膜蒸着時に発生する障壁
層の酸化問題が解決され、電極が応力を受けて割れる現
象が防止されて、キャパシターの信頼性が向上されると
いう効果がある。As described above, in the capacitor of the semiconductor device and the method for manufacturing the same according to the present invention,
Since the TiN plug of the barrier layer is formed in the connection hole of the insulating film and the first electrode of the capacitor is formed on the TiN plug by coating, the problem of oxidation of the barrier layer that occurs when the conventional dielectric film is deposited is solved. The effect of preventing the electrode from cracking due to stress is improved, and the reliability of the capacitor is improved.
【図１】（Ａ）−（Ｊ）本発明に係る半導体素子のキャ
パシター及びその製造工程図である。1A to 1J are views showing a capacitor of a semiconductor device according to the present invention and a manufacturing process diagram thereof.
【図２】従来半導体素子のキャパシターの構造を示した
縦断面図である。FIG. 2 is a vertical cross-sectional view showing a structure of a capacitor of a conventional semiconductor device.
１、２０：半導体基板 ２ａ、２ｂ、２２：ゲート電極 ３：絶縁層 ４：多結晶シリコンプラグ ５：キャパシター ６：ソース叉はドレイン領域 ７ａ：下部電極 ７ｂ：上部電極 ８：誘電フィールム ９：障壁層 ２４、２５：不純物拡散（ソース／ドレイン）領域 ２６：フィールド酸化膜 ２８：絶縁膜 ３０：多結晶シリコン層 ３２：プラグ ３４：障壁層 ３５：ＴｉＮプラグ ３６：キャパシター第１電極 ３８：感光膜 ４０：誘電体層 ４２：キャパシター第２電極 1, 20: Semiconductor substrate 2a, 2b, 22: Gate electrode 3: Insulating layer 4: Polycrystalline silicon plug 5: Capacitor 6: Source or drain region 7a: Lower electrode 7b: Upper electrode 8: Dielectric film 9: Barrier layer 24 and 25: Impurity diffusion (source / drain) regions 26: Field oxide film 28: Insulating film 30: Polycrystalline silicon layer 32: Plug 34: Barrier layer 35: TiN plug 36: Capacitor first electrode 38: Photosensitive film 40: Dielectric layer 42: second electrode of capacitor
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/822 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification number Agency reference number FI Technical indication H01L 21/822
Claims (14)
さを有して形成されたプラグと、 該接続ホール内のプラグ上面に形成された障壁層のＴｉ
ｎプラグと、 それらＴｉｎプラグ及び絶縁膜上に形成されたキャパシ
ター第１電極と、 該キャパシター第１電極上に形成された誘電層と、 該誘電層上に形成されたキャパシター第２電極と、を備
えた半導体素子のキャパシター。1. A capacitor of a semiconductor device, comprising an insulating film formed on a semiconductor substrate and having a connection hole, and having a thickness lower than the thickness of the insulating film in the connection hole of the insulating film. The formed plug and the Ti of the barrier layer formed on the upper surface of the plug in the connection hole
an n plug, a capacitor first electrode formed on the Tin plug and the insulating film, a dielectric layer formed on the capacitor first electrode, and a capacitor second electrode formed on the dielectric layer. Equipped semiconductor device capacitor.
であって、 半導体基板上に絶縁膜を形成する工程と、 該絶縁膜を選択的に食刻し、該絶縁膜所定部位に接続ホ
ールを形成する工程と、 該絶縁膜の接続ホール内に電導性プラグを形成する工程
と、 該接続ホール内の電導性プラグ上に障壁層を形成する工
程と、 それら障壁層及び絶縁膜上にキャパシター第１電極を形
成する工程と、 該キャパシター第１電極上に誘電体層を形成する工程
と、 該誘電体層上にキャパシター第２電極を形成する工程
と、を順次行う半導体素子のキャパシター製造方法。2. A method of manufacturing a capacitor of a semiconductor device, comprising the steps of forming an insulating film on a semiconductor substrate, selectively etching the insulating film, and forming a connection hole at a predetermined portion of the insulating film. And a step of forming a conductive plug in the connection hole of the insulating film, a step of forming a barrier layer on the conductive plug in the connection hole, and a capacitor first on the barrier layer and the insulating film. A method for manufacturing a capacitor of a semiconductor device, which sequentially comprises a step of forming an electrode, a step of forming a dielectric layer on the capacitor first electrode, and a step of forming a capacitor second electrode on the dielectric layer.
上にゲート電極及びフィールド酸化膜を形成し、それら
ゲート電極及びフィールド酸化膜上に絶縁膜を蒸着する
請求項２記載の半導体素子のキャパシター製造方法。3. The semiconductor device according to claim 2, wherein in the step of forming the insulating film, a gate electrode and a field oxide film are formed on a semiconductor substrate, and an insulating film is deposited on the gate electrode and the field oxide film. Capacitor manufacturing method.
る請求項２記載の半導体素子のキャパシター製造方法。4. The method for manufacturing a capacitor of a semiconductor device according to claim 2, wherein the insulating film is deposited to a thickness of 3000 Å.
ール内に電導性プラグを形成する工程間に、該接続ホー
ル及び前記絶縁膜上に多結晶シリコン層を蒸着する段階
と、該多結晶シリコン層をエッチバックする段階と、が
追加して行われる請求項２記載の半導体素子のキャパシ
ター製造方法。5. A step of depositing a polycrystalline silicon layer on the connection hole and the insulating film between the step of forming the connection hole and the step of forming a conductive plug in the connection hole, and the polycrystal. The method for manufacturing a capacitor of a semiconductor device according to claim 2, wherein the step of etching back the silicon layer is additionally performed.
（ＬＰＣＶＤ）により、２０００Åの厚さに蒸着する請
求項５記載の半導体素子のキャパシター製造方法。6. The method for manufacturing a capacitor of a semiconductor device according to claim 5, wherein the polycrystalline silicon layer is deposited to a thickness of 2000 Å by low pressure chemical vapor deposition (LPCVD).
は、Ｃｌ2 ／Ｏ2 エッチング液を用いて行う請求項５記
載の半導体素子のキャパシター製造方法。7. The method of manufacturing a capacitor for a semiconductor device according to claim 5, wherein the step of etching back the polycrystalline silicon layer is performed using a Cl 2 / O 2 etchant.
Ｔａ、Ｗ，Ｍｏの金属合金及びそれらの金属ケイ化物
（silicide）中何れ一つを用いる請求項２記載の半導体
素子のキャパシター製造方法。8. In the step of forming the barrier layer, TiN,
3. The method of manufacturing a capacitor for a semiconductor device according to claim 2, wherein any one of Ta, W, Mo metal alloys and metal silicides thereof is used.
は、２０００Åの厚さにスパッタリング法を施して蒸着
する請求項２記載の半導体素子のキャパシター製造方
法。9. The method of manufacturing a capacitor for a semiconductor device according to claim 2, wherein in the step of forming the first electrode of the capacitor, the thickness of 2000 Å is applied by sputtering.
ｄ、Ｒｕ、ＲｕＯ2及び電導性を有する酸化物中、何れ
一つを用いて形成する請求項２記載の半導体素子のキャ
パシター製造方法。10. The first electrode of the capacitor is Pt, P
The method for manufacturing a capacitor of a semiconductor device according to claim 2, wherein any one of d, Ru, RuO 2, and an oxide having conductivity is used.
程と前記誘電体層を形成する工程間に、該キャパシター
第１電極を形成した後、該キャパシター第１電極上にマ
スク用の感光膜を形成する工程と、該感光膜を湿式溶液
に浸漬して除去する工程と、が追加行われる請求項２記
載の半導体素子のキャパシター製造方法。11. A photosensitive film for a mask is formed on the capacitor first electrode after the capacitor first electrode is formed between the step of forming the capacitor first electrode and the step of forming the dielectric layer. 3. The method of manufacturing a capacitor of a semiconductor device according to claim 2, further comprising the steps of: and a step of immersing and removing the photosensitive film in a wet solution.
／Ｃｌ2 エッチング液を用いて残部を除去し、前記感光
膜はＨ2 ＳＯ4 ／Ｈ2 Ｏ2 湿式溶液に浸漬して除去する
請求項１１記載の半導体素子のキャパシター製造方法。12. The first electrode of the capacitor comprises BCl 3
The method for manufacturing a capacitor of a semiconductor device according to claim 11, wherein the remaining portion is removed using a / Cl 2 etching solution, and the photosensitive film is removed by immersing the photosensitive film in a H 2 SO 4 / H 2 O 2 wet solution.
ａＳｒＴｉＯ3 、ＳｒＴｉＯ3 、ＢａＴｉＯ3 、ＰｂＺ
ｒＯ3 、ＰＺＴ、及びＰＬＺＴでなるグループから選択
された何れ一つの物質を用いて行う請求項２記載の半導
体素子のキャパシター製造方法。13. The formation of the dielectric layer is made of Ta 2 O 5 , B
aSrTiO 3 , SrTiO 3 , BaTiO 3 , PbZ
The method of manufacturing a capacitor of a semiconductor device according to claim 2, wherein the material is selected from the group consisting of rO 3 , PZT, and PLZT.
Ｗ、及びＴｉＮ中何れ一つにより製造される請求項２記
載の半導体素子のキャパシター製造方法。14. The second electrode of the capacitor is Pt,
The method of manufacturing a capacitor for a semiconductor device according to claim 2, wherein the method is manufactured by using one of W and TiN.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR95P35979 | 1995-10-18 | ||
| KR1019950035979A KR100199093B1 (en) | 1995-10-18 | 1995-10-18 | Fabrication method of capacitor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09129849A true JPH09129849A (en) | 1997-05-16 |
| JP2826717B2 JP2826717B2 (en) | 1998-11-18 |
Family
ID=19430543
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8001741A Expired - Fee Related JP2826717B2 (en) | 1995-10-18 | 1996-01-09 | Method for manufacturing capacitor of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2826717B2 (en) |
| KR (1) | KR100199093B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7071071B2 (en) | 2003-03-19 | 2006-07-04 | Elpida Memory, Inc. | Method of manufacturing semiconductor device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001057412A (en) | 1999-08-19 | 2001-02-27 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JP2001217403A (en) * | 2000-02-04 | 2001-08-10 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method therefor |
| JP2007036126A (en) | 2005-07-29 | 2007-02-08 | Fujitsu Ltd | Semiconductor device and method for manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08335680A (en) * | 1995-06-06 | 1996-12-17 | Texas Instr Inc <Ti> | Method and equipment for forming internal electrode in high-density and high-permittivity memory device |
-
1995
- 1995-10-18 KR KR1019950035979A patent/KR100199093B1/en not_active IP Right Cessation
-
1996
- 1996-01-09 JP JP8001741A patent/JP2826717B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08335680A (en) * | 1995-06-06 | 1996-12-17 | Texas Instr Inc <Ti> | Method and equipment for forming internal electrode in high-density and high-permittivity memory device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7071071B2 (en) | 2003-03-19 | 2006-07-04 | Elpida Memory, Inc. | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100199093B1 (en) | 1999-06-15 |
| JP2826717B2 (en) | 1998-11-18 |
| KR970024208A (en) | 1997-05-30 |
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